Chip selection method for SiC MOSFET multi-chip parallel modules

Abstract

This invention addresses the dynamic and static current imbalance problem in multi-chip parallel applications of SiC MOSFETs by constructing a chip selection method suitable for multi-chip parallel modules of SiC MOSFETs. This method integrates a parallel current imbalance prediction model based on multiphysics simulation and machine learning, and also considers the impact of electrical parameter mismatch between SiC MOSFETs on the parallel current sharing characteristics in the chip selection process.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and specifically to a chip selection method suitable for SiC MOSFET multi-chip parallel modules. Background Technology

[0002] Currently, SiC MOSFETs have demonstrated enormous application potential in power electronic systems across various fields due to their excellent characteristics such as high voltage withstand capability, low on-resistance, high switching speed, and high temperature resistance. However, due to various limitations, the rated current of current single-chip SiC MOSFETs is generally low, making it difficult to directly meet the needs of high-current applications. The industry commonly connects multiple independent SiC MOSFETs in parallel within the same package to overcome the current capacity bottleneck of a single transistor and construct high-current multi-chip power modules. However, when using a multi-chip parallel solution, the system often faces the challenge of uneven current distribution, which directly affects system reliability and may even lead to module failure.

[0003] In multi-chip SiC MOSFET parallel systems, their parallel current sharing characteristics can be divided into static and dynamic cases. The positive temperature coefficient of SiC MOSFET on-resistance endows the device with a natural self-regulating capability: when the current distribution is uneven due to resistance differences in the parallel branches, the junction temperature of the branch with higher current rises, and the on-resistance increases accordingly, thereby automatically suppressing current overshoot and forming thermoelectric negative feedback. This mechanism effectively clamps the static current imbalance problem under steady state. However, dynamic current imbalance is considered the primary factor threatening reliability. The imbalance of dynamic current mainly stems from two aspects: first, the dispersion of key parameters of the device itself (such as threshold voltage, transconductance, gate-source capacitance, gate-drain capacitance, and gate resistance); second, the parasitic parameter differences caused by asymmetrical layout and wiring in the parallel circuit. As the operating frequency increases, energy dissipation during the switching process gradually becomes dominant, and its value far exceeds the steady-state conduction loss, which significantly amplifies the transient current imbalance problem.

[0004] Methods to mitigate dynamic current imbalance can be broadly categorized into two types: passive and active. Passive methods minimize the impact of electrical parameter mismatches between loops on current sharing characteristics through optimized layout or device selection. Active methods employ auxiliary circuits or components to achieve current rebalancing, including passive devices and active gate control. Device selection is widely used in industrial production due to its simplicity, convenience, and lower cost compared to other methods. However, commonly used device selection methods have significant shortcomings: Firstly, most methods rely solely on single parameters such as threshold voltage or on-resistance for selection and control, failing to fully consider the complex coupling effects between multiple parameters on current sharing characteristics, nor the influence of parasitic parameters and temperature on current within the module. Secondly, the control standards for parameters cannot be effectively defined; overly stringent standards increase costs, while lenient standards increase the risk of current imbalance. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to address the dynamic and static current imbalance problem in the parallel application of SiC MOSFET multi-chips, and to construct a chip selection method suitable for SiC MOSFET multi-chip parallel modules. This method integrates a parallel current imbalance prediction model based on multiphysics simulation and machine learning, and also considers the impact of the electrical parameter mismatch between SiC MOSFETs on the parallel current sharing characteristics in the chip selection process.

[0006] To achieve the above-mentioned objectives, the technical solution adopted by this invention is as follows:

[0007] A chip selection method for SiC MOSFET multi-chip parallel modules includes the following steps:

[0008] Step 1: Based on the electrical parameters and application requirements of the SiC module, determine two or more electrical parameters that need to be screened and controlled, and at the same time determine the reference value of the electrical parameters. The electrical parameters are device static parameters or dynamic parameters, selected from threshold voltage Vth, on-resistance Ron, transconductance gfs, gate-source capacitance Cgs, gate-drain capacitance Cgd, and gate resistance Rg.

[0009] Step 2: Set the initial control range for the electrical parameters to be screened. For electrical parameter M, let its base value be a, and the initial control range be [ab, a+c], where b and c are numbers greater than zero.

[0010] Step 3: Input the control range of each electrical parameter into the parallel current imbalance prediction model to obtain the current imbalance β of the parallel module. The current imbalance β is used to quantitatively characterize the current difference between parallel devices due to parameter differences. Its calculation formula is as follows:

[0011]

[0012] ,

[0013] Where n is the number of branches in the parallel module, assuming that the SiC chip in a certain branch has its own reference values ​​for each electrical parameter to be screened, then the current flowing through the SiC chip is... Assuming that the SiC chip on the i-th branch has electrical parameters that need to be selected as a combination within their respective control ranges, then the current flowing through the SiC chip is yi. y is the standard deviation of the current values ​​of all branches, and β is the current imbalance of the parallel module;

[0014] Step 4: If β meets the requirements, that is, both the dynamic current imbalance and the static current imbalance are less than a certain specified value, then the combination of the control range of each electrical parameter is determined as the screening criterion for the parallel chip. If β is greater than the specified value, then the control range of one or more electrical parameters is narrowed, and the process described in Step 3 and Step 4 is repeated until the current imbalance meets the design requirements.

[0015] As a preferred approach, the parallel current imbalance prediction model includes the following establishment process:

[0016] Step (1): Use Solidworks software to complete the geometric model of the three-dimensional physical structure of the SiC MOSFET multi-chip parallel power module, and output the file in STEP format for subsequent simulation;

[0017] Step (2): Import the STEP file output in step (1) above into ANSYS multiphysics simulation software, and use ANSYS Q3D to perform electromagnetic simulation on the three-dimensional physical structure of the SiC MOSFET module, thereby extracting the parasitic parameter network of the SiC MOSFET module, including parasitic inductance parameters at different frequencies.

[0018] Step (3): Import the STEP file output in step (1) above into Ansys Icepak, and use the Fluent computational fluid dynamics solver to perform thermal and fluid flow analysis on the chip, DBC substrate, solder layer, bonding wire and heat sink structure of the SiC MOSFET power module, extract its thermal resistance network, and export the LTI ROM model containing the thermal resistance network for subsequent electrothermal coupling simulation.

[0019] Step (4): Construct the electrothermal coupling simulation platform for the SiC MOSFET module in the Ansys Simplorer environment. Using the parasitic parameters and thermal resistance network obtained in Step (2) and Step (3) above, perform electrothermal coupling Monte Carlo simulation. In the Monte Carlo simulation method, the difference between the module parasitic parameters and thermal resistance has been considered. Therefore, the only condition affecting the parallel current sharing characteristics is the dynamic and static characteristics of the device itself. Input the dynamic and static characteristic parameters of multiple devices themselves, perform electrothermal coupling simulation on the branch, and obtain the static and dynamic current imbalance. Based on the principles of random sampling and statistics, repeatedly sample the dynamic and static electrical parameters of multiple devices to be screened within the preset distribution range to obtain the random combination of each parameter value. Input the electrothermal coupling simulation platform for simulation to obtain the corresponding static and dynamic current imbalance, thereby generating a large-scale synthetic data sample. The data sample uses multiple selected electrical parameters as input features and the corresponding dynamic current imbalance and static current imbalance as output labels to provide a data basis for the training of subsequent algorithm models.

[0020] Step (5): Divide the data sample set generated in step (4) into two parts: training set and validation set. The training set is used to adjust the weights and biases of the network, and the validation set is used to test the prediction accuracy of the model after training. The hidden layer activation function is the core nonlinear part in the neural network algorithm. Its role is to introduce nonlinear transformation capability into the model. Different activation functions and the number of hidden layers will affect the prediction accuracy of the model. Different hidden layer activation functions are used for modeling. Feedforward neural network BPNN analysis is performed on the training set. The model accuracy is verified by the validation set. The models established by different activation functions and the number of hidden layers are compared. The normalized error of the prediction of dynamic and static current imbalance is used. The activation function and the number of hidden layers with the smallest normalized error are selected to establish the parallel current imbalance prediction model. This model can realize the prediction of dynamic and static current imbalance of SiC MOSFET. That is, the combination of multiple SiC MOSFET electrical parameters is input into the model, and the current imbalance β can be output.

[0021] As a preferred approach, the normalization error of the parallel current imbalance prediction model must be less than the current imbalance β specified in the screening criteria.

[0022] As a preferred approach, the activation function used in the BPNN algorithm analysis of the parallel current imbalance prediction model is selected from: Linear function, Hardlim function, Elu function, and Tanh function.

[0023] The beneficial effects of this invention are as follows:

[0024] This invention proposes a screening method for parallel SiC MOSFET chips based on multi-parameter coupling. Compared to traditional screening methods that rely on only a single parameter, this invention fully considers the influence of complex nonlinear coupling effects between multiple electrical parameters on parallel current sharing characteristics. In practical applications, when multiple parameters change simultaneously, their coupled influence on current imbalance is not a simple superposition of the independent effects of each parameter. The changing trends and results are difficult to predict directly through theoretical analysis. Relying entirely on multiphysics joint simulation to evaluate the current sharing performance under different parameter combinations results in enormous computational load and long processing time, failing to meet the rapid screening requirements in industrial production. This invention constructs a parallel current imbalance prediction model that integrates multiphysics simulation and machine learning, enabling the rapid establishment of nonlinear mapping relationships between multiple device parameters, layout variables, and current sharing performance indicators. Once the model is trained, only different combinations of SiC MOSFET electrical parameters need to be input to obtain the corresponding current imbalance in a very short time, thus bypassing the complex physical mechanisms and time-consuming iterative simulation process. The model built using the BPNN algorithm has high accuracy in predicting current imbalance for parallel devices. This method not only provides a scientific and quantitative basis for device selection under multi-parameter coupling, but also allows for flexible adjustment of selection criteria according to different current sharing requirements, optimizing chip utilization while ensuring module reliability. It is of great value for guiding device selection in industrialization. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the chip selection method for a SiC MOSFET multi-chip parallel module;

[0026] Figure 2 This is a diagram of the Ansys Simplorer electrothermal coupling simulation framework;

[0027] Figure 3 This is a flowchart of the analysis using the BPNN algorithm;

[0028] Figure 4 This is a schematic diagram of an electrothermal coupling simulation of one phase of a three-phase full-bridge inverter.

[0029] Figure 4 In the diagram, D and M both represent an independent SiC MOSFET in the module, with D acting as a diode. Lg, Lk, Ls, and Ld are parasitic parameters extracted using ANSYS Q3D, and LTI ROM represents the thermal resistance network of each SiC MOSFET extracted using ANSYS Icepak. The figure below is a schematic diagram of the electrothermal coupling simulation of one arm of a three-phase full-bridge inverter constructed using parasitic parameters and thermal resistance networks. Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] Figure 1 This is a schematic diagram of the chip selection method for a SiC MOSFET multi-chip parallel module; for example... Figure 1 As shown in the diagram, according to the process, firstly, the baseline values ​​and initial control ranges of each electrical parameter to be screened are set. Then, the control ranges of each electrical parameter are combined and input into the parallel current imbalance prediction model to obtain the current imbalance β of the module. If the predicted current imbalance meets the requirements, the current combination of control ranges of each electrical parameter is determined as the screening criterion for the parallel chip. If β does not meet the requirements, it is necessary to narrow down the control range of one or more electrical parameters and input them again into the parallel current imbalance prediction model until the obtained β meets the requirements.

[0032] Figure 2 This is a diagram of the Ansys Simplorer electrothermal coupling simulation framework; for example... Figure 2 As shown in the figure, according to the process, first complete the geometric modeling, then perform electromagnetic and thermal simulations, use the obtained parasitic parameter network, thermal resistance network and initial junction temperature to perform electrothermal coupling simulation until the termination condition is met, and output the current waveform and junction temperature.

[0033] Figure 3 This is a flowchart of the analysis using the BPNN algorithm; for example... Figure 3 As shown, a backpropagation neural network (BPNN) model is established using the dataset generated by the electrothermal coupling Monte Carlo simulation. According to the process shown in the figure, the network parameters are initialized, data is input, forward propagation is performed, and the error Loss is calculated. If the error meets the termination condition, the result is output; if the error is greater than the requirement, the gradient is backpropagated, the weights are updated, data is re-inputted, and the calculation is performed until the termination condition is finally met, and the final result is output.

[0034] Figure 4 This is a schematic diagram of an electrothermal coupling simulation of one phase of a three-phase full-bridge inverter; such as Figure 4As shown below, the circuit diagram of one arm of a three-phase full-bridge inverter is shown below. In the figure, D and M both represent an independent SiC MOSFET in the module, including its electrical and thermal characteristics. Its internal connection is shown in the two figures above. M is used as a normally operating MOSFET device, D is used as a diode, Lg, Lk, Ls, and Ld are parasitic parameters extracted using ANSYS Q3D, and LTI ROM represents the thermal resistance network of each SiC MOSFET extracted using ANSYS Icepak.

[0035] like Figure 1 As shown, the embodiment provides a chip selection method suitable for SiC MOSFET multi-chip parallel modules, including the following steps:

[0036] Step 1: Based on the electrical parameters and application requirements of the SiC module, determine two or more electrical parameters that need to be screened and controlled, and at the same time determine the reference value of the electrical parameters. The electrical parameters are device static parameters or dynamic parameters, selected from threshold voltage Vth, on-resistance Ron, transconductance gfs, gate-source capacitance Cgs, gate-drain capacitance Cgd, and gate resistance Rg.

[0037] Step 2: Set the initial control range for the electrical parameters to be screened. For electrical parameter M, let its base value be a, and the initial control range be [ab, a+c], where b and c are numbers greater than zero.

[0038] Step 3: Input the control range of each electrical parameter into the parallel current imbalance prediction model to obtain the current imbalance β of the parallel module. The current imbalance β is used to quantitatively characterize the current difference between parallel devices due to parameter differences. Its calculation formula is as follows:

[0039]

[0040] ,

[0041] Where n is the number of branches in the parallel module, assuming that the SiC chip in a certain branch has its own reference values ​​for each electrical parameter to be screened, then the current flowing through the SiC chip is... Assuming that the SiC chip on the i-th branch has electrical parameters that need to be selected as a combination within their respective control ranges, then the current flowing through the SiC chip is yi. y is the standard deviation of the current values ​​of all branches, and β is the current imbalance of the parallel module;

[0042] Step 4: If β meets the requirements, that is, both the dynamic current imbalance and the static current imbalance are less than a certain specified value, then the combination of the control range of each electrical parameter is determined as the screening criterion for the parallel chip. If β is greater than the specified value, then the control range of one or more electrical parameters is narrowed, and the process described in Step 3 and Step 4 is repeated until the current imbalance meets the design requirements.

[0043] In some embodiments, the parallel current imbalance prediction model includes the following establishment process:

[0044] Step (1): Use Solidworks software to complete the geometric model of the three-dimensional physical structure of the SiC MOSFET multi-chip parallel power module, and output the file in STEP format for subsequent simulation;

[0045] Step (2): Import the STEP file output in step (1) above into ANSYS multiphysics simulation software, and use ANSYS Q3D to perform electromagnetic simulation on the three-dimensional physical structure of the SiC MOSFET module, thereby extracting the parasitic parameter network of the SiC MOSFET module, including parasitic inductance parameters at different frequencies.

[0046] Step (3): Import the STEP file output in step (1) above into Ansys Icepak, and use the Fluent computational fluid dynamics solver to perform thermal and fluid flow analysis on the chip, DBC substrate, solder layer, bonding wire and heat sink structure of the SiC MOSFET power module, extract its thermal resistance network, and export the LTI ROM model containing the thermal resistance network for subsequent electrothermal coupling simulation.

[0047] Step (4): Construct the electrothermal coupling simulation platform for the SiC MOSFET module in the Ansys Simplorer environment. Using the parasitic parameters and thermal resistance network obtained in Step (2) and Step (3) above, perform electrothermal coupling Monte Carlo simulation. In the Monte Carlo simulation method, the difference between the module parasitic parameters and thermal resistance has been considered. Therefore, the only condition affecting the parallel current sharing characteristics is the dynamic and static characteristics of the device itself. Input the dynamic and static characteristic parameters of multiple devices themselves, perform electrothermal coupling simulation on the branch, and obtain the static and dynamic current imbalance. Based on the principles of random sampling and statistics, repeatedly sample the dynamic and static electrical parameters of multiple devices to be screened within the preset distribution range to obtain the random combination of each parameter value. Input the electrothermal coupling simulation platform for simulation to obtain the corresponding static and dynamic current imbalance, thereby generating a large-scale synthetic data sample. The data sample uses multiple selected electrical parameters as input features and the corresponding dynamic current imbalance and static current imbalance as output labels to provide a data basis for the training of subsequent algorithm models.

[0048] Step (5): Divide the data sample set generated in step (4) into two parts: training set and validation set. The training set is used to adjust the weights and biases of the network, and the validation set is used to test the prediction accuracy of the model after training. The hidden layer activation function is the core nonlinear part in the neural network algorithm. Its role is to introduce nonlinear transformation capability into the model. Different activation functions and the number of hidden layers will affect the prediction accuracy of the model. Different hidden layer activation functions are used for modeling. Feedforward neural network BPNN analysis is performed on the training set. The model accuracy is verified by the validation set. The models established by different activation functions and the number of hidden layers are compared. The normalized error of the prediction of dynamic and static current imbalance is used. The activation function and the number of hidden layers with the smallest normalized error are selected to establish the parallel current imbalance prediction model. This model can realize the prediction of dynamic and static current imbalance of SiC MOSFET. That is, the combination of multiple SiC MOSFET electrical parameters is input into the model, and the current imbalance β can be output.

[0049] In some embodiments, the normalization error of the parallel current imbalance prediction model must be less than the current imbalance β specified in the screening criteria.

[0050] In some embodiments, the activation function used in the BPNN algorithm analysis of the parallel current imbalance prediction model is selected from: Linear function, Hardlim function, Elu function, and Tanh function.

[0051] Example 1

[0052] To reduce the impact of electrical parameter mismatch between SiC MOSFETs on the parallel current sharing characteristics in parallel systems, this embodiment selects two key electrical parameters, threshold voltage Vth and on-resistance Ron, for joint screening, including the following steps:

[0053] 1. Based on the electrical parameters of the SiC module, the threshold voltage Vth and on-resistance Ron of the parallel SiC MOSFETs were determined as screening criteria. The reference value for Vth is 3.4V, and the reference value for Ron is 20mΩ.

[0054] 2. Set the initial control ranges for Vth and Ron respectively. Set the initial control range of Vth to [3.0, 3.8]V, that is, the Vth of all selected parallel chips should be greater than or equal to 3.0V and less than or equal to 3.8V; set the initial control range of Ron to [18, 24]mΩ, that is, the Ron of all selected parallel chips should be greater than or equal to 18mΩ and less than or equal to 24mΩ.

[0055] 3. The Vth control range [3.0, 3.8]V and the Ron control range [18, 24]mΩ are simultaneously input into the parallel current imbalance prediction model. It is found that the dynamic current imbalance of the parallel module is 4.52% and the static current imbalance is 1.86% when the second pulse is turned on in the double pulse test.

[0056] 4. According to the design requirements, both dynamic and static current imbalances must be less than 1%. Currently, the dynamic current imbalance is 4.52% and the static current imbalance is 1.86%, both of which do not meet the design requirements. Therefore, the control ranges for each electrical parameter must be narrowed simultaneously. The control range for Vth is narrowed to [3.2, 3.6]V, and the control range for Ron is narrowed to [19, 22]mΩ. These values ​​are then re-introduced into the parallel current imbalance prediction model. Steps 3 and 4 are repeated, iterating and verifying the control ranges multiple times until the current imbalance meets the design requirements. Finally, it is determined that for the SiC MOSFET used to build this power module, the control range for its threshold voltage Vth should be [3.32, 3.48]V, and the control range for its on-resistance Ron should be [19.2, 21.0]mΩ. This means that a SiC MOSFET with a threshold voltage Vth greater than or equal to 3.32V and less than or equal to 3.48V, and an on-resistance Ron greater than or equal to 19.2mΩ and less than or equal to 21.0mΩ should be selected to ensure that the dynamic and static current imbalance of the power module is less than 1%.

[0057] The process of establishing the parallel current imbalance prediction model in step 3 is as follows:

[0058] (1) Establish a three-dimensional structural model of the SiC MOSFET multi-chip parallel power module in SolidWorks. The module is a typical three-phase full-bridge inverter structure. Each bridge arm contains three parallel SiC MOSFET chips in the upper and lower bridge arms. The output format is STEP file for subsequent simulation.

[0059] (2) Import the STEP file from step (1) above into ANSYS Q3D, assign values ​​to the material properties of each structural layer in the module, and extract the parasitic parameters of the module at different frequencies through this platform, mainly including the gate parasitic inductance L. G Drain parasitic inductance L D Source parasitic inductance L S Kelvin source parasitic inductance L K Since the internal layout of the module is not completely symmetrical, the parasitic parameters of each branch are different. The extraction results accurately record the differentiated parasitic inductance values ​​of each branch to truly reflect the asymmetry introduced by the package layout.

[0060] (3) Import the STEP file from step (1) into ANSYS Icepak, assign corresponding material properties according to each layer structure, set boundary conditions and power consumption, and perform temperature field simulation to obtain the temperature cloud map of the module. Export the thermal resistance network of each SiC MOSFET through the built-in LTIROM (linear time-invariant reduced-order model) in Icepak, which is used to calculate the chip junction temperature in real time in subsequent electrothermal coupling simulation.

[0061] (4) Set up the electrothermal coupling simulation environment in Simplier. To simplify the simulation, select one of the bridge arms to build the circuit simulation model. Import the parasitic parameters and thermal resistance network of the module obtained in steps (2) and (3) above, perform electrothermal coupling simulation, and obtain the dataset that causes dynamic and static current imbalance between parallel SiC MOSFETs for subsequent model training. The differences in module parasitic parameters and thermal resistance have been fixed in this simulation environment, so the variables affecting the parallel current sharing characteristics are only the electrical parameters of the device itself. The independent variables required for input in this embodiment are the threshold voltage Vth and on-resistance Ron of the SiC MOSFET device. Set the value range of Vth to [3.0, 3.8]V and the value range of Ron to [18, 24]mΩ, use uniform distribution random sampling to generate input parameter combinations, and perform Monte Carlo simulation of electrothermal coupling. Through large-scale repeated sampling and circuit simulation, 1200 sets of Monte Carlo datasets containing input (Vth, Ron) and output (dynamic current imbalance, static current imbalance) were finally generated.

[0062] (5) The model is trained using the dataset generated by the Monte Carlo simulation in step (4) above, and a backpropagation neural network (BPNN) is used to analyze and establish the model. The data samples generated by the Monte Carlo simulation are divided into two parts: 1000 sets of data are used as the training set and 200 sets of data are used as the validation set. By comparing the normalization error of the models established by different hidden layer activation functions, the Tanh activation function with 8 hidden layers has the smallest error, so the Tanh activation function is selected for model training. The trained model is used to predict the dynamic and static current imbalance of SiC MOSFETs.

[0063] The model's predicted dynamic and static current imbalances on the final validation set were compared with simulated values. Using simulation as the zero error line, the prediction accuracies for the dynamic and static current imbalances of this 1200V SiC MOSFET product reached 97.92% and 96.88%, respectively. This result demonstrates that the model can accurately capture the complex nonlinear behavior of parallel systems under the coupling effect of threshold voltage Vth and on-resistance Ron, achieving rapid prediction of current sharing capabilities among different device combinations. When more electrical parameters are incorporated into the model, its description of complex coupling effects will be more comprehensive, and the prediction accuracy can be further improved.

[0064] In practical engineering applications, the trained model can output prediction results in a very short time. Compared with successively performing multi-physics co-simulation to evaluate the current sharing performance of different parameter combinations, the screening efficiency is greatly improved. This method can be used to perform multi-parameter collaborative screening and grouping of devices according to different current sharing index requirements, which has important application value for guiding device screening in industrial applications.

[0065] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A chip screening method suitable for SiC MOSFET multi-chip parallel connection module, characterized in that Includes the following steps: Step 1: Based on the electrical parameters and application requirements of the SiC module, determine two or more electrical parameters that need to be screened and controlled, and at the same time determine the reference value of the electrical parameters. The electrical parameters are device static parameters or dynamic parameters, selected from threshold voltage Vth, on-resistance Ron, transconductance gfs, gate-source capacitance Cgs, gate-drain capacitance Cgd, and gate resistance Rg. Step 2: Set the initial control range for the electrical parameters to be screened. For electrical parameter M, let its base value be a, and the initial control range be [ab, a+c], where b and c are numbers greater than zero. Step 3: Input the control range of each electrical parameter into the parallel current imbalance prediction model to obtain the current imbalance β of the parallel module. The current imbalance β is used to quantitatively characterize the current difference between parallel devices due to parameter differences. Its calculation formula is as follows: ， Wherein, n is the branch number of the parallel module, assuming that the SiC chip on a branch, each electrical parameter to be screened is the respective reference value, the current value flowing through the SiC chip is ; assuming that the SiC chip on the ith branch, each electrical parameter to be screened takes a certain combination within the respective control range, the current value flowing through the SiC chip is y i ; is the standard deviation of y i of all branch current values, and β is the current imbalance degree of the parallel module; Step 4: If β meets the requirements, that is, both the dynamic current imbalance and the static current imbalance are less than a certain specified value, then the combination of the control range of each electrical parameter is determined as the screening criterion for the parallel chip. If β is greater than the specified value, then the control range of one or more electrical parameters is narrowed, and the process described in Step 3 and Step 4 is repeated until the current imbalance meets the design requirements.

2. The chip selection method for SiC MOSFET multi-chip parallel modules according to claim 1, characterized in that, The parallel current imbalance prediction model includes the following establishment process: Step (1): Use Solidworks software to complete the geometric model of the three-dimensional physical structure of the SiC MOSFET multi-chip parallel power module, and output the file in STEP format for subsequent simulation; Step (2): Import the STEP file output in step (1) above into ANSYS multiphysics simulation software, and use ANSYSQ3D to perform electromagnetic simulation on the three-dimensional physical structure of the SiC MOSFET module, thereby extracting the parasitic parameter network of the SiC MOSFET module, including parasitic inductance parameters at different frequencies. Step (3): Import the STEP file output in step (1) above into Ansys Icepak, and use the Fluent computational fluid dynamics solver to perform thermal and fluid flow analysis on the chip, DBC substrate, solder layer, bonding wire and heat sink structure of the SiC MOSFET power module, extract its thermal resistance network, and export the LTI ROM model containing the thermal resistance network for subsequent electrothermal coupling simulation. Step (4): Construct the electrothermal coupling simulation platform for the SiC MOSFET module in the Ansys Simplorer environment. Using the parasitic parameters and thermal resistance network obtained in Step (2) and Step (3) above, perform electrothermal coupling Monte Carlo simulation. In the Monte Carlo simulation method, the difference between the module parasitic parameters and thermal resistance has been considered. Therefore, the only condition affecting the parallel current sharing characteristics is the dynamic and static characteristics of the device itself. Input the dynamic and static characteristic parameters of multiple devices themselves, perform electrothermal coupling simulation on the branch, and obtain the static and dynamic current imbalance. Based on the principles of random sampling and statistics, repeatedly sample the dynamic and static electrical parameters of multiple devices to be screened within the preset distribution range to obtain the random combination of each parameter value. Input the electrothermal coupling simulation platform for simulation to obtain the corresponding static and dynamic current imbalance, thereby generating a large-scale synthetic data sample. The data sample uses multiple selected electrical parameters as input features and the corresponding dynamic current imbalance and static current imbalance as output labels to provide a data basis for the training of subsequent algorithm models. Step (5): Divide the data sample set generated in step (4) into two parts: training set and validation set. The training set is used to adjust the weights and biases of the network, and the validation set is used to test the prediction accuracy of the model after training. The hidden layer activation function is the core nonlinear part in the neural network algorithm. Its role is to introduce nonlinear transformation capability into the model. Different activation functions and the number of hidden layers affect the prediction accuracy of the model. Different hidden layer activation functions are used for modeling. Feedforward neural network (BPNN) analysis is performed on the training set. The model accuracy is verified by the validation set. The models established by different activation functions and the number of hidden layers are compared. The normalized error of the prediction of dynamic and static current imbalance is used. The activation function and the number of hidden layers with the smallest normalized error are selected to establish a parallel current imbalance prediction model. This model can realize the prediction of dynamic and static current imbalance of SiC MOSFET. That is, the combination of multiple SiC MOSFET electrical parameters is input into the model, and the current imbalance β can be output.

3. The chip selection method for SiC MOSFET multi-chip parallel modules according to claim 2, characterized in that, The normalization error of the parallel current imbalance prediction model must be less than the current imbalance β specified in the screening criteria.

4. The chip selection method for SiC MOSFET multi-chip parallel modules according to claim 2, characterized in that, The activation functions used in the BPNN algorithm analysis of the parallel current imbalance prediction model are selected from: Linear function, Hardlim function, Elu function, and Tanh function.

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