Method and system for optimizing performance of digital signal processor simulation based on mirror memory

Abstract

This invention provides a method and system for optimizing the simulation performance of a digital signal processor (DSP) based on mirrored memory. The method includes acquiring the input data stream to be simulated and the size of the ring buffer; creating a main region and a mirror region in the DSP's virtual memory space; and mapping all main and mirror regions to the same physical memory region of the host machine. During simulation, a simulation pointer and counter are initialized, causing the simulation pointer to linearly increment according to the data unit length within the extended address space formed by the main and mirror regions, completing the unit-by-unit writing of the data stream. Only when the simulation pointer exceeds the boundary of the extended address space is the pointer address restored through a bitwise AND operation. Finally, the data in the extended address space is read and processed by the DSP simulation kernel to obtain the output data stream. This invention effectively reduces simulation computation overhead, simplifies the ring buffer processing logic, and significantly improves the performance and stability of DSP simulation.

Description

Technical Field

[0001] This invention relates to the field of computer simulation technology, and more specifically, to a method and system for optimizing the simulation performance of a digital signal processor (DSP) based on mirrored memory. Background Technology

[0002] Digital signal processors (DSPs), with their superior signal processing capabilities, are widely used in various signal processing scenarios such as communication, audio, and video. During the DSP software development and debugging phase, a host machine (such as a personal computer) is required to run a simulator to simulate the DSP kernel's behavior, completing program function verification and performance debugging. A ring buffer is an indispensable core data structure in a DSP system, primarily used to buffer streaming data, enabling continuous and efficient data stream reading, writing, and transmission processing. It is a key object to be simulated during DSP simulation.

[0003] Existing traditional DSP simulation solutions exhibit significant performance deficiencies when simulating circular cache read / write operations. Conventional simulation logic requires checking the circular cache boundary for the simulation pointer during each data read / write operation. If the pointer exceeds the cache boundary, arithmetic operations such as modulo operations and subtraction reset are used to wrap the pointer back to the valid cache address range. In high-throughput simulation scenarios with large data volumes, the data stream contains massive amounts of data units. These successive conditional branch checks and high-frequency arithmetic operations continuously consume a significant number of host machine processor cycles, resulting in substantial computational redundancy and significantly increasing simulation time. This becomes a core bottleneck restricting the efficiency of the DSP simulation kernel, failing to meet the demands of high-frequency, real-time simulation debugging.

[0004] At the same time, existing memory management technologies suffer from limitations in technical understanding. The industry generally considers the phenomenon of address aliases—multiple different virtual addresses mapping to the same physical memory block—as a security risk. This phenomenon easily leads to problems such as inconsistent memory data read / write operations and abnormal data overwriting. Therefore, current technology development focuses on the detection and avoidance of address aliases, without exploring the technical advantages of this memory mapping mechanism. It has not yet been applied to performance optimization scenarios in DSP ring cache simulation, resulting in long-standing issues of high computational redundancy and low performance in DSP simulation technology.

[0005] A patent search revealed an invention patent with publication number CN113705004A, which discloses a real-time system behavior-level software simulation method suitable for DSPs. This method uses function behavior results as the simulation evaluation basis and employs a high-level language to complete DSP function behavior-level simulation. It uses memory and dynamic arrays of control pointers as links, employing processing node modeling and instantiation, as well as multi-threading technology to complete the DSP real-time system simulation. Based on actual chip latency, it uses independent statistical analysis of transmission and computation times to complete the task software performance evaluation. This patent focuses on the overall task behavior and coarse latency, neglecting the underlying simulation overhead of high-frequency read / write operations to the circular cache, and does not optimize the performance loss caused by pointer boundary judgment and wraparound operations. Furthermore, it emphasizes task-level simulation adaptation and lacks fine-grained optimization at the memory scheduling level.

[0006] In summary, given the problems of the existing technologies, researching a method and system for optimizing the simulation performance of digital signal processors based on mirrored memory has become a critical task that urgently needs to be addressed. Summary of the Invention

[0007] To address the shortcomings of existing technologies, the purpose of this invention is to provide a method and system for optimizing the simulation performance of digital signal processors based on mirrored memory.

[0008] A method for optimizing the simulation performance of a digital signal processor based on mirrored memory, provided by the present invention, includes the following steps: Step S1: Obtain the input data stream to be simulated and the size A of the circular buffer to be simulated. Size A is an integer power of 2. The input data stream contains N data units, where N is a positive integer. Step S2: In the virtual memory space of the digital signal processor, create a main region and at least one mirror region. The size of the main region and at least one mirror region is equal to S, and the virtual addresses of the main region and at least one mirror region are contiguous. Step S3: Map the main region and at least one mirror region to the same physical memory region on the host machine. Step S4: Initialize the simulation pointer so that it points to the starting address of the main region, thereby making the simulation pointer point to the physical memory region through mapping; initialize the counter and set the value of the counter to 0. Step S5: Determine if the counter value is less than N: If the counter value is equal to N, then proceed to step S7; If the counter value is less than N, then execute the following sub-steps: Sub-step S5.1 causes the simulation pointer to increment linearly by the length of a data unit within the extended address space consisting of the main region and at least one mirror region. Sub-step S5.2: Write the (counter value + 1)th data unit in the input data stream to the physical memory area pointed to by the simulation pointer; Sub-step S5.3: Increment the counter value by 1; Step S6: Determine whether the current address of the simulation pointer has exceeded the boundary of the extended address space. If the current address of the simulation pointer does not exceed the boundary of the extended address space, return to step S5; If the current address of the simulation pointer exceeds the boundary of the extended address space, perform a bitwise AND operation to update the current address of the simulation pointer, and then return to step S5; Step S7: Read data from the extended address space, process it through the DSP simulation kernel, and generate an output data stream.

[0009] Preferably, in step S1, the input data stream is at least one of a communication signal, an audio frame, or a video frame.

[0010] Preferably, in step S1, at least one mirror region is created in unused reserved space between channels of the enhanced direct memory access (EDMA) of the digital signal processor.

[0011] Preferably, in step S1, the number of mirror regions is at least three.

[0012] Preferably, in step S1, the digital signal processor is a TMS320C6713 processor.

[0013] Preferably, in step S2, the starting address of the main region is determined by the address of the ring cache in the simulated DSP program.

[0014] Preferably, in step S3, mapping the main region and at least one mirror region to the same physical memory region on the host machine is achieved through a memory mapping interface provided by the operating system, which includes the mmap function in Unix systems or the VirtualAlloc function in Windows systems.

[0015] Preferably, in step S6, the bitwise AND operation includes the following sub-steps: Step S6.1: Obtain the current address of the simulation pointer and the starting address of the main region, and calculate the offset = current address of the simulation pointer - starting address of the main region; Step S6.2: Obtain the size A of the circular buffer and calculate the mask = A-1; Step S6.3, calculate the restored offset = offset & mask; Step S6.4: Calculate the restored address = main region start address + restored offset, and update the current address of the simulation pointer to the restored address.

[0016] Preferably, in step S7, a read pointer is used to read data from the extended address space; both the read pointer and the simulation pointer are linearly incremented in the extended address space, and the linear increment of the read pointer is the same as that of the simulation pointer; when the next linear increment of the read pointer will exceed the boundary of the extended address space, a bitwise AND operation is performed to restore the read pointer to the corresponding position in the main area.

[0017] This invention also provides a digital signal processor simulation performance optimization system based on mirrored memory, comprising: Module M1 obtains the input data stream to be simulated and the size A of the circular buffer to be simulated. Size A is an integer power of 2. The input data stream contains N data units, where N is a positive integer. Module M2 creates a main region and at least one mirror region in the virtual memory space of the digital signal processor. The size of the main region and at least one mirror region is equal to S, and the virtual addresses of the main region and at least one mirror region are contiguous. Module M3 maps the main region and at least one mirror region to the same physical memory region on the host machine; Module M4 initializes the simulation pointer, making it point to the starting address of the main region, thus allowing the simulation pointer to point to the physical memory region through mapping; it also initializes the counter, setting its value to 0. Module M5 determines whether the counter value is less than N: If the counter value is equal to N, then jump to module M7; If the counter value is less than N, then execute the following submodule: Submodule M5.1 enables the simulation pointer to increment linearly by one data unit in the extended address space consisting of the main region and at least one mirror region. Submodule M5.2 writes the (counter value + 1)th data unit in the input data stream to the physical memory area pointed to by the simulation pointer; Submodule M5.3 increments the counter value by 1; Module M6 determines whether the current address of the simulation pointer has exceeded the boundary of the extended address space: If the current address of the simulation pointer does not exceed the boundary of the extended address space, then return to module M5; If the current address of the simulation pointer exceeds the boundary of the extended address space, a bitwise AND operation is performed to update the current address of the simulation pointer, and then the process returns to module M5. Module M7 reads data from the extended address space, processes it through the DSP simulation kernel, and generates an output data stream.

[0018] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention constructs an extended virtual address space consisting of a main region and a mirror region. The simulation pointer can linearly increment throughout the extended address space to complete data stream writing and reading operations without needing to perform ring cache boundary out-of-bounds checks for each data read / write operation. It eliminates the high-frequency conditional branch instructions, pointer wrap-around modulo operations, and subtraction operations in traditional simulation logic, significantly reducing the invalid cycle occupation of the host processor and effectively improving the throughput of the DSP simulation kernel. It is especially suitable for simulation scenarios with large data volumes and high frequencies, and the performance optimization effect is significant.

[0019] 2. This invention eliminates the need to write high-frequency boundary checks and pointer wrap-around processing code, greatly simplifying the program code of the ring cache simulation module, simplifying core business logic, reducing code complexity, reducing the probability of program errors from the development level, and improving the stability and maintainability of the simulation program.

[0020] 3. This invention restores the pointer address by performing a single bitwise AND operation only in critical scenarios where the simulated pointer exceeds the boundary of the extended address space. Compared to the pointer reset method in traditional technologies that involves multiple condition judgments and multi-step subtraction / modulo operations, the bitwise AND operation is a low-level, efficient, single-cycle operation with fewer operation steps and shorter processing time. It avoids computational redundancy in critical scenarios, further ensuring the efficient and stable operation of the overall simulation process and achieving comprehensive optimization of simulation performance. Attached Figure Description

[0021] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the ring cache address space view of the DSP and the physical memory layout of the host machine in an embodiment of the present invention. Detailed Implementation

[0022] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0023] This invention provides a method and system for optimizing the simulation performance of a digital signal processor (DSP) based on mirrored memory. The method includes pre-acquiring the input data stream to be simulated and a circular buffer of size A, which is a power of 2. In the DSP's virtual memory space, a main region and at least one mirror region of equal size and contiguous virtual addresses are created, and all main and mirror regions are mapped to the same physical memory region of the host machine. During simulation, a simulation pointer and counter are initialized, causing the simulation pointer to linearly increment according to the data unit length within the extended address space formed by the main and mirror regions, completing the unit-by-unit writing of the data stream. Only when the simulation pointer exceeds the boundary of the extended address space is the pointer address restored through a bitwise AND operation. Finally, the data in the extended address space is read and processed by the DSP simulation kernel to obtain the output data stream. This invention eliminates the frequent conditional branch judgments and arithmetic operations of traditional circular buffer simulation, effectively reducing simulation computation overhead, simplifying the circular buffer processing logic, and significantly improving the performance and stability of DSP simulation.

[0024] Example 1: This embodiment provides a method for optimizing the simulation performance of a digital signal processor based on mirrored memory. By constructing mirrored memory, the simulation pointer moves linearly within an extended virtual address space, thereby eliminating out-of-bounds checks and pointer wrap-around calculations in each read / write operation of the circular cache. Specifically, the operating system's memory mapping mechanism is used to map multiple different virtual address segments to the same physical memory block, forming a "many-to-one" alias mapping. This mapping relationship ensures that access to any mirrored region is redirected to the same physical memory location, thus automatically achieving the circular effect.

[0025] Specifically, the method for optimizing the simulation performance of a digital signal processor based on mirrored memory includes the following steps: Step S1: Obtain the input data stream to be simulated and the size A of the circular buffer to be simulated. Size A is an integer power of 2. The input data stream contains N data units, where N is a positive integer.

[0026] Specifically, in step S1, the input data stream is at least one of a communication signal, an audio frame, or a video frame.

[0027] In this embodiment, at least one mirror region is created in the unused reserved space between the channels of the enhanced direct memory access (EDMA) of the digital signal processor. The number of mirror regions is at least three, more preferably at least seven. The digital signal processor is a TMS320C6713 processor.

[0028] Step S2: In the virtual memory space of the digital signal processor, create a main region and at least one mirror region. The size of the main region and at least one mirror region is equal to S, and the virtual addresses of the main region and at least one mirror region are contiguous.

[0029] Figure 1 This is a schematic diagram of the ring cache address space view of the DSP and the physical memory layout of the host machine in an embodiment of the present invention.

[0030] like Figure 1 As shown, the DSP kernel ring cache distribution includes a main region with contiguous addresses and multiple mirror regions (mirror region 0, mirror region 1, ..., mirror region n). The main region and mirror regions are all mapped to the same host physical memory.

[0031] Specifically, the starting address of the main region is determined by the address of the ring cache.

[0032] Further, step S2 includes the following sub-steps: Step S2.1, obtain the size A of the circular buffer (or... ); Step S2.2: Determine the starting virtual address of the primary region. ; Step S2.3: Determine the number M of mirror regions, M≥1; Step S2.4, from the starting virtual address of the main region Initially, M+1 virtual memory segments of size A and with contiguous addresses are allocated sequentially. The first virtual memory segment is used as the main region, and the second to M+1 virtual memory segments are used as at least one mirror region.

[0033] Step S3: Map the main region and at least one mirror region to the same physical memory region on the host machine.

[0034] Specifically, step S3 includes the following sub-steps: Step S3.1: Allocate a contiguous physical memory block of size A on the host machine; Step S3.2: Map the entire virtual address range of the main region to contiguous physical memory through the memory mapping interface provided by the operating system. The memory mapping interface includes the mmap function in Unix systems or the VirtualAlloc function in Windows systems. Step S3.3: Through the operating system memory mapping interface, map the entire virtual address range of each of at least one mirror region to contiguous physical memory.

[0035] Step S4: Initialize the simulation pointer so that it points to the starting address of the main region, thereby making the simulation pointer point to the physical memory region through mapping; initialize the counter and set the value of the counter to 0. Step S5: Determine if the counter value is less than N: If the counter value is equal to N, then proceed to step S7; If the counter value is less than N, then execute the following sub-steps: Sub-step S5.1 causes the simulation pointer to increment linearly by the length of a data unit within the extended address space consisting of the main region and at least one mirror region.

[0036] Specifically, obtain the current address of the simulation pointer. Based on the length of a data unit Calculate the new address = + ,use As the address of the incremented simulation pointer.

[0037] Sub-step S5.2: Write the (counter value + 1)th data unit in the input data stream to the physical memory area pointed to by the simulation pointer; Sub-step S5.3: Increment the counter value by 1; Step S6: Determine whether the current address of the simulation pointer has exceeded the boundary of the extended address space. If the current address of the simulation pointer does not exceed the boundary of the extended address space, return to step S5; If the current address of the simulation pointer exceeds the boundary of the extended address space, a bitwise AND operation is performed to update the current address of the simulation pointer, and then the process returns to step S5.

[0038] Specifically, in step S6, the bitwise AND operation includes the following sub-steps: Step S6.1: Obtain the current address of the simulation pointer and the starting address of the main region, and calculate the offset = current address of the simulation pointer - starting address of the main region; Step S6.2: Obtain the size A of the circular buffer and calculate the mask = A-1; Step S6.3, calculate the restored offset = offset & mask; Step S6.4: Calculate the restored address = the starting address of the main region + the restored offset, and update the current address of the simulation pointer to the restored address.

[0039] Step S7: Read data from the extended address space, process it through the DSP simulation kernel, and generate an output data stream.

[0040] Specifically, a read pointer is used to read data from the extended address space; both the read pointer and the simulation pointer are linearly incremented within the extended address space, and the linear increment of the read pointer is the same as that of the simulation pointer; when the next linear increment of the read pointer will exceed the boundary of the extended address space, a bitwise AND operation is performed to restore the read pointer to the corresponding position in the main area.

[0041] Example 2: This embodiment uses a specific set of parameters as an example to illustrate the implementation process of the method in Embodiment 1.

[0042] In this embodiment, the size of the ring buffer to be simulated is A = 4096 bytes (i.e., 4KB, represented in hexadecimal as 0x1000), where A is an integer power of 2. The input data stream contains N data units, each with a length of 1 byte. For simplicity, this embodiment focuses on describing the memory layout and pointer operation process. The specific writing of the input data stream and the generation of the output data stream are the same as in Embodiment 1, and will not be repeated here.

[0043] Specifically, this embodiment includes the following steps: Step S2: In the simulated digital signal processor virtual memory space, create a main region and three mirror regions, for a total of four virtual memory segments.

[0044] Specifically, the size of the circular cache is obtained as A=4096, and the starting virtual address of the main region is determined. (recorded as) ), determine the number of mirror regions M=3. From Initially, allocate M+1=4 virtual memory segments, each of size A and with contiguous addresses, in sequence, where: The first virtual memory segment is designated as the main region, and its virtual address range is [ , +A-1], that is [ , +4096-1]; The second to fourth virtual memory segments are mirrored regions, where: The virtual address range of the first mirror region is [ + , +2× -1], that is, [ +4096, +8192-1]; The virtual address range of the second mirror region is [ +2×A, +3A-1], that is [ +8192, +12288-1]; The virtual address range of the third mirror region is [mainstart+3A, mainstart+4A-1], which is [Vstart+12288, Vstart+16383].

[0045] The above four virtual memory segments together constitute an extended address space with a total size of (M+1)×A=16384 bytes (16KB) and contiguous addresses.

[0046] Step S3: Allocate a contiguous block of physical memory of size A = 4096 bytes on the host machine, denoted as... Through the operating system's memory mapping interface (e.g., in Unix-like systems using...). (System call), mapping the entire virtual address range of the main region and the three mirror regions to The specific implementation of this mapping relationship is the same as that in Example 1, and will not be repeated here.

[0047] Steps S5 and S6: Set the simulation pointer The initial address pointing to the main region When writing data, Incrementing linearly according to the data unit length. When When entering the mirror region from the primary region, write operations automatically access the mirror region due to the aforementioned mapping relationship. The corresponding positions in the diagram are used to achieve ring-shaped coverage. The linear increasing process and boundary judgment are the same as in Example 1, and will not be repeated here.

[0048] when When the next linear increment exceeds the boundary of the extended address space (i.e., the last mirror region), the bitwise AND operation is restored. The specific calculation process of the bitwise AND operation is the same as steps S6.1 to S6.4 in Embodiment 1, and will not be repeated here. In this embodiment, the mask... = A-1 = 4095 (hexadecimal 0x0FFF).

[0049] In this embodiment, during the continuous writing of a 16KB data stream, the simulator does not need to perform any boundary checks for single accesses, greatly reducing conditional branches and significantly improving simulation performance. Furthermore, this embodiment creates three mirror regions, supporting application scenarios that require at least three mirror regions.

[0050] Example 3: This embodiment is a variation of Embodiment 2. The only difference between this embodiment and Embodiment 2 is the number of mirrored regions.

[0051] In this embodiment, the size of the ring cache to be simulated is A = 4096 bytes (i.e., 4KB), where A is an integer power of 2.

[0052] Step S2: In the simulated digital signal processor virtual memory space, create a main region and seven mirror regions, for a total of eight consecutive 4KB virtual memory segments.

[0053] Specifically, the size of the circular cache is obtained as A=4096, and the starting virtual address of the main region is determined. (recorded as) ), determine the number of mirror regions M=7. From Initially, allocate M+1=8 virtual memory segments of size A with contiguous addresses. The first virtual memory segment is used as the main region, and the second to eighth virtual memory segments are used as mirror regions.

[0054] The above 8 virtual memory segments together constitute an extended address space with a total size of (M+1)×A=32768 bytes (32KB) and contiguous addresses.

[0055] Step S3: Allocate a contiguous block of physical memory of size A = 4096 bytes on the host machine, denoted as... Through the operating system's memory mapping interface, the entire virtual address range of the main region and each of the seven mirror regions is mapped to... The mapping process is the same as in Example 2, and will not be repeated here.

[0056] Steps S5 and S6: The linear incrementing of the simulation pointer, boundary judgment, and bitwise AND recovery operations are the same as in Example 2, and will not be repeated here. The mask in this example... = A-1 = 4095 (hexadecimal 0x0FFF), the same as in Example 2.

[0057] The difference between this embodiment and Embodiment 2 is that in Embodiment 2, the number of mirror regions M=3, and the total extended space is 16KB; in this embodiment, the number of mirror regions M=7, and the total extended space is 32KB. Due to the increased extended space, the triggering frequency of the pointer recovery operation is reduced, and the execution interval of the recovery operation changes from once every 16KB to once every 32KB.

[0058] Compared to Example 2, this example reduces the frequency of pointer recovery operations by half. This means that the minimal overhead of pointer recovery operations during simulation is also halved. For simulations of specific digital signal processor applications (such as radar signal processing and high-speed communication) that require processing extremely long data packets or uninterrupted data streams, this optimization results in a smoother and more efficient simulation experience. This example fully demonstrates the good scalability of the proposed method, allowing for further fine-tuning and optimization of performance by adjusting the number of mirror regions based on the characteristics of the specific simulation task and system resources. Furthermore, this example provides explicit support for application scenarios requiring at least seven mirror regions.

[0059] Example 4: The present invention also provides a digital signal processor simulation performance optimization system based on mirrored memory. The digital signal processor simulation performance optimization system based on mirrored memory can be implemented by executing the process steps of the digital signal processor simulation performance optimization method based on mirrored memory. That is, those skilled in the art can understand the digital signal processor simulation performance optimization method based on mirrored memory as a preferred implementation of the digital signal processor simulation performance optimization system based on mirrored memory.

[0060] Specifically, the digital signal processor simulation performance optimization system based on mirrored memory includes: Module M1 obtains the input data stream to be simulated and the size A of the circular buffer to be simulated. Size A is an integer power of 2. The input data stream contains N data units, where N is a positive integer.

[0061] Module M2 creates a main region and at least one mirror region in the virtual memory space of the digital signal processor. The size of the main region and at least one mirror region is equal to S, and the virtual addresses of the main region and at least one mirror region are contiguous.

[0062] Furthermore, module M2 includes the following sub-modules: Module M2.1 retrieves the size A of the circular buffer (or... ); Module M2.2 determines the starting virtual address of the primary region. ; Module M2.3 determines the number M of mirror regions, where M≥1; Module M2.4, starting from the primary region's virtual address Initially, M+1 virtual memory segments of size A and with contiguous addresses are allocated sequentially. The first virtual memory segment is used as the main region, and the second to M+1 virtual memory segments are used as at least one mirror region.

[0063] Module M3 maps the main region and at least one mirror region to the same physical memory region on the host machine.

[0064] Specifically, module M3 includes the following sub-modules: Module M3.1 allocates a contiguous block of physical memory of size A on the host machine; Module M3.2 maps the entire virtual address range of the main region to contiguous physical memory through the memory mapping interface provided by the operating system. The memory mapping interface includes the mmap function in Unix systems or the VirtualAlloc function in Windows systems. Module M3.3 maps the entire virtual address range of at least one mirror region to contiguous physical memory through the operating system memory mapping interface.

[0065] Module M4 initializes the simulation pointer, making it point to the starting address of the main region, thus allowing the simulation pointer to point to the physical memory region through mapping; it also initializes the counter, setting its value to 0. Module M5 determines whether the counter value is less than N: If the counter value is equal to N, then jump to module M7; If the counter value is less than N, then execute the following submodule: Submodule M5.1 enables the simulation pointer to increment linearly by one data unit in the extended address space consisting of the main region and at least one mirror region. Submodule M5.2 writes the (counter value + 1)th data unit in the input data stream to the physical memory area pointed to by the simulation pointer; Submodule M5.3 increments the counter value by 1; Module M6 determines whether the current address of the simulation pointer has exceeded the boundary of the extended address space: If the current address of the simulation pointer does not exceed the boundary of the extended address space, then return to module M5; If the current address of the simulation pointer exceeds the boundary of the extended address space, a bitwise AND operation is performed to update the current address of the simulation pointer, and then the process returns to module M5.

[0066] Specifically, in module M6, the bitwise AND operation includes the following sub-modules: Module M6.1 obtains the current address of the simulation pointer and the starting address of the main region, and calculates the offset = current address of the simulation pointer - starting address of the main region; Module M6.2, obtain the size A of the circular buffer, and calculate the mask = A-1; Module M6.3 calculates the restored offset as offset & mask; Module M6.4 calculates the restored address as the starting address of the main region plus the restored offset, and updates the current address of the simulation pointer to the restored address.

[0067] Module M7 reads data from the extended address space, processes it through the DSP simulation kernel, and generates an output data stream.

[0068] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0069] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features of the present invention can be arbitrarily combined with each other.

Claims

1. A method for optimizing the performance of a digital signal processor simulation based on mirror memory, comprising: Includes the following steps: Step S1: Obtain the input data stream to be simulated and the size A of the circular buffer to be simulated. The size A is an integer power of 2. The input data stream contains N data units, where N is a positive integer. Step S2: In the virtual memory space of the digital signal processor, create a main region and at least one mirror region, the size of the main region and the at least one mirror region are both equal to S, and the virtual addresses of the main region and the at least one mirror region are contiguous. Step S3: Map the main region and the at least one mirror region to the same physical memory region on the host machine; Step S4: Initialize the simulation pointer so that it points to the starting address of the main region, thereby making the simulation pointer point to the physical memory region through the mapping; Initialize the counter by setting its value to 0; Step S5: Determine whether the value of the counter is less than N: If the value of the counter is equal to N, then proceed to step S7; If the value of the counter is less than N, then the following sub-steps are executed: Sub-step S5.1, causing the simulation pointer to linearly increment by the length of a data unit within the extended address space consisting of the main region and the at least one mirror region; Sub-step S5.2: Write the (counter value + 1)th data unit in the input data stream into the physical memory area pointed to by the simulation pointer; Sub-step S5.3: Increment the value of the counter by 1; Step S6: Determine whether the current address of the simulation pointer has exceeded the boundary of the extended address space. If the current address of the simulation pointer does not exceed the boundary of the extended address space, then return to step S5; If the current address of the simulation pointer exceeds the boundary of the extended address space, a bitwise AND operation is performed to update the current address of the simulation pointer, and then the process returns to step S5. Step S7: Read data from the extended address space, process it through the DSP simulation kernel, and generate an output data stream.

2. The method of claim 1, wherein, In step S1, the input data stream is at least one of a communication signal, an audio frame, or a video frame.

3. The method of claim 1, wherein, In step S1, the at least one mirror region is created in the unused reserved space between the channels of the enhanced direct memory access (EDMA) of the digital signal processor.

4. The method for optimizing the simulation performance of a digital signal processor based on mirrored memory according to claim 1, characterized in that, In step S1, the number of mirror regions is at least three.

5. The method for optimizing the simulation performance of a digital signal processor based on mirrored memory according to claim 1, characterized in that, In step S1, the digital signal processor is a TMS320C6713 processor.

6. The method for optimizing the simulation performance of a digital signal processor based on mirrored memory according to claim 1, characterized in that, In step S2, the starting address of the main region is determined by the address of the ring cache in the simulated DSP program.

7. The method for optimizing the simulation performance of a digital signal processor based on mirrored memory according to claim 1, characterized in that, In step S3, mapping the main region and the at least one mirror region to the same physical memory region on the host machine is achieved through a memory mapping interface provided by the operating system. The memory mapping interface includes the mmap function in Unix systems or the VirtualAlloc function in Windows systems.

8. The method for optimizing the simulation performance of a digital signal processor based on mirrored memory according to claim 1, characterized in that, In step S6, the bitwise AND operation includes the following sub-steps: Step S6.1: Obtain the current address of the simulation pointer and the starting address of the main region, and calculate the offset = current address of the simulation pointer - starting address of the main region; Step S6.2: Obtain the size A of the circular buffer and calculate the mask = A-1; Step S6.3, calculate the restored offset = offset & mask; Step S6.4: Calculate the restored address = main region start address + restored offset, and update the current address of the simulation pointer to the restored address.

9. The method for optimizing the simulation performance of a digital signal processor based on mirrored memory according to claim 1, characterized in that, In step S7, a read pointer is used to read data from the extended address space; both the read pointer and the simulation pointer are linearly incremented within the extended address space, and the linear increment of the read pointer is the same as that of the simulation pointer; when the next linear increment of the read pointer will exceed the boundary of the extended address space, a bitwise AND operation is performed to restore the read pointer to the corresponding position in the main area.

10. A digital signal processor simulation performance optimization system based on mirrored memory, employing the digital signal processor simulation performance optimization method based on mirrored memory as described in any one of claims 1-9, characterized in that, include: Module M1 acquires the input data stream to be simulated and the size A of the circular buffer to be simulated, where the size A is an integer power of 2, and the input data stream contains N data units, where N is a positive integer. Module M2 creates a main region and at least one mirror region in the virtual memory space of the digital signal processor. The size of the main region and the at least one mirror region is equal to S, and the virtual addresses of the main region and the at least one mirror region are contiguous. Module M3 maps the main region and the at least one mirror region to the same physical memory region on the host machine; Module M4 initializes the simulation pointer, making the simulation pointer point to the starting address of the main region, so that the simulation pointer points to the physical memory region through the mapping; Initialize the counter by setting its value to 0; Module M5 determines whether the value of the counter is less than N: If the value of the counter is equal to N, then jump to module M7; If the value of the counter is less than N, then the following submodule is executed: Submodule M5.1 causes the simulation pointer to increment linearly by a data unit in the extended address space consisting of the main region and the at least one mirror region. Submodule M5.2 writes the (counter value + 1)th data unit in the input data stream into the physical memory area pointed to by the simulation pointer; Submodule M5.3 increments the value of the counter by 1; Module M6 determines whether the current address of the simulation pointer has exceeded the boundary of the extended address space: If the current address of the simulation pointer does not exceed the boundary of the extended address space, then return to module M5; If the current address of the simulation pointer exceeds the boundary of the extended address space, a bitwise AND operation is performed to update the current address of the simulation pointer, and then the process returns to module M5. Module M7 reads data from the extended address space, processes it through the DSP simulation kernel, and generates an output data stream.

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