A SoC chip prototype verification system and method
By connecting the FPGA verification platform with the processor development board, the dependence on the core processor IP in SoC chip verification is solved, enabling early independent verification of peripheral interface IP, reducing design risks, and improving verification efficiency and success rate.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TIANJIN JINHANG COMP TECH RES INST
- Filing Date
- 2025-12-28
- Publication Date
- 2026-07-31
AI Technical Summary
Traditional SoC chip prototype verification platforms are highly dependent on core processor IP, which makes it impossible to verify peripheral interface IP independently, affecting verification efficiency and parallelism.
An FPGA verification platform is used to connect to a development board of the same model processor. The physical connection is achieved through a high-speed connector. The peripheral interface IP is mapped to the external devices of the processor development board using a bus conversion module and an on-chip bus matrix, so as to achieve independent verification.
It enables early and independent verification of peripheral interface IPs even when the core processor IP is not yet complete, reducing design risks and improving verification efficiency and success rate.
Smart Images
Figure CN122491174A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to prototype verification technology for SoC chips, specifically a prototype verification system and method for SoC chips, which is mainly used to reduce the dependence on the processor during the prototype verification process in the front-end design of SoC chips. Background Technology
[0002] In the design process of SoC chips, multiple verification methods must be combined to maximize the coverage of chip verification. Among them, FPGA-based prototyping verification plays a crucial role in the functional verification of chip designs. Pure software and dynamic simulation techniques, as well as formal verification techniques, have inherent limitations. This means that some chip design errors will not be detected by dynamic functional simulation, because the simulation speed cannot compare to the actual operating speed of the chip. An FPGA system, however, can operate at speeds similar to a real chip system, thus potentially uncovering chip design errors that pure simulation cannot detect.
[0003] Compared to traditional chip design, SoC chip design involves a larger design scale. Furthermore, while traditional chip design often only includes the hardware circuit design, SoC chip design encompasses not only hardware circuit design but also a significant portion of software design. Therefore, the design and verification of the SoC system's accompanying software must be performed simultaneously during the design process, necessitating hardware-software co-verification. Hardware-software co-verification is a crucial step in the SoC verification process; only by successfully completing the hardware-software co-verification can the software designed for the SoC be guaranteed to function correctly on the SoC hardware platform.
[0004] Traditional verification platforms such as Figure 1 As shown, the core processor IP is the core of the entire verification platform; without this IP, chip verification cannot be effectively carried out. Summary of the Invention
[0005] (I) Purpose of the Invention
[0006] The purpose of this invention is to provide a SoC chip prototype verification system and method to solve the problem of the high dependence of traditional SoC chip prototype verification platforms on core processor IP, so as to enable the verification of peripheral interface IP independently and efficiently when the core processor IP is not yet completed or unavailable.
[0007] (II) Technical Solution
[0008] To address the aforementioned technical issues, this invention provides a SoC chip prototype verification system, comprising an FPGA verification platform and a processor development board. The processor development board and the FPGA verification platform are physically connected via a high-speed connector. The FPGA verification platform integrates a bus conversion module, an on-chip bus matrix, and peripheral interface IPs. The bus conversion module receives bus signals from the processor development board, converts the signal format, and transmits them to the on-chip bus matrix. The on-chip bus matrix acts as an internal "highway network," efficiently routing access requests to the peripheral interface IPs. The peripheral interface IPs are connected to the peripheral verification board via connectors.
[0009] Furthermore, the processor development board and the FPGA verification platform share the same core processor IP.
[0010] Furthermore, the processor development board and the FPGA verification platform are physically connected via an FMC electrical connector, and the processor development board sends access requests to the FPGA verification platform via its internal parallel bus or high-speed serial bus.
[0011] Furthermore, the peripheral interface IP to be verified loaded on the FPGA verification platform is functionally mapped to the external device of the processor development board. The driver, firmware or test program on the processor development board interacts directly with the peripheral interface IP through the standard bus access mechanism.
[0012] This invention also provides a method for SoC chip prototype verification, which includes the following steps:
[0013] Step 1: System architecture design and hardware selection;
[0014] Step 2: FPGA internal logic module design and implementation;
[0015] Step 3: Hardware Connection and System Setup;
[0016] Step 4: Verify the execution of the test process;
[0017] Step 5: System optimization and iterative verification;
[0018] Step Six: Verify the output results and solidify the process.
[0019] Furthermore, in step one, a processor development board and an FPGA verification platform FPGA development board are selected, and a standard FMC connector is used as the physical interface between the processor development board and the FPGA verification platform. An FMC adapter board is designed to realize the signal interface between the parallel bus or high-speed serial interface of the processor development board and the FPGA verification platform.
[0020] Furthermore, in step two, the following functional modules are constructed within the FPGA:
[0021] Bus interface module: Used to receive bus request signals from the processor development board, supporting AXI4, AHB or APB protocols;
[0022] Protocol conversion module: Converts external bus protocols into on-chip bus protocols used uniformly within the FPGA, enabling address mapping, data width adaptation, and timing alignment.
[0023] On-chip bus matrix module: It adopts the AXIInterconnect IP core to build a multi-master and multi-slave bus structure, supporting the parallel access of multiple peripheral IPs;
[0024] Peripheral Interface IP Module: Connects the IP core to be verified as a slave device to the on-chip bus matrix and allocates a unique address space;
[0025] Debugging and monitoring module: integrates an ILA core for real-time capture of key signals to assist in fault location.
[0026] Furthermore, in step three, the FPGA development board is physically connected to the processor development board via the FMC adapter board; the FPGA configuration file is downloaded, and the bus conversion logic and peripheral IPs are loaded; the processor development board is started, and the embedded operating system or bare-metal program is run; the device tree on the processor side is configured, and the peripheral IPs on the FPGA verification platform are mapped to system device nodes.
[0027] Furthermore, in step four, a test program is written on the processor side to perform read and write operations on the peripheral interface IP of the FPGA verification platform through standard system calls or register access methods; interrupt requests are simulated to verify the interrupt response mechanism; internal signals of the FPGA are captured using a logic analyzer to confirm the correctness of the bus conversion logic; test results are recorded and a test report is generated.
[0028] Furthermore, in step five, based on test feedback, the timing constraints and resource consumption of the bus conversion module are optimized; the address mapping strategy is adjusted to avoid address conflicts; DMA support is added to improve the efficiency of large data transmission; multiple rounds of iterative verification are supported until all target peripheral IPs pass functional and performance verification; in step six, a verification report is output, including test cases, test results, defect records and repair status; verified IP cores are marked as "integrable" and submitted to the IP library; and documentation is written to form a standardized process.
[0029] (III) Beneficial Effects
[0030] The SoC chip prototype verification system and method provided by the above technical solution utilizes a development board of the same model processor and connects to an FPGA verification platform via a high-speed bus. The IP core loaded on the FPGA can be accessed and verified as an external device of the processor development board, enabling the early verification of peripheral IP without relying on the core processor. Attached Figure Description
[0031] Figure 1 This is a schematic diagram of the SoC chip prototype verification system according to an embodiment of the present invention. Detailed Implementation
[0032] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0033] like Figure 1 As shown, the SoC chip prototype verification system in this embodiment includes an FPGA verification platform and a processor development board. The processor development board and the FPGA verification platform are physically connected through a high-speed connector. The FPGA verification platform integrates a bus conversion module, an on-chip bus matrix, and peripheral interface IP. The bus conversion module receives bus signals from the processor development board, converts the signal format, and transmits them to the on-chip bus matrix. The on-chip bus matrix acts as an internal "highway network," efficiently routing access requests to the peripheral interface IP. The peripheral interface IP is connected to the peripheral verification board through a connector.
[0034] The SoC chip prototype verification system in this embodiment has the following characteristics:
[0035] Architecture Restructuring and Dependency Decoupling: This invention overturns the traditional verification platform's architecture centered on core processor IP (e.g., Figure 1 (As shown). In traditional methods, the verification of peripheral interface IPs depends on the existence and normal operation of the core processor IP, which limits the parallelism and efficiency of the verification work. This invention proposes a novel connection method that uses a processor development board of the same model (rather than the core processor IP) as the "brain" or "master control" of the verification system.
[0036] High-speed interconnect mechanism: A physical connection channel is established between the processor development board and the FPGA verification platform using high-speed connectors (such as the common FMC electrical connector). The processor development board sends access requests to the FPGA platform via its internal bus (such as a parallel bus or a high-speed serial bus).
[0037] Bus Protocol Conversion and Routing: The FPGA verification platform integrates a crucial bus conversion module. This module is responsible for receiving bus signals (whether parallel or high-speed serial) from the processor development board and converting them into signal formats compatible with the on-chip bus matrix (such as the common AXI, AHB, etc.) used internally by the FPGA. The on-chip bus matrix acts as an internal "highway network," efficiently routing access requests to the target peripheral interface IP (such as IP_1, IP_2, ..., IP_N).
[0038] Achieving Verification Goals: Through this architecture, the peripheral interface IPs (such as UART, SPI, I2C, USB controllers, etc.) loaded on the FPGA verification platform are functionally mapped to external devices on the processor development board. The software (drivers, firmware, or test programs) on the processor development board can directly interact with these peripheral interface IPs through standard bus access mechanisms (read / write registers, DMA, etc.), as if they were real peripherals connected to the processor development board. This enables:
[0039] Independent verification: The verification of peripheral interface IP no longer needs to wait for the core processor IP to be designed or integrated into the FPGA platform.
[0040] Early verification: In the early stages of SoC chip design, readily available processor development boards can be used to perform functional verification, performance testing, and driver development for critical peripheral interface IPs.
[0041] Reduce risks: Identify and fix design flaws in peripheral interface IPs in advance, reduce problems during later integration, and improve the success rate of the overall design.
[0042] Resource optimization: The design resources of the core processor IP can be focused on improving its own functions, while the verification of peripheral IPs can be carried out in parallel.
[0043] Based on the SoC chip prototype verification system, the SoC chip prototype verification method in this embodiment includes the following steps:
[0044] Step 1: System Architecture Design and Hardware Selection
[0045] Select a commercial processor development board (such as the Xilinx Zynq-7000 series development board), which has rich peripheral interfaces and high-performance processing capabilities, as the main control terminal of the verification system;
[0046] Select a high-performance FPGA development board (such as the Xilinx Kintex-7 series) to implement the peripheral interface IP and bus conversion logic to be verified;
[0047] The standard FMC (FPGA Mezzanine Card) connector is used as the physical interface between the processor development board and the FPGA verification platform, supporting data transmission rates of up to 10Gbps and above.
[0048] Design an FMC adapter board to enable signal interface between the processor development board's parallel bus (such as AXI4-Lite) or high-speed serial interface (such as PCIe, Ethernet) and the FPGA platform.
[0049] Step 2: FPGA Internal Logic Module Design and Implementation
[0050] The following functional modules are built inside the FPGA:
[0051] Bus interface module: Used to receive bus request signals from the processor development board, supporting AXI4, AHB or APB protocols;
[0052] Protocol conversion module: Converts external bus protocols into on-chip bus protocols (such as AXI4-Full) used uniformly within the FPGA, and implements functions such as address mapping, data width adaptation, and timing alignment;
[0053] On-chip bus matrix module: It adopts the AXI Interconnect IP core to build a multi-master and multi-slave bus structure, supporting the parallel access of multiple peripheral IPs;
[0054] Peripheral interface IP module: Connects the IP core to be verified (such as UART, SPI, I2C, USB 2.0 controller) as a slave device to the on-chip bus matrix and allocates a unique address space;
[0055] Debugging and monitoring module: integrates the ILA (Integrated Logic Analyzer) core for real-time capture of key signals to assist in fault location.
[0056] Step 3: Hardware Connection and System Setup
[0057] The FPGA development board is physically connected to the processor development board via the FMC adapter board;
[0058] Download the FPGA configuration file (.bit stream file), and load the bus conversion logic and peripheral IP;
[0059] Start the processor development board and run an embedded operating system (such as Linux) or a bare-metal program;
[0060] Configure the device tree on the processor side to map peripheral IPs on the FPGA platform to system device nodes.
[0061] Step 4: Verify the execution of the test process
[0062] Write test programs on the processor side to perform read and write operations on the peripheral IP on the FPGA through standard system calls or register access methods;
[0063] For example: write data to the UART IP, receive and verify the output through a serial port assistant;
[0064] Send a configuration command to the SPI controller and read back the status register to confirm successful configuration;
[0065] Simulate an interrupt request to verify the interrupt response mechanism.
[0066] Use a logic analyzer to capture internal FPGA signals and verify the correctness of the bus conversion logic.
[0067] Record test results and generate test reports, including metrics such as functional coverage, timing performance, and error handling capabilities.
[0068] Step 5: System Optimization and Iterative Verification
[0069] Based on test feedback, the timing constraints and resource usage of the bus conversion module were optimized.
[0070] Adjust the address mapping strategy to avoid address conflicts;
[0071] Add DMA support to improve the efficiency of large data transfer.
[0072] It supports multiple rounds of iterative verification until all target peripheral IPs have passed functional and performance verification.
[0073] Step Six: Verify Results Output and Solidify Process
[0074] Output a verification report, including test cases, test results, defect records, and repair status;
[0075] Mark the verified IP cores as "integrable" and submit them to the IP library;
[0076] Compile documents such as "Prototype Verification Operation Specifications" and "Test Case Templates" to form a standardized process;
[0077] This verification system can be reused in subsequent SoC projects, significantly shortening the overall verification cycle.
[0078] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A SoC chip prototyping verification system, characterized in that, It includes an FPGA verification platform and a processor development board, which are physically connected via a high-speed connector. The FPGA verification platform integrates a bus conversion module, an on-chip bus matrix, and peripheral interface IPs. The bus conversion module receives bus signals from the processor development board, converts the signal format, and transmits them to the on-chip bus matrix. The on-chip bus matrix acts as an internal "highway network," efficiently routing access requests to the peripheral interface IPs. The peripheral interface IPs are connected to the peripheral verification board via connectors.
2. The SoC chip prototype verification system of claim 1, wherein, The processor development board and the FPGA verification platform share the same core processor IP.
3. The SoC chip prototype verification system as described in claim 2, characterized in that, The processor development board and the FPGA verification platform are physically connected via an FMC electrical connector. The processor development board sends access requests to the FPGA verification platform via its internal parallel bus or high-speed serial bus.
4. The SoC chip prototype verification system as described in claim 3, characterized in that, The peripheral interface IP to be verified loaded on the FPGA verification platform is functionally mapped to the external device of the processor development board. The driver, firmware or test program on the processor development board interacts directly with the peripheral interface IP through the standard bus access mechanism.
5. A method for SoC chip prototype verification based on the SoC chip prototype verification system of claim 4, characterized in that, Includes the following steps: Step 1: System architecture design and hardware selection; Step 2: FPGA internal logic module design and implementation; Step 3: Hardware Connection and System Setup; Step 4: Verify the execution of the test process; Step 5: System optimization and iterative verification; Step Six: Verify the output results and solidify the process.
6. The SoC chip prototype verification system as described in claim 5, characterized in that, In step one, a processor development board and an FPGA verification platform are selected. A standard FMC connector is used as the physical interface between the processor development board and the FPGA verification platform. An FMC adapter board is designed to realize the signal interface between the parallel bus or high-speed serial interface of the processor development board and the FPGA verification platform.
7. The SoC chip prototype verification system as described in claim 6, characterized in that, In step two, the following functional modules are built inside the FPGA: Bus interface module: Used to receive bus request signals from the processor development board, supporting AXI4, AHB or APB protocols; Protocol conversion module: Converts external bus protocols into on-chip bus protocols used uniformly within the FPGA, enabling address mapping, data width adaptation, and timing alignment. On-chip bus matrix module: It adopts the AXIInterconnect IP core to build a multi-master and multi-slave bus structure, supporting the parallel access of multiple peripheral IPs; Peripheral Interface IP Module: Connects the IP core to be verified as a slave device to the on-chip bus matrix and allocates a unique address space; Debugging and monitoring module: integrates an ILA core for real-time capture of key signals to assist in fault location.
8. The SoC chip prototype verification system as described in claim 7, characterized in that, In step three, the FPGA development board is physically connected to the processor development board via the FMC adapter board; the FPGA configuration file is downloaded, and the bus conversion logic and peripheral IPs are loaded; the processor development board is started, and the embedded operating system or bare-metal program is run; the device tree on the processor side is configured, and the peripheral IPs on the FPGA verification platform are mapped to system device nodes.
9. The SoC chip prototype verification system as described in claim 8, characterized in that, In step four, a test program is written on the processor side to perform read and write operations on the peripheral interface IP of the FPGA verification platform through standard system calls or register access methods. Simulate interrupt requests to verify the interrupt response mechanism; use a logic analyzer to capture internal FPGA signals to confirm the correctness of the bus conversion logic. Record test results and generate test reports.
10. The SoC chip prototype verification system as described in claim 9, characterized in that, In step five, based on test feedback, the timing constraints and resource usage of the bus conversion module are optimized; Adjust the address mapping strategy to avoid address conflicts; add DMA support to improve the efficiency of large data transfer. Supports multiple rounds of iterative verification until all target peripheral IPs have passed functional and performance verification; In step six, output a verification report, which includes test cases, test results, defect records and repair status; mark the verified IP cores as "integrable" and submit them to the IP library; write documentation to form a standardized process.