A method and system for performance optimization of an integrated circuit in a PCBA

Abstract

This invention relates to the field of circuit optimization technology, and discloses a method and system for performance optimization of integrated circuits in PCBAs. The method includes: extracting the opcode of the instruction to be executed during a bus idle period, and simultaneously injecting probe pulses into the actual working trace and the reference dummy trace; acquiring two reflected signals and performing differential subtraction to eliminate common-mode interference; performing quadrature demodulation on the differential reflected signals, and calculating the amplitude attenuation and phase shift of the current trace based on the in-phase and quadrature components; mapping the opcode to a transient current weighting factor; cross-coupling the weighting factor, amplitude attenuation, and phase shift for calculation; and sending the instruction to an adjustable impedance matching network and a power management chip before actual execution. By separating the dynamic load waveform induced only by the instantaneous high current heating of the integrated circuit and load mutations, the problem of severe lag in response and susceptibility to overall chassis heat dissipation noise of traditional external discrete sensors is overcome.

Description

Technical Field

[0001] This invention relates to the field of circuit optimization technology, specifically to a method and system for performance optimization of integrated circuits in PCBA. Background Technology

[0002] Integrated circuits (ICs) are the core foundation of modern information technology. Through microfabrication processes, they highly concentrate a large number of electronic components such as transistors, resistors, and capacitors, along with wiring, onto a small semiconductor wafer, thereby enabling complex computing logic and data storage functions. Printed circuit board (PCB) assemblies are the underlying physical platform that carries ICs and provides them with electrical connections, mechanical support, and power and signal interaction channels. As IC process nodes continue to advance towards the nanometer scale, the transient computing power density of chips increases dramatically, generating extremely high transient surge currents when executing intensive computational instructions. These microsecond-level large currents not only cause significant resistivity surges on the traces but also lead to severe shifts in surrounding parasitic capacitance and inductance. If the operating status of ICs in the PCBA is not optimized in real-time and precisely at the underlying level, these drastic micro-impedance changes and voltage drops will directly disrupt the signal and power integrity of the entire system, leading to data throughput interruptions, logic errors, and even physical damage to the chip itself. Therefore, performance optimization of ICs at the PCBA physical level has become a critical lifeline for ensuring the reliable operation of modern high-performance electronic equipment.

[0003] Currently, the industry generally relies on distributing external discrete temperature sensors across the circuit board surface for performance optimization and status monitoring of integrated circuits on PCBAs, combined with the voltage sampling circuit inside the power management chip to implement post-loop feedback regulation. However, external discrete sensors have a lag in response when acquiring physical conditions, and the signals they acquire are easily interfered with by common-mode noise such as the overall heat dissipation of the chassis and changes in ambient temperature and humidity. This makes it difficult to reproduce the true dynamic load changes of the chip on a nanosecond scale, and it is easy to execute incorrect compensation actions due to misjudging environmental interference, thus losing the ability to protect the chip under extreme transient conditions. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a method and system for optimizing the performance of integrated circuits in PCBAs, which solves the problem of erroneous compensation actions due to misjudgment of environmental interference, resulting in a loss of protection against extreme transient conditions of the chip.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a method for performance optimization of integrated circuits in PCBA, comprising the following steps:

[0006] The data bus of the integrated circuit is monitored. When an idle period is detected, the instruction opcode to be executed in the prefetch queue is extracted, and probe pulses are injected into the actual working traces and reference dummy traces of the PCBA at the same time to obtain the first reflection signal and the second reflection signal respectively.

[0007] Perform differential subtraction on the first reflected signal and the second reflected signal to output the differential reflected signal;

[0008] The differential reflection signal is subjected to quadrature demodulation processing to extract the in-phase component and quadrature component corresponding to the differential reflection signal;

[0009] Based on the in-phase and quadrature components, the amplitude attenuation and phase offset of the current trace are calculated, and the instruction opcode is mapped to the transient current weighting factor.

[0010] The transient current weighting factor, the amplitude attenuation, and the phase offset are cross-coupled and calculated to generate impedance compensation commands and voltage feedforward commands.

[0011] Before the instruction opcode is actually executed, the impedance compensation instruction and the voltage feedforward instruction are respectively sent to the adjustable impedance matching network and the power management chip on the PCBA.

[0012] Preferably, the extraction of the instruction opcode to be executed from the prefetch queue includes the following steps:

[0013] Monitor the instruction pipeline of the integrated circuit and access the prefetch queue cache in the instruction pipeline during the idle period;

[0014] Analyze the instruction sequence in the prefetch queue buffer to locate the target instruction that will be the first to enter the execution phase after the idle period ends;

[0015] The target instruction is pre-decoded, and the opcode field in the target instruction is extracted as the opcode of the instruction to be executed.

[0016] Preferably, the steps of acquiring the first reflected signal and the second reflected signal respectively include the following steps:

[0017] The two simulated echoes generated by the changes in parasitic parameters along the probe pulse propagating along the actual working trace and the reference dummy trace are captured.

[0018] Based on the same sampling clock, the two analog echoes are synchronously converted from analog to digital to generate corresponding two discrete digital echo sequences.

[0019] Based on the injection time of the probe pulse, the two discrete digital echo sequences are time-domain aligned, and the aligned sequences are used as the first reflected signal and the second reflected signal, respectively.

[0020] Preferably, the differential subtraction process performed on the first reflected signal and the second reflected signal to output the differential reflected signal includes the following steps:

[0021] According to the same time-domain index, the discrete sampled values ​​of the first reflected signal and the second reflected signal are subtracted point by point to generate a residual sequence;

[0022] The dynamic load components are separated using the residual sequence;

[0023] The dynamic load components are recombined in the continuous time domain and output as the differential reflection signal.

[0024] Preferably, the step of performing quadrature demodulation processing on the differential reflection signal to extract the in-phase component and quadrature component corresponding to the differential reflection signal includes the following steps:

[0025] Generate a local in-phase carrier sequence and a local quadrature carrier sequence with the same frequency as the carrier frequency of the probe pulse;

[0026] The differential reflected signal is multiplied and mixed with the local in-phase carrier sequence and the local quadrature carrier sequence to generate an in-phase mixing sequence and a quadrature mixing sequence.

[0027] Low-pass filtering is performed on the in-phase mixing sequence and the quadrature mixing sequence respectively to filter out the high-frequency components of the frequency harmonics and extract the corresponding baseband signals, which are respectively used as the in-phase component and the quadrature component.

[0028] Preferably, the calculation of the amplitude attenuation and phase offset of the current trace includes the following steps:

[0029] The in-phase component and the quadrature component are squared and then added together. The square root of the sum is extracted to obtain the vector magnitude, which is then used as the amplitude attenuation.

[0030] The ratio of the quadrature component to the in-phase component is calculated, and the vector phase angle is obtained by performing an arctangent function operation on the ratio. The vector phase angle is then used as the phase offset.

[0031] Preferably, the generation of impedance compensation commands and voltage feedforward commands includes the following steps:

[0032] The phase offset is multiplied by a preset phase impedance mapping coefficient to calculate the target impedance compensation value, and the target impedance compensation value is encoded as the impedance compensation command.

[0033] The amplitude attenuation is mapped to the dynamic line resistance increment, and the dynamic line resistance increment is added to the preset reference line resistance to calculate the transient total resistance of the current trace.

[0034] The transient current weighting factor is multiplied by the system reference current to calculate the predicted transient load current for the next cycle.

[0035] The predicted transient load current is multiplied by the transient total resistance to obtain the predicted voltage drop compensation amount, and the predicted voltage drop compensation amount is encoded as the voltage feedforward command.

[0036] Preferably, the step of sending the impedance compensation command and the voltage feedforward command to the adjustable impedance matching network and power management chip on the PCBA respectively includes the following steps:

[0037] The impedance compensation command and the voltage feedforward command are respectively appended with the corresponding target device physical address, and encapsulated to generate an impedance control data frame and a power configuration data frame.

[0038] Within a preset clock window before the end of the idle period, the impedance control data frame is sent to the adjustable impedance matching network to trigger the adjustable impedance matching network to adjust the equivalent capacitive reactance and inductive reactance of the access link.

[0039] The power configuration data frame is simultaneously sent to the power management chip to drive the power management chip to raise the reference output voltage of the power supply network by the corresponding predicted voltage drop compensation amount before the transient current is triggered by the instruction opcode to be executed.

[0040] Preferably, mapping the instruction opcode to a transient current weighting factor includes the following steps:

[0041] Extract the instruction type identifier field and operand width identifier field from the instruction opcode;

[0042] The instruction type identifier field and the operand width identifier field are concatenated bit by bit to generate an address for accessing memory;

[0043] The address is input to the power weight lookup table preset inside the hardware state machine, and the value in the corresponding storage unit is read.

[0044] Preferably, a performance optimization system for integrated circuits in a PCBA includes the following modules:

[0045] The bus monitoring and instruction extraction module is used to monitor the data bus of the integrated circuit, detect idle cycles, and extract the opcodes of instructions to be executed in the prefetch queue.

[0046] The probe pulse injection and reflection signal acquisition module is used to inject probe pulses into the actual working traces and reference dummy traces of the PCBA during the idle period, and to acquire the first reflection signal and the second reflection signal.

[0047] The differential signal processing module is used to perform differential subtraction on the first reflected signal and the second reflected signal, and output the differential reflected signal.

[0048] The quadrature demodulation and component extraction module is used to perform quadrature demodulation on differential reflection signals and extract in-phase and quadrature components.

[0049] The parameter calculation and weight mapping module is used to calculate the amplitude attenuation and phase offset of the current trace, and to map the instruction opcode into the transient current weight factor.

[0050] The compensation instruction generation module is used to generate impedance compensation instructions and voltage feedforward instructions through cross-coupling calculations.

[0051] The instruction issuance and execution control module is used to encapsulate the two types of compensation instructions and issue them to the adjustable impedance matching network and power management chip on the PCBA, respectively.

[0052] The system parameter storage module is used to store the preset parameters required for the operation of each module.

[0053] This invention provides a method and system for optimizing the performance of integrated circuits in PCBAs. It offers the following advantages:

[0054] 1. This invention injects probe pulses synchronously into the actual working traces and the reference dummy traces during the idle period, and captures the two reflected echoes to perform precise point-by-point differential subtraction processing. By utilizing a spatially symmetrical physical differential architecture, it cancels the common-mode interference substrate caused by substrate ambient temperature drift and dielectric constant changes, and separates the dynamic load waveform induced only by the instantaneous high current heating of the integrated circuit and load mutation. This overcomes the problem of severe lag in response of traditional external discrete sensors and their susceptibility to interference from overall chassis heat dissipation noise.

[0055] 2. This invention introduces a dual-track detection mechanism that combines digital instruction pre-decoding and RF waveform detection. The intercepted software low-level instruction opcodes are hardware-mapped into transient current weighting factors, and simultaneously input into a two-dimensional hardware state machine for deep cross-coupling calculations along with the amplitude attenuation and phase offset extracted from the physical channel. This achieves multi-dimensional cross-border fusion of the expected power consumption attributes of the abstract program code with the real-time physical thermoelectric distortion of the traces, achieving deterministic and accurate calculation of transient voltage drop and impedance drift under complex thermoelectric coupling conditions. This solves the risk of voltage overshoot or undervoltage crash caused by traditional reliance on a single fixed empirical feedback.

[0056] 3. This invention compresses and constrains the data interaction of the main chip within an extremely short idle suspension time window. Before the high-load instruction to be executed actually triggers the transient surge current, it drives the adjustable impedance matching network on the printed circuit board assembly to adjust the capacitive and inductive reactance and forces the power management chip to actively raise the reference output voltage. This achieves that the core power supply and high-speed signal channel enter a perfectly matched standby state in advance at the moment of heavy load impact, fully ensuring the system's operational stability under extreme high-frequency burst computing power demands. Attached Figure Description

[0057] Figure 1 This is a flowchart of a method for performance optimization of integrated circuits in PCBA according to the present invention;

[0058] Figure 2 This is a system architecture diagram of a performance optimization system for integrated circuits in PCBA according to the present invention. Detailed Implementation

[0059] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0060] Example 1

[0061] Please see the appendix Figure 1 This invention provides a method and system for performance optimization of integrated circuits in PCBA, comprising the following steps:

[0062] The monitoring integrated circuit's data bus, upon detecting an idle period, extracts the instruction opcode to be executed from the prefetch queue and simultaneously injects probe pulses into the actual working traces and reference dummy traces of the PCBA to acquire the first reflection signal and the second reflection signal, respectively.

[0063] Furthermore, retrieving the opcodes to be executed from the prefetch queue includes the following steps:

[0064] Monitor the instruction pipeline of the integrated circuit and access the prefetch queue cache in the instruction pipeline during idle cycles;

[0065] Analyze the instruction sequence in the prefetch queue cache to locate the target instruction that will be the first to enter the execution phase after the idle period ends;

[0066] The target instruction is pre-decoded, and the opcode field in the target instruction is extracted as the opcode of the instruction to be executed.

[0067] The steps for acquiring the first reflected signal and the second reflected signal are as follows:

[0068] The two simulated echoes generated by the changes in parasitic parameters along the probe pulse propagating along the actual working trace and the reference dummy trace are captured.

[0069] Based on the same sampling clock, synchronous analog-to-digital sampling conversion is performed on the two analog echoes to generate corresponding two discrete digital echo sequences.

[0070] Based on the injection time of the probe pulse, the two discrete digital echo sequences are time-domain aligned, and the aligned sequences are used as the first reflection signal and the second reflection signal, respectively.

[0071] By adopting the above technical solution, the data bus status of the integrated circuit is continuously monitored. Once the data bus is detected to be in an idle period, instruction sniffing and physical probing are immediately executed simultaneously. For instruction sniffing, the instruction pipeline of the integrated circuit is monitored, and the prefetch queue buffer in the instruction pipeline is accessed during the idle period. By parsing the instruction sequence in the prefetch queue buffer, the target instruction that enters the execution stage first after the idle period ends can be located. Subsequently, the target instruction is pre-decoded, and the opcode field in the target instruction is extracted as the opcode of the instruction to be executed. At the same time, for physical probing, probe pulses are synchronously injected into the actual working traces and reference dummy traces of the printed circuit board assembly. When the probe pulses propagate along the actual working traces and reference dummy traces, reflections are generated due to changes in parasitic parameters along the traces. Subsequently, two simulated echoes generated by the changes in parasitic parameters along the traces are captured, as shown in the formula:

[0072]

[0073] ;

[0074] in, The simulated echo generated by propagation along the actual working path. The simulated echo generated by propagation along the reference dummy trace. For synchronously injected probe pulses, The impulse response of the working channel is determined by the changes in parasitic parameters along the actual working route. The reference channel impulse response is determined by the parasitic parameter variations along the reference dummy trace. Then, based on the same sampling clock, synchronous analog-to-digital sampling conversion is performed on the two analog echoes to generate corresponding two discrete digital echo sequences, as shown in the formula:

[0075]

[0076] ;

[0077] in, These are the discrete digital echo sample points generated corresponding to the actual working traces. To reference the discrete digital echo sample points generated corresponding to the dummy trace, The consecutive sampling interval period of the same sampling clock. Using the step index point in the discrete time domain, and finally, taking the injection time of the probe pulse as the reference, the two discrete digital echo sequences are time-domain aligned, and the aligned two sequences are used as the first reflection signal and the second reflection signal, respectively. By using the time window suspended by the bus, the advance acquisition of the computational intent and the high-frequency extraction of the real impulse response of the physical channel are completed simultaneously.

[0078] Perform differential subtraction on the first reflected signal and the second reflected signal to output the differential reflected signal;

[0079] Furthermore, differential subtraction is performed on the first reflected signal and the second reflected signal to output a differential reflected signal, including the following steps:

[0080] According to the same time-domain index, the discrete sampled values ​​of the first reflection signal and the second reflection signal are subtracted point by point to generate a residual sequence;

[0081] Dynamic load components are separated using residual sequences;

[0082] The dynamic load components are recombined in the continuous time domain and output as a differential reflection signal.

[0083] By adopting the above technical solution, after obtaining the aligned first and second reflection signals, differential subtraction processing is performed on the first and second reflection signals. This involves performing point-by-point subtraction on the discrete sampling points of the first and second reflection signals to generate the corresponding residual sequence, as shown in the formula: ;

[0084] in, These are the discrete sampling points of the residual sequence generated under the corresponding time-domain index node. This represents the discrete sampled value of the first reflected signal at the corresponding time-domain index node. Given the discrete sampled values ​​of the second reflected signal at the same time-domain index node, the dynamic load component caused by the transient operating state of the integrated circuit can be directly separated using the generated residual sequence through this point-by-point subtraction operation. The separation and mapping process of this physical load is equivalent to the sequence assignment formula:

[0085] ;

[0086] in, The dynamic load component separated from the mixed background is represented by its pure discrete sampled value at the corresponding time-domain node. Subsequently, waveform reconstruction logic is used to smoothly reconstruct the separated dynamic load component in the continuous time domain, and output it as a differential reflection signal. The formula is as follows:

[0087] ;

[0088] in, For variables in continuous time Differential reflection signals reconstructed in different dimensions To perform summation operations on the discrete sampling points under all time-domain index nodes, An ideal interpolation function to smoothly transition discrete sampling points into a continuous waveform, The time interval between adjacent discrete sampling points is defined, enabling pure physical space differential operations to be performed based on a strictly aligned time axis in the underlying hardware architecture. The virtual reference channel completely isolates the interference of external substrate environment drift on the measurement results, and extracts the dynamic load waveform that is strongly correlated only with the instantaneous high-frequency electrothermal stress of the target integrated circuit.

[0089] Perform quadrature demodulation on the differential reflection signal to extract the in-phase and quadrature components corresponding to the differential reflection signal;

[0090] Furthermore, quadrature demodulation processing is performed on the differential reflection signal to extract the in-phase and quadrature components corresponding to the differential reflection signal, including the following steps:

[0091] Generate a local in-phase carrier sequence and a local quadrature carrier sequence with the same frequency as the carrier frequency of the probe pulse;

[0092] The differential reflected signal is multiplied and mixed with the local in-phase carrier sequence and the local quadrature carrier sequence respectively to generate the in-phase mixing sequence and the quadrature mixing sequence;

[0093] Low-pass filtering is performed on the in-phase mixing sequence and the quadrature mixing sequence respectively to filter out the high-frequency components of the frequency harmonics and extract the corresponding baseband signals, which are used as the in-phase component and the quadrature component respectively.

[0094] By adopting the above technical solution, after obtaining the pure differential reflection signal, quadrature demodulation processing is then performed on the differential reflection signal to extract the in-phase and quadrature components corresponding to the differential reflection signal. First, a local in-phase carrier sequence and a local quadrature carrier sequence with the same frequency as the carrier frequency of the aforementioned detection pulse are generated. The formula for this local carrier generation process is as follows:

[0095] ;

[0096]

[0097] in, For the generated local in-phase carrier sequence, For the generated local orthogonal carrier sequence, The angular frequency parameter corresponding to the frequency of the probe pulse carrier. As a continuously running time variable, a hardware multiplier array is then used to perform dot-multiplication mixing operations on the differential reflected signal with the local in-phase carrier sequence and the local quadrature carrier sequence, respectively, to generate the in-phase mixing sequence and the quadrature mixing sequence, as shown in the formula:

[0098] ;

[0099] ;

[0100] in, For the generated in-phase mixing sequence, The generated orthogonal mixing sequence, The input is a differential reflection signal. Since the mixed sequence contains unwanted high-frequency harmonics, low-pass filtering is then applied to both the in-phase and quadrature mixing sequences. The filtering formula is as follows:

[0101] ;

[0102] ;

[0103] in, This is the in-phase baseband signal extracted after filtering. This is the orthogonal baseband signal extracted after filtering. The impulse response kernel function of the low-pass filter is used as the baseband signal extracted after filtering out the harmonic components, which are respectively used as the required in-phase and quadrature components. By using the precise local oscillator signal and differential reflection signal to perform quadrature mixing downconversion operation, the extremely weak physical impedance and temperature distortion characteristics that were originally submerged in the high-frequency carrier are transferred to the low-frequency baseband region without loss, while filtering out useless harmonic high-frequency components and out-of-band noise.

[0104] Based on the in-phase and quadrature components, the amplitude attenuation and phase offset of the current trace are calculated, and the instruction opcode is mapped to the transient current weighting factor.

[0105] Furthermore, the amplitude attenuation and phase offset of the current trace are calculated, including the following steps:

[0106] The in-phase component and the quadrature component are squared and then added together. The square root of the sum is extracted to obtain the vector magnitude, which is then used as the amplitude attenuation.

[0107] Calculate the ratio of the quadrature component to the in-phase component, and perform an arctangent function operation on the ratio to obtain the vector phase angle. Use the vector phase angle as the phase offset.

[0108] Mapping instruction opcodes to transient current weighting factors includes the following steps:

[0109] Extract the instruction type identifier field and operand width identifier field from the instruction opcode;

[0110] The instruction type identifier field and the operand width identifier field are concatenated bit by bit to generate the address for accessing memory;

[0111] The address is input to the power weight lookup table preset inside the hardware state machine, and the value in the corresponding memory unit is read.

[0112] By adopting the above technical solution, after obtaining the in-phase and quadrature components of the baseband, the digital calculation logic then calculates the amplitude attenuation and phase shift of the current trace based on the in-phase and quadrature components. The in-phase and quadrature components are squared separately and then added together. The square root of the sum is then extracted to obtain the vector magnitude, as shown in the formula:

[0113] ;

[0114] in, The calculated vector magnitude is directly used as the amplitude attenuation representing the heating state of the trace. For the in-phase input, For the input quadrature components, simultaneously calculate the ratio of the quadrature component to the in-phase component, and then perform an arctangent function operation on this ratio to obtain the vector phase angle, as shown in the formula:

[0115] ;

[0116] in, To obtain the vector phase angle and use it directly as the phase offset reflecting parameter changes, within the same clock cycle of physical feature extraction, the parallel control logic maps the aforementioned intercepted instruction opcode to a transient current weighting factor characterizing the power consumption of the integrated circuit's underlying layers. It then extracts the instruction type identifier field and operand width identifier field from the instruction opcode. Next, it performs a bit-by-bit concatenation operation on the instruction type identifier field and operand width identifier field to generate the addressing address used to access memory. The formula is:

[0117] ;

[0118] in, For the generated memory address, For the field identifying the type of instruction captured, The operand width identifier field is extracted. Finally, the address is input to the power weight lookup table preset inside the hardware state machine, the value in the corresponding memory cell is read, and the value is output as the transient current weight factor. The abstract baseband parameters are accurately restored to intuitive physical amplitude and phase parameters using the determined function logic. Through delay-free address concatenation and memory mapping technology, the abstract software opcode is instantly transformed into specific current prediction weights.

[0119] The transient current weighting factor, amplitude attenuation, and phase offset are cross-coupled and calculated to generate impedance compensation commands and voltage feedforward commands.

[0120] Furthermore, generating impedance compensation commands and voltage feedforward commands includes the following steps:

[0121] The phase offset is multiplied by the preset phase impedance mapping coefficient to calculate the target impedance compensation value, and the target impedance compensation value is encoded as an impedance compensation command.

[0122] The amplitude attenuation is mapped to the dynamic line resistance increment, and the dynamic line resistance increment is added to the preset reference line resistance to calculate the transient total resistance of the current trace.

[0123] The transient current weighting factor is multiplied by the reference current to calculate the predicted transient load current for the next cycle.

[0124] The predicted transient load current is multiplied by the transient total resistance to obtain the predicted voltage drop compensation amount, and the predicted voltage drop compensation amount is encoded as a voltage feedforward command.

[0125] By adopting the above technical solution, after extracting the multidimensional physical and digital features, the transient current weighting factor, amplitude attenuation, and phase offset are cross-coupled and calculated to generate impedance compensation and voltage feedforward commands. First, the phase offset is multiplied by a preset phase impedance mapping coefficient to calculate the target impedance compensation value, as shown in the formula:

[0126] ;

[0127] in, The calculated target impedance compensation value, The preset phase impedance mapping coefficient is fixed. The input phase offset is then used. Subsequently, the target impedance compensation value is encoded into an impedance compensation command according to the underlying protocol. Simultaneously, the amplitude attenuation is mapped into a dynamic line resistance increment, and the dynamic line resistance increment is added to a preset reference line resistance to calculate the transient total resistance of the current trace. The formula is as follows:

[0128] ;

[0129] in, To calculate the transient total resistance of the current trace, The preset reference circuit resistance, The conversion coefficient is the mapping factor from amplitude to resistance increment. The input amplitude attenuation is used. Simultaneously, the transient current weighting factor is multiplied by the reference current to calculate the predicted transient load current of the integrated circuit in the next cycle. The formula is as follows:

[0130] ;

[0131] in, The predicted transient load current is derived from the budget. The input transient current weighting factor. Using the reference current as a reference, the predicted transient load voltage is then directly multiplied by the transient resistance to obtain the predicted voltage drop compensation value. This cross-coupling operation follows the voltage drop calculation formula:

[0132] ;

[0133] in, To obtain the predicted voltage drop compensation value, the predicted voltage drop compensation value is immediately encoded into a voltage feedforward instruction after the calculation is completed. By breaking down the barrier between analog hardware perception and digital instruction execution at the underlying logic level, and using continuous algebraic mapping to deeply integrate physical thermoelectric parameters and abstract software power consumption weights, deterministic advance prediction of future micro impedance mutations and macro power supply drops is achieved, thereby generating precise control instructions for the dynamic reconfiguration of the peripheral network.

[0134] Before the instruction opcode is actually executed, the impedance compensation instruction and the voltage feedforward instruction are sent to the adjustable impedance matching network and power management chip on the PCBA, respectively.

[0135] Furthermore, the impedance compensation command and voltage feedforward command are respectively sent to the adjustable impedance matching network and power management chip on the PCBA, including the following steps:

[0136] The corresponding target device physical address is appended to the impedance compensation command and the voltage feedforward command respectively, and the impedance control data frame and the power configuration data frame are encapsulated and generated.

[0137] Within a preset clock window before the end of the idle period, impedance control data frames are sent to the adjustable impedance matching network to trigger the adjustable impedance matching network to adjust the equivalent capacitive reactance and inductive reactance of the access link.

[0138] The power configuration data frame is sent to the power management chip in sync, which drives the power management chip to raise the reference output voltage of the power supply network by the corresponding predicted voltage drop compensation amount before the transient current is triggered by the instruction opcode to be executed.

[0139] By adopting the above technical solution, after the feedforward instruction is generated, the communication controller immediately initiates the instruction distribution process to ensure that the impedance compensation instruction and voltage feedforward instruction are sent to the adjustable impedance matching network and power management chip on the printed circuit board assembly before the instruction opcode is actually executed. The underlying control logic appends the corresponding target device physical address to the impedance compensation instruction and voltage feedforward instruction, performs underlying protocol formatting, and then encapsulates them to generate impedance control data frames and power configuration data frames. Immediately afterwards, within the preset clock window before the end of the idle cycle, the impedance control data frame is rapidly sent to the adjustable impedance matching network via the hardware communication bus. After the control frame arrives at the target address, it is directly used to trigger the adjustable impedance matching network to change the connection state of the internal hardware switching matrix, thereby adjusting the access chain. The equivalent capacitive and inductive reactance of the circuit are synchronously sent to the power management chip via a power configuration data frame. After the configuration frame is injected into the control register of the power management chip, it is used to drive the power management chip to actively intervene in the internal voltage output regulation loop before the instruction opcode to be executed actually triggers the micro transient current. This raises the reference output voltage of the power supply network in advance and accurately by the corresponding predicted voltage drop compensation. By completing the address mapping encapsulation and parallel high-speed distribution of the underlying control instructions during the idle time interval, the physical infrastructure of the motherboard is forced to complete the preventive state reconstruction before the integrated circuit faces a sudden heavy load impact. This zero-latency feedforward control architecture eliminates the signal distortion and power drop crisis caused by the response lag of the traditional closed-loop feedback mechanism, ensuring the absolute stability and safety of data throughput under extreme high-frequency operating conditions.

[0140] Example 2

[0141] Please see the appendix Figure 2 This invention provides a performance optimization system for integrated circuits in PCBAs, comprising the following modules:

[0142] The bus monitoring and instruction extraction module is used to monitor the data bus of the integrated circuit, detect idle cycles, and extract the opcodes of instructions to be executed in the prefetch queue.

[0143] The probe pulse injection and reflection signal acquisition module is used to inject probe pulses into the actual working traces and reference dummy traces of the PCBA during the idle period, and to acquire the first reflection signal and the second reflection signal.

[0144] The differential signal processing module is used to perform differential subtraction on the first reflected signal and the second reflected signal, and output the differential reflected signal.

[0145] The quadrature demodulation and component extraction module is used to perform quadrature demodulation on differential reflection signals and extract in-phase and quadrature components.

[0146] The parameter calculation and weight mapping module is used to calculate the amplitude attenuation and phase offset of the current trace, and to map the instruction opcode into the transient current weight factor.

[0147] The compensation instruction generation module is used to generate impedance compensation instructions and voltage feedforward instructions through cross-coupling calculations.

[0148] The instruction issuance and execution control module is used to encapsulate the two types of compensation instructions and issue them to the adjustable impedance matching network and power management chip on the PCBA, respectively.

[0149] The system parameter storage module is used to store the preset parameters required for the operation of each module.

[0150] By adopting the above technical solution, once the bus monitoring and instruction extraction module detects that the bus has entered an idle suspension cycle, it immediately probes into the instruction pipeline to access the prefetch queue buffer and parses the instruction sequence therein, thereby locating the first target instruction to enter the execution stage. Then, it performs hardware pre-decoding on the target instruction and extracts the opcode field, using it as the opcode of the instruction to be executed.

[0151] When an idle period is detected, the probe pulse injection and reflection signal acquisition module synchronously injects a broadband probe pulse into the actual working trace and the reference dummy trace on the printed circuit board assembly. Subsequently, the receiving link captures the two analog echoes generated by the parasitic parameter abrupt change as the pulse propagates along the two traces, and performs synchronous analog-to-digital sampling conversion on the analog echoes based on the same high-frequency sampling clock to generate a discrete digital echo sequence. Finally, the module performs time-domain alignment based on the pulse injection time and outputs the first reflection signal and the second reflection signal.

[0152] The differential signal processing module receives the aligned two reflected signals and performs point-by-point hardware subtraction on the discrete sampled values ​​at the register level according to the same time domain index to generate a residual sequence. The residual sequence is used to completely cancel the common-mode interference caused by the substrate ambient temperature and dielectric constant drift. The dynamic load component caused by the transient heating and local stress change of the integrated circuit is separated. Then, the dynamic load component is recombined in the continuous time domain and the differential reflected signal is output. This fundamentally eliminates the interference of the complex environment inside the chassis on the measurement, ensures that the physical signal transmitted to the subsequent stage has an extremely high signal-to-noise ratio, and is entirely attributed to the load evolution of the chip itself.

[0153] The quadrature demodulation and component extraction module receives the clean differential reflection signal. Its internal digital oscillator generates a local in-phase carrier sequence and a local quadrature carrier sequence with the same frequency as the probe pulse carrier. The multiplier array performs dot multiplication and mixing operations on the differential reflection signal and the two local carriers respectively. Subsequently, the low-pass filter performs filtering on the generated in-phase mixing sequence and quadrature mixing sequence, truncates the high-frequency components of the frequency doubling, and extracts the baseband signal as the in-phase component and quadrature component. The parasitic distortion features submerged in the high-frequency band are transferred to the baseband interval without loss, reducing the complexity and power consumption of the subsequent physical parameter calculation logic.

[0154] The parameter calculation and weight mapping module calculates the sum of squares of the in-phase and quadrature components and takes the square root to obtain the vector magnitude value, which is used as the amplitude attenuation. At the same time, it calculates the ratio of the quadrature component to the in-phase component and calculates the arctangent to obtain the vector phase angle, which is used as the phase offset. On the other hand, it extracts the instruction type and operand bit width identifier fields from the instruction opcode, concatenates them into bits to generate the address address, and reads the value from the built-in lookup table as the transient current weight factor. Within the same clock cycle, it completes the parallel analysis of the physical parameters of the RF signal and the translation of the power consumption weight of the software opcode, providing cross-dimensional quantitative indicators for cross-feedforward measurement.

[0155] The compensation instruction generation module multiplies the phase offset by a preset mapping coefficient to obtain the target impedance compensation value, which is then encoded as an impedance compensation instruction. Simultaneously, it maps the amplitude attenuation to a resistance increment and superimposes it with the reference line resistance to obtain the transient total resistance. Next, it multiplies the transient current weighting factor by the reference current to obtain the predicted transient load current. Finally, it multiplies the predicted transient load current by the transient total resistance to obtain the predicted voltage drop compensation amount, which is then encoded as a voltage feedforward instruction. This breaks the boundary between analog physical perception and digital software scheduling, and realizes deterministic advance calculation for complex microscopic parasitic distortions and macroscopic power supply drops.

[0156] The instruction issuance and execution control module attaches the physical bus address of the target device to the impedance compensation instruction and the voltage feedforward instruction respectively, and encapsulates them into impedance control data frames and power configuration data frames. Within the tight clock window before the end of the idle cycle, the impedance control data frame is sent to the adjustable impedance matching network to trigger it to adjust the equivalent capacitive reactance and inductive reactance. At the same time, the power configuration data frame is sent to the power management chip to drive it to actively raise the reference output voltage before the transient surge current arrives, forcing the external adjustment facilities to enter the standby state in advance, avoiding the risk of system downtime caused by power supply drop or impedance mismatch.

[0157] The system parameter storage module has an independent section for securely storing various preset data necessary for compensation calculations and signal processing. It pre-programs global configuration parameters, including phase impedance mapping coefficients, reference line resistance, and system reference current, and provides deterministic addressing and calling services for each feature calculation logic unit. It can flexibly adapt and read the basic configuration for different printed circuit board substrate materials or different batches of integrated circuits, thereby ensuring the accuracy of physical feature conversion and the continuity of system operation.

[0158] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for performance optimization of integrated circuits in PCBA, characterized in that, Includes the following steps: The data bus of the integrated circuit is monitored. When an idle period is detected, the instruction opcode to be executed in the prefetch queue is extracted, and probe pulses are injected into the actual working traces and reference dummy traces of the PCBA at the same time to obtain the first reflection signal and the second reflection signal respectively. Perform differential subtraction on the first reflected signal and the second reflected signal to output the differential reflected signal; The differential reflection signal is subjected to quadrature demodulation processing to extract the in-phase component and quadrature component corresponding to the differential reflection signal; Based on the in-phase and quadrature components, the amplitude attenuation and phase offset of the current trace are calculated, and the instruction opcode is mapped to the transient current weighting factor. The transient current weighting factor, the amplitude attenuation, and the phase offset are cross-coupled and calculated to generate impedance compensation commands and voltage feedforward commands. Before the instruction opcode is actually executed, the impedance compensation instruction and the voltage feedforward instruction are respectively sent to the adjustable impedance matching network and the power management chip on the PCBA.

2. The method for performance optimization of integrated circuits in PCBA according to claim 1, characterized in that, The process of extracting the opcodes to be executed from the prefetch queue includes the following steps: Monitor the instruction pipeline of the integrated circuit and access the prefetch queue cache in the instruction pipeline during the idle period; Analyze the instruction sequence in the prefetch queue buffer to locate the target instruction that will be the first to enter the execution phase after the idle period ends; The target instruction is pre-decoded, and the opcode field in the target instruction is extracted as the opcode of the instruction to be executed.

3. The method for performance optimization of integrated circuits in PCBA according to claim 1, characterized in that, The steps of acquiring the first reflected signal and the second reflected signal respectively include the following: The two simulated echoes generated by the changes in parasitic parameters along the probe pulse propagating along the actual working trace and the reference dummy trace are captured. Based on the same sampling clock, the two analog echoes are synchronously converted from analog to digital to generate corresponding two discrete digital echo sequences. Based on the injection time of the probe pulse, the two discrete digital echo sequences are time-domain aligned, and the aligned sequences are used as the first reflection signal and the second reflection signal, respectively.

4. The method for performance optimization of integrated circuits in PCBA according to claim 1, characterized in that, The differential subtraction process performed on the first reflected signal and the second reflected signal to output the differential reflected signal includes the following steps: According to the same time-domain index, the discrete sampled values ​​of the first reflected signal and the second reflected signal are subtracted point by point to generate a residual sequence; The dynamic load components are separated using the residual sequence; The dynamic load components are recombined in the continuous time domain and output as the differential reflection signal.

5. The method for performance optimization of integrated circuits in PCBA according to claim 1, characterized in that, The step of performing quadrature demodulation processing on the differential reflection signal to extract the in-phase component and quadrature component corresponding to the differential reflection signal includes the following steps: Generate a local in-phase carrier sequence and a local quadrature carrier sequence with the same frequency as the carrier frequency of the probe pulse; The differential reflected signal is multiplied and mixed with the local in-phase carrier sequence and the local quadrature carrier sequence to generate an in-phase mixing sequence and a quadrature mixing sequence. Low-pass filtering is performed on the in-phase mixing sequence and the quadrature mixing sequence respectively to filter out the high-frequency components of the frequency harmonics and extract the corresponding baseband signals, which are respectively used as the in-phase component and the quadrature component.

6. The method for performance optimization of integrated circuits in PCBA according to claim 1, characterized in that, The calculation of the amplitude attenuation and phase offset of the current trace includes the following steps: The in-phase component and the quadrature component are squared and then added together. The square root of the sum is extracted to obtain the vector magnitude, which is then used as the amplitude attenuation. The ratio of the quadrature component to the in-phase component is calculated, and the vector phase angle is obtained by performing an arctangent function operation on the ratio. The vector phase angle is then used as the phase offset.

7. The method for performance optimization of integrated circuits in PCBA according to claim 1, characterized in that, The generation of impedance compensation commands and voltage feedforward commands includes the following steps: The phase offset is multiplied by a preset phase impedance mapping coefficient to calculate the target impedance compensation value, and the target impedance compensation value is encoded as the impedance compensation command. The amplitude attenuation is mapped to the dynamic line resistance increment, and the dynamic line resistance increment is added to the preset reference line resistance to calculate the transient total resistance of the current trace. The transient current weighting factor is multiplied by the system reference current to calculate the predicted transient load current for the next cycle. The predicted transient load current is multiplied by the transient total resistance to obtain the predicted voltage drop compensation amount, and the predicted voltage drop compensation amount is encoded as the voltage feedforward command.

8. The method for performance optimization of integrated circuits in PCBA according to claim 1, characterized in that, The step of sending the impedance compensation command and the voltage feedforward command to the adjustable impedance matching network and power management chip on the PCBA, respectively, includes the following steps: The impedance compensation command and the voltage feedforward command are respectively appended with the corresponding target device physical address, and encapsulated to generate an impedance control data frame and a power configuration data frame. Within a preset clock window before the end of the idle period, the impedance control data frame is sent to the adjustable impedance matching network to trigger the adjustable impedance matching network to adjust the equivalent capacitive reactance and inductive reactance of the access link. The power configuration data frame is simultaneously sent to the power management chip to drive the power management chip to raise the reference output voltage of the power supply network by the corresponding predicted voltage drop compensation amount before the transient current is triggered by the instruction opcode to be executed.

9. The method for performance optimization of integrated circuits in PCBA according to claim 1, characterized in that, The step of mapping the instruction opcode to a transient current weighting factor includes the following steps: Extract the instruction type identifier field and operand width identifier field from the instruction opcode; The instruction type identifier field and the operand width identifier field are concatenated bit by bit to generate an address for accessing memory; The address is input to the power weight lookup table preset inside the hardware state machine, and the value in the corresponding storage unit is read.

10. A performance optimization system for integrated circuits in PCBA, characterized in that, The method for performance optimization of integrated circuits in PCBA as described in any one of claims 1-9 Includes the following modules: The bus monitoring and instruction extraction module is used to monitor the data bus of the integrated circuit, detect idle cycles, and extract the opcodes of instructions to be executed in the prefetch queue. The probe pulse injection and reflection signal acquisition module is used to inject probe pulses into the actual working traces and reference dummy traces of the PCBA during the idle period, and to acquire the first reflection signal and the second reflection signal. The differential signal processing module is used to perform differential subtraction on the first reflected signal and the second reflected signal, and output the differential reflected signal. The quadrature demodulation and component extraction module is used to perform quadrature demodulation on differential reflection signals and extract in-phase and quadrature components. The parameter calculation and weight mapping module is used to calculate the amplitude attenuation and phase offset of the current trace, and to map the instruction opcode into the transient current weight factor. The compensation instruction generation module is used to generate impedance compensation instructions and voltage feedforward instructions through cross-coupling calculations. The instruction issuance and execution control module is used to encapsulate the two types of compensation instructions and issue them to the adjustable impedance matching network and power management chip on the PCBA, respectively. The system parameter storage module is used to store the preset parameters required for the operation of each module.

Images