Chip electronic design simulation method
By splitting and orthogonalizing the electronic design simulation matrix, a reduced-order model is generated, which solves the problems of high computational resource consumption and complex solution in the existing technology, and achieves high-efficiency simulation accuracy and speed improvement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUZHOU QINYAN INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2026-06-15
- Publication Date
- 2026-07-31
AI Technical Summary
Existing electronic design simulations for virtual verification of integrated circuits consume large amounts of computational resources, are complex to solve, and have difficulty distinguishing the degree of response intensity in different frequency bands. This leads to excessive differences in the values of matrix elements, making it easy to fall into ill-conditioned conditions, causing the solution to diverge. Furthermore, insufficient sampling in the high-frequency resonant region results in distortion of the time-domain response.
Extract the packaged interconnect network data, generate the initial system matrix, split the state vector into node voltage and branch current matrices, use the complex plane expansion point set to iteratively calculate the voltage region basis and current region basis vectors, perform orthogonalization processing, remove redundant basis vectors, generate the global projection matrix, reduce the order of the simulation model, and connect it to the circuit simulator for transient testing.
It achieves approximation accuracy in the high-frequency region, avoids ill-conditioned problems in numerical solutions, reduces memory space and time overhead, improves the speed of large-scale physical field co-analysis, and maintains the accuracy of electrical functions and performance.
Smart Images
Figure CN122491182A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic design simulation technology, and in particular to a chip electronic design simulation method. Background Technology
[0002] Electronic design simulation is a core supporting field of modern electronic design automation technology. It mainly relies on computer software, high-performance numerical calculation methods and complex physical and mathematical models to virtually verify, predict and optimize the electrical functions, performance and multiphysics behavior of integrated circuits, printed circuit boards or the entire electronic system before they enter physical manufacturing and tape-out.
[0003] Current electronic design simulations, when facing virtual verification of integrated circuits before physical manufacturing, rely excessively on importing massive amounts of low-level parasitic parameters into computational software for full-matrix iterative solutions. Directly calculating the large and complex original physical field mathematical models consumes extremely high computer memory and computing power resources, easily leading to a catastrophic expansion of computational dimensions. Conventional numerical calculations struggle to adaptively distinguish the severity of responses in different frequency bands when dealing with full-order system matrices containing huge orders of magnitude. They typically employ a constant-step traversal mode, wasting ineffective computing power in smooth frequency bands while under-sampling in high-frequency resonant abrupt regions, resulting in time-domain response distortion. Conventional operations mix voltage and current variables with different physical dimensions in a large matrix and directly invert it, easily causing excessive differences in matrix element values, leading to ill-conditioned conditions and solution divergence. Therefore, improvements are needed. Summary of the Invention
[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a chip electronic design simulation method.
[0005] To achieve the above objectives, the present invention adopts the following technical solution: a chip electronic design simulation method, comprising the following steps:
[0006] Extract the encapsulated interconnect network data to obtain the initial system matrix;
[0007] Estimate the set of resonant frequencies of the initial system matrix and determine the set of complex plane expansion points;
[0008] The state vectors of the initial system matrix are split to generate the node voltage matrix and the branch current matrix;
[0009] The node voltage matrix and the branch current matrix are iteratively calculated using the set of points expanded in the complex plane to generate voltage region basis vectors and current region basis vectors.
[0010] The voltage region basis vectors and the current region basis vectors are orthogonalized to obtain an orthogonalized basis vector set.
[0011] Check the rank deficiency state of the orthogonalized basis vector set, remove redundant basis vectors from the orthogonalized basis vector set, and obtain the target orthogonal basis vector set;
[0012] Concatenate the target orthogonal basis vector set to generate a global projection matrix;
[0013] The initial system matrix is reduced in order using the global projection matrix, and then connected to a circuit simulator to perform transient simulation tests.
[0014] Preferably, the steps for extracting the encapsulated interconnect network data to obtain the initial system matrix are as follows:
[0015] Obtain the parasitic parameter extraction file of the target chip, parse the pin netlist data in the parasitic parameter extraction file, and extract the resistance, inductance, capacitance, and admittance parameter values from the pin netlist data. Based on the resistance parameter values, construct the resistance block of the circuit network topology; based on the inductance parameter values, construct the inductance block of the circuit network topology; based on the capacitance parameter values, construct the capacitance block of the circuit network topology; based on the admittance parameter values, construct the admittance block of the circuit network topology. Perform node analysis on the resistance block, inductance block, capacitance block, and admittance block based on Maxwell's equations to establish an interconnection network algebraic equation system. Use the coefficient matrix of the interconnection network algebraic equation system as the initial system matrix.
[0016] Preferably, the steps of estimating the set of resonant frequencies of the initial system matrix and determining the set of complex plane expansion points are as follows:
[0017] Eigenvalue decomposition is performed on the initial system matrix to extract its eigenvectors. The eigenvectors are then used to calculate the set of pole frequencies of the initial system matrix. Complex conjugate poles in the set of pole frequencies are selected, and the imaginary part values corresponding to the complex conjugate poles are taken as resonant frequency points. All the resonant frequency points are combined to generate the set of resonant frequencies. The system transfer function tracing algorithm is used to calculate the response error norm corresponding to each resonant frequency point in the set of resonant frequencies. It is determined whether the response error norm corresponding to each resonant frequency point is greater than a preset accuracy threshold. When the response error norm corresponding to each resonant frequency point is greater than the preset accuracy threshold, expansion points are assigned to each resonant frequency point in the complex plane. All the assigned expansion points are merged to generate the set of expansion points in the complex plane.
[0018] Preferably, the steps of splitting the state vector of the initial system matrix to generate the node voltage matrix and branch current matrix are as follows:
[0019] The matrix dimensions of the interconnect network algebraic equations are analyzed, and the state vector is extracted based on the matrix dimensions. A first vector interval describing node voltage variables and a second vector interval describing branch current variables in the state vector are identified. A first block matrix is extracted from the initial system matrix based on the first vector interval, and the first block matrix is used as the node voltage matrix. A second block matrix is extracted from the initial system matrix based on the second vector interval, and the second block matrix is used as the branch current matrix. The node voltage matrix is dominated by the capacitance block and the admittance block in the interconnect network algebraic equations, and the branch current matrix is dominated by the inductance block and the resistance block in the interconnect network algebraic equations.
[0020] Preferably, the step of iteratively calculating the nodal voltage matrix and the branch current matrix using the complex plane expansion point set to generate the voltage region basis vector and the current region basis vector specifically includes:
[0021] Each complex plane expansion point in the set of complex plane expansion points is read. A first shifted inverse matrix of the node voltage matrix is constructed at each complex plane expansion point. Moment matching operation is performed on the node voltage matrix using the first shifted inverse matrix to obtain a first intermediate result. The first intermediate result is expanded using the Arnoldi iterative algorithm to generate the voltage region basis vector. A second shifted inverse matrix of the branch current matrix is constructed at each complex plane expansion point. Moment matching operation is performed on the branch current matrix using the second shifted inverse matrix to obtain a second intermediate result. The second intermediate result is expanded using the Arnoldi iterative algorithm to generate the current region basis vector.
[0022] Preferably, the step of orthogonalizing the voltage region basis vectors and the current region basis vectors to obtain an orthogonalized basis vector set specifically involves:
[0023] The voltage region basis vector and the current region basis vector are processed using a double orthogonalization algorithm. A first orthogonal projection calculation is performed on the voltage region basis vector to obtain a first voltage residual vector. A second orthogonal projection calculation is performed on the first voltage residual vector to obtain orthogonal voltage basis vectors. The first orthogonal projection calculation is performed on the current region basis vector to obtain a first current residual vector. A second orthogonal projection calculation is performed on the first current residual vector to obtain orthogonal current basis vectors. The orthogonal voltage basis vectors and orthogonal current basis vectors are then merged to obtain the orthogonalized basis vector set. The formula for the first orthogonal projection calculation is as follows: ,in Denotes the first residual vector. Represents the current input vector. Indicates a circular index. This represents the sequence number of the current input vector. This represents orthogonal basis vectors. This represents the transpose of the orthogonal basis vectors.
[0024] Preferably, the step of checking the rank deficiency state of the orthogonalized basis vector set, removing redundant basis vectors from the orthogonalized basis vector set, and obtaining the target orthogonal basis vector set specifically includes:
[0025] Explicit rank decomposition is performed on each orthogonalized basis vector in the orthogonalized basis vector set. The vector norm value corresponding to each orthogonalized basis vector is extracted. The machine minimum value is extracted from the computer floating-point arithmetic standard file as a detection threshold. The relationship between the vector norm value corresponding to each orthogonalized basis vector and the detection threshold is compared. When the vector norm value corresponding to each orthogonalized basis vector is less than the detection threshold, it is confirmed that each orthogonalized basis vector is in a numerical rank deficiency state. Each orthogonalized basis vector in the numerical rank deficiency state is marked as a redundant basis vector. The redundant basis vector is deleted from the orthogonalized basis vector set using a dynamic shrinkage mechanism. The block dimension parameter of the orthogonalized basis vector set is updated to obtain the target orthogonal basis vector set.
[0026] Preferably, the step of concatenating the target orthogonal basis vector set to generate the global projection matrix specifically includes:
[0027] Extract the expansion point frequency information corresponding to each target orthogonal basis vector in the target orthogonal basis vector set. Arrange all target orthogonal basis vectors in the target orthogonal basis vector set according to the expansion point frequency information to obtain a sorted basis vector sequence. Concatenate all the target orthogonal basis vectors in the sorted basis vector sequence in the column direction to generate a candidate concatenation matrix. Perform column truncation operation on the candidate concatenation matrix using preset macro model dimension parameters to retain the dominant basis vectors in the first column of the candidate concatenation matrix. Encapsulate the dominant basis vectors to generate the global projection matrix. The global projection matrix satisfies the orthogonal constraint condition that preserves passivity.
[0028] Preferably, the steps of reducing the order of the initial system matrix using the global projection matrix and then connecting it to the circuit simulator to perform transient simulation testing are as follows:
[0029] Calculate the transpose of the global projection matrix, multiply the transpose matrix by the initial system matrix to obtain a first intermediate reduced-order matrix, multiply the first intermediate reduced-order matrix by the global projection matrix, perform congruent transformation to obtain a second intermediate reduced-order matrix, use the second intermediate reduced-order matrix as the macro-model matrix, import the macro-model matrix into the circuit simulator, configure the input excitation source and time step of the circuit simulator, use the circuit simulator to parse the time-domain response data of the macro-model matrix, plot the test waveform based on the time-domain response data, and complete the transient simulation test.
[0030] Compared with the prior art, the advantages and positive effects of the present invention are as follows:
[0031] In this invention, the initial system matrix is obtained by extracting data from the encapsulated interconnect network. The set of resonant frequencies of the initial system matrix is estimated to locate key frequency bands, thereby determining the set of complex plane expansion points to ensure the approximation accuracy of the reduced-order model in the high-frequency region. The state vectors of the initial system matrix are split to generate node voltage matrices and branch current matrices, separating variables with different physical dimensions to avoid ill-conditioned problems in numerical solutions. The set of complex plane expansion points is used to iteratively calculate the node voltage matrix and branch current matrix to generate voltage region basis vectors and current region basis vectors, thereby mining the dynamic response characteristics inside the interconnect network. Orthogonalization processing is performed on the voltage region basis vectors and current region basis vectors to obtain orthogonalized basis vectors. The system first checks the rank deficiency of the orthogonalized basis vector set and removes redundant basis vectors to obtain the target orthogonal basis vector set. This eliminates the linear correlation caused by numerical errors, ensuring the simplification and independence of the basis vectors. The target orthogonal basis vector set is then concatenated to generate a global projection matrix. This global projection matrix is used to reduce the dimension of the initial system matrix, generating a low-order, high-fidelity macro model. This model is then connected to a circuit simulator to perform transient simulation tests. This breaks through the bottleneck of dimensional explosion caused by massive parasitic parameters, compresses the memory space and time overhead required to solve large algebraic equation systems, and achieves a leap in the speed of ultra-large-scale physical field collaborative analysis while maintaining the original electrical functions and performance prediction accuracy. Attached Figure Description
[0032] Figure 1 This is a schematic diagram of the steps of the present invention. Detailed Implementation
[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0034] Please see Figure 1 This invention provides a technical solution, a chip electronic design simulation method, comprising the following steps:
[0035] Extract the encapsulated interconnect network data to obtain the initial system matrix;
[0036] Estimate the set of resonant frequencies of the initial system matrix and determine the set of points for the complex plane expansion;
[0037] The state vectors of the initial system matrix are split to generate the node voltage matrix and the branch current matrix;
[0038] The node voltage matrix and branch current matrix are iteratively calculated using the set of points expanded in the complex plane to generate the basis vectors of the voltage region and the basis vectors of the current region.
[0039] The basis vectors of the voltage region and the basis vectors of the current region are orthogonalized to obtain a set of orthogonal basis vectors.
[0040] Check the rank deficiency state of the orthogonalized basis vector set, remove redundant basis vectors from the orthogonalized basis vector set, and obtain the target orthogonal basis vector set;
[0041] Concatenate the target orthogonal basis vector set to generate a global projection matrix;
[0042] The initial system matrix is reduced in order using a global projection matrix, and then connected to a circuit simulator to perform transient simulation tests.
[0043] In this embodiment, the steps for extracting packaged interconnect network data to obtain the initial system matrix are as follows: obtaining the parasitic parameter extraction file of the target chip, parsing the pin netlist data in the parasitic parameter extraction file, extracting the resistance parameter value, inductance parameter value, capacitance parameter value, and admittance parameter value from the pin netlist data, constructing the resistance block of the circuit network topology based on the resistance parameter value, constructing the inductance block of the circuit network topology based on the inductance parameter value, constructing the capacitance block of the circuit network topology based on the capacitance parameter value, constructing the admittance block of the circuit network topology based on the admittance parameter value, performing node analysis on the resistance block, inductance block, capacitance block, and admittance block based on Maxwell's equations, establishing an interconnect network algebraic equation system, and using the coefficient matrix of the interconnect network algebraic equation system as the initial system matrix.
[0044] Specifically, the parasitic parameter extraction file of the target chip is obtained. This file is recorded in a standard parasitic parameter exchange format and contains millions of node and branch connection relationships defined in netlist form. The pin netlist data in the parasitic parameter extraction file is parsed, specifically by reading the netlist definition line by line, identifying keywords representing resistance, inductance, capacitance, and admittance, and extracting the electrical connection node number and corresponding parameter value that follows. For example, "R123 N1 N2 0.05" is extracted to represent a resistance value of 0.05 ohms between nodes N1 and N2, and "C456 N3 0" is extracted to represent a resistance value of 0.05 ohms between nodes N1 and N2. "1.2e-12" represents a capacitance of 1.2 picofarads between node N3 and ground. All extracted resistance, inductance, capacitance, and admittance parameters are filled into a pre-created zero matrix according to their node connections. The resistance block of the circuit network topology built based on the resistance parameter values forms a sparse symmetric resistance matrix R; the inductance block of the circuit network topology built based on the inductance parameter values forms an inductance matrix L; and the capacitance block of the circuit network topology built based on the capacitance parameter values forms a capacitance matrix C. Based on the admittance parameter... The admittance blocks of the constructed circuit network topology form an admittance matrix G. Based on the integral form of Maxwell's equations and combined with an improved node analysis method, system-level mathematical modeling is performed on the resistive blocks, inductor blocks, capacitor blocks, and admittance blocks. Specifically, Kirchhoff's current law equations describing the conservation of current at all nodes and constitutive equations describing the voltage-current relationship of each branch are combined to establish an interconnection network algebraic equation system. The coefficient matrix of the interconnection network algebraic equation system, that is, the system matrix composed of the capacitance matrix and the conductance matrix, is used as the initial system matrix.
[0045] In this embodiment, the steps for estimating the set of resonant frequencies of the initial system matrix and determining the set of complex plane expansion points are as follows: Eigenvalue decomposition is performed on the initial system matrix to extract its eigenvectors; the pole frequency set of the initial system matrix is calculated using the eigenvectors; complex conjugate poles are selected from the set of pole frequencies; the imaginary part values corresponding to the complex conjugate poles are taken as resonant frequency points; all resonant frequency points are combined to generate a set of resonant frequencies; the response error norm corresponding to each resonant frequency point in the set of resonant frequencies is calculated using the system transfer function tracking algorithm; it is determined whether the response error norm corresponding to each resonant frequency point is greater than a preset accuracy threshold; when the response error norm corresponding to each resonant frequency point is greater than the preset accuracy threshold, expansion points are assigned to each resonant frequency point in the complex plane; all assigned expansion points are merged to generate a set of complex plane expansion points.
[0046] Specifically, eigenvalue decomposition is performed on the initial system matrix. This operation uses the implicit restart Arnoldi algorithm, specifically designed for large sparse matrices, to extract all eigenvalues of the initial system matrix. These eigenvalues constitute the system's poles. The eigenvectors are then used to further calculate the set of pole frequencies of the initial system matrix. Complex conjugate poles are then selected from this set. Specifically, all poles are traversed, and only pole pairs with non-zero imaginary parts are retained. The imaginary part values corresponding to these complex conjugate poles are used as potential resonant frequencies. All selected resonant frequencies are combined to generate the initial set of resonant frequencies. Subsequently, the system frequency set is used... The recursive function tracking algorithm calculates the response error norm corresponding to each resonant frequency point in the resonant frequency set. This process involves calculating the amplitude of the system transfer function at each resonant frequency point and determining whether the response error norm corresponding to each resonant frequency point is greater than a preset accuracy threshold. This preset accuracy threshold is not a fixed value but is dynamically calculated. The method for setting it is as follows: First, calculate the average and standard deviation of all response error norms. Then, set the threshold to the average plus 1.5 times the standard deviation. For example, if the calculated average of a set of response error norms is 0.5 and the standard deviation is 0.2, then the preset accuracy threshold is 0.5 + 1.5 * 0.2 = 0.8. When the response error norm corresponding to each resonant frequency point is greater than the calculated preset accuracy threshold of 0.8, the frequency point is identified as a critical resonant point. In the complex plane, an expansion point is assigned to each resonant frequency point. The allocation method is to offset a small amount along the negative direction of the real axis based on the original purely imaginary frequency point. For example, the resonant point jω is assigned as -0.01+jω. All the assigned expansion points are merged to generate a set of expansion points in the complex plane.
[0047] In this embodiment, the steps of splitting the state vector of the initial system matrix to generate the node voltage matrix and the branch current matrix are as follows: parse the matrix dimensions of the interconnection network algebraic equation system, extract the state vector according to the matrix dimensions, identify the first vector interval describing the node voltage variables in the state vector, identify the second vector interval describing the branch current variables in the state vector, extract the first block matrix from the initial system matrix according to the first vector interval, and use the first block matrix as the node voltage matrix; extract the second block matrix from the initial system matrix according to the second vector interval, and use the second block matrix as the branch current matrix. The node voltage matrix is dominated by the capacitance block and admittance block in the interconnection network algebraic equation system, and the branch current matrix is dominated by the inductance block and resistance block in the interconnection network algebraic equation system.
[0048] Specifically, the matrix dimensions of the interconnect network's algebraic equations are analyzed. For example, if the system contains 10,000 nodes and 5,000 inductor branches, the total dimension of the state vector is 15,000. Based on the matrix dimensions, the complete state vector is extracted. The first vector interval describing node voltage variables is identified, corresponding to the first 10,000 elements of the state vector. The second vector interval describing branch current variables is identified, corresponding to the last 5,000 elements of the state vector. Based on the first vector interval, the first block matrix is extracted from the initial system matrix. This operation does not generate an independent physical matrix, but rather marks the rows and columns in the initial system matrix related to node voltage variables, i.e., the parts mainly contributed by the capacitance and admittance matrices. This logically first block matrix is used as the node voltage matrix. Based on the second vector interval, the second block matrix is extracted from the initial system matrix. Similarly, this operation marks the rows and columns in the initial system matrix that are related to the branch current variables, i.e., the parts mainly contributed by the inductance matrix and the resistance matrix. This logically second block matrix is used as the branch current matrix. The node voltage matrix is dominated by the capacitance block and admittance block in the interconnection network algebraic equation system, and its physical meaning corresponds to the matrix expression of Kirchhoff's current law. The branch current matrix is dominated by the inductance block and resistance block in the interconnection network algebraic equation system, and its physical meaning corresponds to the matrix expression of the relationship between inductor branch voltage and current. Through this division, variables with different physical dimensions are processed separately in subsequent calculations.
[0049] In this embodiment, the steps of iteratively calculating the node voltage matrix and branch current matrix using the complex plane expansion point set to generate voltage region basis vectors and current region basis vectors are as follows: Each complex plane expansion point in the complex plane expansion point set is read; a first shifted inverse matrix of the node voltage matrix is constructed at each complex plane expansion point; a moment matching operation is performed on the node voltage matrix using the first shifted inverse matrix to obtain a first intermediate result; the first intermediate result is expanded using the Arnoldi iterative algorithm to generate voltage region basis vectors; a second shifted inverse matrix of the branch current matrix is constructed at each complex plane expansion point; a moment matching operation is performed on the branch current matrix using the second shifted inverse matrix to obtain a second intermediate result; the second intermediate result is expanded using the Arnoldi iterative algorithm to generate current region basis vectors.
[0050] Specifically, each complex plane expansion point in the set of complex plane expansion points is read, and an iterative loop is entered, performing iterations at each complex plane expansion point. First, for the node voltage part, the first shifted inverse matrix of the node voltage matrix is constructed. This matrix is specifically... Where G and C are the admittance block and capacitance block matrices established in the preceding steps, respectively, the moment matching operation is performed on the node voltage matrix using the first shifted inverse matrix, i.e., an input vector B (usually representing the distribution of the excitation source) is selected, and the product is calculated. The first intermediate result is obtained, which represents the system at the expansion point. The zeroth moment at the given position is then used. Subsequently, the first intermediate result is expanded using the Arnoldi iterative algorithm by repeatedly applying the first shifted inverse matrix to the vector generated in the previous step and orthogonalizing it, thus generating a set of vectors spanning the system. The Krylov subspace basis vectors of the nearby main dynamics are used as part of the basis vectors of the voltage region. Then, in the same iteration step, for the branch current part, at each complex plane expansion point... The second shifted inverse matrix of the branch current matrix is constructed as follows: R and L are the resistance block and inductance block matrices, respectively. The second shifted inverse matrix is used to perform moment matching operation on the branch current matrix to obtain the second intermediate result. The Arnoldi iterative algorithm is used to perform the same expansion process on the second intermediate result to generate the current region basis vector. After iterating through all complex plane expansion points, the voltage region basis vector and current region basis vector generated at each expansion point are summarized.
[0051] In this embodiment, the steps for orthogonalizing the voltage region basis vectors and current region basis vectors to obtain the orthogonalized basis vector set are as follows: The voltage region basis vectors and current region basis vectors are processed using two orthogonalization algorithms respectively. A first orthogonal projection calculation is performed on the voltage region basis vectors to obtain the first voltage residual vector. A second orthogonal projection calculation is performed on the first voltage residual vector to obtain the orthogonal voltage basis vector. A first orthogonal projection calculation is performed on the current region basis vectors to obtain the first current residual vector. A second orthogonal projection calculation is performed on the first current residual vector to obtain the orthogonal current basis vector. The orthogonal voltage basis vectors and orthogonal current basis vectors are merged to obtain the orthogonalized basis vector set. The formula for the first orthogonal projection calculation is: ,in Denotes the first residual vector. Represents the current input vector. Indicates a circular index. This represents the sequence number of the current input vector. This represents orthogonal basis vectors. This represents the transpose of orthogonal basis vectors.
[0052] Specifically, a two-stage orthogonalization algorithm is employed, namely an improved and stable version of the classic Gram-Schmidt orthogonalization process, to process the basis vectors of the voltage region and the current region separately. First, the set of basis vectors of the voltage region is processed by performing the first orthogonal projection calculation, the process of which follows the formula: ,in, This represents the basis vector of the k-th voltage region to be processed. The sequence number of the current input vector, counting from 1. For a circular index from 1 to k-1, This represents the i-th orthogonal voltage basis vector that has been calculated. The inner product within the parentheses represents the transpose of orthogonal basis vectors. Calculate exist The projected length in the direction, the summation term is the length of the projection in the direction. Subtract all projective components over the entire orthogonal subspace, and the calculation result is obtained. This refers to the first voltage residual vector, which is completely orthogonal to the already orthogonal subspace. A second orthogonal projection calculation is then performed on this first voltage residual vector, i.e., the vector is again... For all orthogonal basis vectors Projection is performed and the projected components are subtracted to eliminate the numerical errors accumulated in the first calculation. Then, the residual vector after two corrections is normalized to obtain a new standard orthogonal voltage basis vector. The same orthogonalization process is applied twice to the current region basis vector set to obtain orthogonal current basis vectors. Finally, all the calculated orthogonal voltage basis vectors and orthogonal current basis vectors are merged to obtain the orthogonalized basis vector set.
[0053] In this embodiment, the steps of checking the rank deficiency state of the orthogonalized basis vector set, removing redundant basis vectors from the orthogonalized basis vector set, and obtaining the target orthogonal basis vector set are as follows: Explicit rank decomposition is performed on each orthogonalized basis vector in the orthogonalized basis vector set; the vector norm value corresponding to each orthogonalized basis vector is extracted; the machine minimum value is extracted from the computer floating-point arithmetic standard file as a detection threshold; the relationship between the vector norm value corresponding to each orthogonalized basis vector and the detection threshold is compared; when the vector norm value corresponding to each orthogonalized basis vector is less than the detection threshold, it is confirmed that each orthogonalized basis vector is in a numerical rank deficiency state; each orthogonalized basis vector in a numerical rank deficiency state is marked as a redundant basis vector; redundant basis vectors are deleted from the orthogonalized basis vector set using a dynamic shrinkage mechanism; the block dimension parameter of the orthogonalized basis vector set is updated to obtain the target orthogonal basis vector set.
[0054] Specifically, an explicit rank decomposition is performed on each orthogonalized basis vector in the set of orthogonalized basis vectors. This process involves calculating the Euclidean norm of each vector, which is the square root of the sum of the squares of its elements. The vector norm value corresponding to each orthogonalized basis vector is extracted, and the machine minimum is extracted from the computer floating-point arithmetic standard file as a detection threshold. This machine minimum is a standardized constant jointly determined by the computer hardware and compiler, representing the smallest positive floating-point number that can be distinguished from 1.0. In systems using the IEEE 754 double-precision floating-point standard, this value is typically 1. The algorithm compares the norm of each orthogonalized basis vector with the detection threshold. When the calculated norm of each orthogonalized basis vector is less than the detection threshold (e.g., a vector norm of 1...), the algorithm is considered successful. When, the value is less than If each orthogonalized basis vector has degenerated into a zero vector in a numerical computational sense, and a numerical rank deficiency has occurred, then each orthogonalized basis vector in a numerical rank deficiency state is marked as a redundant basis vector. Using a dynamic shrinkage mechanism, all vectors marked as redundant basis vectors are deleted from the orthogonalized basis vector set, and the block dimension parameter of the orthogonalized basis vector set is updated synchronously. For example, if the original set contains 120 vectors, of which 5 are marked as redundant, then after deletion, the set is updated to contain 115 vectors, and the block dimension parameter is also updated from 120 to 115, thus obtaining the target orthogonal basis vector set.
[0055] In this embodiment, the steps of splicing the target orthogonal basis vector set to generate a global projection matrix are as follows: extract the expansion point frequency information corresponding to each target orthogonal basis vector in the target orthogonal basis vector set; arrange all target orthogonal basis vectors in the target orthogonal basis vector set according to the expansion point frequency information to obtain a sorted basis vector sequence; splice and combine all target orthogonal basis vectors in the sorted basis vector sequence in the column direction to generate a candidate splicing matrix; perform column truncation operation on the candidate splicing matrix using preset macro model dimension parameters; retain the dominant basis vectors in the first column of the candidate splicing matrix; encapsulate the dominant basis vectors to generate a global projection matrix; the global projection matrix satisfies the orthogonal constraint condition of preserving passivity.
[0056] Specifically, the frequency information of the expansion point corresponding to each target orthogonal basis vector in the target orthogonal basis vector set is extracted. This process involves querying the mapping relationship recorded during the iteration calculation in step 4 to find out which complex plane expansion point generated each basis vector and obtaining the frequency value of that expansion point. Based on the expansion point frequency information, all target orthogonal basis vectors in the target orthogonal basis vector set are arranged in ascending order according to the frequency value from low to high, resulting in a sorted basis vector sequence. All target orthogonal basis vectors in the sorted basis vector sequence are then concatenated column-wise according to the ordered sequence to generate a candidate concatenation matrix, where each column represents a target orthogonal basis vector. The candidate concatenation matrix is then processed using preset macromodel dimension parameters. The matrix is then truncated. The preset macro model dimension parameter is set as follows: the user pre-determines the order of the target model to be reduced based on the trade-off between simulation accuracy and speed. For example, if the order is set to 100, then this parameter is 100. The dominant basis vectors in the first 100 columns of the candidate splicing matrix are retained. Since these basis vectors correspond to low frequencies, they usually carry the main energy and information of the system response. The retained dominant basis vectors after truncation are encapsulated to generate the final global projection matrix. This matrix is a tall and narrow matrix, and its column vectors are orthogonal to each other. This orthogonality is the fundamental reason why the subsequent order reduction process can satisfy the orthogonal constraint condition of preserving passivity. The global projection matrix satisfies the orthogonal constraint condition of preserving passivity.
[0057] In this embodiment, the steps of reducing the order of the initial system matrix using the global projection matrix and connecting it to the circuit simulator to perform transient simulation testing are as follows: calculate the transpose of the global projection matrix, multiply the transpose matrix by the initial system matrix to obtain the first intermediate reduced-order matrix, multiply the first intermediate reduced-order matrix by the global projection matrix, perform congruent transformation to obtain the second intermediate reduced-order matrix, use the second intermediate reduced-order matrix as the macro-model matrix, import the macro-model matrix into the circuit simulator, configure the input excitation source and time step of the circuit simulator, use the circuit simulator to analyze the time-domain response data of the macro-model matrix, draw the test waveform based on the time-domain response data, and complete the transient simulation test.
[0058] Specifically, to calculate the transpose of the global projection matrix, let the global projection matrix be V, then calculate its transpose V. Multiply the transpose matrix by the initial system matrix, specifically by multiplying V... Multiplying the capacitance matrix C and admittance matrix G of the initial system matrix by left respectively, we obtain the reduced-order capacitance matrix C. =V CV and the reduced admittance matrix G =V GV, this process is the execution of a congruent transformation, transforming the original high-dimensional system into a low-dimensional subspace spanned by the global projection matrix, where V The calculation process of CV is to first calculate the first intermediate reduced-order matrix V. C, then multiply the result on the right by V to obtain the final second intermediate reduced-order matrix C. The second intermediate reduced-order matrix, namely C and G The transformed input and output matrices, together, form the macro-model matrix. This macro-model matrix is imported into a circuit simulator, such as SPICE, in the form of a network table sub-circuit. The input excitation source of the circuit simulator is configured, such as setting a pulse voltage source with a peak value of 1V and both rising and falling edges of 10 picoseconds. The transient simulation time step is set to 1 picosecond, and the total simulation duration is 5 nanoseconds. The circuit simulator is used to analyze the time-domain response data of the macro-model matrix. The simulator solves the reduced-order small-scale state equations at each time step to obtain the sequence of voltage or current changes of the output node over time. Based on the time-domain response data, the test waveform of the voltage change of the output port over time is plotted to complete the transient simulation test.
[0059] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.
Claims
1. A chip electronic design simulation method, characterized in that, Includes the following steps: Extract the encapsulated interconnect network data to obtain the initial system matrix; Estimate the set of resonant frequencies of the initial system matrix and determine the set of complex plane expansion points; The state vectors of the initial system matrix are split to generate the node voltage matrix and the branch current matrix; The node voltage matrix and the branch current matrix are iteratively calculated using the set of points expanded in the complex plane to generate voltage region basis vectors and current region basis vectors. The voltage region basis vectors and the current region basis vectors are orthogonalized to obtain an orthogonalized basis vector set. Check the rank deficiency state of the orthogonalized basis vector set, remove redundant basis vectors from the orthogonalized basis vector set, and obtain the target orthogonal basis vector set; Concatenate the target orthogonal basis vector set to generate a global projection matrix; The initial system matrix is reduced in order using the global projection matrix, and then connected to a circuit simulator to perform transient simulation tests.
2. The chip electronic design simulation method according to claim 1, characterized in that, The specific steps for extracting the encapsulated interconnect network data to obtain the initial system matrix are as follows: Obtain the parasitic parameter extraction file of the target chip, parse the pin netlist data in the parasitic parameter extraction file, and extract the resistance, inductance, capacitance, and admittance parameter values from the pin netlist data. Based on the resistance parameter values, construct the resistance block of the circuit network topology; based on the inductance parameter values, construct the inductance block of the circuit network topology; based on the capacitance parameter values, construct the capacitance block of the circuit network topology; based on the admittance parameter values, construct the admittance block of the circuit network topology. Perform node analysis on the resistance block, inductance block, capacitance block, and admittance block based on Maxwell's equations to establish an interconnection network algebraic equation system. Use the coefficient matrix of the interconnection network algebraic equation system as the initial system matrix.
3. The chip electronic design simulation method according to claim 1, characterized in that, The specific steps for estimating the set of resonant frequencies of the initial system matrix and determining the set of complex plane expansion points are as follows: Eigenvalue decomposition is performed on the initial system matrix to extract its eigenvectors. The eigenvectors are then used to calculate the set of pole frequencies of the initial system matrix. Complex conjugate poles in the set of pole frequencies are selected, and the imaginary part values corresponding to the complex conjugate poles are taken as resonant frequency points. All the resonant frequency points are combined to generate the set of resonant frequencies. The system transfer function tracing algorithm is used to calculate the response error norm corresponding to each resonant frequency point in the set of resonant frequencies. It is determined whether the response error norm corresponding to each resonant frequency point is greater than a preset accuracy threshold. When the response error norm corresponding to each resonant frequency point is greater than the preset accuracy threshold, expansion points are assigned to each resonant frequency point in the complex plane. All the assigned expansion points are merged to generate the set of expansion points in the complex plane.
4. The chip electronic design simulation method according to claim 2, characterized in that, The specific steps for splitting the state vector of the initial system matrix to generate the node voltage matrix and branch current matrix are as follows: The matrix dimensions of the interconnect network algebraic equations are analyzed, and the state vector is extracted based on the matrix dimensions. A first vector interval describing node voltage variables and a second vector interval describing branch current variables in the state vector are identified. A first block matrix is extracted from the initial system matrix based on the first vector interval, and the first block matrix is used as the node voltage matrix. A second block matrix is extracted from the initial system matrix based on the second vector interval, and the second block matrix is used as the branch current matrix. The node voltage matrix is dominated by the capacitance block and the admittance block in the interconnect network algebraic equations, and the branch current matrix is dominated by the inductance block and the resistance block in the interconnect network algebraic equations.
5. The chip electronic design simulation method according to claim 1, characterized in that, The specific steps for generating voltage region basis vectors and current region basis vectors by iteratively calculating the node voltage matrix and the branch current matrix using the complex plane expansion point set are as follows: Each complex plane expansion point in the set of complex plane expansion points is read. A first shifted inverse matrix of the node voltage matrix is constructed at each complex plane expansion point. Moment matching operation is performed on the node voltage matrix using the first shifted inverse matrix to obtain a first intermediate result. The first intermediate result is expanded using the Arnoldi iterative algorithm to generate the voltage region basis vector. A second shifted inverse matrix of the branch current matrix is constructed at each complex plane expansion point. Moment matching operation is performed on the branch current matrix using the second shifted inverse matrix to obtain a second intermediate result. The second intermediate result is expanded using the Arnoldi iterative algorithm to generate the current region basis vector.
6. The chip electronic design simulation method according to claim 1, characterized in that, The specific steps for orthogonalizing the voltage region basis vectors and the current region basis vectors to obtain the orthogonalized basis vector set are as follows: The voltage region basis vector and the current region basis vector are processed using a double orthogonalization algorithm. A first orthogonal projection calculation is performed on the voltage region basis vector to obtain a first voltage residual vector. A second orthogonal projection calculation is performed on the first voltage residual vector to obtain orthogonal voltage basis vectors. The first orthogonal projection calculation is performed on the current region basis vector to obtain a first current residual vector. A second orthogonal projection calculation is performed on the first current residual vector to obtain orthogonal current basis vectors. The orthogonal voltage basis vectors and orthogonal current basis vectors are then merged to obtain the orthogonalized basis vector set. The formula for the first orthogonal projection calculation is as follows: ,in Denotes the first residual vector. Represents the current input vector. Indicates a circular index. This represents the sequence number of the current input vector. This represents orthogonal basis vectors. This represents the transpose of the orthogonal basis vectors.
7. The chip electronic design simulation method according to claim 1, characterized in that, The specific steps for checking the rank deficiency state of the orthogonalized basis vector set, removing redundant basis vectors from the orthogonalized basis vector set, and obtaining the target orthogonal basis vector set are as follows: Explicit rank decomposition is performed on each orthogonalized basis vector in the orthogonalized basis vector set. The vector norm value corresponding to each orthogonalized basis vector is extracted. The machine minimum value is extracted from the computer floating-point arithmetic standard file as a detection threshold. The relationship between the vector norm value corresponding to each orthogonalized basis vector and the detection threshold is compared. When the vector norm value corresponding to each orthogonalized basis vector is less than the detection threshold, it is confirmed that each orthogonalized basis vector is in a numerical rank deficiency state. Each orthogonalized basis vector in the numerical rank deficiency state is marked as a redundant basis vector. The redundant basis vector is deleted from the orthogonalized basis vector set using a dynamic shrinkage mechanism. The block dimension parameter of the orthogonalized basis vector set is updated to obtain the target orthogonal basis vector set.
8. The chip electronic design simulation method according to claim 1, characterized in that, The specific steps for concatenating the target orthogonal basis vector set to generate the global projection matrix are as follows: Extract the expansion point frequency information corresponding to each target orthogonal basis vector in the target orthogonal basis vector set. Arrange all target orthogonal basis vectors in the target orthogonal basis vector set according to the expansion point frequency information to obtain a sorted basis vector sequence. Concatenate all the target orthogonal basis vectors in the sorted basis vector sequence in the column direction to generate a candidate concatenation matrix. Perform column truncation operation on the candidate concatenation matrix using preset macro model dimension parameters to retain the dominant basis vectors in the first column of the candidate concatenation matrix. Encapsulate the dominant basis vectors to generate the global projection matrix. The global projection matrix satisfies the orthogonal constraint condition that preserves passivity.
9. The chip electronic design simulation method according to claim 1, characterized in that, The specific steps for reducing the order of the initial system matrix using the global projection matrix and then connecting it to the circuit simulator to perform transient simulation testing are as follows: Calculate the transpose of the global projection matrix, multiply the transpose matrix by the initial system matrix to obtain a first intermediate reduced-order matrix, multiply the first intermediate reduced-order matrix by the global projection matrix, perform congruent transformation to obtain a second intermediate reduced-order matrix, use the second intermediate reduced-order matrix as the macro-model matrix, import the macro-model matrix into the circuit simulator, configure the input excitation source and time step of the circuit simulator, use the circuit simulator to parse the time-domain response data of the macro-model matrix, plot the test waveform based on the time-domain response data, and complete the transient simulation test.