Method for identifying sensitization of multi-point growth digital channel in smart meter circuit

Abstract

This invention discloses a method for identifying and sensitizing multi-point growing digital paths in smart meter circuits. First, a directed graph model of the circuit is constructed based on a SPICE netlist, and the power supply state is initialized to obtain different test modes. Then, in each test mode, a multi-point growing parallel search mechanism is employed, starting simultaneously from all MOS transistors whose gates are directly connected to the digital power supply port, dynamically updating the voltage state of each path node and the switching conditions of the MOS transistors. By judging pin state conflicts and path blockages in real time, the actual connected complete digital paths under different digital excitations are accurately identified, thereby obtaining the sensitization results for each test mode. This invention achieves circuit growth through systematic initialization and a dynamic propagation mechanism based on breadth-first search, accurately determining the controlled state of each MOS transistor in the circuit for each given test mode, thus obtaining accurate digital path identification and sensitization results.

Description

Technical Field

[0001] This invention belongs to the field of smart meter technology, and more specifically, relates to a method for identifying and sensitizing multi-point grown digital paths in smart meter circuits. Background Technology

[0002] Smart meters are the core equipment for data acquisition in smart grids. Compared to traditional meters, they not only accurately measure electricity consumption but also possess intelligent functions such as bidirectional rate metering, remote communication, anti-theft, and power quality monitoring, forming the foundation for integrated and optimized management of power information. In the circuit implementation of smart meters, analog electrical signals from the power grid are typically collected first through voltage and current transformers. After conditioning and filtering by the front-end analog circuit, an A / D converter converts the analog signals into digital signals. Subsequently, the digital circuit calculates, analyzes, and stores the converted signals, completing functions such as electricity consumption statistics and data processing. Finally, the digital circuit controls the communication module to transmit the data to the management center, while the analog circuit drives the display screen to present electricity consumption information. Therefore, the smart meter circuit is a typical mixed-signal circuit, and the characteristics of mixed-signal circuits must be considered in the circuit design and verification of smart meters.

[0003] In the current design and verification process of mixed-signal circuits, transistor-level defect simulation is a crucial step in ensuring circuit reliability. However, this step faces a significant bottleneck: the sheer volume of computational demands. For a circuit containing tens of thousands of transistors, the potential set of defects is extremely large. Using traditional methods of injecting and simulating defects one by one, a complete defect simulation could take months or even years, which is unacceptable in engineering practice.

[0004] To reduce simulation time, existing technologies mainly address this from two aspects: first, by reducing the total number of defects to be simulated through defect sampling, but this cannot meet the requirements of high-reliability applications for full defect coverage; second, by reducing the complexity of simulating individual defects through circuit partitioning. However, in mixed-signal circuits, especially complex chips containing multiple power domains and multiple operating modes, digital control signals dynamically change the on / off states of MOSFETs, thus altering the connectivity of signal paths. Traditional Automatic Test Vector Generation (ATPG) methods struggle to effectively handle this dynamic path blocking problem caused by power mode or digital excitation modulation. As a result, a large number of defects existing on non-conducting paths (i.e., "unmeasurable defects") are often included in the simulation scope, resulting in a large amount of ineffective simulation calculations and severely hindering verification efficiency.

[0005] Therefore, there is an urgent need for a method that can quickly and accurately identify the true connectivity of signal paths under different digital excitations before the actual simulation of smart meter circuits begins. Only by identifying the paths that are broken due to specific excitations in advance can defects located on these paths be marked as unmeasurable defects under the current excitation, thereby excluding them from the time-consuming simulation list and fundamentally reducing the number of defects that need to be simulated. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for identifying and sensitizing multi-point growing digital paths in smart meter circuits. The method achieves circuit growth through systematic initialization and a dynamic propagation mechanism based on breadth-first search. For each given test mode, the controlled state of each MOS transistor in the circuit is accurately determined, thereby obtaining accurate digital path identification and sensitization results.

[0007] To achieve the above-mentioned objective, the identification and sensitization method for multi-point grown digital paths in the smart meter circuit of the present invention includes the following steps:

[0008] S1: Based on the SPICE netlist of the smart meter circuit, perform directed dependency graph modeling on the smart meter circuit to obtain the directed dependency graph;

[0009] S2: Divide all power sources in the smart meter circuit into digital power sources and analog power sources, and denote the number of digital power sources as... ;

[0010] S3: Obtain all MOSFETs from the SPICE netlist of the smart meter circuit, remove all MOSFETs whose gate and drain or gate and source are directly connected, and form the initial field-effect transistor set with the remaining MOSFETs. Then, it iterates through all analog power supply ports, identifies and initializes the pin potentials of all MOSFETs whose drain or source is directly connected to the analog power supply, and generates an initial set of field-effect transistors accordingly. Initial state of each MOSFET ,in , Represents the initial field-effect transistor assembly Number of MOSFETs Indicates the drain state. Indicates the gate state. Indicates the source state;

[0011] S4: Set the digital power supply voltage to high or low, and the analog power supply voltage to the default value in the SPICE netlist, to obtain... There are several power value selection modes, among which Each power supply value mode is used as a test mode;

[0012] S5: Based on multi-point distributed growth and dynamic propagation, signal path sensitization is performed on each test mode to obtain the identification sensitization results. The specific method is as follows:

[0013] S5.1: Set the test mode number ;

[0014] S5.2: Set the level of each digital power supply according to the current test mode; initialize all MOSFETs whose gates are directly connected to the digital power supply ports and meet the conduction conditions in the current test mode as the starting point for signal propagation, add them to the set of MOSFETs to be analyzed (Stk), and according to the set of field-effect transistors... The test mode generates the state of each MOSFET in the set Stk to be analyzed, and then the MOSFETs in the set Stk to be analyzed are removed from the current set of field-effect transistors. Delete; add all disabled MOSFETs in the current test mode to the disabled MOSFET set. ;

[0015] S5.3: Determine whether there are any MOS transistors whose state can be inferred in the MOS transistor set Stk to be analyzed. If there are, proceed to step S5.4; otherwise, the current test mode sensitization ends and proceed to step S5.9.

[0016] S5.4: Create a processing queue and add all MOS transistors in the set Stk to be analyzed to the processing queue;

[0017] S5.5: Determine if the queue is empty. If it is, return to step S5.3; otherwise, proceed to step S5.6.

[0018] S5.6: Take a MOS transistor from the head of the processing queue and obtain the current state of the MOS transistor, status = [drain, gate, source], where drain represents the drain state, gate represents the gate state, and source represents the source state.

[0019] S5.7: If the drain state and source state of the current MOSFET are known, then further determine whether the drain state and source state are consistent. If they are consistent, then the current MOSFET is determined to be successfully sensitized, it is removed from the set of MOSFETs to be analyzed Stk, and the node sensitization state is updated. If there is a state conflict, then the conflict information is recorded, and the current MOSFET is removed from the set of MOSFETs to be analyzed Stk.

[0020] If the drain and source states of the current MOSFET are both unknown, then the current MOSFET is put back to the end of the processing queue.

[0021] If the state of either the drain or source of the current MOSFET is known, then the unknown state is inferred based on the known state, and the state of the MOSFET in the set Stk to be analyzed is updated; then the current MOSFET is marked as successfully sensitized, and it is removed from the set Stk to be analyzed.

[0022] S5.8: Check whether the drain or source state of the current MOSFET has changed in step S5.7. If it has not changed, no operation is performed. If it has changed, find all other MOSFETs connected to the changed port to form a set of MOSFETs to be grown. Update the set of MOSFETs to be analyzed (Stk) and the current set of field-effect transistors. The state of each MOS transistor to be grown;

[0023] Traversal growth of MOS transistor assembly For each MOSFET to be generated, if the current state change of the MOSFET causes the gate of the MOSFET to be generated to meet the conduction condition, then the MOSFET to be generated is added to the processing queue and the set of MOSFETs to be analyzed, Stk, and removed from the current set of field-effect transistors. Delete; if the current state change of the MOSFET causes the MOSFET to be grown to be turned off in a controlled manner, then add the MOSFET to be grown to the set of turned-off MOSFETs. ;

[0024] Then return to step S5.5;

[0025] S5.9: Output the voltage state of each voltage node on all sensitizable digital paths in the current test mode or the gate state of the corresponding MOS transistor to obtain the identification sensitization result;

[0026] S5.10: Determine if If yes, proceed to step S5.11; otherwise, the smart meter circuit identification sensitization ends.

[0027] S5.11: Order Return to step S5.2.

[0028] The present invention discloses a multi-point growth-type digital path identification and sensitization method in smart meter circuits. First, a directed graph model of the circuit is constructed based on a SPICE netlist, and the power supply state is initialized to obtain different test modes. Then, in each test mode, a multi-point growth-type parallel search mechanism is employed, starting simultaneously from all MOS transistors whose gates are directly connected to the digital power supply port, dynamically updating the voltage state of each path node and the switching conditions of the MOS transistors. By judging pin state conflicts and path blockages in real time, the actual connected complete digital path under different digital excitations is accurately identified, thereby obtaining the sensitization results for each test mode.

[0029] The present invention has the following beneficial effects:

[0030] 1) This invention can accurately determine the controlled state of each MOS transistor in the circuit for each given test mode and dynamically update the node voltage. Finally, it identifies the actual connected digital path under the power supply excitation corresponding to the test mode. This process provides a key basis for quickly screening and eliminating unmeasurable defects before simulation, and is expected to greatly improve the efficiency of transistor-level defect simulation in smart meter circuits.

[0031] 2) This invention breaks through the limitations of traditional single-path sensitization algorithms. It significantly improves the efficiency of path analysis through multi-point parallelism and dynamic updates, and does not require the participation of circuit simulators, providing an efficient solution for the testability design of large-scale smart meter circuits. Attached Figure Description

[0032] Figure 1 This is a flowchart illustrating a specific implementation of the identification and sensitization method for multi-point grown digital paths in the smart meter circuit of the present invention.

[0033] Figure 2 This is an example diagram of a mixed-signal circuit in this embodiment;

[0034] Figure 3 yes Figure 2 The circuit shown is a schematic diagram of the field-effect transistor initialization.

[0035] Figure 4 This is a flowchart of the signal path sensitization based on multi-point distributed growth and dynamic propagation in this invention;

[0036] Figure 5 yes Figure 2 An example diagram of the sensitization process in the circuit shown;

[0037] Figure 6 yes Figure 2 The sensitization results of the circuit shown are illustrated.

[0038] Figure 7 This is the bandgap circuit diagram in this embodiment. Detailed Implementation

[0039] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.

[0040] Example

[0041] Figure 1This is a flowchart illustrating a specific implementation of the identification and sensitization method for multi-point grown digital paths in the smart meter circuit of this invention. (See flowchart for example.) Figure 1 As shown, the specific steps of the identification and sensitization method for multi-point grown digital paths in the smart meter circuit of the present invention include:

[0042] S101: Directed Dependency Graph Modeling:

[0043] Based on the SPICE netlist of the smart meter circuit, a directed dependency graph model is performed on the smart meter circuit to obtain the directed dependency graph.

[0044] S102: Voltage source classification:

[0045] All power sources in the smart meter circuit are divided into digital power sources and analog power sources. The number of digital power sources is denoted as . The specific method for classifying voltage sources in this embodiment is as follows: Traverse each voltage source in the directed dependency graph, and determine whether the voltage source is connected to the gate of a MOSFET after removing the resistor that provides protection for the voltage source. If so, it indicates that the voltage source directly controls the switching state of the MOSFET, and the voltage source is determined to be a digital power supply; otherwise, the voltage source is determined to be an analog power supply, which is typically used to provide bias or operating voltage for analog modules. Since actual smart meter circuits are quite complex, for ease of description, this embodiment uses a simple mixed-signal circuit as an example for illustration. Figure 2 This is an example diagram of a mixed-signal circuit in this embodiment. For example... Figure 2 As shown, we can divide the power supply into a digital power supply set {V1, V2, V3, V4} and an analog power supply set {VCC, VSS}.

[0046] S103: Field-effect transistor initialization:

[0047] Obtain all MOSFETs from the SPICE netlist of the smart meter circuit, remove all MOSFETs whose gate and drain or gate and source are directly connected, and form the initial field-effect transistor set with the remaining MOSFETs. This allows for the exclusion of devices with specific connection structures. Then, all analog power supply ports are iterated through, and the pin potentials of all MOSFETs whose drain or source is directly connected to the analog power supply are identified and initialized, thereby generating an initial set of field-effect transistors. Initial state of each MOSFET ,in , Represents the initial field-effect transistor assembly Number of MOSFETs Indicates the drain state. Indicates the gate state. This indicates the source state.

[0048] Figure 3yes Figure 2 The circuit shown is illustrated with a schematic diagram of the field-effect transistor initialization. Figure 3 As shown, the initial field-effect transistor assembly is constructed. The set is {M1_P, M2_P, M3_P, M4_P, M5_N}. Iterate through all analog power supply ports and update the MOSFET states in the set. If the D pin of a MOSFET M1 is connected to the analog power supply VDD, then update the pin state to high, i.e., from M1(D, G, S) → M1(high, G, S). If it is connected to the analog power supply VSS, then update the state to low, i.e., from M1(D, G, S) → M1(low, G, S).

[0049] S104: Test Mode Generation:

[0050] Different test modes are generated based on the voltage source classification. The specific method is as follows:

[0051] Set the voltage of the digital power supply to high or low, and the voltage of the analog power supply to the default value in the SPICE netlist, to obtain... Each power supply value pattern, among which Each power supply value mode is treated as a test mode. In other words, all combinations of digital power supply level states constitute a test mode, used to simulate different digital control logics of mixed-signal circuits.

[0052] Similarly Figure 2 Taking the circuit shown as an example, since the digital power supply set is {V1, V2, V3, V4}, the test vector [0,0, 0, 0] represents the test mode where the digital power supply is at a low level and the analog power supply is at its default value.

[0053] S105: Signal pathway sensitization based on multi-point distributed growth and dynamic propagation:

[0054] Signal path sensitization is performed on each test mode based on multi-point distributed growth and dynamic propagation to obtain identification sensitization results.

[0055] Figure 4 This is a flowchart illustrating the signal path sensitization based on multi-point distributed growth and dynamic propagation in this invention. For example... Figure 4 As shown, the specific steps of signal path sensitization based on multi-point distributed growth and dynamic propagation in this invention include:

[0056] S401: Set the test mode sequence number ;

[0057] S402: Initialize data:

[0058] Set the level of each digital power supply according to the current test mode. Use all digital power supplies as the starting point for signal propagation, and then set the current MOSFET assembly... All MOSFETs whose gates are directly connected to the digital power supply port and meet the conduction conditions (high level turns on NMOS, low level turns on PMOS) in the current test mode are initialized to the active state, added to the MOSFET set Stk to be analyzed, and then analyzed according to the field-effect transistor set. The test mode generates the state of each MOSFET in the set Stk to be analyzed, and then the MOSFETs in the set Stk to be analyzed are removed from the current set of field-effect transistors. Delete. Add all disabled MOSFETs (e.g., high level turns off PMOS, low level turns off NMOS) in the current test mode to the set of disabled MOSFETs. .

[0059] S403: Determine whether there are any MOS transistors whose state can be inferred in the MOS transistor set Stk to be analyzed. If there are, proceed to step S404; otherwise, the current test mode sensitization ends and proceed to step S409.

[0060] S404: Create a processing queue:

[0061] Create a processing queue and add all MOS transistors in the set Stk to be analyzed to the processing queue.

[0062] S405: Determine if the processing queue is empty. If it is, return to step S403; otherwise, proceed to step S406.

[0063] S406: Read MOSFET status:

[0064] Take a MOS transistor from the head of the processing queue and obtain its current state status = [drain, gate, source], where drain represents the drain state, gate represents the gate state, and source represents the source state.

[0065] S407: Update MOSFET sensitization status:

[0066] If the drain state and source state of the current MOSFET are known, then it is further determined whether the drain state and source state are consistent. If they are consistent, the current MOSFET is determined to be successfully sensitized, it is removed from the set of MOSFETs to be analyzed Stk, and the node sensitization state is updated. If there is a state conflict, the conflict information is recorded, and the current MOSFET is removed from the set of MOSFETs to be analyzed Stk.

[0067] If the drain and source states of the current MOSFET are both unknown, the current MOSFET is placed back at the end of the processing queue, waiting for its state to be updated by subsequent propagation.

[0068] If the state of either the drain or source of the current MOSFET is known (e.g., drain is known, source is unknown), then the unknown state is inferred from the known state (source state ← drain state), and the state of that MOSFET in the set Stk to be analyzed is updated. Then, the current MOSFET is marked as successfully sensitized and removed from the set Stk to be analyzed.

[0069] S408: Dynamic Propagation

[0070] Check whether the drain or source state of the current MOSFET has changed in step S407. If it has not changed, no operation is performed. If it has changed, identify all other MOSFETs connected to the changed port to form a set of MOSFETs to be grown. Update the set of MOSFETs to be analyzed (Stk) and the current set of field-effect transistors. The state of each MOS transistor to be grown.

[0071] Traversal growth of MOS transistor assembly For each MOSFET to be generated, if the current state change of the MOSFET causes the gate of the MOSFET to meet the conduction condition (e.g., the MOSFET to be generated is an NMOS and the gate becomes high), then the MOSFET to be generated is added to the processing queue and the set of MOSFETs to be analyzed, Stk, and removed from the current set of field-effect transistors. The signal path is "grown" by deleting the MOSFET; if the current state change of the MOSFET causes the MOSFET to be grown to be turned off in a controlled manner, then the MOSFET to be grown is added to the set of turned-off MOSFETs. .

[0072] Then return to step S405.

[0073] S409: Output the sensitization result of the current test mode:

[0074] Output the voltage state of each voltage node on all sensitizable digital paths in the current test mode, or the gate state of the corresponding MOS transistor, to obtain the identification and sensitization results.

[0075] S410: Determine if If yes, proceed to step S411; otherwise, the smart meter circuit identification sensitization ends.

[0076] S411: Order Return to step S402.

[0077] As described above, this invention employs hierarchical state propagation. Starting from the digital power supply, the signal (high or low) of the digital power supply is propagated along the direction of the directed edge according to a breadth-first search strategy. This continues until the set of MOS transistors to be analyzed, Stk, is empty in the current test mode. In this case, the signal can no longer propagate forward through any of the conducting MOS transistors, and the path reaches its end. Alternatively, if the pin states at both ends of all MOS transistors in the set Stk to be analyzed are unknown, it indicates that the signal has not been effectively transmitted to these MOS transistors on the current branch (i.e., the signal has not been "conducted"), making it impossible to determine their state. The propagation then naturally ends, and the dynamic propagation terminates.

[0078] Similarly Figure 2 Taking a circuit as an example, this paper explains the specific process of signal path sensitization based on multi-point distributed growth and dynamic propagation. Figure 5 yes Figure 2 The diagram shows an example of the sensitization process in the circuit shown. Figure 5 As shown, firstly, an initial set of field-effect transistors φ={M1, M2, M3, M4, M5} is obtained. Then, MOSFETs whose gates are connected to the digital power supply and meet the conduction condition are added to the set of MOSFETs to be analyzed, Stk. Therefore, the set of MOSFETs to be analyzed, Stk={M1_P, M2_P, M3_P, M4_P}. Starting from these points, signal flow begins. Starting with M1_P, the signal flows to the "1" endpoint, the state is updated to high, M5_N's gate is turned on, and it is added to the set of MOSFETs to be analyzed, Stk. The propagation termination rule is checked. In the set of MOSFETs to be analyzed, M2_P and M3_P have a known state at one of their ports. M2_P is then taken out for signal propagation. The signal flows to the "3" endpoint, the state is updated to high, the propagation termination rule is checked again, and in the set of MOSFETs to be analyzed, M3_P and M5_N have a known state at one of their ports. Thus, the algorithm continues to execute until the end. Figure 6 yes Figure 2 The sensitization results of the circuit shown are illustrated.

[0079] To better illustrate the technical solution of the present invention, specific examples are used to simulate and verify the present invention.

[0080] This embodiment uses the bandgap reference circuit in the Benchmark reference circuit as an example for illustration. Figure 7 This is the bandgap circuit diagram in this embodiment. (For example...) Figure 7 As shown, the bandgap circuit can be used with a maximum voltage of 2.5V and a minimum voltage of 0V. The method of this invention is used to sensitize the bandgap circuit for digital path identification, and the specific process is as follows:

[0081] STEP 1: Based on the SPICE netlist of the bandgap circuit, first model the circuit as a directed dependency graph.

[0082] STEP 2: Locate the three voltage sources in the circuit using keywords. Remove the protection resistors of these three voltage sources in the directed dependency graph. At this point, S3 is connected to the gate of a MOS transistor, so it is determined to be a digital power supply. S2 and S1 do not have this connection method, so they are determined to be analog power supplies.

[0083] STEP 3: Analyze the bandgap netlist to obtain all MOSFETs, remove devices with specific connection structures, and construct the initial MOSFET set. Then, iterate through all analog power supply interfaces, and for this circuit, generate an initial set of field-effect transistors (FETs) for S2 and S1. The initial state of each MOSFET.

[0084] STEP 4: The digital power supply S3 can be adjusted to high or low to generate different test patterns. In test mode 1, power supply S3 is at high voltage, and power supplies S2 and S1 are at their default values. In test mode 2, power supply S3 is at low voltage, and power supplies S2 and S1 are at their default values.

[0085] STEP 5: Under a specific test pattern, the identification and sensitization method of the multi-point grown digital path is used to identify and sensitize circuit devices with digital characteristics. This ultimately yields the voltage levels of each node in the bandgap circuit's digital path and the controlled on / off status of each MOSFET's gate.

[0086] The present invention is used to calculate the voltage levels of each node in the digital path of the Bandgap circuit, and then the correctness is verified by simulation using an HSPICE simulator. Table 1 is a comparison table of the node voltages determined by the present invention and the simulated voltages under test mode 1 in this embodiment.

[0087] XI79.net064 low 45.2223u XI79.net011 high 2.5000 XI79.net016 low 1.9040u XI79.net013 low 1.9040u XI79.net068 high 2.5000 XI79.net078 high 2.5000 XI79.net077 high 2.5000 bg low 7.3742u

[0088] Table 1

[0089] As shown in Table 1, it can be seen that the voltage levels of the digital path nodes obtained by this invention are the same as those simulated, demonstrating high accuracy in calculating the voltage levels of digital path voltage nodes.

[0090] Similarly, this invention can also identify MOS transistors whose gates are controlled by digital power supply to be turned on or off during the sensitization process. The correctness of this identification is then verified using an HSPICE simulator, taking test mode 1 with S3 high voltage and the simulated power supply set to default values ​​as an example. For PMOS transistors, when Vgs < Vth, the PMOS is on; otherwise, it is off. Vth is determined by the characteristics of the PMOS transistor (generally a negative number close to 0; in this example, Vth = -0.4V). For NMOS transistors, when Vgs > Vth, the NMOS is on; otherwise, it is off. Vth is determined by the characteristics of the NMOS transistor (generally a positive number close to 0; in this example, Vth = 0.4V). Table 2 compares the MOS gate on / off states determined by this invention with the simulation results under test mode 1 in this embodiment.

[0091] M80.XI79 (PMOS) Deadline 0.00>-0.4 Deadline M86.XI79 (PMOS) Deadline 0.00>-0.4 Deadline M27.XI79 (PMOS) Deadline 0.00>-0.4 Deadline M71.XI79 (PMOS) Deadline 2.21>-0.4 Deadline M63.XI79 (PMOS) Deadline 0.00>-0.4 Deadline M87.XI79 (PMOS) Deadline 0.00>-0.4 Deadline M79.XI79 (PMOS) Deadline 0.00>-0.4 Deadline M59.XI79 (PMOS) Deadline 0.02>-0.4 Deadline M83.XI79 (PMOS) Deadline 0.00>-0.4 Deadline M60.XI79 (PMOS) Deadline 0.02>-0.4 Deadline M89.XI79 (PMOS) Deadline 0.00>-0.4 Deadline M88.XI79 (PMOS) Deadline 0.00>-0.4 Deadline M56.XI79 (PMOS) Deadline 0.00>-0.4 Deadline M50.XI79 (PMOS) Deadline 0.00>-0.4 Deadline M76.XI79 (PMOS) Deadline 0.00>-0.4 Deadline M90.XI79 (PMOS) Conductivity -2.50<-0.4 Conductivity M70.XI79 (PMOS) Conductivity -2.50<-0.4 Conductivity M84.XI79 (PMOS) Conductivity -2.50<-0.4 Conductivity M75.XI79 (PMOS) Conductivity -2.50<-0.4 Conductivity M61.XI79 (NMOS) Deadline 0.00<0.4 Deadline M48.XI79 (NMOS) Deadline 0.00<0.4 Deadline M69.XI79 (NMOS) Deadline 0.00<0.4 Deadline M72.XI79 (NMOS) Deadline -1.65<0.4 Deadline M49.XI79 (NMOS) Deadline 0.00<0.4 Deadline M68.XI79 (NMOS) Deadline -1.65<0.4 Deadline M73.XI79 (NMOS) Deadline -0.01<0.4 Deadline M62.XI79 (NMOS) Conductivity 2.50>0.4 Conductivity M55.XI79 (NMOS) Conductivity 2.50>0.4 Conductivity M65.XI79 (NMOS) Conductivity 2.50>0.4 Conductivity M74.XI79 (NMOS) Conductivity 2.50>0.4 Conductivity

[0092] Table 2

[0093] As shown in Table 2, the on / off states of the MOS transistors obtained by the present invention are completely consistent with the simulated on / off states of the MOS transistors, which shows that the present invention also has high accuracy in identifying the on / off states of MOS transistors in digital paths.

[0094] Furthermore, to demonstrate the identification sensitization efficiency of the present invention, this embodiment uses the method disclosed in Chinese invention patent with the title "" and application number "" as a comparison method, comparing the algorithm speed of the present invention on two mixed-signal circuits (Bandgap circuit and LDO circuit). Table 3 is a comparison table of the algorithm speed of the present invention and the comparison method in this embodiment.

[0095] Bandgap 0.010s 0.002s 80% LDO 0.193s 0.034s 82.4%

[0096] Table 3

[0097] As shown in Table 3, since the present invention obtains relevant information of digital paths in mixed-signal circuits without simulation by a simulator, the algorithm speed can be improved by more than 80% compared with the comparison method, thereby greatly improving time efficiency. Thus, in the actual large-scale design and verification of smart meter circuits, it can effectively help relevant personnel to quickly and accurately analyze the impact of different patterns on digital paths in smart meter circuits at the transistor level.

[0098] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.

Claims

1. A method for identifying and sensitizing multi-point grown digital paths in a smart meter circuit, characterized in that, Includes the following steps: S1: Based on the SPICE netlist of the smart meter circuit, perform directed dependency graph modeling on the smart meter circuit to obtain the directed dependency graph; S2: Divide all power sources in the smart meter circuit into digital power sources and analog power sources, and denote the number of digital power sources as... ; S3: Obtain all MOSFETs from the SPICE netlist of the smart meter circuit, remove all MOSFETs whose gate and drain or gate and source are directly connected, and form the initial field-effect transistor set with the remaining MOSFETs. Then, it iterates through all analog power supply ports, identifies and initializes the pin potentials of all MOSFETs whose drain or source is directly connected to the analog power supply, and generates an initial set of field-effect transistors accordingly. The initial state of each MOSFET; ,in , Represents the initial field-effect transistor assembly Number of MOSFETs Indicates the drain state. Indicates the gate state. Indicates the source state; S4: Set the voltage of the digital power supply to high or low, and the voltage of the analog power supply to the default value in the SPICE netlist, to obtain... There are several power value selection modes, among which Each power supply value mode is used as a test mode; S5: Based on multi-point distributed growth and dynamic propagation, signal path sensitization is performed on each test mode to obtain the identification sensitization results. The specific method is as follows: S5.1: Set the test mode number ; S5.2: Set the level of each digital power supply according to the current test mode; initialize all MOSFETs whose gates are directly connected to the digital power supply ports and meet the conduction conditions in the current test mode as the starting point for signal propagation, add them to the set of MOSFETs to be analyzed (Stk), and according to the set of field-effect transistors... The test mode generates the state of each MOSFET in the set Stk to be analyzed, and then the MOSFETs in the set Stk to be analyzed are removed from the current set of field-effect transistors. Delete; add all disabled MOSFETs in the current test mode to the disabled MOSFET set. ; S5.3: Determine whether there are any MOS transistors whose state can be inferred in the MOS transistor set Stk to be analyzed. If there are, proceed to step S5.4; otherwise, the current test mode sensitization ends and proceed to step S5.

9. S5.4: Create a processing queue and add all MOS transistors in the set Stk to be analyzed to the processing queue; S5.5: Determine if the queue is empty. If it is, return to step S5.3; otherwise, proceed to step S5.

6. S5.6: Take a MOS transistor from the head of the processing queue and obtain the current state of the MOS transistor, status = [drain, gate, source], where drain represents the drain state, gate represents the gate state, and source represents the source state. S5.7: If the drain state and source state of the current MOSFET are known, then further determine whether the drain state and source state are consistent. If they are consistent, then the current MOSFET is determined to be successfully sensitized, it is removed from the set of MOSFETs to be analyzed Stk, and the node sensitization state is updated. If there is a state conflict, then the conflict information is recorded, and the current MOSFET is removed from the set of MOSFETs to be analyzed Stk. If the drain and source states of the current MOSFET are both unknown, then the current MOSFET is put back to the end of the processing queue. If the state of either the drain or source of the current MOSFET is known, then the unknown state is inferred based on the known state, and the state of the MOSFET in the set Stk to be analyzed is updated; then the current MOSFET is marked as successfully sensitized, and it is removed from the set Stk to be analyzed. S5.8: Check whether the drain or source state of the current MOSFET has changed in step S5.

7. If it has not changed, no operation is performed. If it has changed, find all other MOSFETs connected to the changed port to form a set of MOSFETs to be grown. Update the set of MOSFETs to be analyzed (Stk) and the current set of field-effect transistors. The state of each MOS transistor to be grown; Traversal growth of MOSFET assembly For each MOSFET to be generated, if the current state change of the MOSFET causes the gate of the MOSFET to be generated to meet the conduction condition, then the MOSFET to be generated is added to the processing queue and the set of MOSFETs to be analyzed, Stk, and removed from the current set of field-effect transistors. Delete; if the current state change of the MOSFET causes the MOSFET to be grown to be turned off in a controlled manner, then add the MOSFET to be grown to the set of turned-off MOSFETs. ; Then return to step S5.5; S5.9: Output the voltage state of each voltage node on all sensitizable digital paths in the current test mode or the gate state of the corresponding MOS transistor to obtain the identification sensitization result; S5.10: Determine if If yes, proceed to step S5.11; otherwise, the smart meter circuit identification sensitization ends. S5.11: Order Return to step S5.

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2. The identification and sensitization method for multi-point grown digital paths in a smart meter circuit according to claim 1, characterized in that, The specific method for classifying voltage sources in step S2 is as follows: traverse each voltage source in the directed dependency graph, and determine whether the voltage source is connected to the gate of the MOS transistor after the resistor that provides protection for the voltage source is removed. If so, determine that the voltage source is a digital power supply; otherwise, determine that the voltage source is an analog power supply.

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