Chip power supply systems and methods, electronic devices, and computer-readable storage media

Abstract

This application provides a chip power supply system and method, an electronic device, and a computer-readable storage medium. The chip power supply system includes a multi-core chip, multiple power supply modules, and at least one power controller. The multi-core chip includes N partitions, with each partition including at least two cores. The N power supply modules are configured in a one-to-one correspondence with the N partitions. The power controller is connected to at least one power supply module and is used to control the connected power supply module to convert the received voltage into the voltage required by the core. The output terminal of each power supply module is electrically connected to the core in its corresponding partition, and the power supply module is used to convert the received voltage into the voltage required by the core in its corresponding partition. By partitioning the cores of the multi-core chip for power supply, the number of power supply modules can be reduced, and the packaging difficulty of the multi-core chip can be lowered. Different voltages can be provided to the cores in different partitions.

Description

[0001] This application is a divisional application. The original application has the application number 202111006683.8 and the original application date is August 30, 2021. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip technology, and in particular to a chip power supply system and method, electronic device, and computer-readable storage medium. Background Technology

[0003] Fifth generation mobile communication technology (5G) th The development of applications such as next-generation mobile networks (5G) and artificial intelligence (AI) requires network chips to provide stronger switching and processing capabilities, as well as central processing units (CPUs) and AI chips to provide more powerful computing capabilities. This inevitably leads to these chips requiring greater current and voltage when operating.

[0004] How to reasonably provide greater current and voltage to chips in operation has become an urgent problem to be solved in this field. Summary of the Invention

[0005] This application provides a chip power supply system and method, an electronic device, and a computer-readable storage medium.

[0006] Firstly, this application provides a chip power supply system, including a multi-core chip, multiple power supply modules, and at least one power controller. The multi-core chip includes N partitions, each partition including at least one core. At least some of the N partitions include at least two cores in each partition. The N power supply modules are configured one-to-one with the N partitions. The power controller is connected to at least one power supply module and is used to control the connected power supply module to convert the received voltage into the voltage required by the core. The output terminal of each power supply module is electrically connected to the core in its corresponding partition, and the power supply module is used to convert the received voltage into the voltage required by the core in its corresponding partition. By partitioning the cores of the multi-core chip for power supply, on the one hand, the number of power supply modules can be reduced, lowering the packaging difficulty of the multi-core chip; on the other hand, a high-current power supply can be divided into multiple low-current power supplies, reducing the core power supply current of the multi-core chip, reducing current jumps, and correspondingly reducing the dynamic power drop amplitude; furthermore, different voltages can be provided to the cores in different partitions, and different power supply adjustments can be made to the cores in different partitions.

[0007] In one implementation of the first aspect, one side of the chip includes multiple power supply contacts, and the power supply contacts corresponding to the core in any partition form a power supply contact group; the output terminal of the power supply module is electrically connected to the power supply contacts in the power supply contact group of its corresponding partition. The core is partitioned by grouping the power supply contacts.

[0008] In one implementation of the first aspect, the chip power supply system further includes: a printed circuit board (PCB) and at least one copper sheet; a multi-core chip is disposed on one side of the PCB and electrically connected to the PCB; at least a portion of the copper sheet is attached to the side of the PCB opposite to the multi-core chip; wherein, at least a portion of the power supply contact group has power supply contacts electrically connected to corresponding power supply modules through through-holes in the PCB and the copper sheet. The copper sheet can improve the heat dissipation of the PCB and the multi-core chip.

[0009] In one implementation of the first aspect, the power contacts in one power supply contact group are electrically connected to the corresponding power supply module through vias or blind vias in the printed circuit board, while the power contacts in another power supply contact group are electrically connected to the corresponding power supply module through copper sheets. This improves the heat dissipation of the printed circuit board and multi-core chip, and also reduces the design difficulty and workload of the printed circuit board.

[0010] In one implementation of the first aspect, the N partitions include a first partition and a second partition. The rated voltage of the cores in the first partition is the first voltage, and the rated voltage of the cores in the second partition is the second voltage; the first voltage is greater than the second voltage. When grouping multi-core chips, if the rated voltage of cores within the same partition is the same, then during core computation, the voltage required by cores within the same partition can be the same before and after overclocking. On one hand, the voltage provided by the power supply module to all cores within the same partition will not result in some cores receiving a voltage lower than the required voltage, nor will it result in some cores receiving a voltage higher than the required voltage, thus ensuring the performance of the multi-core chip. On the other hand, since the required voltage of the cores in the partition corresponding to any power supply module is basically the same, the difficulty of voltage conversion by the power supply module can be reduced.

[0011] In one implementation of the first aspect, the highest operating frequency of the kernels in the first partition is greater than that of the kernels in the second partition. Therefore, kernels in the same partition can perform the same type of operation, and since the operation types of kernels in the same partition are the same, the average voltage required for operation by kernels in the partition is basically the same.

[0012] In one implementation of the first aspect, the N partitions include at least two first partitions, and the number of kernels in each first partition is the same. Having the same number of kernels in different first partitions means that high-frequency operating kernels are evenly distributed, reducing the complexity of the power supply module.

[0013] In one implementation of the first aspect, the N partitions include at least two second partitions, and the number of kernels in each second partition is the same. Having the same number of kernels in different second partitions means that low-frequency operating kernels are evenly distributed, reducing the complexity of the power supply module.

[0014] In one implementation of the first aspect, the chip power supply system includes at least two power controllers, each electrically connected to a different power supply module. Having more power controllers allows for better control of multiple power supply modules with different requirements.

[0015] In one implementation of the first aspect, at least two power controllers include a first power controller and a second power controller. In the power supply modules electrically connected to the first power controller, the rated voltage of the core in the corresponding partition of each power supply module is a first voltage. In the power supply modules electrically connected to the second power controller, the rated voltage of the core in the corresponding partition of each power supply module is a second voltage, and the first voltage is greater than the second voltage. Since the cores in the power supply modules controlled by the same power controller have essentially the same performance, a single power controller can easily achieve simultaneous control of multiple power supply modules.

[0016] In a second aspect, this application provides a power supply method for supplying power to a multi-core chip in the chip power supply system provided in the first aspect; the method includes: receiving a power supply service scheduling instruction from the multi-core chip; determining the voltage required by the cores in each partition of the multi-core chip according to the power supply service scheduling instruction; and controlling the power supply modules corresponding to each partition to convert the received voltage into the voltage required by the cores in their respective partitions according to the determined voltages required by the cores in each partition of the multi-core chip.

[0017] In one implementation of the second aspect, the method further includes monitoring the core utilization rate and power consumption and / or temperature of the multi-core chip in each partition of the multi-core chip; determining whether the core utilization rate, power consumption and / or temperature of the multi-core chip in each partition of the chip exceed a threshold; if the core utilization rate in at least one partition reaches the threshold and the power consumption and / or temperature of the multi-core chip does not reach the threshold, then controlling the power supply module corresponding to the at least one partition to increase the output voltage.

[0018] In one implementation of the second aspect, if the core utilization rate in at least one partition does not reach a threshold and the power consumption and / or temperature of the multi-core chip do not reach a threshold, the voltage required by the core in the at least one partition is determined according to the power supply service scheduling instruction.

[0019] Thirdly, this application provides an electronic device including a chip power supply system as provided in the first aspect.

[0020] Fourthly, this application provides a computer-readable storage medium including a stored program, wherein the stored program, when running, controls the device where the computer storage medium is located to execute the method provided in the second aspect. Attached Figure Description

[0021] Figure 1 A schematic diagram of a chip power supply scheme; Figure 2 A schematic diagram of another chip power supply scheme; Figure 3 This is an application scenario diagram corresponding to an embodiment of this application; Figure 4 This is another application scenario diagram corresponding to the embodiments of this application; Figure 5 A schematic diagram of a chip power supply system provided in an embodiment of this application; Figure 6 A schematic diagram of another chip power supply system provided in an embodiment of this application; Figure 7 This is a power supply schematic diagram of a chip power supply system provided in an embodiment of this application; Figure 8 This is a power supply schematic diagram of another chip power supply system provided in an embodiment of this application; Figure 9 This is a power supply schematic diagram of another chip power supply system provided in the embodiments of this application; Figure 10 This is a cross-sectional schematic diagram of a chip power supply system provided in an embodiment of this application; Figure 11 This is a cross-sectional schematic diagram of another chip power supply system provided in an embodiment of this application; Figure 12 This is a power supply schematic diagram of another chip power supply system provided in the embodiments of this application; Figure 13 A power supply diagram of a chip power supply system is provided for an embodiment of this application; Figure 14 A flowchart illustrating a chip power supply method provided in an embodiment of this application; Figure 15A flowchart illustrating another chip power supply method provided in this application embodiment; Figure 16 A flowchart illustrating yet another chip power supply method provided in this application embodiment. Detailed Implementation

[0022] The terminology used in the implementation section of this application is for the purpose of explaining specific embodiments of this application only, and is not intended to limit this application.

[0023] An integrated circuit (IC) is a miniature structure that uses specific processes to interconnect transistors, resistors, capacitors, and inductors, along with their wiring, required for a circuit, and deploys them on at least one semiconductor wafer or substrate to form a miniature structure with the desired circuit function. ICs can include processors, microprocessors, controllers, controller hubs, field-programmable gate arrays (FPGAs), programmable logic arrays (PLAs), microcontrollers, advanced programmable interrupt controllers (APICs), or other semiconductor or electronic devices. In this application, the structure formed after IC packaging is referred to as a chip.

[0024] The bottom of the chip has contacts that serve as input / output terminals for the circuit. These contacts can be soldered onto a printed circuit board, allowing the chip to connect to other chips or devices and transmit signals between them. The contacts on the bottom of the chip can have different functions; for example, they can include signal contacts for transmitting signals and power supply contacts for transmitting voltage.

[0025] The main power supply schemes for the chip are as follows: Figure 1 This is a schematic diagram of a chip power supply scheme. Figure 2 A schematic diagram of another chip power supply scheme.

[0026] Option 1, such as Figure 1 As shown, the power supply module 12' that supplies power to all cores H' in chip 110' is a single power supply module 12'. This power supply module 12' adjusts the received voltage and supplies it to each core H' in chip 110'. This scheme corresponds to a large number of power supply circuits, resulting in a large total supply voltage, thus increasing the difficulty of power supply design. For example, the design difficulty of current sharing for the packaged solder balls increases, the current-carrying design difficulty of the printed circuit board increases, and the number of layers of the printed circuit board increases.

[0027] Option 2, such as Figure 2As shown, a power supply module 12' is designed inside the chip 110' package to supply power to each core H' of the chip 110'. The power supply module 12' converts the voltage provided by the motherboard into the voltage required by its corresponding core H'. For example, if the voltage provided by the motherboard is 1.8V, and the voltage required by one core H' of the chip 110' is 0.9V, then the power supply module 12' corresponding to that core H' can convert the 1.8V voltage to 0.9V and supply it to that core H'. This solution can provide individual power to each core H' of the chip 110', and each power supply system is independently controllable. Therefore, this solution can provide the required voltage to each core H' in the chip 110', and can provide an adjusted voltage to the core H' whose performance changes when the performance of the core H' in the chip 110' changes. However, this solution includes multiple power supply modules 12', which makes the design of packaging multiple power supply modules 12' and the chip 110' simultaneously more difficult, increases the semiconductor processing difficulty, and increases the packaging cost of the chip 110'.

[0028] With the development of information and communication technologies, the requirements for the processing performance of chip 110' are becoming increasingly higher. However, the improvement of chip 110' performance will lead to an increase in the number of cores and the core voltage of chip 110', which will further increase the power supply design difficulty of Scheme 1, and further increase the packaging difficulty and cost of Scheme 2.

[0029] Furthermore, improving the processing performance of chip 110' typically affects the supply voltage of at least some of the cores H' within chip 110'. For example, when overclocking to improve the performance of some cores H' of chip 110', it is necessary to increase the supply voltage of those cores H'. During the transient changes in the operation of chip 110' between high and low loads, the power supply voltage surges or drops significantly. Solution 1's power supply scheme cannot quickly respond to changes in the operation of chip 110', resulting in excessively high surge voltages that shorten the lifespan of chip 110', or excessively high voltage drops that prevent the supply voltage from meeting the minimum voltage requirements of chip 110', causing it to crash. Although Solution 2 can quickly provide the corresponding voltage for performance changes of each core H' in chip 110', its power supply design complexity increases due to the inclusion of more power supply modules 12'.

[0030] This application provides a chip power supply system and a chip power supply method to solve the above problems.

[0031] The chip power supply system and chip power supply method provided in this application embodiment can be applied to at least the following two scenarios. Figure 3 This is an application scenario diagram corresponding to an embodiment of this application. Figure 4 This is another application scenario diagram corresponding to the embodiments of this application.

[0032] With the rapid development of technologies such as big data, IoT, AI, and 5G, higher demands are being placed on cloud computing power, which in turn is driving the rapid development of server-related technologies. For example... Figure 3 As shown, the chip power supply system 10 and chip power supply method provided in this application embodiment can be applied to a server motherboard. The server motherboard, as the carrier of high-performance servers, includes chips that are the brain of the server. The chips of the server motherboard not only need to have good compatibility, interchangeability, and expandability, but also need to have extremely high stability. In addition to the chip power supply system 10, the server motherboard also includes a power input terminal 20, an interface card connector 30, and a memory module 40.

[0033] AI is being widely used in a variety of applications, but with the rapid development of AI technology and applications, traditional processors are no longer sufficient to meet the computing power requirements of AI. Therefore, AI processor modules have emerged. For example... Figure 4 As shown, the chip power supply system 10 and the chip power supply method provided in this application embodiment can be applied to AI processor modules. The chips in the AI ​​processor module need to perform a large amount of computation and inference, thus requiring high power consumption and stability. In addition to the chip power supply system 10, the AI ​​processor module also includes a power and signal connector 20'.

[0034] Figure 5 This is a schematic diagram of a chip power supply system provided in an embodiment of this application. Figure 6 This is a schematic diagram of another chip power supply system provided in an embodiment of this application.

[0035] This application provides a chip power supply system 10, such as... Figures 5-7 As shown, it includes a multi-core chip 110, multiple power supply modules 12 and at least one power controller 13.

[0036] The multi-core chip 110 includes multiple cores (Cores) H. Specifically, the multi-core chip 110 can be a multi-die multi-core chip or a single-die multi-core chip. In this embodiment, the cores are independent processing units packaged within the multi-core chip 110.

[0037] In this application, the multi-core chip 110 includes multiple partitions 11, and each partition 11 includes at least one core H, such as Figure 5-6 As shown, the chip 110 in the chip power supply system 10 provided in this application includes N partitions 11, and the N partitions 11 are partition 111, ..., partition 11N, where N is a positive integer greater than or equal to 2. That is to say, this application groups the multiple cores H in the multi-core chip 110.

[0038] Furthermore, in at least some of the partitions 11 in the multi-core chip 110, each partition 11 includes at least two cores H, that is, at least two cores H are assigned to the same partition 11. In other words, after grouping the multiple cores H in the multi-core chip 110, at least one group includes multiple cores H.

[0039] In one implementation, all partitions 11 include at least two kernels H. In another implementation, some partitions 11 include at least two kernels H, while some partitions 11 include only one kernel H.

[0040] The power supply module 12 is configured to correspond to the partition 11. Specifically, multiple power supply modules 12 can be configured to correspond one-to-one with multiple partitions 11, such as... Figure 5-6 As shown, the chip power supply system 10 provided in this application includes N power supply modules 12, which are power supply modules 121, ..., 12N, respectively. Power supply modules 121, ..., 12N correspond one-to-one with partitions 111, ..., 11N. The output terminal of each power supply module 12 is electrically connected to the core H in its corresponding partition 11, and the power supply module 12 is used to convert the voltage it receives into the voltage required by the core H in its corresponding partition 11.

[0041] Furthermore, the power controller 13 is electrically connected to at least one power supply module 12, and the power controller 13 controls the corresponding electrically connected power supply module 12 to convert the voltage received by the power supply module 12 into the voltage required by the core. For example, as Figure 5 As shown, the power supply module 121 receives a voltage of 1.6V. The core H in partition 111 requires a voltage of 0.8V. The power controller 13 controls the power supply module 121 to convert the received 1.6V voltage to 0.8V and supply it to the core H in partition 111. The core in partition 11N requires a voltage of 0.4V. The power supply module 12N controlled by the power controller 13 converts the received 1.6V voltage to 0.4V and supplies it to the core H in partition 11N.

[0042] By partitioning the core H in the multi-core chip for power supply, on the one hand, the number of power supply modules 12 can be reduced, and the packaging difficulty of the multi-core chip can be reduced; on the other hand, the high current power supply can be divided into multiple low current power supplies, which reduces the size of the core power supply current of the multi-core chip, reduces the current jump drop, and correspondingly reduces the dynamic drop amplitude of the power supply; furthermore, different voltages can be provided to the core H in different partitions 11, and different power supply adjustments can be made to the core H in different partitions 11.

[0043] In this embodiment, a power controller 13 can control multiple power supply modules 12 to perform voltage conversion. A power supply module 12 can provide voltage for multiple cores H in a partition 11, and different power supply modules 12 provide voltage for cores H in different partitions 11.

[0044] Among them, multiple partitions 11 include a first partition and a second partition. The rated voltage of the kernel H in the first partition is the first voltage, and the rated voltage of the kernel H in the second partition is the second voltage, and the first voltage is greater than the second voltage. For example, partition 111 is the first partition, partition 11N is the second partition, and the rated voltage of the kernel H set in partition 111 is greater than the rated voltage of the kernel H in partition 11N.

[0045] Specifically, the cores H in the chip can be grouped according to the highest frequency they can operate at. Cores H that can operate at higher frequencies can perform high-performance computing tasks, which require higher operating voltages, so they can be grouped into the first partition. Cores H that can only operate at lower frequencies can perform ordinary computing tasks, which require lower operating voltages, so they can be grouped into the second partition.

[0046] In other words, the highest operating frequency of each kernel H in the first partition is greater than the highest operating frequency of each kernel H in the second partition.

[0047] Furthermore, kernels H located in the same partition 11 have the same operation type. For example, kernels H in the same partition 11 are all used for high-performance computing, and / or, kernels H in the same partition 11 are all used for scheduling computing.

[0048] In this embodiment of the application, a power controller 13 can control multiple power supply modules 12 to convert the received voltage into the voltage required by the kernel H in the corresponding multiple partitions 11.

[0049] When the multi-core chip 110 is grouped, if the cores H in the same partition 11 perform the same type of operation, then the voltage required by the power supply module 12 for all cores H in the same partition 11 is basically the same, and the voltage required by all cores H in the same partition 11 after overclocking the multi-core chip 110 remains basically the same. On the one hand, the voltage provided by the power supply module 12 for all cores H in the same partition 11 will not result in some cores H receiving a voltage lower than the required voltage, nor will it result in some cores H receiving a voltage higher than the required voltage, thus ensuring the performance of the multi-core chip 110; on the other hand, since the voltage required by the cores H in the partition 11 corresponding to any power supply module 12 is basically the same, the difficulty of voltage conversion by the power supply module 12 can be reduced.

[0050] Furthermore, since multiple cores H can be grouped according to the operation type of core H in the multi-core chip 110, the number of partitions 11 is less than the number of cores H. Therefore, the number of power supply modules 12 corresponding to partitions 11 is less than the number of cores H. Thus, the design difficulty of power supply modules 12 is reduced, thereby reducing the design difficulty of the chip power supply system.

[0051] In this embodiment, the power supply module 12 may include a transistor switch. The input terminal of the transistor switch receives voltage, and its output terminal is electrically connected to multiple cores H in the partition 11 corresponding to the power supply module 12. The control terminal is electrically connected to the power controller 13. The power controller 13 controls the switching of the transistor switch on and off. Furthermore, the voltage output of the power supply module 12N can be controlled by controlling the on-time of the transistor switch in the power supply module 12N.

[0052] In the chip power supply system 10 provided in the embodiments of this application, such as Figure 5 As shown, the number of power controllers 13 can be one.

[0053] In the chip power supply system 10 provided in the embodiments of this application, such as Figure 6 As shown, the number of power controllers 13 can also be multiple, and different power controllers 13 are electrically connected to different power supply modules 12. For example, the chip power supply system 10 includes M power controllers 13, where M is a positive integer greater than or equal to 2, and the M power controllers 13 are power controller 131, ..., power controller 13M. For example, power controller 131 is electrically connected to power supply modules 121, ..., power supply modules 12i, and power supply modules 121, ..., power supply modules 12i provide voltage to the core H in partitions 111, ..., partitions 11i, respectively, where 11 < i ≤ 2; power controller 13M is electrically connected to power supply modules 121k, ..., power controller 12N, and power supply modules 12k, ..., power supply modules 12N provide voltage to the core H in partitions 11k, ..., partitions 11N, respectively, where k < i ≤ N.

[0054] When the chip power supply system 10 includes M power controllers 13, at least one power controller 13 is electrically connected to multiple power supply modules 12. Furthermore, among the multiple power supply modules 12 electrically connected to the same power controller 13, the core H in the corresponding partition 11 of each power supply module 12 has the same or similar computing performance; therefore, the voltage required by the core H in these partitions 11 is also basically the same or similar.

[0055] The plurality of power controllers 13 includes a first power controller and a second power controller. In the power supply modules 12 electrically connected to the first power controller, the rated voltage of the core H in the corresponding partition 11 of each power supply module 12 is a first voltage; in the power supply modules 12 electrically connected to the second power controller, the rated voltage of the core H in the corresponding partition 11 of each power supply module 12 is a second voltage, and the first voltage is greater than the second voltage. That is, the power supply modules 12 controlled by the first power controller are all power supply modules 12 that provide voltage to the core H in the first partition, and the power supply modules 12 connected to the second power controller are all power supply modules 12 that provide voltage to the core H in the second partition.

[0056] In the multi-core chip 110, the type of operation that the core H participates in is usually determined based on the performance of the core H. When the core H in the partition 11 to which multiple power supply modules 12, which are electrically connected to the same power controller 13, have the same or similar performance, that is, when the rated voltage is the same, the power controller 13 can easily control the power supply modules 12 to convert the received voltage and output the same or similar voltage.

[0057] Figure 7 This is a power supply schematic diagram of a chip power supply system provided in an embodiment of this application. Figure 8 This is a power supply schematic diagram of another chip power supply system provided in an embodiment of this application. Figure 9 This is a power supply schematic diagram of another chip power supply system provided in the embodiments of this application.

[0058] In one embodiment of this application, the multiple partitions 11 in the multi-core chip 110 include at least two first partitions, and the kernels H included in the at least two first partitions are all high-performance computing cores.

[0059] In one implementation, all partitions 11 are the first partition, such as... Figure 7 As shown, partitions 111 to 11N are all the first partition, and kernel H in partitions 111 to 11N are all high-performance computing kernels.

[0060] For example, for a balanced multi-core chip 110, the number of cores H can be evenly distributed so that the number of cores H in each partition 11 is equal. Figure 7 As shown, each partition 11 contains j cores.

[0061] In one implementation, all partitions 11 also include at least one second partition, and the kernel H included in the second partition is a scheduling operation kernel, that is, the kernel H in some partitions 11 of the multiple partitions 11 of the multi-core chip 110 is a scheduling operation kernel.

[0062] For example, such as Figure 8As shown, partition 111 is the second partition, and kernel H in partition 111 is the scheduling kernel; partitions 112 to 11n are the first partitions, and kernel H in partitions 112 to 11n is the high-performance kernel. Further, as... Figure 8 As shown, the multi-core chip 110 has only one core as the scheduling core, while the other cores are used as high-performance cores. The scheduling core in this multi-core chip 110 is located in one partition 11, and all other high-performance cores are evenly grouped into multiple partitions 11. For example, ... Figure 8 As shown, each partition 11 includes j high-performance computing cores.

[0063] For example, such as Figure 9 As shown, partitions 111 and 11(n-1) are the second partitions, and the kernel H in partitions 111 and 11(n-1) is the scheduling kernel. The kernel H in the other partitions is the high-performance kernel, and each partition 11 can include the same number of j high-performance kernels. Partitions 112 to 11n are the first partitions, and the kernel H in partitions 112 to 11n is the high-performance kernel.

[0064] In addition, such as Figure 9 As shown, when the multi-core partition 11 includes multiple second partitions, the number of scheduling cores in each second partition can also be the same, such as each second partition including 1 scheduling core.

[0065] In the embodiments of this application, such as Figures 7-9 As shown, the number of high-performance computing cores is the same in each of the first partitions.

[0066] Figure 10 This is a cross-sectional schematic diagram of a chip power supply system provided in an embodiment of this application. Figure 11 This is a cross-sectional schematic diagram of another chip power supply system provided in an embodiment of this application.

[0067] In one embodiment of this application, such as Figure 10 and Figure 11 As shown, the multiple power supply modules 12 in the chip power supply system 10 can be arranged on the outside of the chip package structure.

[0068] In this embodiment, as Figure 7 and Figure 8 As shown, the chip power supply system 10 also includes a printed circuit board 15. The power controller 13, the power supply module 12 and the multi-core chip 110 can all be mounted on the printed circuit board 15. The power controller 13 controls the power supply module 12 to perform voltage conversion through the printed circuit board 15, and the power supply module 12 outputs voltage to the multi-core chip 110 through the printed circuit board 15.

[0069] In addition, a plurality of power supply contacts 110a are provided on one side of the multi-core chip 110. The power supply contacts 110a are soldered to the printed circuit board 15, and the power supply contacts 110a receive the voltage output by the power supply module 12 through the printed circuit board 15 and transmit the received voltage to the core H in the multi-core chip 110.

[0070] Furthermore, the multiple power supply contacts 110a are divided into multiple power supply contact groups, each power supply contact group including at least one power supply contact 110a. The multiple power supply contact groups are configured one-to-one with multiple partitions 11, and the power supply contacts in a power supply contact group are the power supply contacts for the core H in the partition corresponding to that power supply contact group. Then, the power supply module 12 outputs voltage to the multi-core chip 110 through the printed circuit board 15. Specifically, the power supply module 12 outputs the required voltage to the core H in the corresponding partition 11 by electrically connecting the printed circuit board 15 to the corresponding power supply contact 110a in the power supply contact group.

[0071] In one implementation, the power supply module 12 is electrically connected to the power supply contact 110a in the corresponding power supply contact group via a via or a blind via in the printed circuit board 15. For example, as... Figure 10 As shown, the power supply module 12 and the multi-core chip 110 are respectively disposed on opposite sides of the printed circuit board 15, and the power supply module 12 is electrically connected to the power supply contacts 110a in the multiple chips 110.

[0072] In another implementation, such as Figure 11 As shown, the chip power supply system 10 also includes at least one copper sheet 14, at least a portion of which is attached to the side of the printed circuit board 15 facing away from the multi-core chip 110. At least a portion of the power supply contact group has power supply contacts 110a electrically connected to the corresponding power supply module 12 via the copper sheet 14.

[0073] The performance improvement of the multi-core chip 110 leads to an increase in the required supply voltage, and heat dissipation of the chip power supply system is also an urgent problem to be solved. This application improves heat dissipation of the chip power supply system by setting a copper sheet 14 on the back of the printed circuit board 15 on which the multi-core chip 110 is bonded. Furthermore, by electrically connecting part of the power supply module and the power supply contact 110a through the copper sheet 14, the number of through holes and / or blind holes in the printed circuit board 15 can be reduced, and the number of layers and design complexity of the printed circuit board 15 can be reduced.

[0074] Furthermore, the core H in the partition 11 corresponding to the power supply contact 110a that is electrically connected to the power supply module 12 via the copper sheet 14 can be a high-performance computing core.

[0075] In one specific technical solution, the power supply contact 110a corresponding to one of the partitions 11 is electrically connected to the corresponding power supply module 12 through a through hole or a blind hole in the printed circuit board 15, and the power supply contact 110a corresponding to another partition 11 is electrically connected to the corresponding power supply module 12 through a copper sheet 14.

[0076] In one embodiment of this application, the plurality of power supply modules 12 in the chip power supply system 10 may also be disposed inside the chip package structure.

[0077] Figure 12 This is a power supply schematic diagram of another chip power supply system provided in an embodiment of this application. Figure 13 This is a schematic diagram of a chip power supply system provided in an embodiment of this application.

[0078] In this embodiment, the power supply module 12 may include a single-phase power supply circuit 120 or a multi-phase power supply circuit 120.

[0079] It should be noted that, as Figure 12 As shown, each power supply module 12 may include a single-phase power supply circuit 120, or each power supply module 12 may include the same multi-phase power supply circuit 120.

[0080] In addition, such as Figure 13 As shown, the power supply module 12 corresponding to partition 11 containing the high-performance computing kernel H may include a multi-phase power supply circuit 120, and the power supply module 12 corresponding to partition 11 containing the scheduling computing kernel H may include a single-phase power supply circuit 120.

[0081] Figure 14 This is a flowchart illustrating a chip power supply method provided in an embodiment of this application.

[0082] This application also provides a chip power supply method for supplying power to a multi-core chip in any of the chip power supply systems provided in the above embodiments, such as... Figure 14 As shown, the power supply method includes: S1: Receives the power supply service scheduling instruction from the multi-core chip and determines the voltage required by the cores in each partition of the multi-core chip according to the power supply service scheduling instruction.

[0083] The power controller communicates with the multi-core chip. The multi-core chip sends power supply scheduling instructions to the power controller, specifying the voltage required for each partition. The power controller determines the voltage required for each core in each partition of the multi-core chip based on the received power supply scheduling instructions.

[0084] S2: Based on the voltage required by the core of each partition of the multi-core chip, control the power supply module corresponding to each partition to convert the received voltage into the voltage required by the core of its corresponding partition.

[0085] After receiving the power supply service scheduling instruction to power the multi-core chip, the power controller starts the partitioned power supply mode, that is, controls multiple power supply modules to turn on and controls the power supply modules to adjust the voltage output by the power controller to the voltage required by the core in the corresponding partition.

[0086] If the power controller receives a power supply scheduling instruction that requires voltage regulation for all cores, it will activate all power supply modules and control these modules to convert the received voltage. The voltage converted and adjusted by the power supply modules will then be supplied to the cores in each partition of the multi-core chip.

[0087] If the power supply scheduling command received by the single-board management system is to adjust the voltage of some cores, then the power supply modules corresponding to the partitions where those cores reside are activated, and these power supply modules are controlled to convert the received voltage. The voltage converted and adjusted by the power supply modules is then supplied to the cores in the partitions of the multi-core chip. Furthermore, if the power supply scheduling command determines that the voltage required by the cores in other partitions remains unchanged and the corresponding power supply module states remain unchanged, then the states of the power supply modules corresponding to the partitions where other cores do not require voltage adjustment can be kept unchanged.

[0088] It should be noted that the power supply module may include transistors. Therefore, controlling the power supply module corresponding to each partition to convert the received voltage into the voltage required by the core of its corresponding partition means that the power controller controls the turn-on time of the transistors in each power supply module. Different turn-on times of the transistors will result in different voltages.

[0089] Figure 15 A flowchart illustrating another chip power supply method provided in an embodiment of this application.

[0090] In addition, such as Figure 15 As shown, the chip power supply method provided in this application embodiment further includes: S3: Monitors the core utilization rate in each partition of a multi-core chip, as well as the power consumption and / or temperature of the multi-core chip.

[0091] The kernel utilization rate within a partition can indicate the kernel's operational status. If the kernel utilization rate in certain partitions reaches a threshold, it means that these kernels are consistently performing high-performance operations. Therefore, if conditions permit, these consistently high-performance kernels can be overclocked to improve the performance of the multi-core chip.

[0092] The power consumption and temperature of a multi-core chip can indicate whether it is suitable for overclocking. If the power consumption or temperature of the multi-core chip reaches its limit, overclocking is not allowed; if the power consumption and temperature are within the limit, overclocking can be initiated.

[0093] S4: Determine whether the core utilization rate in each partition of the monitored chip, the power consumption of the multi-core chip, and / or the temperature exceed the threshold. If the core utilization rate in at least one partition reaches a threshold and the power consumption and / or temperature of the multi-core chip do not reach a threshold, then the power supply module corresponding to the at least one partition is controlled to increase the output voltage.

[0094] The data on kernel utilization and power consumption and / or temperature of multi-core chips in each monitored partition are analyzed and judged.

[0095] If the core utilization rate of certain partitions in a multi-core chip reaches or exceeds the threshold, and the power consumption and temperature of the multi-core chip do not reach the threshold, then the cores of those partitions can be overclocked; and before overclocking, the power supply module corresponding to those partitions should be controlled to increase the output voltage.

[0096] Furthermore, during and after overclocking, it is still necessary to monitor the power consumption and temperature of the multi-core chip in real time. If the power consumption or temperature reaches a threshold, overclocking should be stopped. For example, if the base frequency of a core in a certain partition is 3GHz, and the core in that partition is overclocked to 3.3GHz, the power consumption and temperature of the multi-core chip have not reached their limits, so the core in that partition can continue to be overclocked. When the core in that partition is overclocked to 3.6GHz, the power consumption and temperature of the multi-core chip are close to the threshold, so overclocking should be stopped. Moreover, the core in that partition will be performing high-performance computing at a 3.6GHz clock speed, and the power consumption of the overclocked core will be much higher than when it is not overclocked.

[0097] If the core utilization rate in at least one partition does not reach the threshold and the power consumption and / or temperature of the multi-core chip do not reach the threshold, the voltage required by the core in that at least one partition is determined according to the power supply service scheduling instruction.

[0098] The data on kernel utilization and power consumption and / or temperature of multi-core chips in each monitored partition are analyzed and judged.

[0099] If the core utilization rate of certain partitions in a multi-core chip does not reach the threshold, and provided that the power consumption and / or temperature of the multi-core chip do not reach the threshold, the required voltage of each partition of the multi-core chip can be determined according to the power supply service scheduling instruction.

[0100] In addition, during the overclocking process, if there are cores in the multi-core chip that do not need to be overclocked, the clock speed of these cores can be reduced or they can be left idle.

[0101] Figure 16 A flowchart illustrating yet another chip power supply method provided in this application embodiment. The following is in conjunction with... Figure 16 The chip power supply method provided in the embodiments of this application is systematically introduced.

[0102] First, since the chip power supply system partitions multiple cores according to the performance of multiple cores in the multi-core chip, and the cores in the same partition have the same operation type, the chip power supply system first initializes the partition power supply according to the operation type of the core, and the power supply of the chip power supply system enters the normal state.

[0103] When the computing performance of a core in a multi-core chip changes, the power controller receives a power supply scheduling instruction from the multi-core chip. The power controller then controls the output voltage of multiple power supply modules, adjusting the voltage of the cores in all partitions according to the power supply scheduling instruction to ensure the cores in the multi-core chip can complete their computations. Once the cores in the multi-core chip have completed their computations, the power controller receives the power supply scheduling instruction again. The chip's power supply system then re-initializes the partitioned power supply according to the core's computation type, and the power supply system returns to its normal state.

[0104] When the chip power supply system is in normal power supply state, the multi-core chip monitors the core utilization rate in each partition and the power consumption and temperature of the multi-core chip in real time or at regular intervals.

[0105] If the kernel utilization rate in a partition does not exceed the threshold, the multi-core chip will monitor the kernel utilization rate in each partition, as well as the power consumption and temperature of the multi-core chip, in real time or periodically.

[0106] If the core utilization rate in a partition exceeds the threshold while the power consumption and temperature of the multi-core chip do not, it indicates that the cores in that partition need to be overclocked and the multi-core chip can be overclocked. Therefore, the voltage of the cores in the overclocking partition is increased to ensure that the cores in the overclocking partition can complete the overclocking, thereby achieving high-performance computing. After the cores in the multi-core chip complete their computation, the power controller will receive the power supply scheduling instruction from the multi-core chip again. The chip power supply system will then initialize the partition power supply according to the core's computation type, and the chip power supply system will return to normal operation.

[0107] In addition, when increasing the voltage of the cores in the overclocking partition, the voltage in the non-overclocking partition can be decreased at the same time, or the state of the cores in the non-overclocking partition can be adjusted to idle, thereby reducing the power consumption of the multi-core chip.

[0108] This application also provides an electronic device, which includes the chip power supply system provided in this application. The electronic device can be a terminal, such as a personal computer, mobile phone, PDA, wearable electronic device, or in-vehicle device. It can also be a network device, such as a switch, router, firewall, base station, wireless access point, or wireless controller. Furthermore, it can be a storage device, such as a storage server or storage array. Finally, it can be a device providing high-performance computing. The various embodiments in this application can be combined with each other without conflict to achieve corresponding technical effects.

[0109] Furthermore, embodiments of this application also provide a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, which, when the stored program is executed, controls the electronic device where the computer storage medium is located to perform the method of any of the above embodiments. The storage medium may be a magnetic disk, an optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0110] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present invention.

[0111] The above description is merely a specific embodiment of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application. The protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A chip power supply system, characterized in that, include: A multi-core chip includes N partitions, each partition including at least one core; at least some of the N partitions include at least two cores in each partition; the N partitions include a first partition and a second partition; all cores in the first partition have the same rated voltage and are all at a first voltage; all cores in the second partition have the same rated voltage and are all at a second voltage; the first voltage is greater than the second voltage; and the highest operating frequency of at least one core in the first partition is greater than the highest operating frequency of at least one core in the second partition. There are N power supply modules, and each of the N power supply modules is configured to correspond one-to-one with one of the N partitions; A power controller, at least one of which is connected to multiple power supply modules among the N power supply modules, and the power controller is used to control the power supply module connected to it to convert the received voltage into the voltage required by the core; The output terminal of the power supply module is electrically connected to the core in the corresponding partition, and the power supply module is used to convert the voltage it receives into the voltage required by the core in the corresponding partition.

2. The chip power supply system according to claim 1, characterized in that, One side of the chip includes multiple power supply contacts, and the power supply contacts corresponding to the kernel in any partition form a power supply contact group; The output terminal of the power supply module is electrically connected to the power supply contact in the power supply contact group of the corresponding partition.

3. The chip power supply system according to claim 2, characterized in that, The chip power supply system also includes: A printed circuit board, wherein the multi-core chip is disposed on one side of the printed circuit board and electrically connected to the printed circuit board; At least one copper sheet, at least a portion of which is attached to the side of the printed circuit board opposite to the multi-core chip; In this configuration, at least some of the power supply contacts in the power supply contact group are electrically connected to the corresponding power supply module through the through holes of the printed circuit board and the copper sheet.

4. The chip power supply system according to claim 3, characterized in that, In one part of the power supply contact group, the power supply contacts are electrically connected to the corresponding power supply module through through holes or blind holes in the printed circuit board, while in another part of the power supply contact group, the power supply contacts are electrically connected to the corresponding power supply module through the copper sheet.

5. The chip power supply system according to claim 4, characterized in that, The N partitions include at least two of the first partitions, and the number of kernels in each of the first partitions is the same.

6. The chip power supply system according to claim 4, characterized in that, The N partitions include at least two of the second partitions, and the number of kernels in each of the second partitions is the same.

7. The chip power supply system according to claim 1, characterized in that, The chip power supply system includes at least two power controllers, each of which is electrically connected to a different power supply module.

8. The chip power supply system according to claim 7, characterized in that, The at least two power controllers include a first power controller and a second power controller; In the power supply modules electrically connected to the first power controller, the rated voltage of the core in the partition corresponding to each power supply module is the first voltage; In the power supply modules electrically connected to the second power controller, the rated voltage of the core in the partition corresponding to each power supply module is the second voltage, and the first voltage is greater than the second voltage.

9. A method for supplying power to a chip, characterized in that, The method is used to supply power to the multi-core chip in the chip power supply system according to any one of claims 1-8; the method includes: Receive power supply service scheduling instructions from a multi-core chip, and determine the voltage required by the cores in each partition of the multi-core chip according to the power supply service scheduling instructions; Based on the voltage required by the core of each partition of the multi-core chip, the power supply module corresponding to each partition is controlled to convert the received voltage into the voltage required by the core of the corresponding partition.

10. The method according to claim 9, characterized in that, The method further includes: Monitor the core utilization rate in each partition of the multi-core chip and the power consumption and / or temperature of the multi-core chip; Determine whether the core utilization rate in each partition of the chip, the power consumption and / or temperature of the multi-core chip exceed the threshold. If the core utilization rate in at least one of the partitions reaches a threshold and the power consumption and / or temperature of the multi-core chip does not reach a threshold, then the power supply module corresponding to the at least one partition is controlled to increase the output voltage.

11. The method according to claim 10, characterized in that, If the utilization rate of the core in at least one of the partitions does not reach a threshold and the power consumption and / or temperature of the multi-core chip does not reach a threshold, then the voltage required by the core in the at least one of the partitions is determined according to the power supply service scheduling instruction.

12. An electronic device, characterized in that, Includes the chip power supply system as described in any one of claims 1-10.

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