A 2.5D packaging design method based on TSV

Abstract

This invention belongs to the field of SiP packaging technology and discloses a 2.5D packaging design method based on TSV. The process is as follows: the FPGA and DSP are flip-chip mounted in the middle layer of the redistribution layer. The FPGA and DSP are bonded to the middle layer of the redistribution layer through upper microbumps, and redistributed through the surface redistribution layer. Electrical interconnection is then achieved through through-silicon vias (TSVs), followed by molding. Subsequently, the FPGA and DSP are bonded to an organic substrate through lower microbumps, and placement and wiring are performed through the organic substrate to form a complete SiP chip. This invention solves the high complexity of FPGA and DSP interconnection, reduces the package geometry and weight, and meets the requirements of multifunctionality and miniaturization. By using TSV vertical interconnection, the interconnect length is reduced, improving the communication speed and bandwidth between various functional modules within the FPGA and DSP, reducing signal delay, solving signal delay problems in 2D technology, and reducing interference.

Description

Technical Field

[0001] This invention belongs to the field of SIP packaging technology and relates to a 2.5D packaging design method based on TSV. Background Technology

[0002] Packaging technology has evolved alongside integrated circuits. Each generation of packaging technology overcomes the packaging defects caused by the increase in the number of I / O pins and the reduction in chip size in integrated circuits. Since the 1960s and 70s, the semiconductor industry has focused on the development of packaging technology. IC packaging can be divided into several stages: through-hole packaging (such as TO and DIP packages), surface mount devices (such as SOP and QFP packages), area array surface mount packaging (such as BGA and CSP packages), and high-density packaging (such as 2.5D packaging and 3D stacking). Each stage of packaging has its specific technical characteristics and advantages. 2.5D is a dimension that does not exist in the objective world because its integration density exceeds 2D but does not reach the integration density of 3D; it is a compromise and is called 2.5D. 2.5D refers to packaging that uses a middle layer for high-density I / O interconnection, characterized by multi-die integration and high density. Currently, silicon is often used for the interposer, utilizing its mature processes and high-density interconnect characteristics. In theory, the middle layer can have TSVs or not. TSVs are vertical interconnect vias that connect the chip to the packaging substrate through hundreds of holes. However, TSVs are indispensable when performing high-density interconnects. Summary of the Invention

[0003] (I) Purpose of the Invention

[0004] The purpose of this invention is to provide a 2.5D packaging design method based on TSV, which addresses the problem of insufficient substrate wiring density during the interconnection packaging of FPGAs and DSPs. Based on 2.5D packaging technology, signal connection is achieved through the interaction between RDL Interposer and organic substrate. Furthermore, the TSV vertical interconnect via technology can improve system integration density, reduce signal delay, and meet the requirements of multifunctionality and miniaturization.

[0005] (II) Technical Solution

[0006] To address the aforementioned technical problems, this invention provides a 2.5D packaging design method based on TSV. The process is as follows: the FPGA and DSP are flip-chip mounted in the middle layer of the redistribution layer. The FPGA and DSP are combined with the middle layer of the redistribution layer through upper microbumps, and redistributed through the surface redistribution layer. They are then electrically interconnected through through-silicon vias (TSVs) and encapsulated. Afterward, they are combined with the organic substrate through lower microbumps, and then layout and wiring are performed through the organic substrate to form a complete SIP chip.

[0007] Furthermore, other chips are mounted on the organic substrate for additional interface interconnection.

[0008] Furthermore, FPGA and DSP chips are arranged side-by-side in the middle layer.

[0009] Furthermore, a through-silicon via (TSV) structure is formed on the middle layer as a channel for electrical connection between the upper and lower surfaces.

[0010] Furthermore, the FPGA and DSP are flip-chipped in the middle layer in the form of FC.

[0011] Furthermore, through-silicon vias (TSVs) are formed by drilling holes in the middle layer using laser etching, wet etching, or deep reactive ion etching techniques.

[0012] Furthermore, an insulating layer is formed inside the through-silicon via (TSV) to prevent leakage or crosstalk between vias.

[0013] Furthermore, an electroplating process is used to fill the through-silicon via (TSV) with copper, tungsten, or polycrystalline silicon metal materials.

[0014] Furthermore, adhesives, metals, or oxides are used to achieve flip-chip bonding of FPGA and DSP chips.

[0015] (III) Beneficial Effects

[0016] The TSV-based 2.5D packaging design method provided by the above technical solution has the following beneficial effects:

[0017] (1) The interconnection design of FPGA and DSP has become a common design method in the field of electronic packaging. This invention can better integrate FPGA and DSP chips to realize the multi-functionality of electronic components, solve the high complexity of FPGA and DSP interconnection, reduce the geometric size and weight of the package, and meet the needs of multi-functionality and miniaturization.

[0018] (2) By using TSV vertical interconnection to reduce interconnection length, improve the communication speed and bandwidth between various functional modules inside the FPGA and DSP, reduce signal delay, solve problems such as signal delay in 2D technology, and reduce interference.

[0019] (3) Using TSV technology for electrical interconnection can improve the heat dissipation of the chip because vertical connection can conduct heat more effectively.

[0020] (4) The current cost situation is severe. Using this invention to design chips can reduce costs. Although TSV technology is expensive, it can reduce the overall system cost because it can achieve high integration and miniaturization. Attached Figure Description

[0021] Figure 1This is a schematic diagram of a 2.5D packaging model based on TSV according to an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0023] 2.5D packaging involves wiring and vias on the interposer layer, and signal connections are achieved through the interaction between the RDL Interposer and TSV with the organic substrate.

[0024] like Figure 1 As shown, the process of the 2.5D packaging design method based on TSV in this embodiment is as follows: the FPGA and DSP are flip-chip mounted in the middle layer of the redistribution layer (RDLInterposer). The FPGA and DSP are combined with the RDLInterposer through the upper microbumps and redistributed through the surface redistribution layer RDL. Then, they are electrically interconnected through through silicon vias (TSVs) and encapsulated. After that, they are combined with the organic substrate through the lower microbumps and then laid out and routed through the organic substrate. Other chips can also be mounted on the organic substrate for additional interface interconnection, finally forming a complete SIP chip.

[0025] In this embodiment, the FPGA and DSP chips are arranged side-by-side on the interposer. Electrical connections between the upper and lower surfaces are established through a TSV structure on the interposer, and redistribution layers (RDLs) are used for rewiring. Microbumps enable higher-density interconnections between chips and between chips and the packaging substrate. This 2.5D integration is suitable for applications with large chip sizes and high pin densities. Chips are typically flip-chip mounted on the interposer in a FC (Flip-Chip) configuration.

[0026] The key technology in this invention is TSV technology. The TSV process requires equipment such as DRIE, CVD, PVD, and CMP. The specific process flow includes:

[0027] 1. Through-hole etching: Drill holes on the interposer using laser etching, wet etching, or deep reactive ion etching techniques.

[0028] 2. An insulating layer is formed inside the silicon via to prevent leakage or crosstalk between vias.

[0029] 3. Use physical vapor deposition and other methods to form a barrier layer and a seed layer.

[0030] 4. Electroplating process is used to fill the through holes with metal materials such as copper, tungsten, and polycrystalline silicon.

[0031] 5. Use adhesives, metals, or oxides to achieve chip flipping and bonding.

[0032] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A 2.5D packaging design method based on TSV, characterized in that, The process is as follows: the FPGA and DSP are flip-chip mounted in the middle layer of the redistribution layer. The FPGA and DSP are combined with the middle layer of the redistribution layer through the upper microbumps, and then redistributed through the surface redistribution layer. They are then electrically interconnected through through-silicon vias (TSVs) and encapsulated. After that, they are combined with the organic substrate through the lower microbumps, and then the organic substrate is used for layout and wiring to form a complete SIP chip.

2. The 2.5D packaging design method based on TSV as described in claim 1, characterized in that, Other chips are mounted on the organic substrate for additional interface interconnection.

3. The 2.5D packaging design method based on TSV as described in claim 2, characterized in that, FPGA and DSP chips are arranged side by side in the middle layer.

4. The 2.5D packaging design method based on TSV as described in claim 3, characterized in that, A through-silicon via (TSV) structure is formed on the middle layer to serve as a channel for electrical connection between the upper and lower surfaces.

5. The 2.5D packaging design method based on TSV as described in claim 4, characterized in that, The FPGA and DSP are flip-chip mounted in the middle layer in the form of FC.

6. The 2.5D packaging design method based on TSV as described in claim 5, characterized in that, Holes are formed in the middle layer by using laser etching, wet etching or deep reactive ion etching techniques to create through silicon vias (TSVs).

7. The 2.5D packaging design method based on TSV as described in claim 6, characterized in that, An insulating layer is formed inside the through-silicon via (TSV) to prevent leakage or crosstalk between vias.

8. The 2.5D packaging design method based on TSV as described in claim 7, characterized in that, The through-silicon via (TSV) is filled with copper, tungsten, or polycrystalline silicon metal material using an electroplating process.

9. The 2.5D packaging design method based on TSV as described in claim 8, characterized in that, FPGA and DSP chips are flip-chip bonded using adhesives, metals, or oxides.

10. A 2.5D packaging model, characterized in that, The packaging design method according to any one of claims 1-9 is used.

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