A wiring rule real-time checking acceleration method and system based on a mask matrix
By adopting a real-time verification method for routing rules based on a mask matrix, the problem of excessively long geometric DRC calculation time in high-density routing is solved. DRC verification with constant time complexity is achieved, accelerating the routing process. It is suitable for modern CPU or GPU architectures and supports inter-layer interconnection in advanced 3D packaging.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING INFORMATION SCI & TECH UNIV
- Filing Date
- 2026-05-11
- Publication Date
- 2026-07-31
AI Technical Summary
In high-density cabling scenarios, existing technologies suffer from significant computational bottlenecks in the design rule checking (DRC) of cabling tools. Traditional floating-point geometric analysis algorithms result in excessive computation time, making them unsuitable for the interlayer interconnection constraints of advanced 3D packaging and unable to achieve online DRC acceleration during the cabling process.
A real-time verification method for routing rules based on a mask matrix is adopted, which transforms the geometric space interference judgment into the Hadamard product and bitwise summation operation of the local matrix, generates a Boolean state tensor map, and selects an appropriate mask matrix for verification, thereby achieving an order-of-magnitude leap in routing speed.
Completely eliminates floating-point geometric calculations, achieves DRC verification with constant-level O(1) time complexity, accelerates the routing process, shortens the design iteration cycle, is suitable for modern CPU or GPU architectures, and supports the interlayer interconnection requirements of advanced 3D packaging.
Smart Images
Figure CN122491196A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic design automation technology, specifically relating to a method and system for accelerating real-time verification of routing rules based on a mask matrix. Background Technology
[0002] In advanced packaging and integrated circuit physical routing, pathfinding algorithms need to perform design rule checks (DRC) frequently when expanding candidate nodes to ensure compliance with electrical and process constraints such as line width, line spacing, and via spacing. Traditional routing tools' DRC modules mostly use floating-point geometric analytical algorithms, such as polygon intersection determination and shortest distance calculation from a point to a line segment. Some solutions introduce machine learning models, but all of these methods have significant computational and resource overhead.
[0003] As the density of heterogeneous integrated interconnects continues to increase, the routing space is discretized into massive grid cells. Frequent geometric floating-point operations within millions of grid nodes will lead to severe computing bottlenecks. The traditional serial execution mode of pathfinding, verification, and correction not only has a long design iteration cycle, but also consumes too much time for local geometric calculations during pathfinding, which significantly restricts routing efficiency.
[0004] Even with existing technologies integrating DRC engines into the routing process, numerous shortcomings remain. Their verification mechanisms still rely on floating-point geometric methods such as point-to-line distance and polygon intersection, resulting in a time complexity of O(n) for a single verification. This efficiency drops drastically in high-density routing scenarios. Furthermore, most solutions only support 2D planar DRC verification, failing to adapt to the inter-layer interconnect constraints of advanced 3D packaging. In addition, existing technologies primarily focus on offline full-layout verification after routing completion, making deep integration with the real-time candidate node evaluation process of routing algorithms difficult, thus failing to solve the challenge of online DRC acceleration during the routing process.
[0005] Therefore, the industry urgently needs an online DRC verification acceleration solution that can perform low-dimensional mapping of complex spatial geometric constraints during the wiring stage and has a constant-level O(1) time complexity. Summary of the Invention
[0006] This invention proposes a real-time verification acceleration method and system for routing rules based on a mask matrix. By transforming geometric space interference determination into the Hadamard product and bitwise summation of local matrices, floating-point geometric calculations are eliminated from the bottom layer, achieving an order-of-magnitude leap in routing speed. This can solve the problem of excessive time consumption for geometric DRC calculations in high-density routing.
[0007] To achieve the above objectives, the technical solution of the present invention includes the following:
[0008] A method for accelerating real-time verification of routing rules based on a mask matrix, the method comprising: Generate a Boolean state tensor map of the encapsulation and routing region; Select a mask matrix based on the physical objects in the candidate mesh nodes; Centered on the candidate grid node, slice and extract the local feature submatrix that is consistent with the mask matrix from the Boolean state tensor map; The verification result of the candidate grid node is obtained based on the mask matrix and the local feature submatrix.
[0009] Further, a Boolean state tensor map of the encapsulation and routing region is generated, including: Generate the mesh structure of the encapsulation and wiring area; The grid values of the physical object and the free grid are initialized to different values to obtain a Boolean state tensor map of the encapsulation and routing region.
[0010] Furthermore, each grid cell of the Boolean state tensor map has several independent data channels; wherein, the data channels include channel 0, channel 1, channel 2, channel 3, channel 4 and channel 5, channel 0 is used to mark data channels for insurmountable fixed obstacles, channel 1 is used to record data channels for currently successfully deployed conductive paths, channel 2 is used to store the via occupancy status of vertical interconnects, channel 3 is used to define areas where routing is prohibited or shielded, channel 4 is used to identify the position of fixed pads, and channel 5 is used to temporarily store the pads of the network currently being routed.
[0011] Furthermore, the process of generating the mask matrix includes: The side length of the mask matrix is calculated based on the physical entity radius, the safety distance required by the process, and the grid side length of the Boolean state tensor map. The numerical weights of the meshes in the mask matrix are set according to the location of the wiring layer and the constraint type.
[0012] Furthermore, the mask matrix includes octagonal mask matrix, circular mask matrix, rectangular mask matrix, annular mask matrix, cylindrical mask matrix, and star mask matrix.
[0013] Further, a mask matrix is selected based on the physical objects in the candidate mesh nodes, including: When the physical object is a via or pad, select a circular mask matrix; When the physical object is a macro module or a hard obstacle, choose an octagonal mask matrix; When the physical object is located in a special constraint region, a rectangular mask matrix, a circular mask matrix, a cylindrical mask matrix, or a star mask matrix is selected according to the design constraints of the special constraint region; wherein, the special constraint region includes a high-frequency signal isolation area.
[0014] Furthermore, based on the mask matrix and the local feature submatrix, the verification result of the candidate grid node is obtained, including: Perform bitwise multiplication of the mask matrix and the local eigenvalue submatrix; The product matrix is summed bit by bit to obtain the verification result of the candidate grid node.
[0015] A real-time verification and acceleration system for routing rules based on a mask matrix, the system comprising: The state tensor map generation module is used to generate Boolean state tensor maps of the encapsulation and routing regions. The mask matrix selection module is used to select a mask matrix based on the physical objects in the candidate mesh nodes; The feature submatrix extraction module is used to extract local feature submatrixes consistent with the mask matrix from the Boolean state tensor map, centered on the candidate grid nodes. The verification module is used to obtain the verification result of the candidate grid node based on the mask matrix and the local feature submatrix.
[0016] A computer device includes: a processor and a memory storing computer program instructions; the processor, when executing the computer program instructions, implements the real-time verification acceleration method for wiring rules based on a mask matrix as described above.
[0017] A computer-readable storage medium, characterized in that the computer-readable storage medium stores computer program instructions, which, when executed by a processor, implement the real-time verification acceleration method for wiring rules based on a mask matrix as described above.
[0018] Compared with the prior art, the present invention has at least the following beneficial effects.
[0019] (1) Completely eliminate floating-point geometric calculations: The traditional complex point-to-polygon distance calculation is reduced to bit operations on N*N local matrices. In modern CPU or GPU architectures, such fixed-length matrix operations can be highly vectorized, and the time cost of a single DRC check is close to the constant level O(1).
[0020] (2) High hardware-level acceleration fit: The matrix-based data structure is naturally suitable for parallel computing and is easily ported to hardware accelerators such as GPUs or FPGAs for execution, providing underlying acceleration feasibility for ultra-large-scale heterogeneous integrated EDA tools.
[0021] (3) Implement design rules in advance: The extremely low verification computing power consumption enables the routing algorithm to perform full DRC checks in real time at each step forward, avoiding the need for dismantling and rerouting in the later stages of routing and greatly shortening the routing convergence time. Attached Figure Description
[0022] Figure 1 Flowchart of a method for accelerating real-time verification of routing rules based on mask matrix.
[0023] Figure 2 Boolean state tensor map of the encapsulation and wiring region.
[0024] Figure 3 Different types of mask matrices.
[0025] Figure 4 Mask matrix library.
[0026] Figure 5 Example diagram of a local submatrix.
[0027] Figure 6 3D interlayer DRC verification.
[0028] Figure 7 Flowchart for obstacle detection.
[0029] Figure 8 Flowchart for via distance verification.
[0030] Figure 9 Running time comparison chart. Detailed Implementation
[0031] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, and to make the objectives, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0032] The present invention discloses a method for accelerating real-time verification of routing rules based on a mask matrix, such as... Figure 1 As shown, it includes the following steps.
[0033] Step S1: Generate a Boolean state tensor map of the package routing region.
[0034] This step is used to realize the meshing of the wiring space and the construction of a strong constraint tensor. The present invention first divides the entire chip or package wiring area into discrete two-dimensional or three-dimensional meshes proportionally, and then initializes the mesh value of the physical objects (obstacles, wired segments, via center points, pad center points) to 1, and initializes the remaining free meshes to 0, thereby constructing a multi-channel Boolean state tensor map for the physical entities in the wiring area. Specifically, each grid cell no longer stores only a single occupancy state, but is expanded to have six independent data channels. These channels work in parallel as Boolean tensors, each responsible for tracking different types of physical entities in real time: Channel 0 is dedicated to marking insurmountable fixed obstacles (Blocks), Channel 1 records currently successfully deployed conductive paths (Paths), Channel 2 stores the occupancy status of vertically interconnected vias (Vias), Channel 3 defines areas where routing is prohibited or shielded, Channel 4 identifies the location of fixed pads (Pads), and Channel 5 serves as a special mechanism specifically for temporarily storing the pads of the currently routing network (Net) itself, so that the avoidance constraints on these pads can be intelligently and temporarily released during algorithm execution to ensure routing connectivity.
[0035] At the macro-level hierarchical architecture, the system instantiates a corresponding number of raster layer objects based on the physical stacking layers of the chip. Taking a three-layer chip as an example, the system initializes three independent raster layer objects (e.g., labeled FL1, FL2, and FL3), which are parallel to each other and do not interfere with each other. Each raster layer object maintains a complete symbolic map raster matrix, which fully inherits the aforementioned six-channel structure. Therefore, the spatial state of the entire chip can be regarded as a three-dimensional Boolean tensor map composed of three stacked layers. Each layer is a six-channel two-dimensional map containing multiple semantic information such as obstacles, paths, and vias, thus obtaining... Figure 2 The Boolean state tensor map shown.
[0036] Step S2: Select a mask matrix based on the physical object of the candidate mesh node.
[0037] (1) Construct a mask library.
[0038] During the routing initialization phase, based on DRC physical rules, taking minimum line width, line spacing, and via diameter as examples, the spatial collision radius is enumerated according to rule thresholds to generate a discretized mask matrix of corresponding size. Different mask matrix topologies are used depending on the verification object. For line-to-line spacing and line-to-obstacle spacing, an octagonal mask matrix is generated to approximate the actual safe distance under diagonal routing; for line-to-via and line-to-pad spacing, a circular mask matrix is generated; and for areas with special constraints, rectangular, annular, cylindrical, star-shaped, and other shaped mask matrices can also be generated. Figure 3In the diagram, (a) is an octagonal mask matrix, (b) is a circular mask matrix, (c) is a rectangular mask matrix, (d) is a ring mask matrix, (e) is a cylindrical mask matrix, and (f) is a star mask matrix.
[0039] These different types of mask matrices constitute a complete mask library, such as Figure 4 As shown, during routing, different mask matrices are dynamically switched based on the location, layer, and constraint type of the current point. The mask matrix is not assigned a traditional single 0 or 1 value; instead, it uses differentiated numerical weights for different routing layers and constraint types. The weight represents the severity of the violation of the corresponding constraint, quantifying the cost of violation and prioritizing decisions when routing is unsolvable.
[0040] In another embodiment, the side length N of the mask matrix is not fixed, but is dynamically determined by the following formula. in, The radius of the physical entity. To ensure the safety distance required by the process, This represents the grid side length.
[0041] (2) Dynamic selection mechanism of mask matrix.
[0042] The mask matrix in this system is selected based on the geometric shape matching of the physical object, but it can also be freely selected according to specific wiring requirements. For example: For via and pad layers: Since vias and pads are typically cylindrical or disk-shaped in physical manufacturing, the system precisely calls a "circular mask matrix". This shape perfectly matches the actual safe spacing of the drilling process, avoiding the waste of diagonal space caused by using a square matrix.
[0043] For macro modules and hard obstacle layers: Obstacles inside the chip are mostly distributed in a rectangular shape, but in high-density routing, it is usually permissible to make 45-degree or 135-degree chamfered routing (diagonal routing) along the corners of obstacles. Therefore, the system calls an "octagonal mask matrix" to approximate the actual safe distance under diagonal routing and maximize space utilization.
[0044] For special constrained areas (such as high-frequency signal isolation areas): special masks such as "ring" and "star" can be dynamically called to form specific forbidden zone shapes.
[0045] Specifically, in this invention, the values at each position within the mask matrix are represented using a non-binary, multi-valued method, transforming spatial violation states into quantifiable penalty costs. The specific assignment logic is directly related to the specific routing algorithm used by the routing engine and design constraints (such as stress, crosstalk, and timing). The matrix operation method described in this invention provides a calculator. The matrix-based verification method proposed in this invention is compatible with and can support penalty cost distributions defined by different algorithms without changing the underlying matrix Hadamard product operation logic. The calculation results... The size of the value directly reflects the severity of the violation at that location.
[0046] Step S3: Using the candidate grid node as the center, slice and extract the local feature submatrix that is consistent with the mask matrix from the Boolean state tensor map.
[0047] During the pathfinding phase of the wiring engine, starting from the starting point, for the currently evaluated candidate mesh node P, there is no need to calculate distance. Instead, the engine directly uses point P as the center and slices out a local feature submatrix from the global state tensor map, which has the same size as the mask matrix. Figure 5 Example diagram of a 5×5 matrix.
[0048] Step S4: Based on the mask matrix and the local feature submatrix, obtain the verification result of the candidate grid node.
[0049] The collision detection and cost output based on matrix operations involves multiplying the submatrix extracted from the slice with the corresponding mask matrix bitwise (Hadamard product operation), and then summing the resulting matrix bitwise. The detection logic is as follows: For local submatrices, Let N be the mask matrix, and N be the side length of the mask matrix. If If the value is greater than 0, then a design rule violation is determined to exist in the corresponding space. The passage cost of the candidate node is set to infinity, and it is removed from the candidate queue. If the value is 0, the node is deemed to meet the design rule check. When the cabling space is extremely congested and there are no fully compliant candidate nodes, a cost tolerance mechanism is activated. A maximum tolerance cost threshold is preset, and the candidate node with the lowest total cost of violation is selected. Low-weight minor violations are tolerated first, while high-weight fatal violations are absolutely prohibited, achieving the optimal trade-off between routing success rate and design compliance.
[0050] In another embodiment, for a three-dimensional multi-layer routing scenario, the two-dimensional state tensor is expanded into a three-dimensional tensor T(x,y,z), where z is the routing layer number. When evaluating candidate nodes (x,y,z), in addition to extracting the local submatrix of the current layer z, the corresponding submatrices of adjacent layers z-1 and z+1 are also extracted simultaneously. These submatrices are then subjected to Hadamard product and bitwise summation with the inter-layer via mask matrix, respectively, to verify the spacing between vias and upper / lower layer traces, and between vias themselves. Similarly, the mask matrix can also be expanded into a three-dimensional tensor. Figure 6 As shown, the 3D mask matrix is an N×N×n cube structure, where the central layer corresponds to the current routing layer, and the upper and lower layers correspond to the adjacent upper and lower routing layers, respectively. During inter-layer verification, the 3D submatrix and the 3D mask matrix are multiplied by a 3D Hadamard product, and all elements are summed to obtain the total cost of inter-layer violations.
[0051] The invention will be further illustrated below through two embodiments.
[0052] Example 1: Rapid verification of the distance between the line and the obstacle.
[0053] The overall process of this embodiment 1 is as follows: Figure 7 As shown, it includes the following steps.
[0054] Step 1: In the global tensor map, the system initializes the grid value of the obstacle to 1, and the surrounding area to blank 0.
[0055] Step 2: Assuming the current process requires a safe distance of 3 grid steps between the line and the obstacle, the system pre-calculates and generates a 7*7 octagonal mask matrix, with the current grid of the line as the center, representing its physical radius plus the safe distance radius.
[0056] Step 3: The pathfinding engine is currently evaluating whether the coordinates (x, y) can be used as the next path node. The system directly extracts a 7x7 submatrix centered at (x, y) from the tensor map.
[0057] Step 4: Multiply the submatrix and the mask matrix bitwise. The sum of all elements in the final matrix is 0. The system instantly determines that the pathfinding at the current node is valid.
[0058] Example 2: A case study on the trade-offs in scenarios where the spacing between lines and vias is non-compliant.
[0059] The overall process of this embodiment 2 is as follows: Figure 8 As shown, it includes the following steps.
[0060] Step 1: In the global 3D state tensor map, the system has mapped the center point coordinates of all deployed vias to the value 1, and the free grid areas outside the vias to the value 0.
[0061] Step 2: Assuming the current process requires a safe distance of 2 grid steps between the line and the via, the system pre-calculates and generates a 5×5 circular multi-value weighted mask matrix based on this rule. Different positions within the mask matrix are assigned differentiated weights according to the severity of the violation, which are used to quantify the violation cost of the line-via distance.
[0062] Step 3: The pathfinding engine currently has two candidate nodes, A and B, to be evaluated. They have the same total cost and are both potential next path nodes. The system takes A and B as the center and cuts out a 5×5 local feature submatrix with the same size as the mask matrix from the global state tensor map.
[0063] Step 4: Perform Hadamard product operations on the local submatrices corresponding to A and B with the circular multivalued weighted mask matrix, and sum the product results bitwise to obtain the total violation cost of the two points: violation cost of point A = 25, violation cost of point B = 33.21.
[0064] Step 5: Since both points A and B have non-zero costs and thus violate regulations, and there are no fully compliant candidate nodes, the system selects point A, which has a lower violation cost, as the final routing node. This minimizes the degree of violation of design rules while ensuring wiring connectivity.
[0065] To verify the performance advantages of the method of the present invention, 60 to 68 sets of advanced packaged netlists of different sizes were selected as test samples to compare the running time of the method of the present invention with that of a mainstream commercial cabling tool.
[0066] Experimental results are as follows Figure 9 As shown, the computation time of a certain commercial software shows a clear linear growth trend with the increase of cabling scale, taking nearly 95 seconds when processing 68 netlists; while the method of the present invention keeps the running time within 10 seconds throughout the entire test range, improving the overall cabling efficiency by more than 8 times.
[0067] In summary, the matrix transformation of real-time DRC during the routing process of this invention transforms the single-candidate node DRC verification in the path search stage of the automatic routing algorithm into the Hadamard product and bitwise summation operation of the local submatrix and the pre-generated mask matrix, achieving constant-level verification with O(1) time complexity.
[0068] The multi-channel Boolean state tensor map construction method of the present invention maps different types of physical entities, such as obstacles, wired segments, vias, pads, and no-wiring areas, as independent channels of tensors, thereby realizing unified management and parallel verification of multiple types of constraints.
[0069] The multi-topology mask matrix pre-generation and matching mechanism of this invention generates octagonal, circular, rectangular and other corresponding topologies for different DRC rules (line-to-line, line-to-via, line-to-pad, line-to-obstacle), which accurately approximate the real physical security distance.
[0070] The interlayer DRC verification extension of the three-dimensional multilayer routing of the present invention extends the two-dimensional tensor into a three-dimensional tensor, supports the spacing verification of cross-layer physical entities, and adapts to the vertical interconnection requirements of three-dimensional advanced packaging.
[0071] Although the present invention has been described through the above preferred embodiments, those skilled in the art will understand that various modifications in form and detail can be made therein without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A method for real-time checking acceleration of wiring rules based on a mask matrix, characterized in that, The method includes: Generate a Boolean state tensor map of the encapsulation and routing region; Select a mask matrix based on the physical objects in the candidate mesh nodes; Centered on the candidate grid node, slice and extract the local feature submatrix that is consistent with the mask matrix from the Boolean state tensor map; The verification result of the candidate grid node is obtained based on the mask matrix and the local feature submatrix.
2. The method according to claim 1, characterized in that, Generate a Boolean state tensor map of the package routing region, including: Generate the mesh structure of the encapsulation and wiring area; The grid values of the physical object and the free grid are initialized to different values to obtain a Boolean state tensor map of the encapsulation and routing region.
3. The method according to claim 1, characterized in that, Each grid cell of the Boolean state tensor map has several independent data channels; wherein, the data channels include channel 0, channel 1, channel 2, channel 3, channel 4 and channel 5, channel 0 is used to mark data channels for insurmountable fixed obstacles, channel 1 is used to record data channels for currently successfully deployed conductive paths, channel 2 is used to store the via occupancy status of vertical interconnects, channel 3 is used to define areas where routing is prohibited or shielded, channel 4 is used to identify the position of fixed pads, and channel 5 is used to temporarily store the pads of the network currently being routed.
4. The method according to claim 1, characterized in that, The process of generating the mask matrix includes: The side length of the mask matrix is calculated based on the physical entity radius, the safety distance required by the process, and the grid side length of the Boolean state tensor map. The numerical weights of the meshes in the mask matrix are set according to the location of the wiring layer and the constraint type.
5. The method according to claim 1, characterized in that, The mask matrix includes octagonal mask matrix, circular mask matrix, rectangular mask matrix, annular mask matrix, cylindrical mask matrix and star mask matrix.
6. The method according to claim 5, characterized in that, Based on the physical objects in the candidate mesh nodes, a mask matrix is selected, including: When the physical object is a via or pad, select a circular mask matrix; When the physical object is a macro module or a hard obstacle, choose an octagonal mask matrix; When the physical object is located in a special constraint region, a rectangular mask matrix, a circular mask matrix, a cylindrical mask matrix, or a star mask matrix is selected according to the design constraints of the special constraint region; wherein, the special constraint region includes a high-frequency signal isolation area.
7. The method according to claim 1, characterized in that, Based on the mask matrix and local feature submatrix, the verification result of the candidate grid node is obtained, including: Perform bitwise multiplication of the mask matrix and the local eigenvalue submatrix; The product matrix is summed bit by bit to obtain the verification result of the candidate grid node.
8. A real-time verification and acceleration system for wiring rules based on a mask matrix, characterized in that, The system includes: The state tensor map generation module is used to generate Boolean state tensor maps of the encapsulation and routing regions. The mask matrix selection module is used to select a mask matrix based on the physical objects in the candidate mesh nodes; The feature submatrix extraction module is used to extract local feature submatrixes consistent with the mask matrix from the Boolean state tensor map, centered on the candidate grid nodes. The verification module is used to obtain the verification result of the candidate grid node based on the mask matrix and the local feature submatrix.
9. A computer device, characterized in that, The computer device includes: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, it implements the real-time verification and acceleration method for wiring rules based on a mask matrix as described in any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions, which, when executed by a processor, implement the real-time verification and acceleration method for wiring rules based on a mask matrix as described in any one of claims 1-7.