Static analysis method and system for circuit layout, electronic device and storage medium

Abstract

This application discloses a static analysis method, system, electronic device, and storage medium for circuit layouts, relating to the field of integrated circuit design technology, which facilitates improved verification efficiency of circuit layouts. The method includes: converting the equivalent resistance value of the standard MOS transistor to the channel width-to-length ratio of the MOS transistor under test (DUT) and a standard MOS transistor to obtain the replacement resistance value of the DUT in the post-simulation netlist, and generating a static simulation netlist; wherein the equivalent resistance value is the on-state equivalent resistance value of the standard MOS transistor during transient switching; applying an excitation signal to the power supply port of the static simulation netlist to perform static simulation, obtaining the voltage drop of the target resistance port corresponding to the replacement resistance value of each DUT; comparing the voltage drop with a preset threshold in a configuration file, and marking the position information of DUTs in the circuit layout whose voltage drops exceed the preset threshold. This application is applicable to scenarios involving MOS port voltage drop checks.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a static analysis method, system, electronic device, and storage medium for circuit layout. Background Technology

[0002] In large-scale integrated circuits, billions of MOS transistors are integrated within the chip. During normal operation, the simultaneous switching of a large number of MOS transistors generates a significant instantaneous resistance voltage drop (IR drop) on the power network. Excessive IR drop can severely impact chip performance, even causing MOS transistor malfunctions and ultimately leading to chip failure. Therefore, checking the MOS port voltage drop has become a critical verification step in integrated circuit design.

[0003] In existing technologies, dynamic simulation is typically used for IR drop analysis. Specifically, after completing the Intellectual Property Core (IP) layout, the IP functionality is analyzed and test stimuli for the corresponding operating states are written. Then, a post-simulation netlist is extracted, and the stimuli are loaded for dynamic simulation. After simulation, the source or drain voltage of the MOSFET is measured and compared with the IR drop threshold. If the threshold is exceeded, the layout is optimized, the netlist is re-extracted, and simulation is repeated iteratively until the requirements are met. However, this approach has limitations in practice: the results of dynamic simulation heavily rely on the completeness of the stimulus file. When the IP functionality is complex, it is difficult to write a stimulus file covering all operating states, leading to missing IR drop analysis for some operating states and potential risks. Furthermore, the post-simulation netlist for large IPs is enormous, and a single dynamic simulation may take several days to complete, failing to effectively shorten the IR drop optimization iteration cycle and resulting in low design verification efficiency. Summary of the Invention

[0004] In view of this, embodiments of this application provide a static analysis method, system, electronic device, and storage medium for circuit layouts, which facilitates improved verification efficiency of circuit layouts.

[0005] In a first aspect, embodiments of this application provide a static analysis method for circuit layout, comprising: converting the equivalent resistance value of the standard MOSFET based on the channel width-to-length ratio of the MOSFET under test and the standard MOSFET to obtain the replacement resistance value of the MOSFET under test in the post-simulation netlist, and generating a static simulation netlist; wherein the equivalent resistance value is the on-state equivalent resistance value of the standard MOSFET during transient switching; applying an excitation signal to the power supply port of the static simulation netlist to perform static simulation, and obtaining the voltage drop of the target resistance port corresponding to the replacement resistance value of each MOSFET under test; comparing the voltage drop with a preset threshold in the configuration file, and marking the position information of the MOSFET under test whose voltage drop exceeds the preset threshold in the circuit layout.

[0006] According to a specific implementation of an embodiment of this application, the configuration information in the configuration file includes: post-simulation netlist file path, simulation process corner, power supply voltage value, PMOS equivalent resistance value, NMOS equivalent resistance value, preset threshold, and the range of MOS transistor cells under test.

[0007] According to a specific implementation of this application, the step of converting the equivalent resistance value of the standard MOS transistor based on the channel width-to-length ratio of the MOS transistor under test and the standard MOS transistor to obtain the replacement resistance value of the MOS transistor under test in the post-simulation netlist includes: obtaining the channel width-to-length ratio of the standard PMOS transistor in the standard cell, and the channel width-to-length ratio of the PMOS transistor under test; using the ratio of the channel width-to-length ratio of the PMOS transistor under test to the channel width-to-length ratio of the standard PMOS transistor as a first coefficient; dividing the equivalent resistance value of the standard PMOS transistor by the first coefficient to obtain the replacement resistance value of the PMOS transistor under test; obtaining the channel width-to-length ratio of the standard NMOS transistor in the standard cell, and the channel width-to-length ratio of the NMOS transistor under test; using the ratio of the channel width-to-length ratio of the NMOS transistor under test to the channel width-to-length ratio of the standard NMOS transistor as a second coefficient; dividing the equivalent resistance value of the standard NMOS transistor by the second coefficient to obtain the replacement resistance value of the NMOS transistor under test.

[0008] According to a specific implementation of an embodiment of this application, the standard MOS transistor is a PMOS transistor or an NMOS transistor in a standard inverter; the on-equivalent resistance value includes the on-equivalent resistance value of the standard PMOS transistor during transient switching or the on-equivalent resistance value of the standard NMOS transistor during transient switching; wherein, the on-equivalent resistance value of the standard PMOS transistor during transient switching includes: applying a falling edge excitation to the input port of the standard inverter to generate a rising edge signal at the output port, and recording the maximum current value on the PMOS transistor, the current source voltage value, and the drain voltage value in the transient simulation; based on the The on-state equivalent resistance of the standard PMOS transistor during transient switching is obtained by taking the maximum current, source voltage, and drain voltage of the PMOS transistor. The on-state equivalent resistance of the standard NMOS transistor during transient switching is obtained by: applying a rising edge excitation to the input port of the standard inverter to generate a falling edge signal at the output port; recording the maximum current, current source voltage, and drain voltage of the NMOS transistor at the current moment during transient simulation; and obtaining the on-state equivalent resistance of the standard NMOS transistor during transient switching based on the maximum current, source voltage, and drain voltage of the NMOS transistor.

[0009] According to a specific implementation of this application, the step of applying an excitation signal to the power supply port of the static simulation netlist to perform static simulation and obtain the voltage drop of the target resistor port corresponding to the replacement resistor value of each of the MOS transistors under test includes: applying a first constant voltage value as a power supply voltage excitation signal to the power supply voltage network connection port of the static simulation netlist, and applying a second constant voltage value as a ground voltage excitation signal to the ground network connection port, wherein the first constant voltage value is the operating voltage and the second constant voltage value is zero voltage; running a simulation tool to perform static simulation on the static simulation netlist after applying the power supply voltage excitation signal; after the simulation is completed, measuring the voltage value of each replacement resistor and the power supply network connection port, taking the difference between the voltage value of the power supply voltage network connection port where the PMOS transistor replacement resistor is located and the first constant voltage value as the power supply voltage drop, and taking the difference between the voltage value of the ground network connection port where the NMOS transistor replacement resistor is located and the second constant voltage value as the ground bounce voltage drop.

[0010] According to a specific implementation of this application, the step of comparing the voltage drop with a preset threshold in the configuration file and marking the location information of the MOSFET under test whose voltage drop exceeds the preset threshold in the circuit layout includes: comparing the measured voltage drop value with the preset threshold in the configuration file one by one, wherein the preset threshold includes a power supply voltage drop threshold and a ground bounce threshold; if the measured power supply voltage drop value of a port of a MOSFET under test is less than or equal to the power supply voltage drop threshold, or if the measured ground bounce voltage drop value of a port of a MOSFET under test is less than or equal to the ground bounce threshold, then it is determined that the voltage drop of the layout area corresponding to the MOSFET under test meets the design requirements; if the measured power supply voltage drop value of a port of a MOSFET under test is greater than the power supply voltage drop threshold, or if the measured ground bounce voltage drop value of a port of a MOSFET under test is greater than the ground bounce threshold, the location information of the MOSFET under test in the circuit layout is marked, and the corresponding layout area is optimized according to the location information; after the layout area optimization is completed, the voltage drop of the resistor port in the remeasured static simulation netlist is compared again with the voltage threshold in the configuration file, until the circuit layout of all MOSFETs under test meets the design requirements.

[0011] Secondly, embodiments of this application provide a static analysis system for circuit layout, comprising: a conversion unit, configured to convert the equivalent resistance value of the standard MOSFET based on the channel width-to-length ratio of the MOSFET under test and the standard MOSFET, to obtain the replacement resistance value of the MOSFET under test in the post-simulation netlist, and generate a static simulation netlist; wherein the equivalent resistance value is the on-state equivalent resistance value of the standard MOSFET during transient switching; a static simulation unit, configured to apply an excitation signal to the power supply port of the static simulation netlist to perform static simulation, and obtain the voltage drop of the target resistance port corresponding to the replacement resistance value of each MOSFET under test; and a determination unit, configured to compare the voltage drop with a preset threshold in a configuration file, and mark the position information of the MOSFET under test in the circuit layout where the voltage drop exceeds the preset threshold.

[0012] According to a specific implementation of an embodiment of this application, the conversion unit includes: a first replacement resistance value module, used to obtain the channel width-to-length ratio of a standard PMOS transistor in a standard unit, and the channel width-to-length ratio of the PMOS transistor under test, using the ratio of the channel width-to-length ratio of the PMOS transistor under test to the channel width-to-length ratio of the standard PMOS transistor as a first coefficient, and dividing the equivalent resistance value of the standard PMOS transistor by the first coefficient to obtain the replacement resistance value of the PMOS transistor under test; and a second replacement resistance value module, used to obtain the channel width-to-length ratio of a standard NMOS transistor in a standard unit, and the channel width-to-length ratio of the NMOS transistor under test, using the ratio of the channel width-to-length ratio of the NMOS transistor under test to the channel width-to-length ratio of the standard NMOS transistor as a second coefficient, and dividing the equivalent resistance value of the standard NMOS transistor by the second coefficient to obtain the replacement resistance value of the NMOS transistor under test.

[0013] According to a specific implementation of an embodiment of this application, the static simulation unit includes: an excitation module, configured to apply a first constant voltage value as a power supply voltage excitation signal to the power supply voltage network connection port of the static simulation netlist, and apply a second constant voltage value as a ground voltage excitation signal to the ground network connection port, wherein the first constant voltage value is the operating voltage and the second constant voltage value is zero voltage; a static simulation module, configured to run a simulation tool to perform static simulation on the static simulation netlist after applying the power supply voltage excitation signal; and a measurement module, configured to measure the voltage value between each replacement resistor and the power supply network connection port after the simulation is completed, and to use the difference between the voltage value of the power supply voltage network connection port where the PMOS transistor replacement resistor is located and the first constant voltage value as the power supply voltage drop, and to use the difference between the voltage value of the ground network connection port where the NMOS transistor replacement resistor is located and the second constant voltage value as the ground bounce voltage drop.

[0014] According to a specific implementation of an embodiment of this application, the determining unit includes: a comparison module, used to compare the voltage drop measurement value with preset thresholds in the configuration file one by one, the preset thresholds including a power supply voltage drop threshold and a ground bounce threshold; a first determination module, used to determine that the voltage drop of the layout area corresponding to the MOSFET under test meets the design requirements if the power supply voltage drop measurement value of a certain MOSFET port is less than or equal to the power supply voltage drop threshold, or if the ground bounce voltage drop measurement value of a certain MOSFET port is less than or equal to the ground bounce threshold; a second determination module, used to mark the position information of the MOSFET under test in the circuit layout if the power supply voltage drop measurement value of a certain MOSFET port is greater than the power supply voltage drop threshold, or if the ground bounce voltage drop measurement value of a certain MOSFET port is greater than the ground bounce threshold, and optimize the corresponding layout area according to the position information; after the layout area optimization is completed, the voltage drop of the resistor port in the remeasured static simulation netlist is compared again with the voltage threshold in the configuration file, until the circuit layout of all MOSFETs under test meets the design requirements.

[0015] Thirdly, embodiments of this application provide an electronic device, the electronic device comprising: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed within the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the static analysis method of the circuit layout described in any of the first aspects.

[0016] Fourthly, embodiments of this application provide a computer-readable storage medium storing one or more computer programs, which, when executed by one or more processors, implement the static analysis method for circuit layout as described in any of the first aspects.

[0017] The static analysis method, system, electronic device, and storage medium for circuit layout provided in this application convert the equivalent resistance value of the standard MOSFET based on the channel width-to-length ratio of the MOSFET under test (MOSFET) and the standard MOSFET, thereby obtaining the replacement resistance value of the MOSFET under test and generating a static simulation netlist. This eliminates the need for dynamic simulation to extract resistance values ​​for MOSFETs of different sizes; a single dynamic simulation of the standard MOSFET is sufficient to obtain the equivalent resistance of all MOSFETs on the entire chip through proportional conversion, significantly reducing the complexity of resistance value acquisition. Furthermore, by applying an excitation signal to the power supply port of the static simulation netlist to perform static simulation, the voltage drop at the target resistance port corresponding to the replacement resistance of each MOSFET under test is obtained. Since all MOSFETs in the static simulation netlist have been replaced with resistors and no excitation is needed at the input signal ports, there is no signal flipping during the simulation, avoiding the tedious process of writing complex simulation excitations and significantly shortening the simulation time. By comparing the voltage drop with the preset threshold in the configuration file, the weak point of the circuit layout where the MOSFET under test is located can be determined. The voltage drop measurement and threshold comparison of all MOSFET ports of the entire chip can be completed at one time, realizing rapid and full-coverage location of weak points in the layout, avoiding the risk of analysis omissions caused by incomplete excitations in dynamic simulation. In summary, the embodiments of this application can effectively solve the problems of low excitation coverage and long simulation time in existing dynamic simulation methods, thereby facilitating the improvement of circuit layout verification efficiency. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic flowchart of a static analysis method for circuit layout provided in an embodiment of this application; Figure 2 A schematic diagram of the MOS transistor distribution in the post-simulation netlist provided for embodiments of this application; Figure 3 A simulation diagram of the replacement resistor value of the PMOS transistor under test provided for an embodiment of this application; Figure 4 A simulation diagram of the replacement resistor value of the NMOS transistor under test provided for an embodiment of this application; Figure 5 A schematic diagram of a PMOS transistor power supply voltage drop measurement circuit provided for an embodiment of this application; Figure 6 A schematic diagram of an NMOS transistor ground spring voltage drop measurement circuit provided for an embodiment of this application; Figure 7 A schematic flowchart illustrating the overall process of static voltage drop testing provided for embodiments of this application; Figure 8 A simplified static voltage drop analysis diagram provided for embodiments of this application; Figure 9 A schematic diagram of a static analysis system for circuit layouts provided for embodiments of this application; Figure 10 A schematic diagram of an electronic device provided for an embodiment of this application. Detailed Implementation

[0020] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0021] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0022] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial effects of the embodiments of this application, detailed descriptions are provided below through specific embodiments.

[0023] Firstly, embodiments of this application provide a static analysis method for circuit layouts, which facilitates improved verification efficiency of circuit layouts.

[0024] like Figure 1 As shown, embodiments of this application provide a static analysis method for circuit layouts, including: S11. Based on the channel width-to-length ratio of the MOSFET under test and the standard MOSFET, the equivalent resistance value of the standard MOSFET is converted to obtain the replacement resistance value of the MOSFET under test in the post-simulation netlist, and a static simulation netlist is generated. The equivalent resistance value is the on-state equivalent resistance value of the standard MOS transistor during the transient switching process.

[0025] After the integrated circuit layout design is completed, verifying the power supply voltage drop of the numerous MOS transistors inside the chip is a crucial step in ensuring the chip functions correctly. Existing technologies typically employ dynamic simulation methods, which involve successively simulating the transient behavior of each MOS transistor under different operating states to extract its equivalent resistance in the conduction state, thereby evaluating whether the voltage drop meets the design threshold. However, with the continuous increase in chip integration density, a single chip may contain hundreds of millions or even billions of MOS transistors, and these MOS transistors have different channel widths and lengths in the layout, i.e., different channel width-to-length ratios. If dynamic simulation is performed individually for each size of MOS transistor, the required number of simulations will be extremely large, and the computational complexity and time cost will increase dramatically, severely limiting the overall efficiency of layout verification.

[0026] To address the aforementioned issues, this application proposes a method for resistance value conversion based on channel width-to-length ratio. Specifically, firstly, a standard MOSFET of representative size is selected, such as a PMOS or NMOS transistor in a standard inverter. The equivalent on-state resistance of the standard MOSFET during transient switching is obtained through dynamic simulation. In some cases, the dynamic simulation only needs to be performed once, serving as the basis for all subsequent conversion operations. For the MOSFET under test in the post-simulation netlist, its actual channel width and length are read, and the scaling factor between the channel width-to-length ratio and the standard MOSFET's channel width-to-length ratio is calculated. Then, the equivalent resistance value of the standard MOSFET is divided by the scaling factor to obtain the replacement resistance value for the MOSFET under test. Next, a script is written to automatically traverse the entire post-simulation netlist, performing the above conversion operation on each PMOS and NMOS transistor under test, and replacing each MOSFET with its corresponding calculated resistance. After all replacements are completed, the original post-simulation netlist containing a large number of MOSFETs is converted into a static simulation netlist consisting only of resistors and power supply networks.

[0027] In this embodiment, the equivalent resistance of all MOS transistors of different sizes in the entire chip, regardless of the difference in their channel width-to-length ratio from that of the standard MOS transistor, can be obtained by performing a dynamic simulation of the standard transistor plus a proportional conversion. This eliminates the need to repeatedly perform dynamic simulation for each size, which not only significantly reduces the number of dynamic simulations and the consumption of computing resources, but also lays the netlist foundation for the subsequent use of static simulation to replace dynamic simulation, thereby creating conditions for improving the efficiency of the entire layout verification process.

[0028] S12, apply an excitation signal to the power port of the static simulation netlist to perform static simulation and obtain the voltage drop of the target resistor port corresponding to the replacement resistor value of each of the MOS transistors under test; After replacing all MOSFETs in the simulation netlist with corresponding resistors and generating the static simulation netlist, the simulation execution phase can begin. Since there are no MOSFETs in the static simulation netlist, all signal toggling functions originally implemented by transistors no longer exist. Therefore, unlike dynamic simulation, there is no need to write complex test stimuli for the chip's input signal ports, nor is it necessary to consider timing switches between different operating states. In some cases, stimulus signals can be directly applied to the power supply ports of the static simulation netlist.

[0029] Specifically, a constant operating voltage is applied to the power supply network connection port, and zero voltage is applied to the ground network connection port, serving as the sole excitation source for the entire simulation. Subsequently, a static simulation is performed using simulation tools. During the static simulation, since there are no signal flips in the netlist, the circuit state remains stable. The simulation tool does not need to repeatedly calculate the conduction state of the nonlinear transistor at each time step; it only needs to perform DC analysis on the linear network composed of resistors to achieve rapid convergence. After the simulation is complete, the voltage values ​​at the target resistor ports corresponding to each replacement resistor are directly read. These voltage values ​​represent the port voltages of the MOSFETs under static conditions. By comparing the measured port voltages with the ideal power supply voltage values ​​and calculating the difference, the voltage drop across the MOSFET ports can be obtained. In one specific embodiment… Figure 2 A schematic diagram of the MOS transistor distribution in the post-simulation netlist provided for embodiments of this application is shown below. Figure 2 The post-simulation netlist of the IP contains a large number of MOSFETs. For example, P1, P2, P3, P4, P5, and P6 represent PMOS transistors, and N1, N2, N3, N4, N5, and N6 represent NMOS transistors. The source or drain of each PMOS transistor is connected to the power supply (VDD) line through a power network, and the source or drain of each NMOS transistor is connected to the ground voltage (GND) through a ground network (VSS). During voltage drop analysis, it is necessary to measure the voltage values ​​at the connection ports of the PMOS transistors and the VDD power network, as well as the voltage values ​​at the connection ports of the NMOS transistors and the GND ground network, to evaluate the voltage drop at each MOSFET port.

[0030] In one specific embodiment, to measure the voltage drop of PMOS and NMOS transistors separately, a netlist processing approach can be used. Specifically, a script is written to process the post-simulation netlist, generating a first netlist file for measuring the PMOS VDD voltage drop and a second netlist file for measuring the NMOS VSS ground bounce. The first netlist file contains only the resistor network obtained from replacing the PMOS transistors, specifically for measuring the power supply voltage drop at the PMOS ports; the second netlist file contains only the resistor network obtained from replacing the NMOS transistors, specifically for measuring the ground voltage bounce at the NMOS ports. Static simulations are then performed on both the first and second netlist files. Specifically, after applying excitation to the power supply ports of the first netlist file, a static simulation is run to measure the voltage drop at the connection ports of the power supply voltage networks containing the PMOS transistor replacement resistors; similarly, after applying excitation to the power supply ports of the second netlist file, a static simulation is run to measure the voltage drop at the connection ports of the ground voltage networks containing the NMOS transistor replacement resistors. By performing two separate static simulations, VDD voltage drop data for all PMOS transistor ports and VSS ground bounce data for all NMOS transistor ports can be obtained.

[0031] In this embodiment, since static simulation does not require handling signal flipping or loading complex input stimuli, the entire simulation process can be completed in a very short time, significantly shortening the simulation time compared to dynamic simulation. Furthermore, since the port voltages of all replacement resistors in the netlist can be measured simultaneously, voltage drop data for all MOS transistor ports of the entire chip can be obtained in a single simulation, providing complete measurement results for subsequent weak point localization.

[0032] S13, compare the voltage drop with a preset threshold in the configuration file, and mark the location information of the MOSFET under test whose voltage drop exceeds the preset threshold in the circuit layout.

[0033] After obtaining the voltage drop at all ports of the MOSFETs under test through static simulation, these measurement results need to be evaluated to identify the specific locations where risks exist in the schematic design.

[0034] Specifically, this embodiment compares the voltage drop values ​​of each MOSFET port obtained from static simulation measurements with the voltage drop thresholds preset in the configuration file one by one. In some examples, the configuration file sets a power supply voltage drop threshold for PMOS transistors and a ground bounce voltage drop threshold for NMOS transistors. These two thresholds represent the maximum voltage drop range and the maximum ground bounce range allowed by the layout design, respectively. For each MOSFET under test, the measured voltage drop can be compared with the corresponding threshold. If the voltage drop is less than or equal to the preset threshold, it is determined that the power integrity of the layout area where the MOSFET is located meets the design requirements and no modification is needed. If the voltage drop is greater than the preset threshold, it is determined that there is a weak point in the layout area where the MOSFET is located, that is, the power network or ground network design of the corresponding layout area is insufficient to support the current demand of the MOSFET during transient switching, which may cause the chip to malfunction in actual operation. In some examples, for MOSFETs determined to be weak points, their position information in the circuit layout can be further marked, such as the coordinates of the MOSFET in the layout, the circuit module to which it belongs, and the corresponding power network connection path. Through the above comparison and judgment process, designers can quickly screen out a few weak areas with excessive voltage drop from hundreds of millions of MOSFETs in the entire chip, without having to check the simulation waveform of each MOSFET or manually analyze the measurement data.

[0035] This embodiment uses an automatic threshold determination method to transform the tedious work of manual point-by-point analysis into an automated data comparison process, making the location of weak points in the layout faster and more accurate, and providing clear guidance for subsequent targeted layout optimization.

[0036] The static analysis method for circuit layout provided in this application converts the equivalent resistance value of the standard MOSFET based on the channel width-to-length ratio of the MOSFET under test (MOSFET) and the standard MOSFET, obtaining the replacement resistance value of the MOSFET under test and generating a static simulation netlist. This eliminates the need for dynamic simulation to extract resistance values ​​for MOSFETs of different sizes; a single dynamic simulation of the standard MOSFET is sufficient to obtain the equivalent resistance of all MOSFETs on the entire chip through proportional conversion, significantly reducing the complexity of resistance value acquisition. Static simulation is performed by applying excitation signals to the power supply ports of the static simulation netlist to obtain the voltage drop at the target resistance port corresponding to the replacement resistance of each MOSFET under test. Since all MOSFETs in the static simulation netlist have been replaced with resistors and no excitation is needed at the input signal ports, there is no signal flipping during simulation, avoiding the tedious process of writing complex simulation excitations and significantly shortening the simulation time. By comparing the voltage drop with a preset threshold in the configuration file, the weak points in the circuit layout where the MOSFET under test is located are determined. It can complete the voltage drop measurement and threshold comparison of all MOS transistor ports of the entire chip in one go, realizing the rapid and full-coverage location of weak points in the layout, avoiding the risk of analysis omissions caused by incomplete excitation in dynamic simulation. In summary, the embodiments of this application can effectively solve the problems of low excitation coverage and long simulation time in existing dynamic simulation methods, thereby facilitating the improvement of circuit layout verification efficiency.

[0037] In some embodiments, the configuration information in the configuration file includes: post-simulation netlist file path, simulation process corner, power supply voltage value, PMOS equivalent resistance value, NMOS equivalent resistance value, preset threshold, and range of MOS transistor cells under test.

[0038] Before performing static analysis of the circuit layout, a configuration file needs to be created in advance to uniformly manage the various parameters and settings relied upon throughout the analysis process.

[0039] In some examples, the configuration file contains several key configuration information. First, it specifies the path to the post-simulation netlist file of the IP. This path points to the post-simulation netlist file extracted after the IP layout design is completed, serving as the input data source for the entire static analysis process. Second, it specifies the simulation process corner, which defines the process model conditions used by the simulation tool during analysis, such as typical process corner, fast-fast process corner, or slow-slow process corner, ensuring that the simulation results reflect the voltage drop performance of the chip under different process deviations. The configuration file also defines the power supply voltage value, which clarifies the ideal voltage applied by the power supply voltage network when the chip is operating normally, serving as a reference benchmark for subsequent voltage drop calculations. Furthermore, the configuration file records the PMOS and NMOS equivalent resistance values ​​obtained through dynamic simulation of a standard inverter under falling edge input excitation, as well as the PMOS and NMOS equivalent resistance values ​​obtained through dynamic simulation of a standard inverter under rising edge input excitation. These four resistance values ​​collectively serve as the standard reference for subsequent resistance value conversion of the MOSFET under test. The configuration file also sets preset thresholds, including threshold voltages for VDD voltage drop and VSS ground bounce, which are used to determine the pass / fail of the measured power supply voltage drop at the PMOS port and the ground bounce voltage drop at the NMOS port after static simulation. The configuration file further defines the range of MOS transistor cells to be measured, specifying the MOS transistors to be analyzed for voltage drop. The range can cover the entire IP, or specific circuit modules or MOS transistor types can be selected for targeted analysis based on design requirements. In some examples, if a certain number of MOS transistors do not need to be measured, they can be excluded from the measurement range using the Exclude option provided in the configuration file. Excluded MOS transistors will be replaced with infinitely large resistors during netlist processing and will not participate in subsequent voltage drop analysis.

[0040] This embodiment, through the unified management of the above configuration files, can flexibly adapt to different IPs, different process conditions, different analysis needs, and selectively exclude voltage drop verification tasks of specific modules, providing complete and standardized parameter support for subsequent netlist processing, static simulation, and threshold comparison.

[0041] In some embodiments, the step of converting the equivalent resistance value of the standard MOS transistor based on the channel width-to-length ratio of the MOS transistor under test and the standard MOS transistor to obtain the replacement resistance value of the MOS transistor under test in the post-simulation netlist includes: obtaining the channel width-to-length ratio of the standard PMOS transistor in the standard cell, and the channel width-to-length ratio of the PMOS transistor under test; using the ratio of the channel width-to-length ratio of the PMOS transistor under test to the channel width-to-length ratio of the standard PMOS transistor as a first coefficient; dividing the equivalent resistance value of the standard PMOS transistor by the first coefficient to obtain the replacement resistance value of the PMOS transistor under test; obtaining the channel width-to-length ratio of the standard NMOS transistor in the standard cell, and the channel width-to-length ratio of the NMOS transistor under test; using the ratio of the channel width-to-length ratio of the NMOS transistor under test to the channel width-to-length ratio of the standard NMOS transistor as a second coefficient; dividing the equivalent resistance value of the standard NMOS transistor by the second coefficient to obtain the replacement resistance value of the NMOS transistor under test.

[0042] After completing the configuration file settings, it is also necessary to replace the resistors of the MOSFETs in the post-simulation netlist. The calculation of the replacement resistor value depends on the size ratio between the MOSFET under test and the standard MOSFET.

[0043] Specifically, firstly, the equivalent resistance value of the standard PMOS transistor in the standard inverter is obtained through dynamic simulation. For the PMOS transistor under test in the post-simulation netlist, the channel width-to-length ratio of the standard PMOS transistor in the standard cell is read, and the channel width-to-length ratio of the PMOS transistor under test itself is also read. The channel width-to-length ratio of the PMOS transistor under test is divided by the channel width-to-length ratio of the standard PMOS transistor, and the resulting ratio is used as the first coefficient. Then, the equivalent resistance value of the standard PMOS transistor is divided by the first coefficient, and the result is the replacement resistance value of the PMOS transistor under test. Similarly, the equivalent resistance value of the standard NMOS transistor in the standard inverter is obtained through dynamic simulation. For the NMOS transistor under test in the post-simulation netlist, the channel width-to-length ratio of the standard NMOS transistor in the standard cell and the channel width-to-length ratio of the NMOS transistor under test are read. The channel width-to-length ratio of the NMOS transistor under test is divided by the channel width-to-length ratio of the standard NMOS transistor, and the resulting ratio is used as the second coefficient. The equivalent resistance value of the standard NMOS transistor is then divided by the second coefficient to obtain the replacement resistance value of the NMOS transistor under test.

[0044] In this embodiment, through the above conversion method, MOSFETs of different sizes in the post-simulation netlist can obtain their corresponding replacement resistor values ​​according to the ratio between their channel width-to-length ratio and that of the standard MOSFET, thereby realizing a complete conversion from obtaining standard resistor values ​​from dynamic simulation to assigning resistor values ​​in the static simulation netlist.

[0045] In some embodiments, the standard MOS transistor is a PMOS transistor or an NMOS transistor in a standard inverter; the on-equivalent resistance value includes the on-equivalent resistance value of the standard PMOS transistor during transient switching or the on-equivalent resistance value of the standard NMOS transistor during transient switching; wherein, the on-equivalent resistance value of the standard PMOS transistor during transient switching includes: applying a falling edge excitation to the input port of the standard inverter to generate a rising edge signal at the output port, and recording the maximum current value on the PMOS transistor, the current source voltage value, and the drain voltage value in the transient simulation; based on the PMOS... The on-state equivalent resistance of the standard PMOS transistor during transient switching is obtained by using the maximum current on the transistor, the source voltage, and the drain voltage. The on-state equivalent resistance of the standard NMOS transistor during transient switching is obtained by: applying a rising edge excitation to the input port of the standard inverter to generate a falling edge signal at the output port; recording the maximum current on the NMOS transistor, the current source voltage, and the drain voltage during transient simulation; and obtaining the on-state equivalent resistance of the standard NMOS transistor during transient switching based on the maximum current, source voltage, and drain voltage of the NMOS transistor.

[0046] When determining the standard reference value for resistance value conversion, this embodiment selects the PMOS and NMOS transistors in the standard inverter as standard MOS transistors, and obtains the equivalent conduction resistance values ​​of the two transistors during the transient switching process through dynamic simulation.

[0047] Specifically, Figure 3 A simulation diagram of the replacement resistor value of the PMOS transistor under test provided for an embodiment of this application is shown below. Figure 3A standard inverter consists of a PMOS transistor P0 and an NMOS transistor N0. The input port is labeled A, and the output port is labeled Z. To obtain the equivalent on-state resistance of the standard PMOS transistor during its transient switching process, a falling-edge excitation signal is first applied to the input port A of the standard inverter. This excitation signal transitions from high to low. Under the influence of the falling edge of the input signal, the output port Z of the inverter generates a rising-edge signal, transitioning from low to high. During the rising-edge transition of the output port Z, the PMOS transistor P0 is in the on state, and current flows from the power supply network through the PMOS transistor P0 to the output port Z. During transient simulation, the current flowing through PMOS transistor P0 is monitored over time. The maximum current value reached during the rising edge is recorded as Ip0. Simultaneously, at the moment the maximum current occurs, the source voltage VPsrc and drain voltage VPdrn of PMOS transistor P0 are recorded. VPsrc refers to the potential at the end of PMOS transistor P0 connected to the power supply network, and VPdrn refers to the potential at the end of PMOS transistor P0 connected to output port Z. After recording, according to Ohm's law, the difference between the source and drain voltages is divided by the maximum current value, i.e., Rp0 = (VPsrc - VPdrn) / Ip0, to obtain the equivalent on-state resistance Rp0 of the standard PMOS transistor during transient switching. Similarly, Figure 4 A simulation diagram of the replacement resistor value of the NMOS transistor under test provided for an embodiment of this application is shown below. Figure 4A standard inverter consists of a PMOS transistor P1 and an NMOS transistor N1, with its input port labeled A and output port labeled Z. To obtain the equivalent resistance of the standard NMOS transistor during transient switching, a rising edge excitation signal is applied to the input port A of the standard inverter, transitioning from low to high. Under the influence of the rising edge of the input signal, the output port Z of the inverter generates a falling edge signal, transitioning from high to low. During the falling edge of output port Z, NMOS transistor N1 is in the on-state, and current flows from output port Z through NMOS transistor N1 to the ground network. During transient simulation, the current flowing through NMOS transistor N1 is monitored over time, and the maximum current value reached during the falling edge is recorded as In1. Simultaneously, at the moment the maximum current value occurs, the source voltage VNsrc and drain voltage VNdrn of NMOS transistor N1 are recorded. For NMOS transistors, the source is typically connected to the ground network, and the drain is typically connected to the output port Z. Therefore, the source voltage VNsrc refers to the potential at the end of NMOS transistor N1 connected to the ground network, and the drain voltage VNdrn refers to the potential at the end of NMOS transistor N1 connected to the output port Z. After recording, according to Ohm's law, the difference between the drain voltage and the source voltage is divided by the maximum current, i.e., using the formula Rn1 = (VNdrn - VNsrc) / In1, to calculate the equivalent on-state resistance Rn1 of the standard NMOS transistor during transient switching.

[0048] In this embodiment, the equivalent on-state resistance Rp0 of a standard PMOS transistor and the equivalent on-state resistance Rn1 of a standard NMOS transistor were obtained through the two dynamic simulation processes described above. These two resistance values ​​are reference values ​​extracted from a standard inverter under specific transient switching conditions, reflecting the equivalent resistance characteristics of a standard-size MOS transistor in the switching on-state. At the same time, in the subsequent netlist processing, these two reference resistance values ​​will be used to convert the resistance values ​​of different-sized PMOS transistors and NMOS transistors under test in the post-simulation netlist, thereby providing the necessary resistance parameters for generating a static simulation netlist.

[0049] In some embodiments, applying an excitation signal to the power supply port of the static simulation netlist to perform static simulation and obtain the voltage drop of the target resistor port corresponding to the replacement resistor value of each MOS transistor under test includes: applying a first constant voltage value as a power supply voltage excitation signal to the power supply voltage network connection port of the static simulation netlist, and applying a second constant voltage value as a ground voltage excitation signal to the ground network connection port, wherein the first constant voltage value is the operating voltage and the second constant voltage value is zero voltage; running a simulation tool to perform static simulation on the static simulation netlist after applying the power supply voltage excitation signal; after the simulation is completed, measuring the voltage value of each replacement resistor and the power supply network connection port, taking the difference between the voltage value of the power supply voltage network connection port where the PMOS transistor replacement resistor is located and the first constant voltage value as the power supply voltage drop, and taking the difference between the voltage value of the ground network connection port where the NMOS transistor replacement resistor is located and the second constant voltage value as the ground bounce voltage drop.

[0050] After the static simulation netlist is generated, the static simulation execution phase begins.

[0051] Specifically, Figure 5 A schematic diagram of a PMOS transistor power supply voltage drop measurement circuit provided for an embodiment of this application is shown below. Figure 5 Suppose that all PMOS transistors in the post-simulation netlist are replaced with resistors RP1, RP2, RP3, RP4, RP5, and RP6, and all NMOS transistors are replaced with resistors RN1, RN2, RN3, RN4, RN5, and RN6. At this point, there are no MOS transistors left in the entire netlist. Figure 6 A schematic diagram of an NMOS transistor ground bounce voltage drop measurement circuit provided for an embodiment of this application is shown below. Figure 6The netlist structure is also composed of the replaced resistor network. For the processed static simulation netlist, a first constant voltage value is applied to the power supply network connection port as the power supply voltage excitation signal. In some examples, the first constant voltage value is set to the power supply voltage required for normal chip operation, such as 1.0V or 1.2V, with the specific value determined according to the chip's process node and design specifications. Simultaneously, a second constant voltage value is applied to the ground network connection port as the ground voltage excitation signal. In some examples, the second constant voltage value is set to zero voltage, i.e., consistent with the circuit reference ground potential. After applying the excitation signals, the simulation tool is run to perform static simulation analysis on the static simulation netlist. Since all MOSFETs in the static simulation netlist have been replaced with resistors, and no excitation signals need to be added to the input signal ports, the entire netlist consists only of resistors and the power supply network, without any signal flipping or transient changes. Therefore, the simulation tool does not need to perform iterative calculations of the time step, nor does it need to handle the switching of nonlinear transistor conduction states. It only needs to perform a steady-state solution on the linear DC network composed of resistors to complete the simulation calculation and achieve convergence in a very short time.

[0052] After the simulation is complete, the voltage measurement step begins. For details, please refer to [link to relevant documentation]. Figure 5 For PMOS transistors, measure the voltage at the power supply network connection port of each replacement resistor, labeled VP1, VP2, VP3, VP4, VP5, and VP6. These voltage values ​​represent the actual potential of the power supply voltage after it has been transmitted through the power supply network to the connection point of each PMOS transistor's replacement resistor. Subtract the measured voltage value from the previously applied first constant voltage value; that is, calculate the difference between the first constant voltage value and the measured voltage value. For example, if the first constant voltage value is 1.0V and the measured voltage at the port of a PMOS transistor's replacement resistor is 0.85V, the difference is 0.15V, which is the power supply voltage drop at the location of the PMOS transistor. For NMOS transistors, see [link to relevant documentation]. Figure 6 The voltage values ​​at the ground network connection ports of each replacement resistor are measured and labeled VN1, VN2, VN3, VN4, VN5, and VN6. These voltage values ​​represent the actual potential of the ground network at the connection points of each NMOS transistor replacement resistor. Since the applied second constant voltage is 0V, the measured voltage value is subtracted from the second constant voltage value, i.e., the measured voltage value is subtracted from 0. The result is still the measured voltage value itself, which is the ground bounce voltage drop at the location of the NMOS transistor. For example, if the measured voltage value at the port of a certain NMOS transistor replacement resistor is 0.08V, then the ground bounce voltage drop is 0.08V, indicating that the ground potential at that location has risen by 0.08V relative to the ideal ground.

[0053] This embodiment, through the above-described static simulation process, eliminates the need to write complex input signal excitation files or simulate the signal switching process of the chip under different operating states. It only requires applying a constant DC excitation to the power supply port to simultaneously obtain the power supply voltage drop measurement values ​​of all PMOS transistor ports and the ground bounce voltage drop measurement values ​​of all NMOS transistor ports in a single simulation. Furthermore, since there is no signal switching involved in the entire simulation process, the simulation time is significantly shortened compared to dynamic simulation, thereby significantly improving the efficiency of voltage drop analysis.

[0054] In some embodiments, comparing the voltage drop with a preset threshold in the configuration file and marking the location information of the MOSFET under test whose voltage drop exceeds the preset threshold in the circuit layout includes: comparing the measured voltage drop value with the preset threshold in the configuration file one by one, the preset threshold including a power supply voltage drop threshold and a ground bounce threshold; if the measured power supply voltage drop value of a port of a MOSFET under test is less than or equal to the power supply voltage drop threshold, or if the measured ground bounce voltage drop value of a port of a MOSFET under test is less than or equal to the ground bounce threshold, then it is determined that the voltage drop of the layout area corresponding to the MOSFET under test meets the design requirements; if the measured power supply voltage drop value of a port of a MOSFET under test is greater than the power supply voltage drop threshold, or if the measured ground bounce voltage drop value of a port of a MOSFET under test is greater than the ground bounce threshold, the location information of the MOSFET under test in the circuit layout is marked, and the corresponding layout area is optimized according to the location information; after the layout area optimization is completed, the voltage drop of the resistor port in the remeasured static simulation netlist is compared again with the voltage threshold in the configuration file, until the circuit layout of all MOSFETs under test meets the design requirements.

[0055] After obtaining the power supply voltage drop and ground bounce voltage drop of all the MOSFET ports under test through static simulation, it is necessary to determine the pass / fail status of the above measurement results in order to identify the specific locations where there are risks in the layout design.

[0056] Specifically, Figure 7 A schematic flowchart illustrating the overall process of static voltage drop testing provided for embodiments of this application includes: S101. Write the configuration file; Before starting the analysis, a configuration file is first created to manage all parameters relied upon throughout the analysis process. This configuration file includes the storage path of the post-IP simulation netlist file, the process corner conditions required for simulation, the power supply voltage values, the equivalent resistance values ​​of standard PMOS and NMOS transistors obtained through dynamic simulation, the power supply voltage drop threshold and ground bounce threshold used for compliance judgment, and the range of MOS transistor cells to be measured. If a certain number of MOS transistors do not need to be measured, they can be excluded using the exclusion options in the configuration file. Excluded MOS transistors will be replaced with resistors with infinite resistance in subsequent processing and will not participate in the voltage drop analysis.

[0057] S102, IP network list processing; After completing the configuration file, a script is written to read the parameters from the configuration file and process the simulation netlist after IP. Specifically, based on the channel width-to-length ratio of the MOSFET under test (DUT) and the standard MOSFET, the equivalent resistance value of the standard MOSFET is converted to obtain the replacement resistor value corresponding to each DUT. All PMOS transistors to be measured in the netlist are replaced with resistors of corresponding values, and all NMOS transistors to be measured are replaced with resistors of corresponding values. After the replacement is completed, one or more static simulation netlists are generated. These netlists no longer contain any MOSFETs and consist only of resistors and power supply networks.

[0058] S103, IP static simulation; After the netlist processing is complete, excitation signals are applied to the power supply ports of the static simulation netlist. Specifically, a constant operating voltage is applied to the power supply voltage network connection port as the power supply voltage excitation signal, and zero voltage is applied to the ground network connection port as the ground voltage excitation signal. The simulation tool is then run to perform static simulation analysis on the static simulation netlist. Since there are no MOSFETs in the netlist and no excitation is required at the input signal ports, there are no signal inversions during the simulation. The simulation tool only needs to solve the linear DC network composed of resistors, which can complete the simulation calculation in a very short time.

[0059] S104. Measure the static voltage drop; After static simulation, the voltage value at the power network connection port of each replacement resistor is measured. For the PMOS transistor replacement resistor, the voltage value at its power network connection port is measured, and the measured value is subtracted from the ideal power supply voltage to obtain the power supply voltage drop at the location of the PMOS transistor. For the NMOS transistor replacement resistor, the voltage value at its ground network connection port is measured. Since the ideal ground voltage is zero, this measured value is the ground bounce voltage drop at the location of the NMOS transistor. Through the above process, the voltage drop data of all the MOS transistors under test ports on the entire chip can be obtained.

[0060] S105. Determine if the voltage drop is reasonable; Each measured power supply voltage drop and ground bounce voltage drop is compared one by one with the pre-set power supply voltage drop threshold and ground bounce threshold in the configuration file. If the voltage drop at all MOSFET ports is less than or equal to the corresponding threshold, the voltage drop is considered reasonable, the entire verification process is completed, and the IP layout design passes the voltage drop verification. If the voltage drop at any MOSFET port is greater than the corresponding threshold, the IR Drop is considered unreasonable, and the next step is required for layout optimization.

[0061] In one specific embodiment, for the determination of a PMOS transistor, if the measured power supply voltage drop at a certain port is less than or equal to the power supply voltage drop threshold set in the configuration file, it is determined that the power supply voltage drop of the layout area where the PMOS transistor is located meets the design requirements, and the power network can provide sufficient voltage margin for the MOS transistor, without the need for layout modification. Conversely, if the measured power supply voltage drop is greater than the power supply voltage drop threshold, it is determined that there is a weak point in the layout area where the PMOS transistor is located, that is, the power supply voltage is excessively lost during the transmission from the chip's power input port to the MOS transistor location, and the power network design is insufficient to support the current demand of the MOS transistor during transient switching, which may lead to logic errors, timing violations, or functional abnormalities in actual chip operation.

[0062] For NMOS transistors, if the measured ground bounce voltage drop at a certain port is less than or equal to the ground bounce threshold set in the configuration file, the ground bounce of the layout area where the NMOS transistor is located is determined to meet the design requirements, the ground network can maintain a stable low potential, and no layout modification is required. Conversely, if the measured ground bounce voltage drop is greater than the ground bounce threshold, the layout area where the NMOS transistor is located is determined to have a weak point, that is, the ground potential rises excessively under transient current impact, the ground network design has defects, which may lead to relative changes in the threshold voltage of the MOS transistor, deterioration of signal integrity, or false triggering of adjacent circuits.

[0063] S106, Circuit layout optimization; For MOSFETs with unreasonable voltage drops, they are marked as layout weak points, and their location information in the layout, including coordinates, the circuit module they belong to, and the corresponding power network connection path, is recorded. Based on the marked information, the layout area containing the weak point is optimized in a targeted manner. For example, the width of power or ground traces is increased to reduce resistance; the density of power or ground networks is increased to provide more current paths; additional power-to-ground decoupling capacitors are added near the weak point; the placement of the MOSFET is adjusted to be closer to the power pads; or the number of power pads is increased. After layout optimization, the optimized IP is re-extracted and simulated with a netlist, and the process returns to the second step of IP netlist processing, re-executing the netlist processing, static simulation, measurement, and judgment steps. This iterative process continues until the voltage drop of all MOSFET ports under test meets the threshold requirements, at which point the voltage drop verification and layout optimization of the entire IP are complete.

[0064] This embodiment, through the aforementioned threshold-based automatic judgment method, can quickly screen out a few weak areas with excessive voltage drop from hundreds of millions of MOSFETs in the entire chip, providing designers with clear optimization guidance. Furthermore, compared to the tedious process of manually analyzing numerous simulation waveforms and relying on experience to judge weak points in traditional dynamic simulation methods, the automatic judgment and marking mechanism of this embodiment significantly reduces the workload of manual analysis, improves the targeting and efficiency of layout optimization, and ultimately achieves an overall improvement in circuit layout verification efficiency.

[0065] Based on the complete static voltage drop analysis method described above, this embodiment also provides a simplified analysis method. Figure 8 A simplified static voltage drop analysis diagram is provided for embodiments of this application, such as... Figure 8 In a normal analysis process, two independent static simulation netlist files need to be generated. One netlist is used to measure the VDD voltage drop of the PMOS transistor, and the other netlist is used to measure the VSS ground bounce of the NMOS transistor. Then, two static simulations are performed to obtain all the voltage drop data. However, in this embodiment, only one static simulation netlist file needs to be generated.

[0066] Specifically, all PMOS transistors in the post-simulation netlist are replaced with resistors RP, where the resistance of RP is equal to the equivalent resistance Rp0 of a standard PMOS transistor divided by the size scaling factor of the corresponding PMOS transistor under test. Simultaneously, all NMOS transistors in the post-simulation netlist are replaced with resistors RN, where the resistance of RN is equal to the equivalent resistance Rn1 of a standard NMOS transistor divided by the size scaling factor of the corresponding NMOS transistor under test. After this uniform replacement, only one static simulation netlist is generated, containing the replacement resistors for all PMOS transistors and all NMOS transistors. A static simulation is then performed on this single netlist. After the simulation, the voltage values ​​at the power supply network connection ports where the replacement PMOS transistor resistors are located are simultaneously measured and denoted as VP1, VP2 to VP6, and the voltage values ​​at the ground network connection ports where the replacement NMOS transistor resistors are located are denoted as VN1, VN2 to VN6. Through this static simulation and voltage measurement, the power supply voltage drop at all PMOS transistor ports and the VSS ground bounce value at all NMOS transistor ports can be obtained simultaneously. Compared to the normal process that requires generating two netlists and performing two static simulations, the simplified analysis method reduces the number of simulations to one, and the netlist processing workload is halved accordingly. This further improves the efficiency of voltage drop analysis while ensuring that the analysis coverage remains unchanged.

[0067] Secondly, embodiments of this application provide a static analysis system for circuit layouts, which facilitates improved verification efficiency of circuit layouts.

[0068] like Figure 9 As shown, embodiments of this application also provide a static analysis system for circuit layout, including: a conversion unit 31, a static simulation unit 32, and a determination unit 33.

[0069] The conversion unit 31 is used to convert the equivalent resistance value of the standard MOS transistor according to the channel width-to-length ratio of the MOS transistor under test and the standard MOS transistor, to obtain the replacement resistance value of the MOS transistor under test in the post-simulation netlist, and to generate a static simulation netlist; wherein the equivalent resistance value is the on-equivalent resistance value of the standard MOS transistor during the transient switching process. The static simulation unit 32 is used to apply an excitation signal to the power port of the static simulation netlist to perform static simulation and obtain the voltage drop of the target resistor port corresponding to the replacement resistor value of each of the MOSFETs under test; the determination unit 33 is used to compare the voltage drop with a preset threshold in the configuration file and mark the position information of the MOSFETs under test whose voltage drop exceeds the preset threshold in the circuit layout.

[0070] The static analysis system for circuit layouts provided in this application converts the equivalent resistance value of the standard MOSFET based on the channel width-to-length ratio of the MOSFET under test (DUT) and the standard MOSFET, obtains the replacement resistance value of the DUT, and generates a static simulation netlist. This eliminates the need for dynamic simulation to extract resistance values ​​for MOSFETs of different sizes; a single dynamic simulation of the standard MOSFET is sufficient to obtain the equivalent resistance of all MOSFETs on the entire chip through proportional conversion, significantly reducing the complexity of resistance value acquisition. By applying excitation signals to the power supply ports of the static simulation netlist to perform static simulation, the voltage drop at the target resistance port corresponding to the replacement resistance of each DUT is obtained. Since all MOSFETs in the static simulation netlist have been replaced with resistors and no excitation is needed at the input signal ports, there is no signal flipping during simulation, avoiding the tedious process of writing complex simulation excitations and significantly shortening simulation time. By comparing the voltage drop with a preset threshold in the configuration file, the weak points in the circuit layout where the DUT is located are determined. It can complete the voltage drop measurement and threshold comparison of all MOS transistor ports of the entire chip in one go, realizing the rapid and full-coverage location of weak points in the layout, avoiding the risk of analysis omissions caused by incomplete excitation in dynamic simulation. In summary, the embodiments of this application can effectively solve the problems of low excitation coverage and long simulation time in existing dynamic simulation methods, thereby facilitating the improvement of circuit layout verification efficiency.

[0071] In some embodiments, the conversion unit includes: a first replacement resistance value module, configured to obtain the channel width-to-length ratio of a standard PMOS transistor in a standard unit, and the channel width-to-length ratio of the PMOS transistor under test, using the ratio of the channel width-to-length ratio of the PMOS transistor under test to the channel width-to-length ratio of the standard PMOS transistor as a first coefficient, and dividing the equivalent resistance value of the standard PMOS transistor by the first coefficient to obtain the replacement resistance value of the PMOS transistor under test; and a second replacement resistance value module, configured to obtain the channel width-to-length ratio of a standard NMOS transistor in a standard unit, and the channel width-to-length ratio of the NMOS transistor under test, using the ratio of the channel width-to-length ratio of the NMOS transistor under test to the channel width-to-length ratio of the standard NMOS transistor as a second coefficient, and dividing the equivalent resistance value of the standard NMOS transistor by the second coefficient to obtain the replacement resistance value of the NMOS transistor under test.

[0072] In some embodiments, the static simulation unit includes: an excitation module, configured to apply a first constant voltage value as a power supply voltage excitation signal to the power supply voltage network connection port of the static simulation netlist, and apply a second constant voltage value as a ground voltage excitation signal to the ground network connection port, wherein the first constant voltage value is the operating voltage and the second constant voltage value is zero voltage; a static simulation module, configured to run a simulation tool to perform static simulation on the static simulation netlist after applying the power supply voltage excitation signal; and a measurement module, configured to measure the voltage value between each replacement resistor and the power supply network connection port after the simulation is completed, and to use the difference between the voltage value of the power supply voltage network connection port where the PMOS transistor replacement resistor is located and the first constant voltage value as the power supply voltage drop, and to use the difference between the voltage value of the ground network connection port where the NMOS transistor replacement resistor is located and the second constant voltage value as the ground bounce voltage drop.

[0073] In some embodiments, the determining unit includes: a comparison module, configured to compare the voltage drop measurement value with preset thresholds in the configuration file one by one, the preset thresholds including a power supply voltage drop threshold and a ground bounce threshold; a first determination module, configured to determine that the voltage drop of the layout area corresponding to the MOSFET under test meets the design requirements if the power supply voltage drop measurement value of a port of a MOSFET under test is less than or equal to the power supply voltage drop threshold, or if the ground bounce voltage drop measurement value of a port of a MOSFET under test is less than or equal to the ground bounce threshold; a second determination module, configured to mark the position information of the MOSFET under test in the circuit layout if the power supply voltage drop measurement value of a port of a MOSFET under test is greater than the power supply voltage drop threshold, or if the ground bounce voltage drop measurement value of a port of a MOSFET under test is greater than the ground bounce threshold, and optimize the corresponding layout area according to the position information; after the layout area optimization is completed, the voltage drop of the resistor port in the remeasured static simulation netlist is compared again with the voltage threshold in the configuration file, until the circuit layout of all MOSFETs under test meets the design requirements.

[0074] Thirdly, embodiments of this application also provide an electronic device that facilitates improved circuit layout verification efficiency.

[0075] like Figure 10As shown, the electronic device provided in the embodiments of this application may include: a housing 51, a processor 52, a memory 53, a circuit board 54, and a power supply circuit 55, wherein the circuit board 54 is disposed inside the space enclosed by the housing 51, and the processor 52 and the memory 53 are disposed on the circuit board 54; the power supply circuit 55 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 53 is used to store executable program code; the processor 52 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 53, for executing the static analysis method of the circuit layout provided in any of the foregoing embodiments.

[0076] The specific execution process of the above steps by the processor 42, as well as the steps further executed by the processor 42 by running executable program code, can be found in the description of the foregoing embodiments, and will not be repeated here.

[0077] Fourthly, embodiments of this application also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement the static analysis method of circuit layout provided in the foregoing embodiments, thus achieving the corresponding technical effects. This has been described in detail above and will not be repeated here.

[0078] This embodiment uses scripts to replace PMOS and NMOS transistors in the IP post-simulation netlist with resistors of different resistance values, thereby simulating the on-resistance characteristics of MOS transistors during transient switching in the IP. After replacement, static simulation is used instead of traditional dynamic simulation. Excitation signals are applied to the power supply ports, and the voltage drop at the PMOS transistor ports and the ground bounce at the NMOS transistor ports are measured. Since static simulation does not need to consider the specific operating state of the IP, and the simulation conditions are independent of the input excitation, this embodiment can cover all MOS transistors in the IP, avoiding the risk of analysis omissions caused by incomplete excitation in dynamic simulation. Furthermore, there is no signal switching during static simulation, significantly shortening the simulation time compared to dynamic simulation, resulting in faster optimization iteration and a significantly shorter layout design verification cycle. This embodiment can also set the range of MOS transistors to be viewed according to the configuration file, supporting targeted viewing of the voltage drop of MOS transistors in a specific area or module, facilitating designers to analyze local layout design problems in a targeted manner. In summary, this embodiment can quickly locate weak points in the power network of the IP layout, quickly complete IP optimization iteration, and effectively improve layout verification efficiency.

[0079] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0080] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0081] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0082] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this application, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0083] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0084] The above description is merely a specific embodiment of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A static analysis method for circuit layout, characterized in that, include: Based on the channel width-to-length ratio of the MOSFET under test and the standard MOSFET, the equivalent resistance value of the standard MOSFET is converted to obtain the replacement resistance value of the MOSFET under test in the post-simulation netlist, and a static simulation netlist is generated; wherein, the equivalent resistance value is the on-equivalent resistance value of the standard MOSFET during the transient switching process. Apply an excitation signal to the power port of the static simulation netlist to perform static simulation and obtain the voltage drop at the target resistor port corresponding to the replacement resistor value of each of the MOSFETs under test. The voltage drop is compared with a preset threshold in the configuration file, and the location information of the MOSFET under test whose voltage drop exceeds the preset threshold is marked in the circuit layout.

2. The static analysis method for circuit layout according to claim 1, characterized in that, The configuration information in the configuration file includes: post-simulation netlist file path, simulation process corner, power supply voltage value, PMOS equivalent resistance value, NMOS equivalent resistance value, preset threshold, and the range of MOS transistor cells under test.

3. The static analysis method for circuit layout according to claim 1, characterized in that, The process of converting the equivalent resistance value of the standard MOSFET based on the channel width-to-length ratio of the MOSFET under test and the standard MOSFET to obtain the replacement resistance value of the MOSFET under test in the post-simulation netlist includes: Obtain the channel width-to-length ratio of the standard PMOS transistor in the standard cell, and the channel width-to-length ratio of the PMOS transistor under test. Use the ratio of the channel width-to-length ratio of the PMOS transistor under test to the channel width-to-length ratio of the standard PMOS transistor as a first coefficient. Divide the equivalent resistance value of the standard PMOS transistor by the first coefficient to obtain the replacement resistance value of the PMOS transistor under test. Obtain the channel width-to-length ratio of the standard NMOS transistor in the standard cell, and the channel width-to-length ratio of the NMOS transistor under test. Use the ratio of the channel width-to-length ratio of the NMOS transistor under test to that of the standard NMOS transistor as a second coefficient. Divide the equivalent resistance value of the standard NMOS transistor by the second coefficient to obtain the replacement resistance value of the NMOS transistor under test.

4. The static analysis method for circuit layout according to claim 1, characterized in that, The standard MOS transistor is either a PMOS transistor or an NMOS transistor in a standard inverter; the on-equivalent resistance value includes the on-equivalent resistance value of the standard PMOS transistor during transient switching or the on-equivalent resistance value of the standard NMOS transistor during transient switching. The on-equivalent resistance value of the standard PMOS transistor during transient switching includes: A falling edge excitation is applied to the input port of the standard inverter to generate a rising edge signal at the output port. The maximum current on the PMOS transistor, the current source voltage, and the drain voltage are recorded in the transient simulation. Based on the maximum current, source voltage, and drain voltage of the PMOS transistor, the equivalent on-resistance of the standard PMOS transistor during transient switching is obtained. The equivalent on-resistance of the standard NMOS transistor during transient switching includes: By applying a rising edge excitation to the input port of the standard inverter, a falling edge signal is generated at the output port. In the transient simulation, the maximum current on the NMOS transistor, the current source voltage value, and the drain voltage value of the NMOS transistor are recorded. Based on the maximum current, source voltage, and drain voltage on the NMOS transistor, the equivalent on-resistance of the standard NMOS transistor during transient switching is obtained.

5. The static analysis method for circuit layout according to claim 1, characterized in that, The step of applying an excitation signal to the power port of the static simulation netlist to perform static simulation and obtaining the voltage drop at the target resistor port corresponding to the replacement resistor value of each of the MOSFETs under test includes: A first constant voltage value is applied to the power supply voltage network connection port of the static simulation netlist as a power supply voltage excitation signal, and a second constant voltage value is applied to the ground network connection port as a ground voltage excitation signal, wherein the first constant voltage value is the operating voltage and the second constant voltage value is zero voltage; Run the simulation tool to perform static simulation on the static simulation netlist after applying the power supply voltage excitation signal; After the simulation is completed, the voltage value of each replacement resistor connected to the power network connection port is measured. The difference between the voltage value of the power network connection port where the PMOS transistor replacement resistor is located and the first constant voltage value is taken as the power supply voltage drop. The difference between the voltage value of the ground network connection port where the NMOS transistor replacement resistor is located and the second constant voltage value is taken as the ground bounce voltage drop.

6. The static analysis method for circuit layout according to claim 1, characterized in that, The step of comparing the voltage drop with a preset threshold in the configuration file and marking the location information of the MOSFET under test whose voltage drop exceeds the preset threshold in the circuit layout includes: The voltage drop measurement value is compared one by one with the preset thresholds in the configuration file, including the power supply voltage drop threshold and the ground bounce threshold. If the measured power supply voltage drop at a port of a MOSFET under test is less than or equal to the power supply voltage drop threshold, or if the measured ground bounce voltage drop at a port of a MOSFET under test is less than or equal to the ground bounce threshold, then it is determined that the voltage drop of the layout area corresponding to the MOSFET under test meets the design requirements. If the measured power supply voltage drop at a port of a certain MOSFET under test is greater than the power supply voltage drop threshold, or if the measured ground bounce voltage drop at a port of a certain MOSFET under test is greater than the ground bounce threshold, mark the position information of the MOSFET under test in the circuit layout, and optimize the corresponding layout area according to the position information; After the layout area optimization is completed, the voltage drop of the resistor port in the obtained static simulation netlist will be remeasured and compared with the voltage threshold in the configuration file again until the circuit layout of all the MOSFETs under test meets the design requirements.

7. A static analysis system for circuit layout, characterized in that, include: The conversion unit is used to convert the equivalent resistance value of the standard MOSFET based on the channel width-to-length ratio of the MOSFET under test and the standard MOSFET, to obtain the replacement resistance value of the MOSFET under test in the post-simulation netlist, and to generate the static simulation netlist; wherein, the equivalent resistance value is the on-equivalent resistance value of the standard MOSFET during the transient switching process. The static simulation unit is used to apply an excitation signal to the power supply port of the static simulation netlist to perform static simulation and obtain the voltage drop of the target resistor port corresponding to the replacement resistor value of each of the MOSFETs under test. The determination unit is used to compare the voltage drop with a preset threshold in the configuration file and mark the location information of the MOSFET under test whose voltage drop exceeds the preset threshold in the circuit layout.

8. The static analysis system for circuit layout according to claim 7, characterized in that, The conversion unit includes: The first replacement resistor value module is used to obtain the channel width-to-length ratio of the standard PMOS transistor in the standard cell, and the channel width-to-length ratio of the PMOS transistor under test. The ratio of the channel width-to-length ratio of the PMOS transistor under test to the channel width-to-length ratio of the standard PMOS transistor is used as a first coefficient. The equivalent resistance value of the standard PMOS transistor is divided by the first coefficient to obtain the replacement resistor value of the PMOS transistor under test. The second replacement resistor value module obtains the channel width-to-length ratio of the standard NMOS transistor in the standard cell, and the channel width-to-length ratio of the NMOS transistor under test. It uses the ratio of the channel width-to-length ratio of the NMOS transistor under test to the channel width-to-length ratio of the standard NMOS transistor as a second coefficient, and divides the equivalent resistance value of the standard NMOS transistor by the second coefficient to obtain the replacement resistor value of the NMOS transistor under test.

9. The static analysis system for circuit layout according to claim 7, characterized in that, The static simulation unit includes: The excitation module is used to apply a first constant voltage value as a power supply voltage excitation signal to the power supply voltage network connection port of the static simulation netlist, and to apply a second constant voltage value as a ground voltage excitation signal to the ground network connection port, wherein the first constant voltage value is the operating voltage and the second constant voltage value is zero voltage; The static simulation module is used to run simulation tools to perform static simulation on the static simulation netlist after applying a power supply voltage excitation signal; The measurement module is used to measure the voltage value of each replacement resistor connected to the power network connection port after the simulation is completed, and to take the difference between the voltage value of the power network connection port where the PMOS transistor replacement resistor is located and the first constant voltage value as the power voltage drop, and to take the difference between the voltage value of the ground network connection port where the NMOS transistor replacement resistor is located and the second constant voltage value as the ground bounce voltage drop.

10. The static analysis system for circuit layout according to claim 7, characterized in that, The determining unit includes: The comparison module is used to compare the voltage drop measurement value with preset thresholds in the configuration file one by one. The preset thresholds include power supply voltage drop threshold and ground bounce threshold. The first determination module is used to determine that the voltage drop of the layout area corresponding to the MOSFET under test meets the design requirements if the measured value of the power supply voltage drop at the port of a certain MOSFET under test is less than or equal to the power supply voltage drop threshold, or if the measured value of the ground bounce voltage drop at the port of a certain MOSFET under test is less than or equal to the ground bounce threshold. The second determination module is used to mark the position information of the MOSFET under test in the circuit layout if the measured power supply voltage drop of a certain MOSFET port is greater than the power supply voltage drop threshold, or if the measured ground bounce voltage drop of a certain MOSFET port is greater than the ground bounce threshold, and optimize the corresponding layout area according to the position information. After the layout area optimization is completed, the voltage drop of the resistor port in the obtained static simulation netlist will be remeasured and compared with the voltage threshold in the configuration file again until the circuit layout of all the MOSFETs under test meets the design requirements.

11. An electronic device, characterized in that, The electronic device includes: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the static analysis method of the circuit layout according to any one of claims 1 to 6.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the static analysis method of the circuit layout according to any one of claims 1 to 6.

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