A performance simulation prediction method of an electrostatic protection device

Abstract

This invention relates to the field of integrated circuit technology, specifically to a performance simulation and prediction method for electrostatic discharge (ESD) protection devices. The method includes: acquiring the intrinsic parameters of each discharge unit in the ESD protection device, and the parasitic parameters of the interconnect network of the ESD protection device; determining the priority start-up unit based on the propagation delay from the external stress injection port to each discharge unit, and determining the start time of the suppression signal emitted by the priority start-up unit; for each discharge unit in the ESD protection device other than the priority start-up unit, determining the arrival time of the suppression signal of the discharge unit; and determining whether the discharge unit is in the start-up state based on the arrival time of the suppression signal of the discharge unit and the self-triggering time when the discharge unit reaches the conduction voltage threshold under the sole action of external stress. This invention improves the accuracy and computational efficiency of predicting the start-up uniformity of ESD protection devices under transient stress.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a method for performance simulation and prediction of electrostatic discharge (ESD) protection devices. Background Technology

[0002] Electrostatic discharge (ESD) protection is a critical aspect of integrated circuit reliability design. In deep submicron processes, to meet the demands of high current discharge capabilities, ESD protection devices commonly employ a multi-finger parallel structure, where multiple identical discharge units are connected in parallel between the external input / output port and ground. Ideally, when transient electrostatic stress is applied to the external port, all parallel discharge units should conduct simultaneously to provide the maximum discharge path. However, in actual devices, due to layout constraints and the physical distribution of interconnect traces, the electrical distance between each discharge unit and the external port varies. This causes the timing of stress signal reception differs among the discharge units, resulting in uneven activation and severely impacting the overall protection capability of the device.

[0003] Currently, existing performance simulations of electrostatic discharge (ESD) devices primarily focus on the intrinsic characteristics of individual discharge units or simply consider some parasitic parameters of the interconnect network. They fail to comprehensively and systematically combine the combined effects of the intrinsic parameters of the discharge units and the parasitic parameters of the interconnect network, leading to discrepancies between the simulation process and actual operating scenarios. The overall accuracy and reliability of existing ESD device performance simulation methods are insufficient, failing to accurately reflect the activation state of each discharge unit under actual ESD stress. Consequently, it is difficult to accurately predict the overall ESD withstand capability of ESD devices, thus failing to meet the design requirements for high-precision and high-reliability devices. Summary of the Invention

[0004] To address the technical challenge of balancing accuracy and computational efficiency in predicting the uniformity of electrostatic discharge (ESD) device activation under transient stress, this invention aims to provide a performance simulation and prediction method for ESD devices. The specific technical solution adopted is as follows: Firstly, a performance simulation and prediction method for electrostatic discharge (ESD) protection devices is provided. This method includes: acquiring intrinsic parameters of each discharge unit in the ESD protection device, and parasitic parameters of the interconnection network of the ESD protection device. The intrinsic parameters characterize the conduction voltage threshold, action delay, and equivalent capacitance of the discharge unit under transient stress. The parasitic parameters characterize the physical delay and path impedance of signal transmission between any two discharge units. Based on the propagation delay from the external stress injection port to each discharge unit, a priority activation unit is determined from all discharge units. The start time of the priority activation unit emitting a suppression signal is determined based on the conduction voltage threshold, action delay, and propagation delay of the priority activation unit. For each discharge unit in the ESD protection device other than the priority activation unit, the arrival time of the suppression signal of the discharge unit is determined based on the start time corresponding to the priority activation unit, the physical delay between the priority activation unit and the discharge unit, and the waveform loss delay of the corresponding path. The waveform loss delay is determined based on the path impedance and the equivalent capacitance of the discharge unit. Based on the arrival time of the suppression signal of the discharge unit and the self-triggering time when the discharge unit reaches the conduction voltage threshold under the sole action of external stress, it is determined whether the discharge unit is in an activated state.

[0005] In one possible design, the intrinsic parameters of each discharge unit in the electrostatic discharge device are obtained, including: applying an ultrafast transmission line pulse to a single-finger discharge unit with the same process as the discharge unit in the electrostatic discharge device, and acquiring the transient response voltage waveform of the single-finger discharge unit; determining the voltage value corresponding to the peak point of the rising edge in the transient response voltage waveform as the turn-on voltage threshold, and determining the time difference between the voltage dropping from the turn-on voltage threshold to the preset low impedance holding voltage as the action delay; obtaining the equivalent capacitance of each discharge unit according to the structural type of each discharge unit, the equivalent capacitance being used to characterize the equivalent capacitance value of the discharge unit trigger node to ground.

[0006] In one possible design, obtaining the parasitic parameters of the interconnect network of the electrostatic discharge (ESD) protection device includes: extracting parasitic parameters from the layout netlist of the ESD protection device; identifying the metal interconnect path connecting any two discharge cells for any two discharge cells; for each metal interconnect path, obtaining the total parasitic inductance and total parasitic capacitance of the metal interconnect path, and determining the lossless propagation time of the signal between the two discharge cells corresponding to the metal interconnect path based on the total parasitic inductance and total parasitic capacitance; constructing a first parameter matrix based on the lossless propagation time corresponding to each metal interconnect path, the first parameter matrix being used to characterize the physical delay of signal transmission between any two discharge cells; and constructing a second parameter matrix based on the series DC resistance of each metal interconnect path, the second parameter matrix being used to characterize the path impedance of signal transmission between any two discharge cells.

[0007] In one possible design, the priority activation units are determined from all discharge units based on the propagation delay from the external stress injection port to each discharge unit. This includes: acquiring the group delay of the signal propagating from the external stress injection port to the input of each discharge unit, and obtaining the propagation delay corresponding to each discharge unit; sorting the propagation delays corresponding to all discharge units in ascending order of value, and determining the discharge units with the smallest preset number of propagation delays as priority activation units.

[0008] In one possible design, the start time for the priority activation unit to emit a suppression signal is determined based on the conduction voltage threshold, action delay, and propagation delay of the priority activation unit. This includes: for each priority activation unit, determining the first voltage setup time required for the external stress to drive the priority activation unit to reach the conduction voltage threshold based on the conduction voltage threshold and the stress voltage rise rate of the priority activation unit; and superimposing the first voltage setup time, propagation delay, and action delay corresponding to the priority activation unit to obtain the start time for the priority activation unit to emit a suppression signal. The start time is used to characterize the moment when the priority activation unit completes the conduction trigger and begins to transmit the suppression signal to other discharge units.

[0009] In one possible design, determining the waveform loss delay includes: obtaining the path impedance of the metal interconnect path between the priority turn-on unit and the discharge unit; determining the waveform loss delay based on the path impedance, the equivalent capacitance of the discharge unit, and a preset waveform equivalence coefficient, wherein the preset waveform equivalence coefficient is used to convert the signal edge slowing effect caused by the RC network on the metal interconnect path into a time delay increment.

[0010] In one possible design, the arrival time of the suppression signal of the discharge unit is determined based on the start time corresponding to the priority activation unit, the physical delay between the priority activation unit and the discharge unit, and the waveform loss delay of the corresponding path. This includes: for each priority activation unit, the physical delay between the priority activation unit and the discharge unit, and the waveform loss delay of the corresponding path between the priority activation unit and the discharge unit are superimposed on the start time corresponding to the priority activation unit to obtain the candidate suppression arrival time corresponding to the priority activation unit; the candidate suppression arrival time with the smallest value among all candidate suppression arrival times is determined as the arrival time of the suppression signal of the discharge unit.

[0011] In one possible design, determining the self-triggering time when the discharge unit reaches the conduction voltage threshold under the sole action of external stress includes: determining the second voltage establishment time required for the external stress to drive the discharge unit to reach the conduction voltage threshold based on the conduction voltage threshold of the discharge unit and the stress voltage rise rate; superimposing the second voltage establishment time corresponding to the discharge unit with the propagation delay to obtain the self-triggering time of the discharge unit. The self-triggering time is used to characterize the moment when the discharge unit can be driven to the conduction state by external stress without internal suppression signal interference.

[0012] In one possible design, the discharge unit is determined to be in an on state based on the arrival time of the suppression signal of the discharge unit and the self-triggering time when the discharge unit reaches the conduction voltage threshold under the action of external stress alone. This includes: determining that the discharge unit is in a suppression failure state when the arrival time of the suppression signal is earlier than the self-triggering time; and determining that the discharge unit is in an on state when the arrival time of the suppression signal is later than or equal to the self-triggering time.

[0013] In one possible design, the above method further includes: for each discharge unit in the electrostatic discharge protection device, excluding the priority activation unit, determining the difference between the arrival time of the suppression signal and the self-triggering time of the discharge unit as the timing safety margin of the discharge unit, which is used to characterize the activation reliability of the discharge unit; setting the timing safety margin of the priority activation unit to a preset safety value; mapping the timing safety margins of all discharge units in the electrostatic discharge protection device to the layout geometric coordinates of the electrostatic discharge protection device to generate a visual distribution map for identifying timing failure regions; and determining the predicted total failure current of the electrostatic discharge protection device based on the number of all discharge units in the activation state, the preset discharge unit failure current value, and the preset derating factor.

[0014] The present invention has the following beneficial effects: In the performance simulation and prediction method for electrostatic discharge (ESD) devices provided by this invention, a complete parameter system describing the transient response characteristics of the discharge unit itself and the interconnection transmission characteristics between discharge units is established by acquiring the intrinsic parameters of each discharge unit in the ESD device and the parasitic parameters of the interconnection network of the ESD device. Based on this, a priority activation unit is determined from all discharge units according to the propagation delay from the external stress injection port to each discharge unit. The start time of its suppression signal emission is determined based on the conduction voltage threshold, action delay, and propagation delay of the priority activation unit, thereby establishing the emission source and start time reference of the internal suppression effect in terms of timing. For each discharge unit other than the priority activation unit, the start time corresponding to the priority activation unit, the relationship between the priority activation unit and the current discharge unit, and other parameters are considered comprehensively. By taking into account the physical delay between the two discharge units and the waveform loss delay caused by the combined effect of path impedance and the equivalent capacitance of the current discharge unit, the arrival time of the suppression signal at the current discharge unit is determined. This time is then compared with the self-triggering time when the current discharge unit reaches the conduction voltage threshold under external stress alone. This achieves precise quantification of the timing competition relationship between the propagation of the internal suppression effect and the external stress drive. In this way, by equating the hysteresis attenuation effect of the interconnect network on the signal waveform to waveform loss delay and incorporating it into the timing calculation, the hidden failure risk caused by high impedance interconnect paths can be effectively captured without the need for complex full-physics simulation. This significantly improves the accuracy of predicting the turn-on uniformity of multi-finger parallel electrostatic protection devices under nanosecond-level transient stress, while maintaining a computational complexity far lower than that of full-physics simulation. Attached Figure Description

[0015] To more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of a performance simulation and prediction system for an electrostatic protection device provided in one embodiment of the present invention; Figure 2 This is a flowchart illustrating a performance simulation and prediction method for an electrostatic protection device provided in one embodiment of the present invention. Detailed Implementation

[0017] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of a performance simulation and prediction method for an electrostatic protection device proposed according to the present invention. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments can be combined in any suitable form.

[0018] In embodiments of the present invention, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in embodiments of the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0019] In the description of this invention, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" and "more than one" refer to two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0021] The specific scheme of the performance simulation and prediction method for electrostatic protection devices provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Please see Figure 1 The diagram illustrates a structural schematic of a performance simulation and prediction system for an electrostatic protection device according to an embodiment of the present invention. Figure 1 As shown, the performance simulation and prediction system 10 for electrostatic protection devices includes a parameter acquisition module 11, a priority activation unit determination module 12, a suppression time determination module 13, a state decision module 14, and a post-processing analysis module 15.

[0023] The parameter acquisition module 11 is used to acquire the intrinsic parameters of each discharge unit in the electrostatic discharge protection device, as well as the parasitic parameters of the interconnection network of the electrostatic discharge protection device. Among them, the intrinsic parameters are used to characterize the conduction voltage threshold, action delay, and equivalent capacitance of the discharge unit under transient stress, while the parasitic parameters of the interconnection network are used to characterize the physical delay and path impedance of signal transmission between any two discharge units.

[0024] In some embodiments, the parameter acquisition module 11 applies an ultrafast transmission line pulse to a single-finger discharge unit with the same process as the electrostatic discharge device, acquires the transient response voltage waveform of the single-finger discharge unit, determines the voltage value corresponding to the peak point of the rising edge in the transient response voltage waveform as the conduction voltage threshold, and determines the time difference between the voltage dropping from the conduction voltage threshold to the preset low impedance holding voltage as the action delay; and acquires the equivalent capacitance of each discharge unit according to the structure type of each discharge unit. When the discharge unit is a metal-oxide-semiconductor field-effect transistor structure, its gate node to ground capacitance is extracted as the equivalent capacitance. When the discharge unit is a silicon controlled rectifier structure or a diode structure, its trigger node to ground equivalent junction capacitance is extracted as the equivalent capacitance. Simultaneously, the parameter acquisition module 11 extracts parasitic parameters from the layout netlist of the electrostatic protection device. For any two discharge cells, it identifies the metal interconnect path connecting the two discharge cells, obtains the total parasitic inductance and total parasitic capacitance of each metal interconnect path, and determines the lossless propagation time of the signal between the two discharge cells corresponding to the metal interconnect path based on the total parasitic inductance and total parasitic capacitance, so as to construct a first parameter matrix to characterize the physical delay; and constructs a second parameter matrix to characterize the path impedance based on the series DC resistance of each metal interconnect path.

[0025] The priority activation unit determination module 12 is used to determine the priority activation unit from all discharge units based on the propagation delay from the external stress injection port to each discharge unit, and to determine the start time of the priority activation unit emitting the suppression signal based on the conduction voltage threshold, action delay and propagation delay of the priority activation unit.

[0026] In some embodiments, the priority activation unit determination module 12 acquires the group delay of the signal propagating from the external stress injection port to the input terminal of each discharge unit, obtaining the propagation delay corresponding to each discharge unit; the propagation delays corresponding to all discharge units are sorted in ascending order of value, and a preset number of discharge units with the smallest propagation delay are determined as priority activation units. For each priority activation unit, the priority activation unit determination module 12 determines the first voltage establishment time required for the external stress to drive the priority activation unit to reach the conduction voltage threshold based on the conduction voltage threshold and the stress voltage rise rate of the priority activation unit; based on the first voltage establishment time, the propagation delay and action delay corresponding to the priority activation unit are superimposed to obtain the start time when the priority activation unit emits the suppression signal. The stress voltage rise rate is determined by the ratio of the peak voltage of the external transient pulse to the standard rise time.

[0027] The suppression time determination module 13 is used to determine the arrival time of the suppression signal of each discharge unit in the electrostatic protection device, except for the priority opening unit, based on the start time corresponding to the priority opening unit, the physical delay between the priority opening unit and the discharge unit, and the waveform loss delay of the corresponding path. The waveform loss delay is determined based on the path impedance and the equivalent capacitance of the discharge unit.

[0028] In some embodiments, the suppression time determination module 13 first determines the waveform loss delay: it obtains the path impedance of the metal interconnect path between the priority turn-on unit and the discharge unit, and determines the waveform loss delay based on the path impedance, the equivalent capacitance of the discharge unit, and a preset waveform equivalence coefficient. The preset waveform equivalence coefficient is used to convert the signal edge slowing effect caused by the RC network on the metal interconnect path into a time delay increment. For each priority turn-on unit, the suppression time determination module 13 adds the physical delay between the priority turn-on unit and the discharge unit, as well as the waveform loss delay of the path corresponding to the priority turn-on unit and the discharge unit, to the start time corresponding to the priority turn-on unit to obtain the candidate suppression arrival time corresponding to the priority turn-on unit; the candidate suppression arrival time with the smallest value among all candidate suppression arrival times is determined as the suppression signal arrival time of the discharge unit.

[0029] The status decision module 14 is used to determine whether the discharge unit is in the open state based on the arrival time of the suppression signal of the discharge unit and the self-triggering time when the discharge unit reaches the conduction voltage threshold under the action of external stress alone.

[0030] In some embodiments, the state determination module 14 determines the second voltage establishment time required for the external stress to drive the discharge unit to reach the conduction voltage threshold based on the conduction voltage threshold of the discharge unit and the stress voltage rise rate; based on the second voltage establishment time, the propagation delay corresponding to the discharge unit is superimposed to obtain the self-triggering time of the discharge unit. If the arrival time of the suppression signal is earlier than the self-triggering time, the state determination module 14 determines that the discharge unit is in a suppression failure state; if the arrival time of the suppression signal is later than or equal to the self-triggering time, the state determination module 14 determines that the discharge unit is in an on state.

[0031] The post-processing analysis module 15 is used to generate quantitative evaluation indicators and visualization maps based on the state decision results of the discharge unit.

[0032] In some embodiments, the post-processing analysis module 15 determines the timing safety margin of each discharge unit in the electrostatic discharge protection device (ESD device), excluding the priority activation unit, by the difference between the arrival time of the suppression signal and the self-trigger time of the discharge unit. This timing safety margin characterizes the activation reliability of the discharge unit. The timing safety margin of the priority activation unit is set to a preset safety value. The post-processing analysis module 15 maps the timing safety margins of all discharge units in the ESD device to the layout geometric coordinates of the ESD device, generating a visual distribution map to identify timing failure regions. Furthermore, the post-processing analysis module 15 determines the predicted total failure current of the ESD device based on the number of all discharge units in the activation state, the preset discharge unit failure current value, and the preset derating factor.

[0033] Please see Figure 2 The diagram illustrates a flowchart of a performance simulation and prediction method for an electrostatic protection device according to an embodiment of the present invention, including the following steps S201-S204.

[0034] S201. Obtain the intrinsic parameters of each discharge unit in the electrostatic discharge protection device, as well as the parasitic parameters of the interconnection network of the electrostatic discharge protection device.

[0035] Among them, the intrinsic parameters are used to characterize the conduction voltage threshold, action delay and equivalent capacitance of the discharge unit under transient stress, while the parasitic parameters of the interconnection network are used to characterize the physical delay and path impedance of signal transmission between any two discharge units.

[0036] As one possible approach, an ultrafast transmission line pulse (VF-TLP) is applied to a single-finger discharge unit with the same process as the discharge unit in an electrostatic protection device, and the transient response voltage waveform of the single-finger discharge unit is acquired.

[0037] Optionally, a single-finger discharge unit with the same process as the discharge unit in the electrostatic protection device is selected, and an ultrafast transmission line pulse with a pulse width of 5 nanoseconds and a rise time of 100 picoseconds is applied to the single-finger discharge unit. The transient response voltage waveform at both ends of the discharge unit is recorded using a high-bandwidth oscilloscope.

[0038] Furthermore, the voltage value corresponding to the peak point of the rising edge in the transient response voltage waveform is determined as the turn-on voltage threshold, and the time difference between the voltage dropping from the turn-on voltage threshold to the preset low impedance holding voltage is determined as the action delay.

[0039] In some embodiments, the peak point of the voltage rising edge is identified in the acquired transient response voltage waveform, and the voltage value corresponding to the peak point is determined as the turn-on voltage threshold. Turn-on voltage threshold This characterizes the critical terminal voltage value that a single discharge cell can withstand before being triggered to conduct, and is a key parameter for subsequently mapping the voltage-dimensional triggering condition to the time-dimensional triggering moment. Then, in the same transient response voltage waveform, the measured voltage decreases from the conduction voltage threshold. The time difference required for the voltage to drop to the preset low impedance holding voltage is defined as the action delay. The preset low impedance holding voltage can be set to 0.8 times the turn-on voltage threshold, i.e. This preset low-impedance holding voltage corresponds to the holding voltage level after the discharge unit enters a stable low-impedance discharge state. (Action delay) The discharge unit was quantified from reaching the turn-on voltage threshold. The inherent physical inertia time required for the bounce to complete and the impedance to drop sharply to a low impedance state.

[0040] Furthermore, the equivalent capacitance of each discharge unit is obtained according to the structural type of each discharge unit, wherein the equivalent capacitance is used to characterize the equivalent capacitance value of the discharge unit trigger node to ground.

[0041] In some embodiments, for discharge cells of different structural types, the equivalent capacitance The acquisition methods include: if the discharge unit is a metal-oxide-semiconductor field-effect transistor structure, then extracting the capacitance to ground of the gate node of the discharge unit as the equivalent capacitance. If the discharge unit is a thyristor rectifier structure or a diode structure, then the equivalent junction capacitance of the discharge unit trigger node or anode to ground is extracted as the equivalent capacitance. Equivalent capacitance This can be obtained through the small-signal AC simulation model provided by the process design suite. In addition, to cope with the situation where there is no measured data, this step is also configured with a preset parameter library. If no measured data is detected, the standard model parameters of the corresponding process node in the process design suite will be automatically called as default values ​​to ensure the continuity of the subsequent calculation process.

[0042] Furthermore, parasitic parameters are extracted from the layout netlist of the electrostatic protection device, and for any two discharge cells, the metal interconnect path connecting the two discharge cells is identified.

[0043] It should be noted that the various discharge units of the electrostatic discharge protection device are electrically connected through a complex metal interconnect network. The transmission of signals between any two discharge units is simultaneously affected by the physical propagation delay caused by path parasitic inductance and capacitance, and the path impedance caused by parasitic resistance. To quantify these two effects, this embodiment of the invention constructs a first parameter matrix characterizing physical delay and a second parameter matrix characterizing path impedance based on the parasitic parameter extraction results of the layout netlist.

[0044] For each metal interconnect path, the total parasitic inductance and total parasitic capacitance of the metal interconnect path are obtained, and the lossless propagation time of the signal between the two discharge cells corresponding to the metal interconnect path is determined based on the total parasitic inductance and total parasitic capacitance.

[0045] In some embodiments, for including The layout netlist of the electrostatic discharge protection device for each parallel discharge unit was used to extract parameters using a parasitic parameter extraction tool. For each metal interconnect path, the total parasitic inductance and total parasitic capacitance of the metal interconnect path were obtained. The total parasitic inductance is determined by the length, width, thickness of the metal interconnect path and its spacing from adjacent conductors, while the total parasitic capacitance is determined by the coupling effect between the metal interconnect path and the substrate or other conductors.

[0046] For any two discharge units in the layout and ,in Identify the metal interconnect path connecting the two, and based on transmission line theory, identify the two discharge units corresponding to the signal in the metal interconnect path. and The lossless propagation time between them can be calculated using the following formula: In the formula, For discharge unit With discharge unit The total parasitic inductance of the metal interconnect path between them. This represents the total parasitic capacitance of the corresponding metal interconnect path. For the signal in the discharge unit With discharge unit The lossless propagation time between them, also known as physical delay, can also be called flight time.

[0047] Then, based on the lossless duration corresponding to each metal interconnect path, a first parameter matrix is ​​constructed. All The lossless durations are arranged in rows and columns, and the construction dimension is... First parameter matrix , its first Line 1 Column elements That is, characterizing the discharge unit With discharge unit The physical delay of signal transmission between them. First parameter matrix. It is a symmetric matrix, that is And diagonal elements This characterizes the time it takes for a signal to propagate within the same discharge unit.

[0048] Furthermore, a second parameter matrix is ​​constructed based on the series DC resistance of each metal interconnect path, wherein the second parameter matrix is ​​used to characterize the path impedance of signal transmission between any two discharge units.

[0049] In some embodiments, the series DC resistance of each metal interconnect path is obtained. The series DC resistance is determined based on the material resistivity, length, and cross-sectional area of ​​the metal interconnect path. It is determined by the series DC resistance of each metal interconnect path. The construction dimension is The second parameter matrix , its first Line 1 Column elements That is, characterizing the discharge unit With discharge unit The path impedance for signal transmission between them. (Compared to the first parameter matrix.) Similarly, the second parameter matrix Also a symmetric matrix, i.e. And diagonal element .

[0050] Based on this, the intrinsic parameters of each discharge unit in the electrostatic discharge protection device and the parasitic parameters of the interconnection network of the electrostatic discharge protection device were obtained through the above process.

[0051] S202. Based on the propagation delay from the external stress injection port to each discharge unit, determine the priority start unit from all discharge units, and determine the start time of the priority start unit issuing the suppression signal based on the conduction voltage threshold, action delay, and propagation delay of the priority start unit.

[0052] It should be noted that before selecting priority activation units, a unified absolute time reference must first be established within the scope of the ESD protection device to eliminate the spatiotemporal differences caused by the different physical locations of each discharge unit, ensuring that all subsequent timing comparisons are performed in the same time coordinate system. Specifically, the external stress injection port of the ESD protection device, i.e., the input / output pad nodes, is defined as the signal injection source, and its corresponding time zero point is set to [missing information]. .

[0053] As one possible implementation, for each discharge unit in the electrostatic protection device ,in , To determine the total number of discharge units in an electrostatic discharge (ESD) device, the group delay of the signal propagating from the external stress injection port to the input of the discharge unit is calculated using electromagnetic field simulation or static timing analysis tools. This yields the total number of discharge units. Corresponding propagation delay Among them, the propagation delay Used to characterize the arrival of external stress signals from the port at the discharge unit. The required propagation time also represents the moment when the discharge unit is relative to the external stress applied. The time offset.

[0054] Furthermore, the propagation delays of all discharge units are sorted in ascending order. A predetermined number of discharge units with the smallest propagation delays are identified as priority activation units. These predetermined number of priority activation units form a priority activation unit set, denoted as […]. .

[0055] It should be noted that, since external stress is injected through the same port, and due to the limited propagation speed of electromagnetic waves, the discharge unit closest to the port in electrical distance will inevitably accumulate charge and reach the conduction condition first. Therefore, the group of discharge units that are first subjected to stress impact can be selected by measuring the propagation delay of each discharge unit, and these units can be identified as the priority activation units.

[0056] In some embodiments, the preset quantity is denoted as Its value selection strategy can be based on the total scale of the discharge units of the electrostatic protection device. Make dynamic adjustments. For example, consider... ,in This is the coverage factor, ranging from 5% to 10%, for example, it can be set to 8% to ensure coverage stress concentration in the worst-case scenario; a very small time window can also be set. For example, for 10 picoseconds, select all that meet the criteria. The discharge unit is used as the priority activation unit. This is the minimum propagation delay among all discharge units. This flexible screening mechanism ensures that the core area first subjected to stress impact can be accurately captured regardless of the size of the electrostatic protection device, avoiding the calculation anomalies that occur with fixed-ratio strategies in small-scale electrostatic protection devices.

[0057] Furthermore, for the set of units that are prioritized for activation... Each priority activation unit in First, based on the conduction voltage threshold of the priority activation unit and the stress voltage rise rate, the first voltage establishment time required for the external stress to drive the priority activation unit to reach the conduction voltage threshold is determined. Then, propagation delay and action delay are superimposed on the first voltage establishment time to obtain the start time when the priority activation unit sends out the suppression signal. This start time is used to characterize the moment when the priority activation unit completes the conduction trigger and begins to transmit the suppression signal to other discharge units.

[0058] In some embodiments, the formula for determining the start time of the suppression signal emitted by the priority activation unit is as follows: In the formula, To prioritize the activation of the unit The start time of issuing the suppression signal, To prioritize the activation of the unit The on-state voltage threshold, Let be the rate of rise of the stress voltage, and be the slope of the linear change of the external transient pulse voltage over time. The formula for their calculation is: ,in The peak voltage specified by the ESD test standard to be evaluated. The rise time of the pulse specified in this test standard is non-zero, and correspondingly... It is not zero either. The initial voltage setup time, i.e., the time required to activate the unit under the condition that the stress voltage increases linearly with a constant slope, is defined as the time required to activate the unit first. The voltage builds up from zero to the turn-on voltage threshold. Required duration. External stress signals propagate from the port to the priority activation unit. The delay in propagation To prioritize the activation of the unit Action delay indicates priority activation unit From reaching the turn-on voltage threshold The inherent physical inertia time required for the bounce to complete and the impedance to drop sharply to a low impedance state.

[0059] The priority activation unit is determined by the sum of the three durations in the above calculation formula. The start time of issuing the suppression signal This signifies that the priority activation unit is activated. The time starting point for triggering conduction and injecting a low-potential suppression signal into the common bus. The superimposed propagation delay is due to the time required for the external stress signal to travel from the external stress injection port to the input of the priority turn-on unit. The superimposed action delay is due to the time required for the priority turn-on unit to complete its internal carrier avalanche multiplication process and enter a low-impedance bounce state after the input voltage reaches the turn-on voltage threshold. This generates an effective voltage drop effect on the common bus and propagates the suppression signal to other discharge units.

[0060] S203. For each discharge unit in the electrostatic protection device except for the priority activation unit, determine the arrival time of the suppression signal of the discharge unit based on the start time corresponding to the priority activation unit, the physical delay between the priority activation unit and the discharge unit, and the waveform loss delay of the corresponding path.

[0061] Among them, the waveform loss delay is determined based on the path impedance and the equivalent capacitance of the discharge unit.

[0062] As one possible implementation, for each discharge unit in the electrostatic protection device, excluding the priority activation unit... , , This refers to the total number of discharge units in the electrostatic discharge protection device. To prioritize the activation of the unit set The total number of discharge units included, and the priority activation unit is obtained. With discharge unit The path impedance of the metal interconnect path determines the priority of cell activation. To prioritize the activation of the unit set Any one of the priority activation units in the process. Then, based on the path impedance, the equivalent capacitance of the discharge unit, and the preset waveform equivalence coefficient, the waveform loss delay is determined.

[0063] It should be noted that the unit should be enabled first. With discharge unit There are one or more electrical connection paths between them via a metal interconnect network. When a signal propagates along this path, the path impedance of the interconnect path and the discharge unit... The equivalent capacitance forms a first-order RC network, which generates a damping hysteresis effect on the voltage waveform edge of the suppressed signal, causing the signal falling edge to slow down. In this embodiment of the invention, this waveform slowing effect is equivalent to an additional delay increment on the time axis, i.e., waveform loss delay.

[0064] In some embodiments, the formula for calculating waveform loss delay is as follows: In the formula, To prioritize the activation of the unit With discharge unit Waveform loss delay of the corresponding path, To prioritize the activation of the unit With discharge unit The path impedance of the metal interconnect path, i.e., the series DC resistance of the path, is obtained from the second parameter matrix constructed in step S201 above. The data is read from the data, which characterizes the resistive loss experienced by the signal as it travels along the path. For discharge unit The equivalent capacitance is used to characterize the discharge unit. Loading effect on signal waveforms on interconnect paths The preset waveform equivalence coefficient is used to convert the signal edge slowing effect caused by the RC network on the metal interconnect path into a time delay increment, thereby calibrating the error between the first-order linear RC model and the actual nonlinear device response.

[0065] It should be noted that the preset waveform equivalent coefficients The value of is based on the step response characteristics of a first-order RC circuit. If the voltage drop to 10% of the initial value is used as the criterion for the suppression signal to take effect, then is taken as follows: In applications requiring higher precision, a transient simulation of the single-finger discharge unit in the electrostatic discharge device under analysis can be performed to extract the actual waveform's falling edge duration, which can then be used to deduce and calibrate the device. The value of can be chosen, for example, if the simulation results show that the actual waveform is established 20% slower than the theoretical resistor-capacitor model, then ... Revised to This improves adaptability and engineering adjustability.

[0066] Understandably, by mapping the physical phenomenon of signal amplitude attenuation and waveform slowing caused by resistive loss on the interconnection path of the discharge units into an equivalent processing of delay increments that can be directly superimposed in the time domain, subsequent timing comparisons can be completed without complex waveform simulations, using only simple algebraic operations.

[0067] Furthermore, in determining the priority activation unit With discharge unit Waveform loss delay of corresponding paths Then, by prioritizing the activation unit Based on the corresponding start time, a priority activation unit is superimposed. With discharge unit The physical delay and waveform loss delay between them, and the synthesized suppression signal from the priority activation unit. Propagation to the discharge unit The single-path arrival time, i.e., the time to priority activation of the unit. The corresponding candidate suppression arrival time.

[0068] In some embodiments, the formula for determining the arrival time of the candidate suppression is as follows: In the formula, To be enabled with priority unit The corresponding candidate suppression arrival time, i.e., the suppression signal from the priority enable unit. After departing, the signal is delayed by both physical propagation and waveform loss before reaching the discharge unit. The candidate suppression arrival time. To prioritize the activation of the unit The start time of issuing the suppression signal indicates the priority activation unit. The absolute starting point of the trigger conduction and the injection of a low-potential suppression signal into the common bus. To prioritize the activation of the unit With discharge unit The physical delay between them, i.e., the lossless propagation limit of the signal along the metal interconnect path between them, is derived from the first parameter matrix constructed in step S201 above. The data is read from the data, representing the signal flight time constrained by parasitic inductance and capacitance. To prioritize the activation of the unit With discharge unit The waveform loss delay of the corresponding path between them represents the equivalent delay increment in the time domain caused by the signal edge slowing effect of the RC network formed by the interconnect path impedance and the equivalent capacitance of the discharge unit.

[0069] Furthermore, the candidate suppression arrival time with the smallest value among all candidate suppression arrival times is determined as the discharge unit. The arrival time of the suppression signal is denoted as . .

[0070] It should be noted that because multiple priority activation units in the electrostatic discharge protection device simultaneously emit suppression signals, the discharge unit... The actual state depends on the first effective suppression signal to arrive. Therefore, embodiments of the present invention traverse the set of priority activation units. Each priority-enabled unit in Calculate the arrival time of the corresponding candidate suppression. The smallest value among them is selected as the discharge unit. The arrival time of the suppression signal The arrival time of the suppression signal This indicates that, after comprehensively considering the emission timing, physical propagation delay, and waveform loss delay of all priority activation units, the internal suppression mechanism can control the discharge unit. The earliest time point of the terminal voltage.

[0071] Based on this, the arrival time of the corresponding suppression signal is determined for each discharge unit in the electrostatic protection device, except for the priority activation unit.

[0072] S204. Determine whether the discharge unit is in the open state based on the arrival time of the suppression signal of the discharge unit and the self-triggering time when the discharge unit reaches the conduction voltage threshold under the action of external stress alone.

[0073] The self-triggering time is used to characterize the moment when the discharge unit can be driven to the conduction state by external stress in the absence of internal suppression signal interference.

[0074] As one possible approach, the self-triggering moment when the discharge unit reaches the conduction voltage threshold under the sole action of external stress is first determined.

[0075] In some embodiments, based on the conduction voltage threshold of the discharge unit and the stress voltage rise rate, the second voltage setup time required for the external stress to drive the discharge unit to reach the conduction voltage threshold is determined. Then, the second voltage setup time corresponding to the discharge unit is superimposed with the propagation delay to obtain the self-triggering time of the discharge unit. The calculation formula for determining the self-triggering time is as follows: In the formula, For discharge unit The self-triggering time characterizes the discharge unit in the absence of internal suppression signal interference. The absolute moment at which an object can be driven to a conductive state by external stress. For discharge unit The on-state voltage threshold, This is the rate of increase of stress voltage, and its value is not zero. The establishment time for the second voltage, i.e., the discharge unit under the condition that the stress voltage rises linearly with a constant slope. The voltage builds up from zero to the turn-on voltage threshold. Required duration. External stress signals propagate from the port to the discharge unit. The propagation delay.

[0076] Furthermore, in obtaining each discharge unit in the electrostatic protection device, excluding the priority activation unit... The arrival time of the suppression signal With self-triggering time Then, by comparing the numerical values ​​of the two, a race decision is made. The process of external stress driving the voltage rise at the discharge unit terminal and the process of internal suppression signal propagation and clamping the voltage at the discharge unit terminal constitute a time-domain competition relationship, and the one that arrives first determines the final state of the discharge unit.

[0077] At the time of arrival of the suppression signal Earlier than the self-triggered moment In the case that, This means that the internal suppression signal will cause the discharge unit to discharge under external stress. The terminal voltage is pushed up to the turn-on voltage threshold. It had already arrived and taken effect. At this point, the discharge unit... The terminal voltage is suppressed, and the signal is clamped at a low potential, unable to rise further. Therefore, it cannot be turned on, thus discharging the unit. Marked as a suppression failure state, with a corresponding state value of 0.

[0078] At the time of arrival of the suppression signal Later than or equal to the self-triggering time In the case that, This means that external stress will first damage the discharge unit. The terminal voltage is pushed up to the turn-on voltage threshold. The discharge unit has already completed its triggering and entered a low-impedance discharge state before the suppression signal arrives, thus discharging the unit. Marked as enabled, with a corresponding status value of 1.

[0079] For those belonging to the priority-enabled unit set The discharge unit within the system, acting as the causal starting point of the competitive logic, is the first to be subjected to external stress and the first to complete its triggering and conduction. It is the source of the internal suppression signal and is not affected by it. Therefore, the set of units that are preferentially activated will be prioritized. All discharge units in the system are directly set to the ON state, with a state value of 1.

[0080] Finally, iterate through all the electrostatic discharge protection devices. Each discharge unit stores the decision result of its discharge unit into an on-state distribution vector. Open state distribution vector It is a dimension A binary array, whose first... element Corresponding to the The final state of each discharge unit is represented by a value of 1, indicating that the discharge unit is in the open state, and a value of 0, indicating that the discharge unit is in the suppressed failure state. This vector intuitively reflects the opening pattern of the electrostatic protection device under transient stress conditions.

[0081] In one design, the on-state distribution vector is obtained. Based on this, embodiments of the present invention can further perform engineering quantification on the judgment results, transforming the micro-level racing judgment results into macro-level performance indicators that can directly guide engineering design.

[0082] In some embodiments, firstly, for each discharge unit in the electrostatic protection device, excluding the priority activation unit... Discharge unit The arrival time of the suppression signal With self-triggering time The difference is determined as the discharge unit. The timing safety margin is denoted as , Among them, time-series safety margin Used to characterize discharge units The reliability of the startup process.

[0083] when When the value is greater than the self-trigger time, it indicates that the suppression signal arrives later than the self-trigger time, and the discharge unit is in the open state. The larger the value, the more sufficient the safety margin for the discharge unit to open, and the less susceptible it is to interference from process fluctuations or interconnection deviations; when When the value is greater than or equal to the self-trigger time, it indicates that the suppression signal arrives earlier than the self-trigger time, and the discharge unit is in a state of suppression failure. The larger the absolute value, the earlier the suppression signal arrives, the deeper the discharge unit is clamped, and the more difficult the repair. For the priority activation unit set... Priority Enabling Unit in Since it is directly determined to be in the on state and is not involved in the above comparison, its timing safety margin is... Set it to a preset safety value, such as positive infinity or a positive value much larger than the normal margin range (e.g., 100).

[0084] Furthermore, the timing safety margin of all discharge units in the electrostatic discharge protection device... Mapped to the geometric coordinates of each discharge cell in the layout This generates a visual distribution map to identify timing failure areas. The map uses color coding technology, marking areas with positive timing safety margins as cool colors (such as green or blue) and areas with negative timing safety margins as warm colors (such as red or orange). This allows layout engineers to intuitively identify "timing failure dead zones" on ESD protection devices, enabling rapid problem localization.

[0085] Furthermore, based on the number of all discharge units in the on state, the preset discharge unit failure current value, and the preset derating factor, the predicted total failure current of the electrostatic protection device is determined, and its calculation formula is as follows: In the formula, This refers to the total number of discharge units in the electrostatic protection device that are in the ON state. The preset discharge unit failure current value characterizes the maximum current value that a single discharge unit can withstand under independent discharge conditions. The preset derating factor has a value range of 0.8 to 0.95. For example, an empirical value of 0.9 can be used to compensate for the uneven current distribution caused by thermal coupling and non-ideal current sharing effect when multiple fingers are connected in parallel. The predicted total failure current of an electrostatic discharge (ESD) device reflects its maximum current discharge capability under transient stress conditions, providing a direct quantitative basis for evaluating the device's protective performance.

[0086] In one possible design, after completing the on-state determination and timing safety margin analysis, the failed discharge units marked as having a suppression failure state are first identified from all discharge units. These failed discharge units are those whose suppression signal arrival time is earlier than their self-triggering time, and their timing safety margin is negative or zero. For each failed discharge unit, this embodiment of the invention also provides an optimization strategy to determine the suppression signal propagation path corresponding to that failed discharge unit. The suppression signal propagation path is the metal interconnection path from the priority on-state unit to the failed discharge unit. Then, based on the source information of the candidate suppression arrival times recorded during the previous calculation, the priority on-state unit that plays a decisive role in suppressing the failed discharge unit is determined, and the metal interconnection path between the priority on-state unit and the failed discharge unit is identified as the suppression signal propagation path that needs to be corrected.

[0087] After determining the suppression signal propagation path that needs modification, the arrival of the suppression signal is delayed by increasing the DC resistance value of the path. Specific methods for increasing the DC resistance include, for example, reducing the linewidth of at least a portion of the metal interconnects in the suppression signal propagation path, which increases the resistance per unit length; or adding a serpentine routing structure to the path, which extends the physical length of the metal interconnects within a limited layout space, thereby increasing both the total DC resistance and physical delay of the path. After increasing the DC resistance, the product of the path impedance and the equivalent capacitance of the failed discharge unit increases accordingly, based on the method for determining waveform loss delay, thus increasing the waveform loss delay and ultimately delaying the arrival time of the suppression signal from the priority activation unit to the failed discharge unit.

[0088] Furthermore, the increase in DC resistance must meet preset engineering constraints. The first constraint is the maximum interconnect voltage drop constraint, meaning the DC voltage drop generated by the modified suppression signal propagation path under electrostatic discharge current must not exceed the oxide breakdown voltage limit of the core circuit in the electrostatic protection device. The second constraint is the electromigration rule constraint, meaning the current density of the modified metal interconnect under electrostatic discharge transient current pulses must not exceed the electromigration limit specified for this process node. Under the premise of meeting these constraints, the DC resistance value of the suppression signal propagation path should be increased as much as possible to improve the timing safety margin of the failed discharge unit to a positive value.

[0089] Based on this, after completing the layout correction, parasitic parameters are extracted again from the corrected ESD protection device layout, the parasitic parameters of the interconnect network are updated, and the complete process from determining the priority start-up cell to calculating the timing safety margin is re-executed to verify whether the timing safety margin of the corrected failed discharge cell has turned positive. If there are still discharge cells in the suppressed failure state, the above correction steps are repeated until the timing safety margin of all discharge cells has turned positive; or, for discharge cells that are still in the suppressed failure state, the DC resistance value of the corresponding suppressed signal propagation path has reached the upper limit allowed by the maximum interconnect voltage drop constraint or electromigration rule constraint, and the DC resistance value cannot be increased without violating the constraint conditions. This achieves closed-loop optimization of the ESD protection device start-up uniformity, directly transforming the decision result of the timing competition model into engineering guidance for layout optimization. Under the premise of satisfying the maximum interconnect voltage drop constraint and electromigration rule constraint, the start-up uniformity of multi-finger parallel ESD protection devices is maximized, providing designers with a deterministic correction direction and quantitative basis, avoiding the inefficient iterative process of relying on experience trial and error in traditional design.

[0090] Understandably, in the performance simulation and prediction method for electrostatic discharge (ESD) devices provided in this embodiment of the invention, a complete parameter system describing the transient response characteristics of the discharge unit itself and the interconnection transmission characteristics between discharge units is established by acquiring the intrinsic parameters of each discharge unit in the ESD device and the parasitic parameters of the interconnection network of the ESD device. Based on this, a priority activation unit is determined from all discharge units according to the propagation delay from the external stress injection port to each discharge unit. The start time of its suppression signal emission is determined based on the conduction voltage threshold, action delay, and propagation delay of the priority activation unit, thereby establishing the emission source and start time reference of the internal suppression effect in terms of timing. For each discharge unit other than the priority activation unit, the start time corresponding to the priority activation unit, the physical delay between the priority activation unit and the current discharge unit, and other factors are comprehensively considered. The waveform loss delay caused by the combined effect of path impedance and the equivalent capacitance of the current discharge unit is used to determine the moment when the suppression signal arrives at the current discharge unit. This moment is then compared with the self-triggering moment when the current discharge unit reaches the conduction voltage threshold under external stress alone. This achieves precise quantification of the timing competition relationship between the propagation of the internal suppression effect and the external stress drive. In this way, by equating the hysteresis attenuation effect of the interconnect network on the signal waveform to waveform loss delay and incorporating it into the timing calculation, the hidden failure risk caused by high-impedance interconnect paths can be effectively captured without the need for complex full-physics simulation. This significantly improves the accuracy of predicting the uniformity of multi-finger parallel electrostatic protection devices under nanosecond-level transient stress, while maintaining a computational complexity far lower than that of full-physics simulation. This solves the technical problem in the prior art where prediction accuracy and computational efficiency cannot be simultaneously achieved.

[0091] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. The processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0092] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

Claims

1. A method of performance simulation prediction of an electrostatic protection device, characterized in that, The method includes: The intrinsic parameters of each discharge unit in the electrostatic discharge protection device and the parasitic parameters of the interconnection network of the electrostatic discharge protection device are obtained. The intrinsic parameters are used to characterize the conduction voltage threshold, action delay and equivalent capacitance of the discharge unit under transient stress. The parasitic parameters of the interconnection network are used to characterize the physical delay and path impedance of signal transmission between any two discharge units. Based on the propagation delay from the external stress injection port to each discharge unit, a priority start unit is determined from all discharge units, and based on the conduction voltage threshold, action delay, and propagation delay of the priority start unit, the start time at which the priority start unit emits a suppression signal is determined. For each discharge unit in the electrostatic protection device other than the priority activation unit, the arrival time of the suppression signal of the discharge unit is determined according to the start time corresponding to the priority activation unit, the physical delay between the priority activation unit and the discharge unit, and the waveform loss delay of the corresponding path. The waveform loss delay is determined based on the path impedance and the equivalent capacitance of the discharge unit. Based on the arrival time of the suppression signal of the discharge unit and the self-triggering time when the discharge unit reaches the conduction voltage threshold under the action of external stress alone, it is determined whether the discharge unit is in the on state.

2. The performance simulation prediction method of an electrostatic protection device according to claim 1, wherein, Obtain the intrinsic parameters of each discharge unit in the electrostatic discharge protection device, including: An ultrafast transmission line pulse is applied to a single-finger discharge unit with the same process as the discharge unit in the electrostatic protection device, and the transient response voltage waveform of the single-finger discharge unit is acquired. The voltage value corresponding to the peak point of the rising edge in the transient response voltage waveform is determined as the turn-on voltage threshold, and the time difference between the voltage dropping from the turn-on voltage threshold to the preset low impedance holding voltage is determined as the action delay. The equivalent capacitance of each discharge unit is obtained according to the structural type of each discharge unit. The equivalent capacitance is used to characterize the equivalent capacitance value of the discharge unit trigger node to ground.

3. The method of claim 1, wherein the performance simulation prediction of the electrostatic protection device is performed by a computer program. Obtaining the parasitic parameters of the interconnect network of the electrostatic protection device includes: Parasitic parameters are extracted from the layout netlist of the electrostatic protection device, and for any two discharge cells, the metal interconnect path connecting the two discharge cells is identified. For each metal interconnect path, the total parasitic inductance and total parasitic capacitance of the metal interconnect path are obtained, and the lossless propagation time of the signal between the two discharge cells corresponding to the metal interconnect path is determined based on the total parasitic inductance and total parasitic capacitance. Based on the lossless duration corresponding to each metal interconnect path, a first parameter matrix is ​​constructed. The first parameter matrix is ​​used to characterize the physical delay of signal transmission between any two discharge units. A second parameter matrix is ​​constructed based on the series DC resistance of each metal interconnect path. This second parameter matrix is ​​used to characterize the path impedance of signal transmission between any two discharge cells.

4. The method of claim 1, wherein the performance simulation prediction of the electrostatic protection device is performed by a computer program. Based on the propagation delay from the external stress injection port to each discharge unit, priority activation units are determined from all discharge units, including: The group delay of the signal propagating from the external stress injection port to the input of each discharge unit is obtained, and the propagation delay corresponding to each discharge unit is obtained. The propagation delays of all discharge units are sorted in ascending order, and a preset number of discharge units with the smallest propagation delays are determined as the priority activation units.

5. The performance simulation and prediction method for electrostatic protection devices according to claim 1, characterized in that, Based on the on-voltage threshold, action delay, and propagation delay of the priority activation unit, the start time for the priority activation unit to issue the suppression signal is determined, including: For each priority turn-on unit, the first voltage setup time required for the external stress to drive the priority turn-on unit to reach the turn-on voltage threshold is determined based on the turn-on voltage threshold of the priority turn-on unit and the stress voltage rise rate. The first voltage establishment time, propagation delay, and action delay corresponding to the priority activation unit are superimposed to obtain the start time when the priority activation unit sends out the suppression signal. The start time is used to characterize the moment when the priority activation unit completes the conduction trigger and begins to transmit the suppression signal to other discharge units.

6. The performance simulation and prediction method for electrostatic protection devices according to claim 1, characterized in that, Determining the waveform loss delay includes: Obtain the path impedance of the metal interconnect path between the priority turn-on unit and the discharge unit; The waveform loss delay is determined based on the path impedance, the equivalent capacitance of the discharge unit, and the preset waveform equivalence coefficient. The preset waveform equivalence coefficient is used to convert the signal edge slowing effect caused by the RC network on the metal interconnect path into a time delay increment.

7. The performance simulation and prediction method for electrostatic protection devices according to claim 1, characterized in that, The arrival time of the suppression signal of the discharge unit is determined based on the start time corresponding to the priority activation unit, the physical delay between the priority activation unit and the discharge unit, and the waveform loss delay of the corresponding path, including: For each priority activation unit, based on the start time corresponding to the priority activation unit, the physical delay between the priority activation unit and the discharge unit, as well as the waveform loss delay of the path corresponding to the priority activation unit and the discharge unit, are superimposed to obtain the candidate suppression arrival time corresponding to the priority activation unit. The candidate suppression arrival time with the smallest value among all candidate suppression arrival times is determined as the suppression signal arrival time of the discharge unit.

8. The performance simulation and prediction method for electrostatic protection devices according to claim 1, characterized in that, Determining the self-triggering time at which the discharge unit reaches the conduction voltage threshold under the sole action of external stress includes: Based on the conduction voltage threshold of the discharge unit and the stress voltage rise rate, determine the second voltage establishment time required for the external stress to drive the discharge unit to reach the conduction voltage threshold; The self-triggering time of the discharge unit is obtained by superimposing the second voltage establishment time corresponding to the discharge unit with the propagation delay. The self-triggering time is used to characterize the moment when the discharge unit can be driven to the conduction state by external stress without internal suppression signal interference.

9. The performance simulation and prediction method for electrostatic protection devices according to claim 1, characterized in that, Based on the arrival time of the suppression signal of the discharge unit and the self-triggering time when the discharge unit reaches the conduction voltage threshold under the sole action of external stress, it is determined whether the discharge unit is in the on state, including: If the arrival time of the suppression signal is earlier than the self-triggering time, it is determined that the discharge unit is in a suppression failure state; If the arrival time of the suppression signal is later than or equal to the self-trigger time, the discharge unit is determined to be in the on state.

10. The performance simulation and prediction method for electrostatic protection devices according to claim 1, characterized in that, The method further includes: For each discharge unit in the electrostatic protection device other than the priority activation unit, the difference between the arrival time of the suppression signal and the self-triggering time of the discharge unit is determined as the timing safety margin of the discharge unit. The timing safety margin is used to characterize the activation reliability of the discharge unit. Set the timing safety margin of the priority activation unit to a preset safety value; The timing safety margin of all discharge units in the electrostatic discharge protection device is mapped to the layout geometric coordinates of the electrostatic discharge protection device to generate a visual distribution map for identifying timing failure regions. The predicted total failure current of the electrostatic protection device is determined based on the number of all discharge units in the on state, the preset failure current value of the discharge unit, and the preset derating factor.

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