Method for determining rfid backscatter link frequency and rfid tag

Abstract

This disclosure relates to a method for determining the backscatter link frequency (BLF) of an RFID tag and an RFID tag. The method discloses a method for determining the backscatter link frequency (BLF) value in an RFID tag device by continuously evaluating an incoming waveform. Upon detection of the start of a TRCAL symbol, a first clock-driven counter and a second clock-driven counter are initialized. The first counter is associated with a first division ratio, and the second counter is associated with a second division ratio. The counters increment per clock cycle until the end of the TRCAL symbol is detected. At the end of a query command, the division ratio is determined, and the corresponding counter is selected. The counter values ​​are stored as a BLF indicator and indicate the BLF. An RFID tag is also disclosed.

Description

Technical Field

[0001] This disclosure relates to an RFID tag and a method for determining the backscatter link frequency (BLF) value in an RFID tag device by continuously evaluating an incoming waveform. Upon detection of the start of a TRCAL symbol, a first clock-driven counter and a second clock-driven counter are initialized. The first counter is associated with a first division ratio, and the second counter is associated with a second division ratio. The counters increment every clock cycle until the end of the TRCAL symbol is detected. At the end of a query command, the division ratio is determined, and the corresponding counter is selected. The counter value is stored as a BLF indicator and indicates the BLF.

[0002] Therefore, this disclosure relates to the technical field of radio frequency identification tags. Background Technology

[0003] The Radio Frequency Identification (RFID) protocol defines the physical and logical requirements for a passive backscatter, reader-first-talk (ITF) RFID system operating in the 860 MHz–960 MHz frequency range. The system includes an interrogator, also known as a reader, and a tag, also known as an electronic tag or transponder. The reader transmits information to the tag by modulating an RF signal within the 860 MHz–960 MHz frequency range. The tag receives both the information and operational energy from this RF signal. The tags are passive, meaning they receive all their operational energy from the reader's RF signal. The reader sends information to the tag by transmitting a continuous wave (CW) RF signal; the tag responds by modulating the reflection coefficient of its antenna, thereby backscattering the information signal back to the reader.

[0004] According to the protocol, the backscatter link frequency needs to conform to equation (1).

[0005] (1) BLF [Hz] = (DR [1]) / (TRCAL [s]),

[0006] The left side represents the backscatter link frequency, and the right side represents the frequency division ratio transmitted by the reader and the length of the TRCAL sent by the reader to the tag, where TRCAL is the tag-to-reader calibration symbol.

[0007] The backscatter link frequency is in Hertz (Hz), the division ratio is dimensionless, and the length of the TRCAL is in seconds (s).

[0008] According to existing technology, the calculation of the backscatter link frequency (BLF) of an RFID tag requires a digital processing unit to decode the query T→R calibration symbol TRCAL and the division ratio DR. Known circuit implementations measure the length of the TRCAL symbol and determine the BLF through calculations (e.g., by dividing and adjusting the measured TRCAL).

[0009] The known method, which involves counting the length of TRCAL symbols followed by division and adjustment to determine the backscatter link frequency, has several drawbacks. It requires the implementation of a symbol length counter and dedicated memory to store the resulting symbol lengths. Furthermore, the required divider and multiplication logic are complex, bits are freed, and adjustments are needed to account for rounding errors. Summary of the Invention

[0010] An improved method for determining the backscatter link frequency may be required, which avoids the implementation of a symbol length counter and a dedicated memory for storing the obtained symbol length, avoids complex dividers and multiplication logic, avoids bit release, and avoids adjustments to account for rounding errors. This disclosure provides a method and RFID tag utilizing a dedicated counter that can directly determine the BLF, thereby avoiding division, multiplication, and adjustment algorithms.

[0011] According to one aspect of this disclosure, a method for determining the backscatter link frequency (BLF) value in an RFID tag device is described. The method includes continuously evaluating an incoming waveform to determine the reception of a query command, wherein the query command includes the start of a T→R calibration TRCAL symbol, the end of a TRCAL symbol, and a division ratio (DR) parameter. Upon determining the start of a received TRCAL symbol, a first counter and a second counter are initialized, wherein the counters are clock-driven, and wherein the first counter is associated with a first division ratio, and the second counter is associated with a second division ratio. Before determining the end of a received TRCAL symbol, the first counter is incremented every first incrementing number of oscillator clock cycles, and the second counter is incremented every second incrementing number of oscillator clock cycles. Upon determining the received DR parameter, the division ratio is determined based on the DR parameter, and the counter associated with the determined division ratio is selected from the first and second counters as the applicable counter. The current counter value of the applicable counter is stored as a BLF indicator value, where the BLF is 1 / (BLF indicator value * oscillator clock cycle length).

[0012] According to another aspect of this disclosure, a radio frequency identification (RFID) tag device is described. The RFID tag includes a connecting member, an analog demodulator, a clock device, and a digital processing unit. The connecting member is configured to connect the RFID tag device to an antenna. The analog demodulator is configured to continuously evaluate an incoming waveform. The clock device is configured to drive a first counter and a second counter. The first counter is associated with a first division ratio, and the second counter is associated with a second division ratio. The digital processing unit is configured to determine the reception of a query command based on the evaluated waveform, wherein the query command includes the start of a T→R calibration TRCAL symbol, the end of a TRCAL symbol, and a division ratio (DR) parameter. The digital processing unit is further configured to initialize the first and second counters when the start of a received TRCAL symbol is determined. The digital processing unit is further configured to increment the first counter every first incrementing number of oscillator clock cycles, and increment the second counter every second incrementing number of oscillator clock cycles, until the end of a received TRCAL symbol is determined. The digital processing unit is further configured to determine the reception of the DR parameter. The digital processing unit is further configured to determine the division ratio based on the DR parameter after receiving a query command, and select the counter associated with the determined division ratio from the first counter and the second counter as the applicable counter. The digital processing unit is further configured to store the current counter value of the applicable counter as a BLF indicator value, where BLF is 1 / (BLF indicator value * oscillator clock cycle length).

[0013] By using a counter to count the cycles of two different division ratios, both counter values ​​for the two possible division ratios are available when the DR parameter is transmitted near the end of the query command. Since the counter increments based on the clock cycle, the counter value is based on the TRCAL symbol length. The BLF indicator value can be directly used to generate the requested return link data rate; therefore, no calculation is required and rounding errors are avoided.

[0014] In summary, this disclosure enables improvements in determining the backscatter link frequency in RFID tags.

[0015] The foregoing limitations and other aspects of this disclosure will become apparent from the examples of embodiments described below, and will be explained with reference to these examples. This disclosure will be described in more detail below with reference to examples of embodiments, but the disclosure is not limited to these examples.

[0016] Exemplary embodiments

[0017] According to an embodiment, the method may further include verifying the received query command. In the RFID tag device, the digital processing unit may be further configured to verify the received query command. Verification of the query command can enhance communication security and prevent communication errors.

[0018] According to another embodiment, the first counter may be associated with a division ratio of 8 and a first increment of 8, and / or the second counter may be associated with a division ratio of 64 / 3 and a second increment of 21 twice and 22 once within the three increment periods. Other division ratios and increments are possible, such as 16 or 128 / 3. Division ratios of 8 and 64 / 3 are the most common, and the use of these values ​​provides the best compatibility.

[0019] According to another embodiment, the first and second counters can be driven by a gated clock provided by a clock generator block driven by an oscillator. In an RFID tag device, the clocking device may include a clock generator block driven by an oscillator, and the clock generator block may be configured to provide a gated clock that drives the first and second counters. This saves energy because the gated clock is the most power-efficient clock. However, alternatives for controlling the first and second counters can be used.

[0020] According to another embodiment, the first increment number and / or the second increment number for the initial increment of the first counter and / or the second counter are predefined values. In the RFID tag device, the digital processing unit may be further configured to use the predefined values ​​as the first increment number and / or the second increment number for the initial increment of the first counter and / or the second counter. The predefined values ​​act as an offset for the initial count, thereby improving the accuracy of the resulting BLF indicator value.

[0021] According to another embodiment, the first and second counters can be directly driven by a clock provided by an oscillator, and a control signal is used to initialize and increment the counters. In the RFID tag device, the clocking device may include a clock provided by an oscillator, and the digital processing unit may be additionally configured to provide control signals to initialize and increment the counters. This option is easier to implement and integrate into existing RFID tags.

[0022] According to another embodiment, the method may further include generating a return link data rate based on the BLF indicator value and using the return link data rate to transmit data. The RFID tag device may further include an analog modulator, and the digital processing unit may be further configured to generate the return link data rate based on the BLF indicator value, and the analog modulator is configured to use the return link data rate to transmit data. Because the BLF indicator value can be directly used to generate the requested return link data rate, the RFID tag can begin transmitting data back to the reader without first performing calculations, thus consuming less time and energy.

[0023] According to another aspect, the above features can also be implemented by a computer program product, the computer program product including instructions that cause the computing device to implement any of the above methods when the program is executed by the computing device.

[0024] Furthermore, the features disclosed herein can also be implemented as hardware state machines, finite state machines, or simulations. Attached Figure Description

[0025] Figure 1 A schematic configuration of a BLF system for RFID tags according to exemplary embodiments of the present disclosure is shown;

[0026] Figure 2 A schematic circuit diagram is shown according to an exemplary embodiment of the present disclosure;

[0027] Figure 3 A flowchart illustrating a method according to an exemplary embodiment of the present disclosure is shown;

[0028] Figure 4 A schematic waveform diagram of a short TRCAL symbol according to an exemplary embodiment of the present disclosure is shown; and

[0029] Figure 5 A schematic waveform diagram of a long TRCAL symbol according to an exemplary embodiment of the present disclosure is shown. Detailed Implementation

[0030] The disclosed features will be described below with reference to the accompanying drawings. These features may include using a dedicated counter to implement the division ratio (e.g., implementing a division ratio DR=8, and implementing a division ratio DR=64 / 3 in parallel). The increment of the first (e.g., for DR=8) counter is performed periodically (e.g., every 8th clock cycle). The increment of the second (e.g., for DR=64 / 3) counter is also periodically (e.g., every 21st, 21st, and 22nd clock cycles, as...). Figure 5 (As can be seen in the image). Both counters increment only during the TRCAL period, that is, after the start of the TRCAL symbol is received and before the end of the TRCAL symbol is received. This means that the counter incrementing stops at the end of the TRCAL symbol. At this point in time, the counter value represents the desired BLF indicator value.

[0031] Figure 1 A schematic configuration of the BLF system for the RFID tag device 10 is shown. The BLF system includes a connection member 1, which may be an RF input pin that allows connection to an antenna. The BLF system further includes an analog demodulator 2, a clock device 3 (e.g., an oscillator), and a digital processing unit 4. The digital processing unit 4 has a clock divider and a BLF counter. The BLF system may also include an analog modulator 5.

[0032] The diagram does not show the power supply voltage rails, level shifters for signal level conversion, other circuit blocks of the RFID tag IC, or the antenna.

[0033] Figure 2 A schematic circuit diagram according to an exemplary embodiment of the present disclosure is shown. In this embodiment, each counter is driven by a gated clock provided by an oscillator-driven clock generator block. The signal received from the clock is recorded as the input to the counter, which is referred to as counter 1 and counter 2. Both counters also have a reset input, at which a signal for resetting the counter can be received. Each counter may have a separate reset counter, or both counters may receive a reset input signal from the same reset input. For ease of depiction, Figure 2 One or more reset inputs are not shown. The counters can be DR8 and DR64 / 3 counters, but without loss of generality, the division ratios can be different, such as 16 and 128 / 3. The signal from the clock to the counters is referred to as the first clock for the first counter (e.g., DR8) and the second clock for the second counter (e.g., DR64 / 3). The state TRCAL signal can gate the counter inputs, which ensures that the counters increment only during the reception of TRCAL symbols. In addition, gating saves energy. The two counters increment in parallel, meaning that the first counter increments whenever the first clock provides the input signal, and the second counter increments whenever the second clock provides the input signal. During the state TRCAL, that is, during the time when the BLF system is in the state of receiving TRCAL symbols, in other words, after the start of receiving TRCAL symbols and before the end of receiving TRCAL symbols by the BLF system, the first and second clocks provide the input signals. Once the state TRCAL ends, that is, the end of receiving TRCAL symbols is reached, both counters, i.e., their increments, stop, and the counters retain their values. Since these two counters cease incrementing after receiving the end of the TRCAL symbol, they retain their last values. Optionally, the values ​​can be stored in a memory element, which may be long-term memory. Alternatively, each increment can trigger the saving of the updated values. Clock signals can also be generated, transmitted, and received outside of the TRCAL symbol, but outside of the TRCAL symbol, the clock signals will not affect any incrementing of the counters.

[0034] After receiving the TRCAL symbol, that is, after receiving the end of the TRCAL symbol, process the remaining query commands including the TRCAL symbol.

[0035] Optionally, the query command can be verified to ensure its correctness.

[0036] After processing the query command, the counter values ​​for the first counter and the second counter, namely counter_1_output and counter_2_input, can be stored respectively.

[0037] Since the query command also includes the division ratio (DR) parameter, the division ratio can be determined from it. Because only one DR can be used, it is sufficient to store the counter values ​​of the counters associated with the DR indicated by the DR parameter.

[0038] Optionally, the phases of the first and second clock signals can be shifted to optimize counting accuracy; in other words, the counters have an offset of a predefined number of oscillator clock cycles, which improves accuracy. This can be achieved by using predefined values ​​(i.e., the offset) as the first and / or second increment numbers for the initial counting step (i.e., the increment of the first and / or second counters). This can be achieved, for example, in... Figure 4 and 5 As seen in the diagram, the clock divider phase, which occurs just before phase 00, enters the TRCAL state. The counters are initialized to zero, and the predefined increment for the first increment is two, while the predefined increment for the second increment is eight. Then, the increment for subsequent increment cycles is eight for the first counter (DR8) and twenty-one for the second counter (DR64 / 3).

[0039] As an overview, in Figure 3 The exemplary BLF determination sequence shown as method 100 may include the following features. This exemplary embodiment considers a reader or writer transmitting a waveform encoded with T→R calibration (TRCAL) symbols and a frequency division ratio (DR). The RFID tag device 10 continuously evaluates the incoming waveform, which in Figure 3 The figure is shown with reference numeral 110. The RFID tag device is configured to receive a query command from a reader. The query command includes the start of the T→R calibration TRCAL symbol, the end of the TRCAL symbol, and the frequency division ratio DR parameter.

[0040] RFID tag 10 receives a TRCAL symbol as part of a preamble sequence, which is part of a query command. Digital processing unit 4 can determine that the TRCAL symbol is starting and can enter a unique state for receiving the TRCAL symbol.

[0041] Tag 10 has two counters, each associated with a different division ratio. During evaluation 110, the RFID reader device determines the start of a received TRCAL symbol and, in response, initializes the counters in step 120. In step 130, the counters increment according to the clock cycle of the clock device until the end of the TRCAL symbol is received, as described below.

[0042] Both counters are initialized to 120 at the start of the TRCAL state and increment by 130 periodically during the TRCAL state. The first counter increments after a first number of cycles, and the second counter increments after a second number of cycles. For example, if the first counter is associated with a division ratio of 8, it increments every 8th oscillator clock cycle. Similarly, if the second counter is associated with a division ratio of 64 / 3, it increments every 21st or 22nd oscillator clock cycle. Thus, in three increments, 21 cycles are used twice and 22 cycles are used once, such that after three increments, 64 oscillator clock cycles have elapsed. Any order can be used (21, 21, 22; 21, 22, 21; or 22, 21, 21).

[0043] The counter is associated with a division ratio, which in turn relates to the number of clock cycles elapsed before the corresponding counter increments. As a first example, a division ratio of 8 can be associated with a first counter, which may be referred to as DR8 to indicate the associated division ratio. The DR8 counter increments after every 8 oscillator clock cycles. This can be achieved... Figure 4 and 5 As seen in the diagram, the DR8 counter value is shown as the first counter. After receiving the start of TRCAL, the first counter is initialized (after a short offset as detailed above), which indicates that the TRCAL symbol signal changes from zero to one, meaning the BLF system enters the TRCAL state in the next clock cycle, as indicated by the TRCAL state signal. The value of the first counter increments by one every eight oscillator clock cycles, as shown in the diagram, until the end of the TRCAL symbol, for example, in... Figure 4 As shown, after clock cycle 30, the TRCAL symbol changes from zero to one again.

[0044] After receiving the end of the TRCAL symbol, the exit state TRCAL is entered. Figure 4 and 5 The TRCAL state returns to zero to indicate that the continuous evaluation of waveform 110 continues during clock cycle 31, but subsequent steps are independent of the evaluation cycle.

[0045] The counter stops incrementing at the end of the TRCAL symbol, and the corresponding counter value can be stored separately. Figure 4 In the diagram, at the end of the TRCAL state, counter 1 has a value of 4, and counter 2 has a value of 2. Several transitions in the diagram are indicated by the / / symbol. Figure 5In this context, the values ​​are 10 and 4, respectively. Query commands continue to be received, and, for example, the frequency division ratio (DR) parameter is received near the end of the query command. This DR parameter may also be stored separately. Optionally, the complete query command can be verified in step 145 to enhance security after it has been received.

[0046] In step 140, the division ratio is determined based on the DR parameter. For example, a DR parameter of zero indicates that the RFID tag will use a division ratio of 8, and a DR parameter of one indicates that the RFID tag will use a division ratio of 64 / 3.

[0047] It should be noted that verification 145 and division ratio determination 140 can be performed simultaneously or sequentially in any order. Because they are independent of each other, Figure 3 The order in the sequence is only one possibility, without loss of generality.

[0048] Based on the determined division ratio, an applicable counter can be selected in step 150. If the DR parameter of the query command indicates a value of zero, and a value of zero indicates a division ratio of 8, then the counter associated with division ratio 8 is applicable. The current value of the applicable counter is then stored as a BLF indicator value in step 160.

[0049] Therefore, the corresponding backscatter link frequency (BLF) used by the RFID tag 10 is indicated by the BLF indicator value, and the specific BLF can be determined by dividing 1 by the product of the BLF indicator value and the oscillator clock cycle length.

[0050] As an example, a typical oscillator clock period is approximately 700 ns long. The DR8 counter indicates four counts of the TRCAL symbol over approximately eight cycles, which is 4 * 8 * 700 ns = 22400 ns long.

[0051] Therefore, in other words, to generate a serial bit stream with the requested data link rate, the BLF indicator value is given to a counter timed by the oscillator clock:

[0052] 1 / (BLF indicator value * oscillator clock cycle length)

[0053] Using the above value as an example: 1 / (4*700 ns) = 357.14 kHz

[0054] The oscillator clock period can range from 100 ns to 1000 ns. Typical TRCAL symbol lengths can vary between 17200 ns and 200000 ns for DR8, and between 33200 ns and 225000 ns for DR=64 / 3. Correspondingly, the BLF range is between 465 kHz and 40 kHz for DR8, and between 640 kHz and 95 kHz for DR64 / 3.

[0055] Since the division ratio is known at the end of the query command reception, only the applicable counter value is of interest. The applicable counter value can be stored in memory as a BLF indicator value for further use.

[0056] Method 100 may proceed to step 170, which generates the return link data rate. A typical return link data rate can be in the range of 40 to 640 kbit / s, derived from the aforementioned frequency values ​​(i.e., 40 kHz to 640 kHz). Since the return link data rate can be generated solely from the BLF indicator value, the actual calculation of the BLF as described above is not necessary.

[0057] While the frequencies detailed above fall within the range commonly referred to as low frequency (LF, approximately 30 kHz to 300 kHz) or medium frequency (MF, approximately 300 to 3000 kHz), high frequency (HF, approximately 3 to 30 MHz) or even other frequency ranges applicable to RFID use the same method to identify tags, namely by incrementing a counter timed by an oscillator clock until the BLF indicator value is reached.

[0058] The data link rate can then be determined based on the encoding used. For example, using biphase space coding (also known as FM0 coding), a frequency of 40 kHz produces a data link rate of 40 kbit / s. If other coding types are used, such as Miller coding schemes, the data link rate can be determined by using divisors such as 2, 4, or 8.

[0059] For the transmission mode, the digital modulator 5 of the RFID tag 10 uses the BLF indicator value to generate the requested return link data rate. This data rate can then be used to transmit data to the reader in step 180. The data to be transmitted is digitally encoded and sent as modulated data to the analog modulator 5.

[0060] Figure 4 An example of a counter used for short TRCAL symbols is shown. In the following text, the terms "phase" or "cycle" are used to indicate... Figure 4The signal is depicted in stages. In the clock divider stages before stage 00, the TRCAL symbol is received, indicated by the TRCAL symbol signal changing from zero to one, and the TRCAL state is entered, indicated by the TRCAL state signal changing from zero to one. The first counter is initialized, indicated by the first counter's stage 0 and the reset counter signal. The first counter increments by the offset of two stages, indicated as first counter stage 0, and then increments to a value of one in stage 02. Then, every eight clock divider stages, i.e., in stages 10, 18, and 26, the first counter increments to values ​​two, three, and four, respectively. Since the TRCAL symbol ends after stage 30, indicated by the TRCAL symbol signal changing from zero to one, the TRCAL state exits in stage 31, indicated by the TRCAL state signal changing from one to zero in response to the TRCAL symbol changing from zero to one after stage 30 (i.e., the rising edge of the TRCAL symbol). Therefore, the first counter does not increment after stage 31, and its final value is four.

[0061] The second counter is initialized in phase 00 and receives an offset of 8 cycles. The second counter then increments to one and two in phases 08 and 29, respectively. The incrementing stops after the TRCAL state has returned to zero in phase 31.

[0062] Figure 5 Examples of the first and second counters used for long TRCAL symbols are shown. It can be seen that the TRCAL symbol signal has a value of one from stage 00 until stage 71, and the TRCAL state has a value of one from stage 00 to stage 76. The reset counter signal initializes the counters in stage 00, and the first counter increments a total of ten times with an offset of two in stages 02, 10, 18, 26, 34, 42, 50, 58, 66, and 74. Due to interruptions made for the sake of brevity, only the increments in stages 02, 10, 26, and 74 are shown. Similarly, the second counter increments four times after an offset of eight in stages 08, 29, 50, and 72.

[0063] The described subject matter can be implemented as a method, apparatus (i.e., RFID tag), or BLF system. The described subject matter can also be implemented in a hardware state machine or finite state machine. Furthermore, the described subject matter can be implemented as a computer program product comprising instructions that, when executed by a computing device, cause the computing device to implement the described subject matter.

[0064] Figure Labels

[0065] 1 Connecting Components

[0066] 2 Analog Demodulators

[0067] 3 clock devices

[0068] 4 digital processing units

[0069] 5 Analog Modulator

[0070] 10 RFID tag devices

[0071] 100 Method for determining backscatter link frequency

[0072] 110 Evaluate the incoming waveform

[0073] 120 Initialize Counter

[0074] 130 incrementing counter

[0075] 140 determines the frequency division ratio

[0076] 145 Verify Query Command

[0077] 150 Select Applicable Counter

[0078] 160 stores the BLF indicator value

[0079] 170 Generate Return Link Data Rate

[0080] 180 transmits data.

Claims

1. A method (100) for determining the backscatter link frequency (BLF) value in an RFID tag device, characterized in that, The method (100) includes: Continuous evaluation (110) of the incoming waveform to determine the receipt of a query command, wherein the query command includes the start of the T→R calibration TRCAL symbol, the end of the TRCAL symbol, and the division ratio DR parameter; Upon determining the start of receiving the TRCAL symbol, (120) a first counter and a second counter are initialized, wherein the counters are clock-driven, and wherein the first counter is associated with a first division ratio, and the second counter is associated with a second division ratio; Before determining that the end of the TRCAL symbol has been received, the first counter is incremented (130) every first increment number of oscillator clock cycles, and the second counter is incremented (130) every second increment number of oscillator clock cycles. Upon determining that the DR parameter has been received, the frequency division ratio is determined (140) based on the DR parameter, and a counter associated with the determined frequency division ratio is selected (150) from the first counter and the second counter as an applicable counter; and Store the current counter value of the applicable counter (160) as a BLF indicator value; The BLF is 1 / (BLF indicator value * oscillator clock cycle length).

2. The method (100) according to claim 1, characterized in that, Additionally, it includes verifying the received query command (145).

3. The method (100) according to any one of claims 1 and 2, characterized in that, The first counter is associated with a division ratio of 8, and the first increment is 8.

4. The method (100) according to any one of claims 1 to 3, characterized in that, The second counter is associated with a division ratio of 64 / 3, and the second increment number is 21 twice and 22 once during the three increment periods.

5. The method (100) according to any one of claims 1 to 4, characterized in that, The first counter and the second counter are driven by a gated clock provided by a clock generator block, which is driven by an oscillator.

6. The method (100) according to any one of claims 1 to 5, characterized in that, At least one of the following groups applies, and the group consists of the following items: The first increment number used for the initial increment (130) of the first counter is a predefined value; and The second increment number used for the initial increment (130) of the second counter is a predefined value.

7. The method (100) according to any one of claims 1 to 4, characterized in that, The first counter and the second counter are directly driven by a clock provided by an oscillator, and a control signal is used to initialize (120) and increment (130) the counter.

8. The method (100) according to any one of claims 1 to 7, characterized in that, Additionally, it includes generating (170) a return link data rate based on the BLF indicator value, and using the return link data rate to transmit (180) data.

9. A radio frequency identification (RFID) tag device (10), characterized in that, include: A connecting member (1) is configured to connect the RFID tag device to an antenna; Analog demodulator (2), which is configured to continuously evaluate the incoming waveform; A clock device (3) is configured to drive a first counter and a second counter, wherein the first counter is associated with a first division ratio and the second counter is associated with a second division ratio; as well as Digital processing unit (4), the digital processing unit being configured to The reception of the query command is determined based on the evaluated waveform, wherein the query command includes the start of the T→R calibration TRCAL symbol, the end of the TRCAL symbol, and the division ratio DR parameter. Upon determining the start of receiving the TRCAL symbol, the first counter and the second counter are initialized; The first counter is incremented every first increment number of oscillator clock cycles, and the second counter is incremented every second increment number of oscillator clock cycles, until the end of the TRCAL symbol is determined to be received. Determine the reception of DR parameters; After receiving the query command, the division ratio is determined based on the DR parameter, and the counter associated with the determined division ratio is selected from the first counter and the second counter as the applicable counter; as well as Store the current counter value of the applicable counter as a BLF indicator value; The BLF is 1 / (BLF indicator value * oscillator clock cycle length).

10. A computer program product, characterized in that, Includes instructions that, when the program is executed by a computing device, cause the computing device to perform the method (100) according to any one of claims 1 to 8.

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