An implementation method of an FPGA on-chip adaptive neural network
By using a neural network model with clearly defined roles on the PL and PS sides of the FPGA, adaptive updating of neural network parameters is achieved, solving the problem of fixed parameters after deployment of traditional on-chip neural networks on FPGAs, and improving the inference accuracy and stability of the model in complex scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAMEN UNIV
- Filing Date
- 2026-05-09
- Publication Date
- 2026-07-31
AI Technical Summary
The parameters of existing on-chip neural networks on FPGAs are fixed after deployment and cannot be adjusted adaptively, resulting in decreased inference accuracy or even failure in complex and ever-changing industrial inspection scenarios.
Neural network models are built on the PL and PS sides of the FPGA respectively. The PL side is responsible for real-time inference, and the PS side is responsible for model retraining. Data interaction is achieved through the AXI bus. The PS side updates the model parameters based on online data and deploys them to the PL side in a coordinated manner through BRAM and address lines.
It achieves adaptive updating of neural network parameters, improves the inference accuracy and stability of the model in complex scenarios, meets various industrial inspection needs, and ensures real-time performance.
Smart Images
Figure CN122491364A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of FPGA system-on-chip technology, and in particular to a method for implementing an adaptive neural network on an FPGA chip. Background Technology
[0002] With the rapid development of industrial automation and intelligent detection technologies, neural networks have been widely used in industrial inspection, environmental monitoring and other fields due to their powerful data processing and inference capabilities. FPGA (Field Programmable Gate Array) has advantages such as high parallel processing speed, low power consumption and strong customizability, making it the preferred carrier for on-chip deployment of neural networks and able to meet the high-performance requirements of real-time inference.
[0003] Currently, traditional FPGA-based on-chip neural network implementations typically deploy the neural network model only in a single region of the FPGA (PL or PS). Deploying it on the PL fully utilizes its parallel inference capabilities, but the model parameters remain fixed after deployment, making adaptive adjustments to changes in the actual application scenario impossible. Deploying it on the PS allows for parameter updates, but real-time inference performance is poor. In practical applications such as industrial inspection, the scenarios are often complex and variable. Changes in the temperature and humidity of the inspection environment, as well as fluctuations in the characteristics of the inspected object, can all cause changes in the data distribution input to the neural network, leading to a decrease in the inference accuracy of the fixed-parameter neural network model. After long-term operation, this can even result in model failure.
[0004] Therefore, how to provide a method and system that can achieve adaptive updating of neural network parameters on FPGA chip, efficiently utilize the parallel real-time inference performance of PL terminal, have a wide protection range, and be adaptable to various industrial detection scenarios has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] The purpose of this invention is to solve the problems in the prior art.
[0006] The technical solution adopted by this invention to solve its technical problem is: to provide an implementation method of an on-chip adaptive neural network for FPGA, comprising the following steps:
[0007] The deployment steps involve building neural network models on the PL and PS sides of the FPGA respectively. The PL side model is responsible for online real-time data inference, while the PS side model is responsible for retraining on the latest data. The PL side model and the PS side model are completely identical.
[0008] Start-up steps: Start the FPGA on-chip system, the PL-side model enters the real-time inference ready state, and the data acquisition channel is opened simultaneously to continuously collect online data in the application scenario.
[0009] In the inference process, the PL-side model performs real-time inference on the collected online data based on the currently deployed neural network parameters and outputs the inference results. At the same time, a continuously rewritable storage space is allocated in the FPGA to synchronously store the online data collected within a fixed period of time before the current moment, which is then stored for the PS-side model to call.
[0010] The judgment step is to determine whether a parameter update instruction for the neural network model has been received. If not, the PL end continues to perform real-time inference and data acquisition and storage operations, while the PS end remains in standby mode. If a parameter update instruction is received, the update step is initiated.
[0011] The update process involves the PS end extracting data from the current storage space as a training set, initiating a model retraining process based on the original model parameters to achieve rapid iteration of model parameters and complete the update of neural network model parameters; the PS end then packages the updated neural network model parameters, sends and deploys them to the corresponding parameter positions of the neural network model on the PL end, and completes the synchronous update of neural network parameters on the PL end.
[0012] By repeating the inference and update steps, the neural network model can continuously track and iterate on changes in the application scenario, ensuring that the model's inference performance always adapts to the actual application requirements.
[0013] Preferably, when the updated neural network model parameters are deployed to the PL-side model, the inference function is paused, and inference is quickly resumed after the parameters are updated.
[0014] Preferably, the online data collected within a fixed period of time prior to the current moment is synchronously stored and retained for use by the PS-side model. The data storage and update adopts the form of cyclically overwriting old data or stacks according to the collection time order, ensuring that the data in the storage area is always the recently collected valid data, providing reliable data support for PS-side model retraining, while avoiding the waste of storage resources.
[0015] Preferably, the storage space uses BRAM, ROM, or FIFO storage units.
[0016] Preferably, the neural network model parameter update instruction is automatically generated by preset trigger conditions on the FPGA chip or manually sent by an external control terminal; the preset trigger conditions include, but are not limited to, one or more of the following: the inference error at the PL end exceeds a threshold, a certain amount of time has passed since the last parameter update, or a preset change has occurred in the application scenario.
[0017] Preferably, the retraining process of the PS-side model adaptively adjusts the number of training iterations based on the real-time training effect of the model, ensuring the accuracy and efficiency of parameter updates, while avoiding resource consumption and time delays caused by overtraining.
[0018] Preferably, the PS terminal packages the updated neural network model parameters, sends and deploys them to the corresponding parameter location of the neural network model on the PL terminal, including the following steps:
[0019] The PS end packages the updated neural network model parameters and sends the packaged parameter data to the PL end via the AXI bus;
[0020] The PL terminal receives parameter data sent by the PS terminal and stores the parameter data in the BRAM according to the preset address;
[0021] The updated parameter data stored in BRAM is deployed to the corresponding parameter positions of the neural network model on the PL side.
[0022] Preferably, the PS terminal packages the updated neural network model parameters using an encoding method corresponding to the BRAM storage address of the PL terminal. This ensures that the PL terminal can directly store the parameters at the address after receiving them, without the need for additional address mapping conversion, thus improving parameter deployment efficiency.
[0023] Preferably, the updated parameter data stored in the BRAM is deployed to the corresponding parameter positions of the neural network model at the PL end, specifically as follows:
[0024] By using an address line and a data line, the updated parameter data stored in the BRAM is deployed to the corresponding parameter position in the PL-side neural network model. The address line is used to locate the parameter position to be updated in the PL-side neural network model, and the data line is used to transmit the updated parameter data stored in the BRAM. The two work together to achieve fast and accurate parameter deployment, ensuring the synchronization and integrity of parameter updates on the PL side.
[0025] Preferably, the PS-side model starts the model retraining process based on the model parameters updated in the last time. The model convergence speed is significantly improved compared to training with random initial parameters, and the ideal iterative effect can be achieved in a short time.
[0026] The present invention has the following beneficial effects: The present invention provides an implementation method for an adaptive neural network on an FPGA chip, which can complete the online training, parameter update and real-time inference of the neural network on the FPGA chip, giving full play to the performance advantages of parallel real-time inference on the PL end and online model training on the PS end.
[0027] 2. This invention achieves on-chip adaptive adjustment of neural network model parameters by retraining the PS-side model based on data collected within a fixed period before the current moment and synchronously updating the parameters of the PL-side model. This enables continuous tracking of changes in application scenarios, solves the industry pain point of fixed parameters and easy failure after deployment of traditional on-chip neural networks, and significantly improves the long-term stability and accuracy of model inference.
[0028] 3. This invention can adapt to the on-chip deployment requirements of various types of neural networks, has a wide range of applications, and has good application prospects in various industrial inspection scenarios.
[0029] 4. The parameter update process of this invention adopts a triggering method that combines automation and manual operation, which can be flexibly selected according to the needs of actual application scenarios. At the same time, the parameter transmission and deployment process has been optimized, and a BRAM storage and address line and data line collaborative deployment method is adopted to improve the efficiency and accuracy of parameter updates, ensure that the PL end can quickly resume real-time inference, and further guarantee the real-time performance of the system.
[0030] 5. The system structure provided by this invention is reasonably designed, with clear division of labor and collaborative work among the modules. The control module realizes real-time status monitoring and automatic command generation, and the data acquisition module can be adapted to a variety of sensors. The overall system has strong flexibility, stability and scalability, and can meet the actual needs of different industrial testing scenarios.
[0031] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments, but the present invention is not limited to the embodiments. Attached Figure Description
[0032] Figure 1 This is a flowchart illustrating an implementation method of an on-chip adaptive neural network in an FPGA according to an embodiment of the present invention.
[0033] Figure 2 This is a block diagram of the FPGA system of the present invention;
[0034] Figure 3 This is a comparison chart of the model retraining effect before and after changes in the application scenario according to an embodiment of the present invention;
[0035] Figure 4 In this embodiment of the invention, the original model parameters and random parameters are used as initial parameters to train the Loss convergence graph;
[0036] Figure 5 This is a visualization of the online root mean square error changing over time after model retraining in an embodiment of the present invention. Detailed Implementation
[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.
[0038] This invention provides a method and system for implementing an on-chip adaptive neural network on an FPGA. It can solve the problems of traditional on-chip neural networks on FPGAs, such as the inability to adaptively update parameters after deployment, easy failure, or poor real-time inference performance due to the model architecture being on the PS side. By clarifying the functional division between the PL and PS sides and constructing an efficient data interaction mechanism, it can realize on-chip adaptive updating of neural network parameters, ensuring that the model inference performance always adapts to changes in application scenarios, and is also suitable for various industrial inspection scenarios.
[0039] See Figure 1 The diagram shown is a flowchart illustrating an implementation method of an on-chip adaptive neural network for an FPGA according to an embodiment of the present invention, including the following steps:
[0040] S101, Deployment steps: Build neural network models on the PL and PS ends of the FPGA respectively. The PL end model is responsible for online real-time inference, and the PS end model is responsible for retraining with the latest data. The PL end model and the PS end model are completely identical. Establish the data interaction timing and control logic between the PL end and the PS end based on the AXI bus. The control logic is used to coordinate the working timing of the PL end and the PS end, avoid data interaction conflicts, and ensure that the parameter update process of the PS end does not affect the normal operation of the real-time inference function of the PL end.
[0041] S102, Startup steps: Start the FPGA on-chip system, the PL-side model enters the real-time inference ready state, and the data acquisition channel is opened simultaneously to continuously collect online data in the application scenario.
[0042] S103, Inference Step: The PL-side model performs real-time inference on the collected online data based on the currently deployed neural network parameters, outputs the inference results, and simultaneously allocates a continuously rewritable storage space in the FPGA to synchronously store the online data collected within a fixed period of time before the current moment, for later use by the PS-side model.
[0043] S104, Judgment step: Determine whether a neural network model parameter update instruction has been received. If not, the PL end continues to perform real-time inference and data acquisition and storage operations, while the PS end remains in standby mode. If a parameter update instruction is received, proceed to the update step.
[0044] S105, Update Steps: The PS end extracts the data in the current storage space as the training set, starts the model retraining process based on the original model parameters, realizes rapid iteration of model parameters, and completes the update of neural network model parameters; the PS end packages the updated neural network model parameters, sends and deploys them to the corresponding parameter positions of the neural network model on the PL end, and completes the synchronous update of neural network parameters on the PL end.
[0045] S106, repeat the inference step to the update step to realize the continuous tracking and iteration of the neural network model to the changes in the application scenario, and ensure that the model inference performance always adapts to the actual application requirements.
[0046] This invention uses the online gas concentration detection process as an application scenario to provide a detailed explanation of the implementation method of the FPGA on-chip adaptive neural network described in this invention, and to verify the feasibility and advantages of this method in a real-world scenario.
[0047] This embodiment is applied to online gas concentration detection. It requires real-time acquisition of relevant data obtained from laser detection of gases in a specific environment. Real-time inference is then performed using a fully connected neural network model to output accurate gas concentration values. Furthermore, fluctuations in temperature, humidity, and other factors in industrial environments can cause changes in the distribution of gas concentration detection data. Therefore, the method of this invention is needed to adaptively update the model parameters to ensure long-term stability of inference accuracy. In this embodiment, data acquisition uses an ADC real-time acquisition method. The acquired data is pooled to build a 10-6-3-1 fully connected regression model for real-time gas concentration inference.
[0048] See Figure 2 As shown, in this embodiment, a 10-6-3-1 fully connected regression neural network model is built on both the PL and PS ends of the FPGA. The PL-end model is responsible for receiving real-time data on the gas concentration related to laser detection acquired by the ADC, performing real-time inference after pooling processing, and outputting the gas concentration value. The PS-end model is responsible for continuously retaining the effective data recently acquired by the ADC after pooling processing. When a parameter update command is received, the fully connected regression model is retrained based on the recently acquired data to update the model parameters. The updated parameters are transmitted to the PL end via the AXI bus, stored in BRAM, and then deployed to the PL-end model via address and data lines to complete the synchronous parameter update and achieve adaptive adaptation of the model to changes in the gas concentration detection scenario. The fully connected regression neural network model is a 10-6-3-1 regression model, that is, the input layer has 10 neurons, the first hidden layer has 6 neurons, the second hidden layer has 3 neurons, and the output layer has 1 neuron, outputting the predicted gas concentration value.
[0049] Specifically, using FPGA development tools, a 10-6-3-1 fully connected regressive neural network model was built for both the PL and PS ends, ensuring that their network structures, number of neurons, activation functions, etc., are completely identical, differing only in functional division. Based on the AXI4-Lite bus protocol, a data interaction interface was designed. In this embodiment, two BRAM storage spaces were allocated for parameters and online data. Communication between the PL and PS ends is achieved by placing or retrieving data from the BRAM spaces according to their addresses, which reduces the dependence of data transmission on timing to a certain extent (reducing the transmission error rate) and simplifies the program logic. Control signals were also designed: the PL end provides real-time feedback on the inference status to the PS end (e.g., inference normal, inference error exceeding limits), and the PS end sends signals such as parameter update start and parameter transmission completion to the PL end, avoiding conflicts between the two operations.
[0050] Specifically, in S102, the FPGA on-chip system is started, and the 10-6-3-1 fully connected regressive neural network model on the PL end enters the real-time inference ready state. The ADC data acquisition channel is opened simultaneously, and the ADC module acquires relevant data obtained from the laser detection of gas concentration in real time. The acquisition frequency is set according to the actual detection requirements to ensure the real-time performance of the data. The pooled online data is then transmitted to the allocated BRAM.
[0051] Specifically, in S103, the PL-side model performs real-time inference on the collected online data based on the currently deployed neural network parameters, outputting the inference results. Simultaneously, a continuously rewritable storage space is allocated within the FPGA to synchronously store the online data collected within a fixed period prior to the current moment, for later use by the PS-side model. After the ADC collects the raw data, it first performs a pooling operation. In this embodiment, average pooling is used to improve subsequent inference efficiency. The pooled 10-dimensional data (corresponding to 10 neurons in the model input layer) is transmitted to the fully connected regression neural network model on the PL side. The PL-side model performs real-time inference on the data based on the currently deployed parameters, outputting a 1-dimensional gas concentration prediction value (corresponding to 1 neuron in the model output layer). The inference results are printed to the computer via serial port for viewing. Simultaneously, the pooled 10-dimensional data is synchronously stored in the storage unit, with the retention quantity set to a preset threshold. When the data volume reaches the threshold, a cyclic overwrite method is used to ensure the timeliness of the retained data.
[0052] Specifically, in S104, the inference error of the PL terminal is monitored in real time. The predicted gas concentration output by the PL terminal is compared with the actual calibrated gas concentration, the error value is calculated, and it is determined whether a neural network model parameter update instruction has been received. As time goes by, the detection scene changes due to factors such as temperature and humidity, and the model error increases or even fails. This embodiment adopts an automatic triggering method with a preset inference error threshold. When the inference error exceeds the threshold multiple times in a row or a neural network model parameter update instruction is received, the control module generates a parameter update instruction and sends it to the PS terminal. If the triggering condition is not met, the PL terminal continues to perform real-time inference, data acquisition, data pooling, and data storage operations, while the PS terminal is in a standby state and does not perform retraining operations.
[0053] During retraining, the PS (Power Supply) extracts data from the current storage space as the training set and initiates the model retraining process based on the original model parameters, enabling rapid iteration of model parameters and updating the neural network model parameters. Upon receiving the parameter update command, the PS immediately calls the data stored in the storage unit and initiates the retraining process of the 10-6-3-1 fully connected regression neural network model. During training, pooled data is used as input, and actual gas concentration calibration values are used as labels. The gradient descent algorithm is employed to iteratively update the model parameters. The number of iterations is adaptively adjusted based on the model's convergence performance until the model's training error is reduced to a preset range, completing the model parameter update. The PS packages the updated neural network model parameters and sends the packaged parameter data to the PL (Power Supply) via the AXI bus. The PS's packaging of the updated parameters uses an encoding method corresponding to the PL's BRAM storage address, ensuring that the PL can directly store the received parameters at the address without additional address mapping conversion, thus improving parameter deployment efficiency. The PS end packages the updated fully connected regressive neural network model parameters into a parameter data packet according to the preset encoding format corresponding to the BRAM storage address on the PL end, and sends the parameter data packet to the PL end via the AXI4-Lite bus.
[0054] The PL receives parameter data from the PS and stores it in the BRAM according to preset addresses. The PL also receives parameter data packets from the PS via a data interaction module, extracts the updated parameters for each layer, and stores each parameter in its corresponding address within the BRAM according to a preset address allocation rule. Each storage address in the BRAM corresponds one-to-one with each parameter in the PL's fully connected regressive neural network model, ensuring rapid parameter location and retrieval. Through the cooperation of an address line and a data line, the updated parameter data stored in the BRAM is deployed to the corresponding parameter positions in the PL's neural network model, completing the synchronous update of the PL's neural network parameters. The address line is used to locate the parameter positions to be updated in the PL's neural network model, while the data line transmits the updated parameter data stored in the BRAM. Their collaborative operation enables rapid and accurate parameter deployment, ensuring the synchronicity and integrity of the PL's parameter updates. The address line transmits the location address of the parameter to be updated in the PL model, and the data line transmits the parameter at the corresponding location. The receiver connected to the address line identifies the parameter. When the parameter is identified as its own address, it receives the data transmitted by the data line and locks it until the corresponding address is identified again. The address line and data line switch synchronously to complete the update of all parameters in sequence.
[0055] After the model parameters on the PL side are updated, the real-time inference process for gas concentration data is immediately resumed based on the updated parameters. It continues to receive online data collected by the ADC and processed by pooling, outputting predicted gas concentration values. Simultaneously, the pooled online data is stored in the storage unit, awaiting the next parameter update instruction. This inference-to-update process is repeated, enabling the fully connected regression neural network model to continuously track and iterate on changes in the gas concentration detection scenario. This ensures the model consistently outputs high-accuracy gas concentration predictions, adapting to the impact of environmental changes such as temperature and humidity fluctuations. A comparison of the model's performance before and after retraining when the application scenario changes is shown in the figure below. Figure 3 As shown, the online root mean square error data and visualization are as follows: Figure 5 As shown in Table 1, the accuracy of the retrained model is significantly improved.
[0056] Table 1 - Data on the variation of online root mean square error of the model after retraining over time:
[0057] Detected gas concentration value / % RMSE before retraining RMSE after retraining 1 4.96480131e+00 7.48010799e-02 2 4.26771021e+00 7.10247904e-02 3 3.82827282e+00 1.09726630e-01 4 2.97475123e+00 7.40504116e-02 5 1.62384832e+00 8.44383389e-02 6 1.73927739e-01 8.92483518e-02 7 1.91116059e+00 1.03465319e-01 8 3.52526760e+00 1.14799194e-01 9 4.81064701e+00 4.62221950e-02 10 6.01482821e+00 4.61094938e-02
[0058] Specifically, in step S105, the model retraining process is initiated based on the original model parameters, using the original model parameters and random parameters as initial parameters to train the loss convergence graph, as shown below. Figure 4As shown, compared to random parameters, starting the model retraining process based on existing model parameters results in a faster convergence of the loss function curve, enabling a new round of model parameter iteration to be completed more quickly.
[0059] In this embodiment, the FPGA on-chip adaptive neural network implemented by the above method can achieve adaptive parameter updates in the online gas concentration detection scenario. When the environment changes and the distribution of detection data changes, the model parameters can be quickly adjusted, and the inference error is always controlled within the preset range. Compared with the traditional fixed-parameter on-chip neural network, the inference accuracy is significantly improved, and it does not rely on an external processor, with strong real-time performance and high stability.
[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for implementing an on-chip adaptive neural network on an FPGA, characterized in that, Includes the following steps: The deployment steps involve building neural network models on the PL and PS sides of the FPGA respectively. The PL side model is responsible for online real-time data inference, while the PS side model is responsible for retraining on the latest data. The PL side model and the PS side model are completely identical. Start-up steps: Start the FPGA on-chip system, the PL-side model enters the real-time inference ready state, and the data acquisition channel is opened simultaneously to continuously collect online data in the application scenario. In the inference process, the PL-side model performs real-time inference on the collected online data based on the currently deployed neural network parameters and outputs the inference results. At the same time, a continuously rewritable storage space is allocated in the FPGA to synchronously store the online data collected within a fixed period of time before the current moment, which is then stored for the PS-side model to call. The judgment step is to determine whether a parameter update instruction for the neural network model has been received. If not, the PL end continues to perform real-time inference and data acquisition and storage operations, while the PS end remains in standby mode. If a parameter update instruction is received, the update step is initiated. The update process involves the PS end extracting data from the current storage space as a training set, initiating a model retraining process based on the original model parameters to achieve rapid iteration of model parameters and complete the update of neural network model parameters; the PS end then packages the updated neural network model parameters, sends and deploys them to the corresponding parameter positions of the neural network model on the PL end, and completes the synchronous update of neural network parameters on the PL end. By repeating the inference and update steps, the neural network model can continuously track and iterate on changes in the application scenario, ensuring that the model's inference performance always adapts to the actual application requirements.
2. The method for implementing an on-chip adaptive neural network on an FPGA according to claim 1, characterized in that, When the updated neural network model parameters are deployed to the PL-side model, the inference function is paused, and inference is quickly resumed after the parameters are updated.
3. The implementation method of the on-chip adaptive neural network in FPGA according to claim 1, characterized in that, The process involves synchronously storing online data collected within a fixed period prior to the current moment for use by the PS-side model. The data storage and update adopts a method of cyclically overwriting old data or stacks according to the collection time sequence to ensure that the data in the storage area is always the recently collected valid data, providing reliable data support for PS-side model retraining, while avoiding the waste of storage resources.
4. The method for implementing an on-chip adaptive neural network on an FPGA according to claim 1, characterized in that, The storage space uses BRAM, ROM, or FIFO storage units.
5. The method for implementing an on-chip adaptive neural network on an FPGA according to claim 1, characterized in that, The neural network model parameter update command is automatically generated by preset trigger conditions on the FPGA chip or manually sent by an external control terminal; the preset trigger conditions include, but are not limited to, one or more of the following: the inference error at the PL end exceeds a threshold, a certain amount of time has passed since the last parameter update, or a preset change has occurred in the application scenario.
6. The method for implementing an on-chip adaptive neural network on an FPGA according to claim 1, characterized in that, The retraining process of the PS-side model adaptively adjusts the number of training iterations based on the real-time training effect of the model, ensuring the accuracy and efficiency of parameter updates, while avoiding resource consumption and time delays caused by overtraining.
7. The method for implementing an on-chip adaptive neural network on an FPGA according to claim 1, characterized in that, The PS terminal packages the updated neural network model parameters, sends and deploys them to the corresponding parameter locations of the neural network model on the PL terminal, including the following steps: The PS end packages the updated neural network model parameters and sends the packaged parameter data to the PL end via the AXI bus; The PL terminal receives parameter data sent by the PS terminal and stores the parameter data in the BRAM according to the preset address; The updated parameter data stored in BRAM is deployed to the corresponding parameter positions of the neural network model on the PL side.
8. The method for implementing an on-chip adaptive neural network on an FPGA according to claim 7, characterized in that, The PS terminal packages the updated neural network model parameters using an encoding method corresponding to the BRAM storage address on the PL terminal. This ensures that the PL terminal can directly store the parameters at the address without additional address mapping conversion, thus improving parameter deployment efficiency.
9. The method for implementing an on-chip adaptive neural network on an FPGA according to claim 7, characterized in that, The updated parameter data stored in the BRAM is deployed to the corresponding parameter positions of the neural network model at the PL end, specifically as follows: By using an address line and a data line, the updated parameter data stored in the BRAM is deployed to the corresponding parameter position in the PL-side neural network model. The address line is used to locate the parameter position to be updated in the PL-side neural network model, and the data line is used to transmit the updated parameter data stored in the BRAM. The two work together to achieve fast and accurate parameter deployment, ensuring the synchronization and integrity of parameter updates on the PL side.
10. The method for implementing an on-chip adaptive neural network on an FPGA according to claim 1, characterized in that, The PS-side model starts the model retraining process based on the model parameters updated in the last time. The model convergence speed is significantly improved compared to training with random initial parameters, and the ideal iterative effect can be achieved in a short time.