Time-domain memory-in-compute neural network accelerator and layout generation method

Abstract

This application discloses a time-domain in-memory computational neural network accelerator and its layout generation method, relating to the field of integrated circuit design. It includes multiple memory cells, each storing a weight value; multiple delay cells, each coupled to a corresponding memory cell, used to generate a corresponding delay based on the weight value stored in the memory cell and an external input value; the multiple delay cells are selectively connected in series to form a delay chain based on the weight values ​​stored in their corresponding memory cells, and the delay chain is used to output the accumulated delay; wherein only the delay cell corresponding to the memory cell with a weight value of a first logic value is connected to the delay chain, while the delay cell corresponding to the memory cell with a weight value of a second logic value is not connected to the delay chain. This application can improve the energy efficiency of the time-domain in-memory computational neural network accelerator.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and in particular to a time-domain in-memory computational neural network accelerator and a layout generation method. Background Technology

[0002] With the development of IoT technology, the amount of unstructured data generated at the edge is growing rapidly, and neural networks have excellent unstructured data processing capabilities, so they are widely used in edge devices.

[0003] Edge devices have high requirements for power consumption and latency. Traditional hardware based on the von Neumann architecture requires a large amount of data transfer between the processor and memory, making it difficult to meet the requirements for power consumption and latency.

[0004] In-memory computing neural network accelerators are a promising solution, integrating computation and storage into a single unit. This enables the parallel execution of multiple simulated MAC operations within a memory array, offering one to two orders of magnitude improvement in computational energy efficiency and wake-up speed compared to traditional hardware. In-memory computing encompasses various computation mechanisms, among which time-domain computing has garnered significant attention due to its high energy efficiency and high signal margin.

[0005] However, in existing time-domain in-memory neural network accelerators, all delay units must be connected in series to ensure continuous transmission of the delay signal. This results in invalid delay operations that cannot be eliminated, thus limiting further improvements in the energy efficiency of time-domain in-memory neural network accelerators. Summary of the Invention

[0006] The purpose of this application is to provide a time-domain in-memory computational neural network accelerator and a layout generation method, which can improve the energy efficiency of the time-domain in-memory computational neural network accelerator.

[0007] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides a time-domain in-memory computation neural network accelerator, comprising: Multiple storage units, each used to store a weight value; Multiple delay units, each coupled to a corresponding storage unit, are used to generate a corresponding delay based on the weight value stored in the storage unit and the input value from an external input. The multiple delay units are selectively connected in series to form a delay chain based on the weight value stored in the corresponding storage unit. The delay chain is used to output the accumulated delay. Only the delay unit corresponding to the storage unit with a weight value of a first logical value is connected to the delay chain, while the delay unit corresponding to the storage unit with a weight value of a second logical value is not connected to the delay chain.

[0008] Secondly, this application provides a layout generation method for a time-domain in-memory computational neural network accelerator, the layout generation method being used to generate the time-domain in-memory computational neural network accelerator described in the first aspect, the method comprising: Obtain the weight parameters of the neural network to be deployed; Based on the weight parameters, a circuit schematic is generated that contains only delay units with weight values ​​of the first logic value; Based on the circuit schematic, the layout file of the standard cell library is called to generate the circuit sub-module layout of each delay unit; Automatic placement and routing is performed by calling the circuit submodule layout, wherein a delay unit is placed at the position in the layout corresponding to the storage unit with a weight value of the first logic value, and all placed delay units in the same delay chain are connected in series sequentially.

[0009] According to the specific embodiments provided in this application, the following technical effects are disclosed: This application provides a time-domain in-memory neural network accelerator and a layout generation method. In this disclosure, only the delay units corresponding to memory cells with weight values ​​of the first logical value are connected to the delay chain, while the delay units corresponding to memory cells with weight values ​​of the second logical value are not connected. Therefore, on the transmission path of the delayed signal, the delay units corresponding to the second logical value are physically skipped and no longer serve as part of the signal path. These skipped delay units do not need to flip, thus eliminating dynamic power consumption. Compared to the existing structure where all delay units must be connected in series and invalid flips cannot be avoided, this solution fundamentally eliminates the power loss caused by invalid delay operations, achieving a significant improvement in accelerator energy efficiency. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the structure of a conventional time-domain in-memory computing neural network accelerator according to an exemplary embodiment; Figure 2 This is a schematic diagram of the structure of a time-domain in-memory computing neural network accelerator according to an exemplary embodiment; Figure 3 This is a schematic diagram illustrating the effect of the structure disclosed herein compared to a traditional structure; Figure 4An exemplary embodiment of this disclosure illustrates a time-domain in-memory computing neural network accelerator based on non-volatile memory; Figure 5 An exemplary embodiment of this disclosure illustrates a time-domain in-memory computing neural network accelerator based on FeFET; Figure 6 An exemplary embodiment of this disclosure illustrates a Flash-based in-memory computational neural network accelerator. Figure 7 An exemplary embodiment of this disclosure illustrates a time-domain in-memory computation neural network accelerator based on volatile memory; Figure 8 This is a flowchart illustrating a layout generation method for a time-domain in-memory computing neural network accelerator according to an exemplary embodiment; Figure 9 This is a flowchart illustrating a layout generation method for a time-domain in-memory computing neural network accelerator according to an exemplary embodiment; Figure 10 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0013] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0014] Figure 1 This is a schematic diagram illustrating the structure of a conventional time-domain in-memory computing neural network accelerator according to an exemplary embodiment, such as... Figure 1 As shown, it includes: n storage units ( Figure 1 The storage units (bit units) are numbered sequentially as bit unit 0, bit unit 1, bit unit 2, bit unit 3... bit unit n-1. Each storage unit stores one neural network weight value. The weight value contains only two states: a first logical value (logic 1) and a second logical value (logic 0). Figure 1 The values ​​shown are "weight 0=1", "weight 1=0", "weight 2=0", "weight 3=1", etc.

[0015] n delay units ( Figure 1In the neural network, each delay unit is coupled to a corresponding storage unit, and the core parameter of the delay unit is the basic delay amount τ. The input terminals of the delay unit include: a trigger signal input terminal, a weight control terminal, and an input signal terminal. The trigger signal input terminal is the output terminal of the previous delay unit (the trigger terminal of the first delay unit is connected to the external input rising edge signal). The weight control terminal is electrically connected to the output terminal of the corresponding storage unit and receives the stored weight value. The input signal terminal receives the input value from the external input to the neural network, such as... Figure 1 The input symbols shown are "Input 0", "Input 1", "Input 2", "Input 3", ... "Input n-1".

[0016] exist Figure 1 In this approach, a delay unit is used to perform the multiplication of the neural network input and weights. When the input value multiplied by the weights equals 0, the delay unit only generates a delay. When both the input value and the weight are 1, the delay unit generates a delay. + Delay units are connected end-to-end to form a delay chain, thereby achieving delay accumulation, and the final delay is: ; Where i represents the delay unit number, weight i represents the weight value input to the i-th delay unit, input i represents the input value input to the i-th delay unit, and n represents the number of delay units. This indicates the delay generated by the delay unit when the weight value of the delay unit is 0.

[0017] The power consumption of this circuit structure is proportional to the sum of the number of toggles of all delay units.

[0018] For example, for a length of The delay chain, assuming each delay unit requires one flip... Power consumption, then the power consumption required to perform one calculation is Even if the input multiplied by the weight equals 0, the delay unit still needs to be flipped to drive the next delay unit, ensuring that the time-domain signal continues to propagate on the delay chain. This flipping does not affect the final calculation result, but it still causes power consumption.

[0019] In neural network applications, weights typically exhibit strong sparsity. For units with a weight of 0, the delay produced by the delay unit will be zero regardless of whether the input is 0 or 1. Therefore, many computational steps can be skipped in the time domain, thereby reducing power consumption.

[0020] exist Figure 1In the past, existing time-domain in-memory computing neural network accelerators could not effectively utilize unstructured sparsity. Even with zero weights, the delay units in the time-domain in-memory computing circuit would still flip and generate power consumption, which limited further improvements in the energy efficiency of time-domain computing.

[0021] To address the aforementioned issues, this disclosure proposes an unstructured sparse optimized delay chain structure for a time-domain in-memory neural network accelerator. The core principle is to interconnect only delay units with a weight of 1, while omitting those with a weight of 0, thus avoiding the switching power consumption generated by delay units with a weight of 0 during computation. This time-domain computing circuit structure can fully utilize unstructured weight sparsity, reducing delay chain power consumption to 1 / 10 to 1 / 4 of traditional structures, and is expected to achieve an INT8 computing energy efficiency greater than 200 TOPS / W.

[0022] Figure 2 This is a schematic diagram of the structure of a time-domain in-memory computing neural network accelerator according to an exemplary embodiment, such as... Figure 2 As shown, it includes: Multiple storage units ( Figure 2 Each storage unit (a bit cell) is used to store a weight value; Multiple delay units ( Figure 2 Each delay unit (where τ is located) is coupled to a corresponding storage unit and is used to generate a corresponding delay based on the weight value stored in the storage unit and the input value of the external input. The multiple delay units are selectively connected in series to form a delay chain based on the weight value stored in the corresponding storage unit. The delay chain is used to output the accumulated delay. Only the delay unit corresponding to the storage unit with a weight value of the first logical value is connected to the delay chain, and the delay unit corresponding to the storage unit with a weight value of the second logical value is not connected to the delay chain.

[0023] This accelerator is equipped with multiple independent storage units, each serving as an independent weight storage medium. Its function is to store a single 1-bit weight value for the neural network. The weight storage state of each storage unit is independent, and it can store either a first logic value or a second logic value, providing a unique weight basis for the subsequent access control of the delay unit. The storage unit type is adaptable to various memory architectures, including but not limited to non-volatile memories such as resistive random access memory (RRAM), magnetoresistive RRAM, phase-change RRAM, ferroelectric transistors, and flash memory, as well as volatile memories such as static random access memory (SRAM) and dynamic random access memory (DRAM). Each type of storage unit is electrically coupled to its corresponding delay unit, ensuring that the stored weight value can be stably transmitted to the control terminal of the delay unit.

[0024] This accelerator is equipped with multiple delay units matching the number of storage units. Each delay unit is exclusively coupled to only one storage unit and does not interact with other storage units. The delay unit generates a corresponding delay duration based on two input signals: the weight value transmitted to the corresponding storage unit and the input value of the externally input neural network. The weight value is the operating state control signal for the delay unit, and the external input value is the delay duration adjustment signal. Together, they determine whether the delay unit generates effective delay and the specific duration of the effective delay.

[0025] Multiple delay units are selectively connected in series to form a delay chain. This delay chain is used to accumulate the effective delays generated by each of the connected delay units and outputs the final accumulated delay signal through the tail end of the delay chain. This accumulated delay signal is the time domain result of the neural network multiplication and accumulation operation and can be directly used as the input for subsequent operations.

[0026] When a storage cell stores a weight value of the first logic value, its corresponding delay cell completes the path conduction and is formally connected to the serial structure of the delay chain. The effective delay it generates will participate in the accumulation operation of the delay chain. When a storage cell stores a weight value of the second logic value, its corresponding delay cell remains in the path off state and is not connected to the serial structure of the delay chain. This delay cell does not generate an effective delay and does not participate in any signal transmission or accumulation operation of the delay chain. The operation steps corresponding to this weight are skipped directly at the hardware level.

[0027] The delay units connected in the delay chain are connected in series to form a continuous signal transmission path. The input terminal of the first delay unit in the delay chain serves as the signal input terminal of the entire delay chain, used to receive external input pulse signals. The output terminal of the previous delay unit is connected to the input terminal of the next delay unit, triggering the pulse signal to be transmitted sequentially along the series direction of the delay chain. Each time the signal passes through an access delay unit, the effective delay duration generated by that unit is superimposed. The output terminal of the last access delay unit in the delay chain serves as the signal output terminal of the entire delay chain, used to output the accumulated delay signal after superimposing all effective delays. The delay duration of this signal is the sum of the effective delay durations of all access delay units, precisely corresponding to the result of the multiplication and accumulation operation of the weights and input values ​​in the neural network.

[0028] exist Figure 2 The final delay obtained is: .

[0029] In this formula, j represents the number of the delay unit in the delay chain, weight j represents the weight value of the j-th delay unit input in the delay chain, input j represents the input value of the j-th delay unit input in the delay chain, and m represents the number of delay units in the delay chain. This indicates the delay generated by the delay unit when the weight value of the delay unit is 0.

[0030] In this disclosure, only the delay units corresponding to the memory cells with a weight value of the first logic value are connected to the delay chain, while the delay units corresponding to the memory cells with a weight value of the second logic value are not connected. Therefore, on the transmission path of the delayed signal, the delay units corresponding to the second logic value are physically skipped and no longer serve as part of the signal path. These skipped delay units do not need to flip, thus eliminating dynamic power consumption. Compared to the existing structure where all delay units must be connected in series and invalid flips cannot be avoided, this solution fundamentally eliminates the power loss caused by invalid delay operations, achieving a significant improvement in accelerator energy efficiency.

[0031] In one embodiment, the first logic value is logic 1 and the second logic value is logic 0.

[0032] Since most edge computing tasks do not require modification of the network structure, the connection relationship of the delay chain can be customized during the circuit design stage based on the distribution of weights in each row. That is, all delay units with a weight of 0 are skipped, and only delay units with a weight of 1 are connected (delay units corresponding to bit units with a weight of 0 can also be directly removed to save area).

[0033] This method avoids the power consumption caused by a large number of invalid delay unit flips. Taking a neural network with a weight sparsity of 10% as an example, such as... Figure 3 The diagram shown illustrates the effect of the structure disclosed herein compared to a traditional structure.

[0034] The unstructured sparse delay chain proposed in this disclosure is applicable to time-domain in-memory computing based on various storage media, such as non-volatile memories like resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), phase-change random access memory (PCRAM), ferroelectric transistor (FeFET) and flash memory, as well as volatile memories like static random access memory (SRAM) and dynamic random access memory (DRAM). Examples based on non-volatile memories and volatile memories are given below.

[0035] Figure 4 An exemplary embodiment of this disclosure illustrates a time-domain in-memory computation neural network accelerator based on non-volatile memory, such as... Figure 4 As shown: The memory cell is a non-volatile memory, which includes: an N-type MOS transistor N3 and a non-volatile storage resistor W; the gate of the N-type MOS transistor N3 is electrically connected to the word line WL, the source is electrically connected to the source line SL, the drain is electrically connected to one end of the non-volatile storage resistor W, and the other end of the non-volatile storage resistor W is electrically connected to the bit line BL; the drain of the N-type MOS transistor N3 is also electrically connected to the source terminal of the corresponding delay cell N1.

[0036] The delay unit includes: P-type MOSFET P0, P-type MOSFET P1, N-type MOSFET N0, N-type MOSFET N1, and N-type MOSFET N2; The source of P-type MOSFET P0 is electrically connected to the power supply VDD, and its drain is electrically connected to the drain of N-type MOSFET N1. The gates of P-type MOSFET P0 and N-type MOSFET N1 are shared as the trigger signal input terminal of the delay unit. The source of N-type MOSFET N1 is electrically connected to the external input signal terminal IN, and also electrically connected to the drain of N-type MOSFET N0. The gate of N-type MOSFET N0 is the control terminal of the delay unit, electrically connected to the drain of the corresponding memory cell N-type MOSFET N3, and its source is electrically connected to ground GND. The drains of S-type transistor P0 and N-type MOSFET N1 are connected to a common junction, and are also electrically connected to the gates of P-type MOSFET P1 and N-type MOSFET N2. The source of P-type MOSFET P1 is electrically connected to the power supply VDD, and its drain is electrically connected to the drain of N-type MOSFET N2. The source of N-type MOSFET N2 is electrically connected to ground GND. The common junction of the drains of P-type MOSFET P1 and N-type MOSFET N2 is the output terminal of the delay unit. The output terminal of the previous delay unit is electrically connected to the trigger signal input terminal of the next delay unit, forming a delay chain. When the weight value stored in the storage unit is logic 1, the trigger signal input terminal of its corresponding delay unit is connected to the output terminal of the preceding delay chain via a wire, and the output terminal of its corresponding delay unit is connected to the trigger signal input terminal of the subsequent delay chain via a wire, thereby enabling the delay unit to participate in the calculation by being connected to the delay chain; when the weight value stored in the storage unit is logic 0, the trigger signal input terminal of its corresponding delay unit is short-circuited to GND, and the output terminal of its corresponding delay unit is floating, thereby enabling the corresponding delay unit to not be connected to the delay chain.

[0037] In this implementation, the memory cell stores the weights, while the delay cell generates the delay based on the product of the weights and the input. When the input is logic 1 (low level), transistor N0 is turned off, the source of transistor N1 is connected to the drain of transistor N3, and the bit line BL of the memory is grounded, forming a path from the power supply (VDD) to ground (GND). When the memory resistance is high, the path driving capability is low, resulting in a larger delay; when the resistance is low, the path driving capability is strong, resulting in a smaller delay. When the input is logic 0 (high level), transistor N0 is turned on, forming another path with a smaller toggle delay. Transistors P1 and N2 are used to invert the signal to keep the signal polarity consistent with the trigger signal, driving the next stage delay cell.

[0038] Traditional delay chains require all delay units to be connected in series, resulting in a large number of invalid flips in memory units with a weight of 0, which wastes power.

[0039] In contrast, unstructured sparse delay chains only connect delay cells corresponding to memory cells with a weight of 1, reducing power consumption waste caused by invalid flips.

[0040] like Figure 4 As shown, only the weights of storage cell one and storage cell three are 1, and the weight of storage cell two is 0. Therefore, only the output terminal of delay cell one corresponding to storage cell one is connected to the input terminal of delay cell three corresponding to storage cell three, and not the delay cell two corresponding to storage cell two.

[0041] It is worth noting that, Figure 4 The structure shown is applicable to RRAM, PCRAM, and MRAM.

[0042] If FeFET and Flash are used, only the current-limiting diode N3 needs to be removed, and the rest of the structure remains unchanged. Figure 5 An exemplary embodiment of this disclosure illustrates a time-domain in-memory computing neural network accelerator based on FeFET. Figure 6 This disclosure provides an exemplary embodiment of a Flash-based in-memory computational neural network accelerator.

[0043] exist Figure 5In this memory cell, the storage unit is a ferroelectric transistor (FeFET). The gate of the FeFET is electrically connected to the word line WL, the source is electrically connected to the source line SL, and the drain is electrically connected to the bit line BL. The drain of the FeFET is also electrically connected to the control terminal of the corresponding delay unit. The delay unit includes P-type MOSFETs P0, P1, N-type MOSFETs N0, N1, and N2. The source of P0 is electrically connected to the power supply VDD, and the drain is electrically connected to the drain of N1. The gates of P0 and N1 are shared as the trigger signal input terminal of the delay unit. The source of N1 is electrically connected to the external input signal terminal IN, and simultaneously connected to the N1... The drain of N0 is electrically connected; the gate of the N-type MOS transistor N0 is the control terminal of the delay unit, and is electrically connected to the drain of the ferroelectric transistor FeFET of the corresponding memory unit, and its source is electrically connected to ground GND; the drains of the P-type MOS transistor P0 and the N-type MOS transistor N1 are connected at a common point, and are also electrically connected to the gates of the P-type MOS transistor P1 and the N-type MOS transistor N2; the source of the P-type MOS transistor P1 is electrically connected to the power supply VDD, and its drain is electrically connected to the drain of the N-type MOS transistor N2, and the source of the N-type MOS transistor N2 is electrically connected to ground GND; the common point of the drains of the P-type MOS transistor P1 and the N-type MOS transistor N2 is the output terminal of the delay unit; the output terminal of the previous delay unit is electrically connected to the trigger signal input terminal of the next delay unit to form the delay chain.

[0044] When the weight value stored in the ferroelectric transistor FeFET is logic 1, the trigger signal input terminal of its corresponding delay unit is connected to the output terminal of the preceding delay chain through a wire, and the output terminal of its corresponding delay unit is connected to the trigger signal input terminal of the subsequent delay chain through a wire, thereby enabling the corresponding delay unit to be connected to the delay chain; when the weight value stored in the ferroelectric transistor FeFET is logic 0, the trigger signal input terminal of its corresponding delay unit is short-circuited to GND, and the output terminal of its corresponding delay unit is floating, thereby enabling the corresponding delay unit to be not connected to the delay chain.

[0045] exist Figure 6In this context, the storage unit is a flash memory. The gate of the flash memory is electrically connected to the word line WL, the source is electrically connected to the source line SL, and the drain is electrically connected to the bit line BL. The drain of the flash memory is also electrically connected to the control terminal of the corresponding delay unit. The delay unit includes P-type MOSFETs P0, P1, N-type MOSFETs N0, N1, and N2. The source of the P-type MOSFET P0 is electrically connected to the power supply VDD, and its drain is electrically connected to the drain of the N-type MOSFET N1. The gates of the P-type MOSFET P0 and the N-type MOSFET N1 are shared as the trigger signal input terminal of the delay unit. The source of the N-type MOSFET N1 is electrically connected to the external input signal terminal IN, and simultaneously connected to the gate of the N-type MOSFET N0. The drains are electrically connected; the gate of the N-type MOS transistor N0 is the control terminal of the delay unit, and is electrically connected to the drain of the flash memory of the corresponding storage unit, while its source is electrically connected to ground (GND); the drains of the P-type MOS transistor P0 and the N-type MOS transistor N1 share a common connection point, and are also electrically connected to the gates of the P-type MOS transistor P1 and the N-type MOS transistor N2; the source of the P-type MOS transistor P1 is electrically connected to the power supply VDD, and its drain is electrically connected to the drain of the N-type MOS transistor N2, while the source of the N-type MOS transistor N2 is electrically connected to ground (GND); the common connection point of the drains of the P-type MOS transistor P1 and the N-type MOS transistor N2 is the output terminal of the delay unit; the output terminal of the previous delay unit is electrically connected to the trigger signal input terminal of the next delay unit, forming the delay chain. When the weight value stored in the Flash memory is logic 1, the trigger signal input terminal of its corresponding delay unit is connected to the output terminal of the preceding delay chain via a wire, and the output terminal of its corresponding delay unit is connected to the trigger signal input terminal of the subsequent delay chain via a wire, thereby enabling the corresponding delay unit to be connected to the delay chain; when the weight value stored in the Flash memory is logic 0, the trigger signal input terminal of its corresponding delay unit is short-circuited to GND, and the output terminal of its corresponding delay unit is floating, thereby enabling the corresponding delay unit to be disconnected from the delay chain.

[0046] Figure 7 An exemplary embodiment of this disclosure illustrates a time-domain in-memory computational neural network accelerator based on volatile memory, such as... Figure 7 As shown, The storage unit is a static random access memory (SRAM), which has a positive output terminal Q and a negative output terminal QB. The delay unit includes P-type MOSFETs P0, P1, N-type MOSFETs N0, N1, N2, and N3. The source of P0 is electrically connected to the power supply VDD, and its drain is electrically connected to the drain of N1. The gates of P0 and N1 are shared as the trigger signal input terminal of the delay unit. The source of N1 is electrically connected to the drains of N0 and N3, respectively. The gate of N0 is connected to the positive output terminal of the corresponding storage unit. The output terminal Q is electrically connected, and the source terminal is electrically connected to the external input signal terminal IN. The gate of the N-type MOS transistor N3 is electrically connected to the inverted output terminal QB of the corresponding memory cell, and the source terminal is electrically connected to ground GND. The drain of the P-type MOS transistor P0 and the N-type MOS transistor N1 share a common connection point, and are also electrically connected to the gate of the P-type MOS transistor P1 and the gate of the N-type MOS transistor N2. The source of the P-type MOS transistor P1 is electrically connected to the power supply VDD, and the drain of the P-type MOS transistor N2 is electrically connected to the drain of the N-type MOS transistor N2. The source of the N-type MOS transistor N2 is electrically connected to ground GND. The common connection point of the drains of the P-type MOS transistor P1 and the N-type MOS transistor N2 is the output terminal of the delay unit. The output terminal of the previous delay unit is electrically connected to the trigger signal input terminal of the next delay unit to form the delay chain. When the weight value stored in the static random access memory (SRAM) is logic 1, the trigger signal input terminal of the corresponding delay unit is connected to the output terminal of the preceding delay chain via a wire, and the output terminal of the corresponding delay unit is connected to the trigger signal input terminal of the subsequent delay chain via a wire, thereby enabling the corresponding delay unit to be connected to the delay chain; when the weight value stored in the SRAM is logic 0, the trigger signal input terminal of the corresponding delay unit is short-circuited to GND, and the output terminal of the corresponding delay unit is floating, thereby enabling the corresponding delay unit to be not connected to the delay chain.

[0047] Specifically, in this implementation, the unstructured sparse delay chain based on volatile memory consists of N pairs of delay units cascaded with memory units. Each delay unit consists of transistors N0–N2 and P0–P1, where N1–N2 and P0–P1 form two cascaded inverters to generate the delay. The source terminal of N1 is connected to the input voltage or ground through N0 or N3, respectively, while the outputs Q and QB of the memory unit (taking SRAM as an example) control the conduction state of N0 or N3.

[0048] Taking SRAM as an example: When the stored value is "1", Q is high, QB is low, N0 is on, and N3 is off, forming a path from power supply to ground through P0, N1, and N0. The delay is determined by the input voltage; a high input voltage (e.g., 200 mV) results in a larger delay, while a low input voltage (e.g., 0 V) ​​results in a smaller delay, and the corresponding weighted multiplication result is 1. When the stored value is "0", Q is low, QB is high, N3 is on, and the source of N1 is grounded, breaking the path and generating only intrinsic delay, resulting in a multiplication result of 0. By cascading N such units, the multiplication and accumulation operation of N inputs and weights can be achieved.

[0049] In practical implementation, if the SRAM stores "1" and the input is 1 bit, the input voltage can be V0 = 0 V or V1 = 200mV (VDD = 0.6 V). When the input is V0, the delay is smaller; when the input is V1, the delay is larger. For cells storing "0", their delay units are not connected to the signal path; while for cells storing "1", such as cell three, their input is connected to the output of cell one, forming a cascaded structure.

[0050] In one embodiment, the delay unit corresponding to the storage unit with the weight value of the second logic value is equipped with a power switch, which is connected in series between the power input terminal of the delay unit and the power supply network; when the delay unit is not connected to the delay chain, the power switch is turned off, cutting off the power supply path of the delay unit.

[0051] Specifically, each delay unit has an independent power input terminal, which is connected to the global power supply network via a power switch. The power switch can be a PMOS transistor, an NMOS transistor, a transmission gate, or any switching element with on / off control function, and its control terminal is connected to the output signal of the corresponding memory unit or its logic combination.

[0052] When the weight value stored in the storage unit is the first logic value, the delay unit needs to be connected to the delay chain to participate in the delay accumulation operation. At this time, the power switch is in the on state, the delay unit receives normal power supply, and can receive input signals and generate corresponding delays.

[0053] When the weight value stored in the storage unit is the second logic value, the delay unit is not connected to the delay chain, and its output is physically disconnected from the delay chain. At this time, the power switch is in the off state, the delay unit is completely isolated from the power supply network, and the delay unit is in a completely power-off state, that is, there is no voltage supply to all power pins, and neither dynamic switching power consumption nor static leakage power consumption is generated.

[0054] This embodiment further eliminates the static power consumption of the delay units by configuring independent power switches for the delay units corresponding to the sparse weights, based on the selective series structure. Since the proportion of sparse weights in neural network models is usually high, a large number of delay units in a completely power-off state can significantly reduce the static power consumption of the entire accelerator, thereby further improving energy efficiency.

[0055] In one embodiment, the layout position of the delay unit corresponds to the layout position of the storage unit whose weight value is the first logical value.

[0056] Specifically, during the layout design phase, each memory cell occupies a specific physical region in the layout (typically composed of transistor active areas, polysilicon gates, metal interconnects, etc.). Delay cells coupled to this memory cell should be arranged in the vicinity of the corresponding memory cell, forming a one-to-one physical correspondence. This correspondence can be achieved in the following ways: During the automatic placement and routing process, electronic design automation tools place delay cell instances in adjacent areas to their corresponding memory cell instances according to the netlist definition, so as to minimize the interconnect length between them and reduce the impact of parasitic parameters on delay accuracy.

[0057] For a storage cell with a weight value of the first logical value, its corresponding delay cell will not only be placed in a nearby location, but will also be actually connected to the delay chain; for a storage cell with a weight value of the second logical value, its corresponding delay cell will not exist in the layout at all (not placed), or it will exist but not be connected (depending on the specific implementation). However, in order to save area, it is preferable not to place the delay cell at all.

[0058] Since the delay unit corresponding to the storage unit with the weight value of the second logical value is not placed, the layout area is proportional to the number of effective weights, thus avoiding wasted area.

[0059] Figure 8 This is a flowchart illustrating a layout generation method for a time-domain in-memory computing neural network accelerator according to an exemplary embodiment, such as... Figure 8 As shown, this method is used to generate a time-domain in-memory computation neural network accelerator as described in any of the above claims. The method includes the following steps S101-S104: In step S101, the weight parameters of the neural network to be deployed are obtained.

[0060] Input the weight parameters of the neural network to be deployed and the Integrated Circuit Design Toolkit (PDK) into the system. The system refers to the operating system used to run electronic design automation tools, such as Linux. It should be noted that using other operating systems to execute this method should also be protected. The weight parameters contain the weight values ​​(i.e., the first or second logical value) corresponding to each storage unit in each layer of the neural network. The PDK contains the layout files of the standard cell library (such as GDS files), Design Rule Check (DRC) rules, layout and schematic... Figure 1 Information such as consistency check (LVS) rules.

[0061] In step S102, a circuit schematic is generated based on the weight parameters, which only contains delay units with weight values ​​of the first logic value.

[0062] In one embodiment, step S102 includes the following sub-steps A1-A3: A1. Use the first scripting language to convert the weight parameters into a netlist; The weight parameters are converted into a netlist using a first scripting language (such as Python). This netlist records the weight value of each memory cell and its position in the delay chain. It should be noted that this disclosure is not limited to Python; other programming languages ​​may also be used.

[0063] A2. Load the netlist using a second scripting language and call the instantiation function to map the weights in the netlist whose weight values ​​are the first logical values ​​to delay cell instances in the standard cell library.

[0064] The netlist is loaded using a second scripting language (e.g., Skill script), and an instantiation function (e.g., schCreateInstance function) is called to map weights in the netlist with weights equal to the first logical value (e.g., logical 1) to delay cell instances in the standard cell library. For weights with weights equal to the second logical value (e.g., logical 0), no corresponding delay cell instance is created.

[0065] A3. Call the connection function to connect the delay unit instances sequentially according to the order in the delay chain to generate the circuit schematic.

[0066] The delay unit instances are connected sequentially in the delay chain by calling a connection function (such as the schCreateWire function), that is, the output of the previous delay unit is connected to the input of the next delay unit, thereby generating the circuit schematic. This netlist only contains delay units with a weight value of the first logic value; delay units with a weight value of the second logic value are not present in the netlist at all.

[0067] In step S103, based on the circuit schematic, the layout file of the standard cell library is called to generate the circuit sub-module layout of each delay unit.

[0068] Based on the circuit schematic generated in step S102, the standard cell library layout file (e.g., GDS file) in the PDK is called to generate a corresponding circuit sub-module layout for each delay cell instance. These sub-module layouts are physical graphical representations of the delay cells, containing geometric information such as transistors, contact holes, and metal interconnects.

[0069] In step S104, the circuit submodule layout is invoked to perform automatic placement and routing. Delay units are placed at positions in the layout corresponding to the storage units with weight values ​​of the first logic value, and all placed delay units in the same delay chain are connected in series sequentially.

[0070] Specifically, the circuit submodule layout generated in step S103 is invoked, and automatic placement and routing operations are performed. The placement rules are as follows: For memory cells with a weight value of the first logic value, a delay cell is placed in the layout at the position corresponding to the memory cell using a placement instruction (such as the Skill's placeinstance instruction). "Corresponding" means that the layout position of the delay cell is physically adjacent to the layout position of its corresponding memory cell; typically, the delay cell is placed next to or directly above / below the corresponding memory cell. For memory cells with a weight value of the second logic value, no delay cell is placed in its corresponding position.

[0071] After placing all delay units according to the above rules, use wiring instructions (such as Skill's connect wire instruction) to connect all the placed delay units in the same delay chain in series. That is, the output of the previous delay unit is connected to the input of the next delay unit through a metal interconnect, forming a complete delay chain structure.

[0072] In one embodiment, the above method further includes the following steps S105-S106: In step S105, the layout with completed routing is checked for design rules and connection relationships.

[0073] In step S106, if the check fails, the layout parameters or routing parameters are adjusted and automatic layout and routing is re-executed, and the check is performed again until the check passes.

[0074] After automatic placement and routing, the generated layout undergoes Design Rule Check (DRC) and Connectivity Check (LVS). DRC verifies whether the layout meets the geometric constraints of the manufacturing process (such as minimum line width, minimum spacing, etc.), while LVS verifies whether the layout's connectivity matches the circuit schematic. Figure 1To.

[0075] If the layout fails the DRC or LVS check, the layout or routing parameters are adjusted, and automatic placement and routing is re-executed, with the check repeated until it passes. Adjusting the layout or routing parameters includes at least one of the following: adjusting the placement position of delay cells, adjusting the connection paths between delay cells, changing the routing layer, or changing the trace width. This iterative optimization process can be automatically controlled by a script.

[0076] Once the layout passes all checks, the process ends, and the final layout file is output. This layout file can be directly used for chip fabrication.

[0077] The entire process described above is executed as described in a script file.

[0078] In this embodiment, although Linux is used as an example of the operating system for running electronic design automation tools, and Python and Skill are used as examples of the first and second scripting languages, respectively, the present invention is not limited thereto. Any operating system (including but not limited to Windows, macOS, etc.) capable of implementing the above scripting process, and any programming language (including but not limited to C, C++, Tcl, Perl, etc.) capable of performing functions such as weight parameter conversion, netlist loading, instantiation, and connection, should fall within the protection scope of the present invention.

[0079] Figure 9 This is a flowchart illustrating a layout generation method for a time-domain in-memory computing neural network accelerator according to an exemplary embodiment, such as... Figure 9 As shown, this method is used to generate a time-domain in-memory computation neural network accelerator as described in any of the above claims. The method includes the following steps S201-S205: The entire process is described and executed by a script file.

[0080] Step S201: Input the neural network weights and PDK file.

[0081] First, input the weight parameters of the neural network to be deployed and the integrated circuit design toolkit (PDK) into the system, which refers to the Linux system used to run electronic design automation (the method should also be protected when using other operating systems).

[0082] Step S202: Determine the connection relationship of the delay unit according to the network weight, and call the cdl file to generate the circuit schematic.

[0083] Subsequently, a circuit schematic with specific connection relationships is generated based on the network's weight parameters. Specifically, the method involves first using Python code (execution of this method using other programming languages ​​should also be protected) to convert the neural network weights into a CDL netlist file. Then, a skill script is used to load the CDL netlist file, and the `schCreateInstance` function is used to map all weights of 1 in the CDL netlist file to delay cells in a standard cell library. Finally, the `schCreateWire` function is used to connect the delay cells, thus completing the circuit schematic generation process.

[0084] Step S203: Based on the circuit schematic, call the GDS file to generate the circuit sub-module layout and automatically place and route the circuit.

[0085] Next, based on the circuit schematic, the GDS file in the PDK is called to generate the layout of all the required circuit sub-modules.

[0086] Step S204: Perform design rule checks and connection relationship checks based on the DRC file and LVS file.

[0087] The automatic placement and routing method for mapping weights in a neural network to delay units in a delay chain is as follows: If a weight in the neural network is 1, then the `place instance` command of the skill is used to place a delay unit at the corresponding position; if a weight in the neural network is 0, then no delay unit is placed at the corresponding position. After placing the delay units according to the above rules, the mapping of the neural network weights is completed. The second step is to use the `connectwire` command of the skill script to connect all delay units in the same row end to end, thus forming a complete delay chain structure. If the check fails, iterative optimization of layout and routing is required, and step S203 needs to be executed again.

[0088] Step S205: If the check is passed, the process ends.

[0089] In one exemplary embodiment, a computer device is provided, which may be a server or a terminal, and its internal structure diagram may be as follows. Figure 10As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and databases. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a layout generation method for a time-domain in-memory computational neural network accelerator.

[0090] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0091] In one exemplary embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0092] In one exemplary embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0093] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0094] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0095] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

[0096] The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchain. The processors involved in the embodiments provided in this application may be, but are not limited to, general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc.

[0097] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0098] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A time-domain in-memory computing neural network accelerator, comprising: include: Multiple storage units, each used to store a weight value; Multiple delay units, each coupled to a corresponding storage unit, are used to generate a corresponding delay based on the weight value stored in the storage unit and the input value from an external input. The multiple delay units are selectively connected in series to form a delay chain based on the weight value stored in the corresponding storage unit. The delay chain is used to output the accumulated delay. Only the delay unit corresponding to the storage unit with a weight value of a first logical value is connected to the delay chain, while the delay unit corresponding to the storage unit with a weight value of a second logical value is not connected to the delay chain.

2. The accelerator according to claim 1, characterized in that, The first logic value is logic 1, and the second logic value is logic 0.

3. The accelerator according to claim 1, characterized in that, The delay units connected to the delay chain are connected in series, wherein the output of the previous delay unit is connected to the input of the next delay unit, the input of the first delay unit in the delay chain is used to receive external input pulse signals, and the output of the last delay unit is used to output the accumulated delay signal.

4. The accelerator according to claim 1, characterized in that, The storage unit includes: non-volatile memory or volatile memory.

5. The accelerator according to claim 1, characterized in that, The delay unit corresponding to the storage unit with the weight value of the second logic value is equipped with a power switch. The power switch is connected in series between the power input terminal of the delay unit and the power supply network. When the delay unit is not connected to the delay chain, the power switch is turned off, cutting off the power supply path of the delay unit.

6. The accelerator according to claim 1, characterized in that, The layout position of the delay unit corresponds to the layout position of the storage unit whose weight value is the first logical value.

7. A method for generating the layout of a time-domain in-memory computational neural network accelerator, characterized in that, The layout generation method is used to generate a time-domain in-memory computing neural network accelerator as described in any one of claims 1 to 6, the method comprising: Obtain the weight parameters of the neural network to be deployed; Based on the weight parameters, a circuit schematic is generated that contains only delay units with weight values ​​of the first logic value; Based on the circuit schematic, the layout file of the standard cell library is called to generate the circuit sub-module layout of each delay unit; Automatic placement and routing is performed by calling the circuit submodule layout, wherein a delay unit is placed at the position in the layout corresponding to the storage unit with a weight value of the first logic value, and all placed delay units in the same delay chain are connected in series sequentially.

8. The method according to claim 7, characterized in that, The step of generating a circuit schematic containing only delay units with weight values ​​equal to the first logic value, based on the weight parameters, includes: The weight parameters are converted into a netlist using a first scripting language; The netlist is loaded using a second scripting language, and the instantiation function is called to map the weights in the netlist whose weight values ​​are the first logical values ​​to delay cell instances in the standard cell library. The connection function is called to connect the delay unit instances sequentially according to the order in the delay chain, thereby generating the circuit schematic.

9. The method according to claim 7, characterized in that, The method further includes: Perform design rule checks and connection relationship checks on the completed layout and routing; If the check fails, adjust the layout or routing parameters and re-execute automatic placement and routing, and check again until the check passes.

10. The method according to claim 9, characterized in that, The adjustment of layout parameters or wiring parameters includes at least one of the following: Adjust the placement of delay units, adjust the connection paths between delay units, change the wiring layer, and change the line width.

Images