A memristor associative memory neural network circuit with latent learning capability and time encoding function

Abstract

This invention proposes a memristor associative memory neural network circuit with latent learning capability and time-coding function. It includes a conventional learning module, a latent learning module, a time-coding module, and a synaptic neuron module. The signal input terminals of the conventional learning module, the latent learning module, and the time-coding module are all connected to external stimulus signals, receiving reinforcement stimulus signals and predictive stimulus signals, respectively. The output terminal of the synaptic neuron module outputs a neuron activation signal as the associative memory response signal. The synaptic neuron module, the conventional learning module, the latent learning module, and the time-coding module are connected in pairs through control voltage and feedback voltage to form closed-loop connections. The latent learning module is used to realize latent memory storage without reinforcement stimulus and rapid learning after the appearance of reinforcement stimulus. The time-coding module is used to encode and modulate the input stimulus time interval. This invention can more realistically simulate associative memory, latent learning, and time-coding behavior in biological neural systems.

Description

Technical Field

[0001] This invention relates to the technical field of analog-to-digital circuits, and more particularly to a memristor associative memory neural network circuit that realizes Pavlovian associative memory function through the plasticity of memristor synapses. Background Technology

[0002] Memristors, as fundamental circuit elements with adjustable resistance and non-volatile storage capabilities, can effectively simulate the changes in synaptic weights in biological neural systems due to their non-volatility and adjustable resistance. With the development of neuromorphic computing and artificial intelligence technologies, building hardware neural networks based on memristors has become an important research direction, showing broad application prospects in neuromorphic computing, intelligent information processing, and adaptive systems.

[0003] In biological neural systems, associative memory is an important learning mechanism. Its basic principle lies in establishing connections between different input signals through the associative effects of multiple stimuli, thus triggering a complete response even when only part of the signal is present. Most existing memristor associative memory neural network circuits are based on this principle, updating synaptic weights by adjusting the resistance of the memristor, thereby achieving conditioned reflex behavior.

[0004] However, the learning process in biological systems is also closely related to pre-learning of stimuli. For example, in some cases, individuals can record information about neutral stimuli without reinforcement, and the learning process accelerates significantly when reinforcement signals are subsequently introduced; this phenomenon is commonly known as latent learning. Patent CN116611487A discloses a Pavlovian associative memory circuit with latent inhibition and multiple forgetting patterns, taking into account the phenomenon of latent inhibition. When a stimulus is repeatedly presented without reinforcement, it interferes with subsequent learning tasks involving that stimulus, making it more difficult to learn when paired with a reinforcer later. In reality, however, when a biological nervous system is exposed to a neutral stimulus in advance, it establishes a memory of that stimulus, making subsequent learning involving that stimulus faster.

[0005] Furthermore, existing circuits typically focus on the synchronization between input signals, meaning the learning process can only be completed when the warning signal and the reinforcement signal appear simultaneously, limiting their ability to simulate more complex learning behaviors. With further research, invention patent CN109002647B discloses a memristor associative memory neural network circuit with delayed learning functionality. This circuit achieves delayed learning, enabling the establishment of associative memory even when the reinforcement signal lags behind the warning signal. However, this type of circuit does not actually possess complete time encoding capabilities; it can only achieve learning when the reinforcement signal appears with a delay. After the stimulus signal is emitted, existing circuits cannot guarantee that the activated conditioned reflex signal will lag behind the occurrence of the warning signal.

[0006] Specifically, existing technologies generally suffer from the following shortcomings: On the one hand, circuits typically rely on immediate reinforcement signals to trigger the learning process, lacking the ability to pre-store input information under no reinforcement conditions, making it difficult to accumulate potential memories; on the other hand, there is a lack of effective modeling of the time interval between signals, making it impossible to adjust the response timing of conditioned reflexes according to time differences, thus making it difficult for the circuits to exhibit complete time-dependent characteristics. Summary of the Invention

[0007] To address the technical problems of existing memristor associative memory neural network circuits lacking the ability to store information under unreinforced conditions and failing to effectively represent the temporal relationship of input signals, this invention proposes a memristor associative memory neural network circuit with latent learning capability and time encoding function. This circuit enables the circuit to latently store input information under unreinforced stimuli and encode the time interval between input signals, thus more closely resembling the actual learning behavior of biological nervous systems.

[0008] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0009] A memristor associative memory neural network circuit with latent learning capability and time encoding function includes a conventional learning module, a latent learning module, a time encoding module, and a synaptic neuron module. The signal input terminals of the conventional learning module, the latent learning module, and the time encoding module are all connected to external stimulus signals to receive reinforcement stimulus signals and predictive stimulus signals, respectively. The output terminal of the synaptic neuron module outputs a neuron activation signal as an associative memory response signal. The synaptic neuron module, the conventional learning module, the latent learning module, and the time encoding module are connected in pairs to form a closed loop through control voltage and feedback voltage. The latent learning module is used to realize latent memory storage without reinforcement stimulus and rapid learning after reinforcement stimulus appears. The time encoding module is used to realize the encoding and modulation of the input stimulus time interval.

[0010] Specifically, the conventional learning module generates a conventional learning control voltage related to the synchronously input reinforcement stimulus signal and predictive stimulus signal through memristor M2; the latent learning module stores the latent memory state representing the history of input stimuli under conditions without reinforcement stimulus signal through memristor M3 and outputs the latent learning modulation voltage after the reinforcement stimulus signal appears; the time encoding module realizes time retention and time decay through memristors M4, M5, and M6 and outputs a delayed learning voltage related to the stimulation time interval of the input reinforcement stimulus signal and predictive stimulus signal; the conventional learning control voltage, the latent learning modulation voltage, and the delayed learning voltage work together to act on memristor M1 in the synaptic neuron module, so that the resistance change of memristor M1 is simultaneously affected by the correlation between reinforcement and predictive stimuli, the latent memory state, and the stimulation time interval, thereby realizing the latent learning ability and time encoding function.

[0011] Specifically, in the conventional learning module, the input reinforcement stimulus signal N1 is connected to the first input terminals of AND gates D1, D3, and D4, respectively; the input predictive stimulus signal N2 is connected to the first input terminal of OR gate D2 and the second input terminal of AND gate D3, respectively; the output terminal of AND gate D1 is connected to the second input terminal of OR gate D2; the output terminal of OR gate D2 is connected to the positive control terminal of voltage-controlled switch S1 for controlling voltage-controlled switch S1; the negative control terminal of voltage-controlled switch S1 is grounded; the negative terminal of the main circuit of voltage-controlled switch S1 is connected to the positive terminal of power supply V3; the negative terminal of power supply V3 is grounded; a resistor R3 is connected in parallel between the positive terminal of the main circuit of voltage-controlled switch S1 and the negative terminal of power supply V3; the positive terminal of the main circuit of voltage-controlled switch S1 is connected to the first input terminal of voltage summation unit SUM1; the feedback voltage U2 from the synaptic neuron module is connected to the positive control terminal of voltage-controlled switch S2 for controlling voltage summation unit SUM1. The negative control terminal of the voltage-controlled switch S2 is grounded. The negative terminal of the main circuit of the voltage-controlled switch S2 is connected to the positive terminal of the power supply V4, and the negative terminal of the power supply V4 is grounded. A resistor R4 is connected in parallel between the positive terminal of the main circuit of the voltage-controlled switch S2 and the negative terminal of the power supply V4. The positive terminal of the main circuit of the voltage-controlled switch S2 is then connected to the second input terminal of the voltage summing unit SUM1. The voltage summing unit SUM1 superimposes the voltages from the voltage-controlled switches S1 and S2 and outputs the result to the plus terminal of the memristor M2. The minus terminal of the memristor M2 is connected to the inverting input terminal of the operational amplifier OP4. The non-inverting input terminal of the operational amplifier OP4 is grounded. A resistor R5 is connected between the inverting input terminal and the output terminal of the operational amplifier OP4. The output terminal of the operational amplifier OP4 is connected to the input terminal of the absolute value unit ABS2. When the input voltage exceeds the threshold of the memristor M2, the resistance of the memristor M2 changes, thereby changing the output voltage of the operational amplifier OP4.

[0012] Specifically, in the conventional learning module, the feedback voltage U6 from the time encoding module is connected to the second input terminals of AND gate D1 and AND gate D4, respectively. The output terminals of AND gate D3 and AND gate D4 are connected to the first and second input terminals of OR gate D5, respectively. The output terminal of OR gate D5 is connected to the input terminal of NOT gate D6, and OR gate D5 outputs a control voltage U7. Control signals are generated between the logic gates through combinational logic relationships. The output terminal of NOT gate D6 is connected to the positive control terminal of voltage-controlled switch S3. The negative control terminal of S3 is grounded, and the positive terminal of the main circuit of the voltage-controlled switch S3 is connected to the input terminal of the absolute value unit ABS2; the output terminal of the OR gate D5 is connected to the positive control terminal of the voltage-controlled switch S4, the negative control terminal of the voltage-controlled switch S4 is grounded, the negative terminal of the main circuit of the voltage-controlled switch S4 is connected to the negative terminal of the main circuit of the voltage-controlled switch S3, the negative terminal of the main circuit of the voltage-controlled switch S4 outputs the conventional learning control voltage U5, the conventional learning control voltage U5 is connected to the first input terminal of the voltage summation unit SUM2, and the positive terminal of the main circuit of the voltage-controlled switch S4 is connected to the output terminal of the absolute value unit ABS2.

[0013] Specifically, in the latent learning module, the input reinforcement stimulus signal N1 is connected to the input terminal of NOT gate D7, and the output terminal of NOT gate D7 is connected to the logic AND gate D. 10 The first input terminal is connected to the logic AND gate D. 10 The output of the AND-OR gate D 12 The first input terminal is connected; the predictive stimulus signal N2 is connected to the input terminal of NOT gate D8, and the output terminal of NOT gate D8 is connected to the AND gate D. 10 The second input terminal and the logic AND gate D 11 The first input terminal is connected to the feedback voltage U6 from the time encoding module and the input terminal of NOT gate D9. The output terminal of NOT gate D9 is connected to the AND gate D. 11 The second input terminal is connected to the logic AND gate D. 11 The output of the AND-OR gate D 12 The second input terminal is connected.

[0014] Specifically, in the latent learning module, the OR gate D 12The output terminal of the signal is connected to the positive control terminal of the pressure-controlled switch S6 to control the conduction state of the pressure-controlled switch S6. The negative control terminal of the pressure-controlled switch S6 is grounded. The negative terminal of the main circuit of the pressure-controlled switch S6 is connected to the negative terminal of the power supply V6, and the positive terminal of the power supply V6 is grounded. The pre-stimulation signal N2 (U8 in the figure) is connected to the positive control terminal of the pressure-controlled switch S5 to control the conduction state of the pressure-controlled switch S5. The negative control terminal of the pressure-controlled switch S5 is grounded. The negative terminal of the main circuit of the pressure-controlled switch S5 is connected to the positive terminal of the power supply V5, and the negative terminal of the power supply V5 is grounded. The positive terminals of the main circuits of both the pressure-controlled switch S6 and the pressure-controlled switch S5 are connected to the minus terminal of the memristor M3 and the output terminal of the feedback voltage U3. The plus terminal of memristor M3 is connected to the inverting input terminal of operational amplifier OP5. The non-inverting input terminal of operational amplifier OP5 is grounded. Resistor R6 is connected between the inverting input terminal and the output terminal of operational amplifier OP5. The output terminal of operational amplifier OP5 is connected to the negative terminal of the main circuit of voltage-controlled switch S7 via resistor R7. The positive control terminal of voltage-controlled switch S7 receives control voltage U7, and the negative control terminal of voltage-controlled switch S7 is grounded. The positive terminal of the main circuit of voltage-controlled switch S7 outputs a latent learning modulation voltage U9. The latent learning modulation voltage U9 is connected to the second input terminal of voltage summing unit SUM2. The output terminal of voltage summing unit SUM2 is connected to the first input terminal of voltage summing unit SUM3.

[0015] Specifically, in the time encoding module shown, the input reinforcement stimulus signal N1 is ANDed with the logic gate D. 13 The first input terminal is connected to the N2 stimulus signal AND gate D. 15 The input terminals are connected to the NOT gate D. 15 The output terminal of the logic AND gate D 14 The first input terminal is connected, and the feedback voltage U6 is ANDed with the logic gate D. 14 The second input terminal is connected to the logic AND gate D. 14 The output terminal of the logic AND gate D 13 The second input terminal is connected to the logic AND gate D. 13 The output terminals are respectively connected to the voltage-controlled switch S 12The positive control terminal of the voltage-controlled switch S7 is connected to the positive control terminal of the voltage-controlled switch S7. The negative control terminal of the voltage-controlled switch S7 is grounded. The positive terminal of the main circuit of the voltage-controlled switch S7 receives feedback voltage U3. The negative terminal of the main circuit of the voltage-controlled switch S7 is connected to the minus terminal of the memristor M4. The minus terminal of the memristor M4 is also connected to the positive terminal of the main circuit of the voltage-controlled switch S8. The negative terminal of the main circuit of the voltage-controlled switch S8 is connected to the negative terminal of the power supply V7. The positive terminal of the power supply V7 and the negative control terminal of the voltage-controlled switch S8 are both grounded. The positive control terminal of the voltage-controlled switch S8 is connected to the output terminal of the pulse generator P2. The input terminal of the pulse generator P2 receives feedback voltage U4. The plus terminal of the memristor M4 is connected to the inverting input terminal of the operational amplifier OP6. The non-inverting input terminal of the operational amplifier OP6 is grounded. The resistor R8 is connected between the inverting input terminal and the output terminal of the operational amplifier OP6.

[0016] Specifically, in the time encoding module shown, the minus terminal of memristor M4 is also connected to the first input terminal of mathematical operation unit ABM2, the output terminal of operational amplifier OP6 is connected to the second input terminal of mathematical operation unit ABM2, the output terminal of mathematical operation unit ABM2 is connected to the inverting input terminal of operational amplifier OP7, the non-inverting input terminal of operational amplifier OP7 is connected to the positive terminal of power supply V8, the negative terminal of power supply V8 is grounded, and the output terminal of operational amplifier OP7 is connected to the NAND gate D. 17 The input terminals are connected to the NOT gate D. 17 The output terminal is connected to the positive control terminal of the voltage-controlled switch S9, and the negative control terminal of the voltage-controlled switch S9 is grounded; the negative terminal of the main circuit of the voltage-controlled switch S9 is connected to the NAND gate D. 16 The output terminal of the NOT gate is connected to the D gate. 16 The input terminal receives the predictive stimulus signal N2 (U8 in the figure), and the positive terminal of the main circuit of the pressure-controlled switch S9 is connected to the pressure-controlled switch S... 10 Connect the positive control terminal to the voltage-controlled switch S. 10 The negative control terminal is grounded, and the voltage-controlled switch S 10 The negative terminal of the main circuit of the switch is connected to the positive terminal of power supply V9, and the negative terminal of power supply V9 ​​is grounded; voltage-controlled switch S 10 The positive terminal of the main circuit of the switch is connected to the minus terminal of the memristor M4; the voltage-controlled switch S 11 The positive control terminal receives the predictive stimulus signal N2 (U8 in the figure), and the pressure-controlled switch S 11 The negative control terminal is grounded, and the voltage-controlled switch S 11 The negative terminal of the main circuit of the switch is connected to the power supply V. 10 Negative terminal connection, power supply V 10 Positive terminal grounded; voltage-controlled switch S 11The positive terminal of the main circuit of the switch is connected to the minus terminal of memristor M5; the plus terminal of memristor M5 is connected to the inverting input terminal of operational amplifier OP8, the non-inverting input terminal of operational amplifier OP8 is grounded, resistor R9 is connected between the inverting input terminal and the output terminal of operational amplifier OP8, the output terminal of operational amplifier OP8 is connected to the non-inverting input terminal of operational amplifier OP9, the inverting input terminal of operational amplifier OP9 is connected to the positive terminal of power supply V7, the negative terminal of power supply V7 is grounded, and the output terminal of operational amplifier OP9 outputs feedback voltage U6; the output terminal of operational amplifier OP8 is also connected to the second input terminal of operational unit ABM3, the first input terminal of operational unit ABM3 is connected to the minus terminal of memristor M5, and the output terminal of operational unit ABM3 is connected to the operational amplifier OP8. 11 The non-inverting input terminal is connected; the output terminal of operational amplifier OP8 is also connected to the input terminal of absolute value unit ABS3, and the output terminal of absolute value unit ABS3 is connected to voltage-controlled switch S. 12 The main circuit positive terminal of the switch is connected, and the voltage-controlled switch S is connected. 12 The main circuit of the switch outputs a delayed learning voltage U at the negative terminal. 10 And through resistor R 11 Grounding, delayed learning voltage U 10 The voltage summator is input to the second input terminal of the voltage summator SUM3, and the output terminal of the voltage summator SUM3 is connected to the resistor R. 12 Then connect to the output terminal of the feedback voltage U3, and the voltage-controlled switch S 12 The negative control terminal is grounded.

[0017] Specifically, in the time encoding module, the reinforcing stimulus signal N1 is ANDed with the NOT gate D. 18 The input terminals are connected to the NOT gate D. 18 The output terminal of the logic AND gate D 21 The first input terminal is connected to the N2 stimulus signal AND gate D. 19 The input terminals are connected to the NOT gate D. 19 The output terminal of the logic AND gate D 20 The first input terminal is connected, and the output terminal of operational amplifier OP7 is connected to logic AND gate D. 20 The second input terminal is connected to the logic AND gate D. 20 The output terminal of the logic AND gate D 21 The second input terminal is connected to the logic AND gate D. 21 The output terminal is connected to the voltage-controlled switch S 13 Connect the positive control terminal to the voltage-controlled switch S. 13 The negative control terminal is grounded, and the voltage-controlled switch S 13 The negative terminal of the main circuit of the switch is connected to the power supply V. 11 Positive terminal connection, power supply V 11 Negative terminal grounded, voltage-controlled switch S 13The positive terminal of the main circuit of the switch is connected to the minus terminal of the memristor M6, indicating that the stimulation signal N2 is also connected to the voltage-controlled switch S. 14 Connect the positive control terminal to the voltage-controlled switch S. 14 The negative control terminal is grounded, and the voltage-controlled switch S 14 The negative terminal of the main circuit of the switch is connected to the power supply V. 12 Negative terminal connection, power supply V 12 Positive terminal grounded, voltage-controlled switch S 14 The positive terminal of the main circuit of the switch is connected to the minus terminal of memristor M6. The minus terminal of memristor M6 is also connected to the first input terminal of operational unit ABM4. The plus terminal of M6 is connected to operational amplifier OP. 10 Connect the inverting input terminal to the operational amplifier OP. 10 The non-inverting input terminal is grounded, and the resistor R 10 Connected to operational amplifier OP 10 Between the inverting input and output terminals, used to simulate the time decay process, operational amplifier OP 10 The output terminal is connected to the second input terminal of the operational amplifier ABM4, and the output terminal of the operational amplifier ABM4 is connected to the operational amplifier OP. 11 The inverting input terminal is connected to the operational amplifier OP. 11 The output terminal of the pulse generator is connected to the input terminal of the pulse generator P1, and the output terminal of the pulse generator P1 outputs the feedback voltage U2.

[0018] Specifically, in the synaptic neuron module, the input reinforcement stimulation signal N1 is connected to the first input terminal of OR gate N3 via resistor R1; the output terminal of feedback voltage U3 is connected to the minus terminal of memristor M1, the plus terminal of memristor M1 is connected to the inverting input terminal of operational amplifier OP1, and the non-inverting input terminal of operational amplifier OP1 is grounded; resistor R2 is connected between the inverting input terminal and the output terminal of operational amplifier OP1, the output terminal of operational amplifier OP1 is connected to the input terminal of absolute value unit ABS1, and the output terminal of absolute value unit ABS1 is connected to the non-inverting input terminal of operational amplifier OP2; the inverting input terminal of operational amplifier OP2... The phase input terminal is connected to the positive terminal of power supply V1, and the negative terminal of power supply V1 is grounded; the output terminal of operational amplifier OP2 is connected to the second input terminal of OR gate N3 and the output terminal of pulse generator P1 respectively, and outputs feedback voltage U2; the output terminal of operational amplifier OP1 is also connected to the first input terminal of operational unit ABM1, the minus terminal of memristor M1 is connected to the second input terminal of operational unit ABM1, the output terminal of operational unit ABM1 is connected to the non-inverting input terminal of operational amplifier OP3, the inverting input terminal of operational amplifier OP3 is connected to the positive terminal of power supply V2, the negative terminal of power supply V2 is grounded, and the output terminal of operational amplifier OP3 outputs feedback voltage U4.

[0019] The beneficial effects of this invention are that it enables the memristor-based associative memory neural network circuit to learn not only "whether it happens" but also "when it happens", thereby improving the system's biofit and temporal information processing capabilities.

[0020] Furthermore, this invention: can store input information under conditions without reinforcement stimulation, exhibiting latent learning capabilities; can significantly improve the learning rate and increase learning efficiency after the appearance of reinforcement signals; can encode the time intervals between input signals, realizing time-dependent learning functions; and can more realistically simulate associative memory, latent learning, and time-encoding behaviors in biological neural systems, providing a new implementation method for brain-like computing circuits. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of the present invention.

[0023] Figure 2 for Figure 1 Circuit diagram of the mesosynaptic neuron module.

[0024] Figure 3 for Figure 1 Circuit diagram of a standard learning module.

[0025] Figure 4 for Figure 1 Circuit diagram of the latent learning module.

[0026] Figure 5 for Figure 1 Circuit diagram of the time encoding module.

[0027] Figure 6 for Figure 1 The specific circuit connection diagram.

[0028] Figure 7 This is a simulation result diagram of the conventional learning process of this invention.

[0029] Figure 8 This is a simulation result diagram of the latent learning method of the present invention.

[0030] Figure 9 The image shows the simulation results of the time encoding function of this invention. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] First, let me introduce the functions achieved by this invention. In Pavlov's associative memory experiment, animals do not respond when only a predictive stimulus (such as a bell) is given, but they do respond when only a reinforcing stimulus (such as food) is given. When the two stimuli appear simultaneously or in association multiple times, the animals can establish a connection, thus responding even when only the predictive stimulus is given. Based on the above principle, this invention uses a memristor to simulate changes in synaptic weights to achieve associative memory: In the initial state, the system only responds to the reinforcing signal. After the predictive and reinforcing signals act together multiple times, the memristor resistance gradually decreases under the action of the conventional learning module, and the synaptic connection is strengthened, so that the output can be triggered even when the predictive signal appears alone. At the same time, this invention introduces a latent learning mechanism. When only the predictive signal is given and there is no reinforcing signal, the latent learning module stores the input information, causing the memristor to slowly change and form a latent memory. When the reinforcing signal appears later, the learning rate is significantly improved. In addition, this invention introduces a time coding mechanism, which records the time interval between the predictive signal and the reinforcement signal through a time coding module, thereby enabling the learning of the timing of the stimulus occurrence. This ensures that the output is generated only after the time following the occurrence of the predictive stimulus reaches the coding time, thus more closely resembling the learning behavior characteristics of biological nervous systems.

[0033] A memristor associative memory neural network circuit with latent learning capability and time encoding function, such as Figure 1 As shown, the system includes a conventional learning module, a latent learning module, a time-coding module, and a synaptic neuron module. The signal input terminals of the conventional learning module, the latent learning module, and the time-coding module are all connected to external stimulus signals, receiving reinforcement stimulus signals and predictive stimulus signals, respectively. The output terminal of the synaptic neuron module outputs a neuron activation signal as an associative memory response signal. The synaptic neuron module, the conventional learning module, the latent learning module, and the time-coding module are connected in pairs through control voltage and feedback voltage to form a closed loop. The latent learning module is used to realize latent memory storage without reinforcement stimulus and rapid learning after reinforcement stimulus appears. The time-coding module is used to realize the encoding and modulation of the input stimulus time interval.

[0034] In the embodiments of this application, such as Figure 3As shown, the conventional learning module is used to realize the learning process when reinforcement stimuli and predictive stimuli occur simultaneously or in association. The input reinforcement stimulus signal N1 of the conventional learning module is connected to the first input terminals of AND gates D1, D3, and D4, respectively. The input predictive stimulus signal N2 is connected to the first input terminal of OR gate D2 and the second input terminal of AND gate D3, respectively. The output terminal of AND gate D1 is connected to the second input terminal of OR gate D2. The output terminal of OR gate D2 is connected to the positive control terminal of pressure-controlled switch S1 to control pressure-controlled switch S1. The negative control terminal of pressure-controlled switch S1 is grounded. The negative terminal of the main circuit of pressure-controlled switch S1 is connected to the positive terminal of power supply V3. The negative terminal of power supply V3 is grounded. A resistor R3 is connected in parallel between the positive terminal of the main circuit of pressure-controlled switch S1 and the negative terminal of power supply V3. The positive terminal of the main circuit of pressure-controlled switch S1 is then connected to the first input terminal of voltage summation unit SUM1. The feedback voltage U2 from the synaptic neuron module is connected to the positive control terminal of pressure-controlled switch S2 to control the pressure-controlled switch. S2, the negative control terminal of voltage-controlled switch S2 is grounded, the negative terminal of the main circuit of voltage-controlled switch S2 is connected to the positive terminal of power supply V4, the negative terminal of power supply V4 is grounded, a resistor R4 is connected in parallel between the positive terminal of the main circuit of voltage-controlled switch S2 and the negative terminal of power supply V4, and the positive terminal of the main circuit of voltage-controlled switch S2 is connected to the second input terminal of voltage summing unit SUM1; voltage summing unit SUM1 superimposes the voltages from voltage-controlled switches S1 and S2 and outputs them to the plus terminal of memristor M2, the minus terminal of memristor M2 is connected to the inverting input terminal of operational amplifier OP4, the non-inverting input terminal of operational amplifier OP4 is grounded, a resistor R5 is connected between the inverting input terminal and the output terminal of operational amplifier OP4, and the output terminal of operational amplifier OP4 is connected to the input terminal of absolute value unit ABS2; when the input voltage exceeds the threshold of memristor M2, the resistance of memristor M2 changes, thereby changing the output voltage of operational amplifier OP4.

[0035] Furthermore, the feedback voltage U6 from the time encoding module is connected to the second input terminals of AND gate D1 and AND gate D4, respectively. The output terminals of AND gate D3 and AND gate D4 are connected to the first and second input terminals of OR gate D5, respectively. The output terminal of OR gate D5 is connected to the input terminal of NOT gate D6, and OR gate D5 outputs control voltage U7. Control signals are generated between the logic gates through combinational logic relationships. The output terminal of NOT gate D6 is connected to the positive control terminal of voltage-controlled switch S3, and the negative control terminal of voltage-controlled switch S3 is connected to the negative control terminal of voltage-controlled switch S3. The control terminal is grounded, and the positive terminal of the main circuit of the voltage-controlled switch S3 is connected to the input terminal of the absolute value unit ABS2; the output terminal of the OR gate D5 is connected to the positive control terminal of the voltage-controlled switch S4, the negative control terminal of the voltage-controlled switch S4 is grounded, the negative terminal of the main circuit of the voltage-controlled switch S4 is connected to the negative terminal of the main circuit of the voltage-controlled switch S3, the negative terminal of the main circuit of the voltage-controlled switch S4 outputs the conventional learning control voltage U5, the conventional learning control voltage U5 is connected to the first input terminal of the voltage summation unit SUM2, and the positive terminal of the main circuit of the voltage-controlled switch S4 is connected to the output terminal of the absolute value unit ABS2.

[0036] During operation, in the conventional learning module, pulse sources N1 and N2 generate reinforcement and predictive stimulus signals, respectively. Input pulse sources N1 and N2, along with feedback voltage U6, act on logic gates D1 to D5, selectively energizing voltage-controlled switches S1 and S2 under different input combinations. When both pulse source signals N1 and N2 and feedback voltage U2 are present simultaneously, power supplies V3 and V4 provide a superimposed voltage to the voltage summing unit SUM1 via voltage-controlled switches S1 and S2 and resistors R3 and R4. This superimposed voltage is then converted into a conventional learning voltage via memristor M2 and operational amplifier OP4. When pulse source signal N2 exists alone or the feedback voltage state changes, NOT gate D6 controls the conduction state of voltage-controlled switches S3 and S4, selectively outputting the output of absolute value unit ABS2 or operational amplifier OP4. This allows the output conventional learning control voltage U5 to be selected with different polarities, thereby realizing the learning and forgetting process.

[0037] In the embodiments of this application, such as Figure 4 As shown, the latent learning module is used to store input information without reinforcement signals. The reinforcement stimulus signal N1 (U1 in the figure) input to the latent learning module is connected to the input terminal of NOT gate D7, and the output terminal of NOT gate D7 is connected to the AND gate D. 10 The first input terminal is connected to the logic AND gate D. 10 The output of the AND-OR gate D 12 The first input terminal is connected; the predictive stimulus signal N2 (U8 in the figure) is connected to the input terminal of NOT gate D8, and the output terminal of NOT gate D8 is connected to the AND gate D. 10 The second input terminal and the logic AND gate D11 The first input terminal is connected to the feedback voltage U6 from the time encoding module and the input terminal of NOT gate D9. The output terminal of NOT gate D9 is connected to the AND gate D. 11 The second input terminal is connected to the logic AND gate D. 11 The output of the AND-OR gate D 12 Connect to the second input terminal;

[0038] Furthermore, OR gate D 12 The output terminal of the signal is connected to the positive control terminal of the pressure-controlled switch S6 to control the conduction state of the pressure-controlled switch S6. The negative control terminal of the pressure-controlled switch S6 is grounded. The negative terminal of the main circuit of the pressure-controlled switch S6 is connected to the negative terminal of the power supply V6, and the positive terminal of the power supply V6 is grounded. The pre-stimulation signal N2 (U8 in the figure) is connected to the positive control terminal of the pressure-controlled switch S5 to control the conduction state of the pressure-controlled switch S5. The negative control terminal of the pressure-controlled switch S5 is grounded. The negative terminal of the main circuit of the pressure-controlled switch S5 is connected to the positive terminal of the power supply V5, and the negative terminal of the power supply V5 is grounded. The positive terminals of the main circuits of both the pressure-controlled switch S6 and the pressure-controlled switch S5 are connected to the minus terminal of the memristor M3 and the output terminal of the feedback voltage U3. The plus terminal of memristor M3 is connected to the inverting input terminal of operational amplifier OP5. The non-inverting input terminal of operational amplifier OP5 is grounded. Resistor R6 is connected between the inverting input terminal and the output terminal of operational amplifier OP5. The output terminal of operational amplifier OP5 is connected to the negative terminal of the main circuit of voltage-controlled switch S7 via resistor R7. The positive control terminal of voltage-controlled switch S7 receives control voltage U7, and the negative control terminal of voltage-controlled switch S7 is grounded. The positive terminal of the main circuit of voltage-controlled switch S7 outputs a latent learning modulation voltage U9. The latent learning modulation voltage U9 is connected to the second input terminal of voltage summing unit SUM2. The output terminal of voltage summing unit SUM2 is connected to the first input terminal of voltage summing unit SUM3.

[0039] During operation, in the latent learning module, when only the premonitory stimulus signal N2 appears, the voltage-controlled switch S5 is turned on under the control signal, causing the memristor M3 to slowly change its resistance under the action of power supply V5. This resistance change is stored as implicit memory information under the condition of no reinforcement. When the subsequent reinforcement stimulus signal N1 appears, the voltage-controlled switch S7 is turned on, allowing the latent learning voltage to participate in the synaptic learning process. The voltage output of operational amplifier OP5 is output as latent learning voltage U9 via voltage-controlled switch S7 and combined with the learning voltage U5 from the conventional learning module through voltage summing unit SUM1 before being sent to the subsequent module. This converts the latent memory previously stored in memristor M3 into an explicit learning modulation voltage, thereby causing memristor M1 in the synaptic neuron module to rapidly change its resistance, achieving an increase in the learning rate after latent learning. When both the premonitory stimulus signal N2 and the reinforcement stimulus signal N1 are absent, the voltage-controlled switch S6 is turned on under the control signal, and the resistance of memristor M3 gradually recovers under the action of power supply V6, achieving latent memory decay.

[0040] In the embodiments of this application, such as Figure 5 As shown, the time encoding module is used to encode the temporal relationship between input signals. The input reinforcement stimulus signal N1 (U1 in the figure) of the time encoding module is ANDed with logic gate D. 13 The first input terminal is connected to the NOT gate D, indicating the stimulus signal N2 (U8 in the figure). 15 The input terminals are connected to the NOT gate D. 15 The output terminal of the logic AND gate D 14 The first input terminal is connected, and the feedback voltage U6 is ANDed with the logic gate D. 14 The second input terminal is connected to the logic AND gate D. 14 The output terminal of the logic AND gate D 13 The second input terminal is connected to the logic AND gate D. 13 The output terminals are respectively connected to the voltage-controlled switch S 12The positive control terminal of the voltage-controlled switch S7 is connected to the positive control terminal of the voltage-controlled switch S7, and the negative control terminal of the voltage-controlled switch S7 is grounded. The positive terminal of the main circuit of the voltage-controlled switch S7 receives the feedback voltage U3, and the negative terminal of the main circuit of the voltage-controlled switch S7 is connected to the minus terminal of the memristor M4, transmitting the learning voltage U3 to the minus terminal of the memristor M4. The memristor M4 only synchronously receives the learning voltage of the synaptic neuron module when the reinforcement stimulus and the delay signal occur simultaneously. The operational amplifier OP6, resistor R8, and memristor M4 constitute a memristor amplification branch with negative feedback. The minus terminal of the memristor M4 is also connected to the voltage-controlled switch S8. The positive terminal of the main circuit of the switch is connected, the negative terminal of the main circuit of the voltage-controlled switch S8 is connected to the negative terminal of the power supply V7, the positive terminal of the power supply V7 and the negative control terminal of the voltage-controlled switch S8 are both grounded, the positive control terminal of the voltage-controlled switch S8 is connected to the output terminal of the pulse generator P2, and the input terminal of the pulse generator P2 receives the feedback voltage U4. When the pulse signal is generated, the resistance of the memristor M4 is quickly pulled up to the initial state; the plus terminal of the memristor M4 is connected to the inverting input terminal of the operational amplifier OP6, the non-inverting input terminal of the operational amplifier OP6 is grounded, and the resistor R8 is connected between the inverting input terminal and the output terminal of the operational amplifier OP6.

[0041] Furthermore, the minus terminal of memristor M4 is also connected to the first input terminal of mathematical operation unit ABM2, and the output terminal of operational amplifier OP6 is connected to the second input terminal of mathematical operation unit ABM2. The output terminal of mathematical operation unit ABM2 serves as the intermediate signal output for time encoding. The output terminal of mathematical operation unit ABM2 is connected to the inverting input terminal of operational amplifier OP7, forming a threshold comparison circuit. The output of operational amplifier OP7 indicates that the memory of the synaptic neuron module is acquired when the reinforcing stimulus lags behind the predictive stimulus, and that associative memory has been formed. The non-inverting input terminal of operational amplifier OP7 is connected to the positive terminal of power supply V8, and the negative terminal of power supply V8 is grounded. The output terminal of operational amplifier OP7 is connected to the NOT gate D. 17 The input terminals are connected to the NOT gate D. 17 The output terminal is connected to the positive control terminal of the voltage-controlled switch S9, and the negative control terminal of the voltage-controlled switch S9 is grounded; the negative terminal of the main circuit of the voltage-controlled switch S9 is connected to the NAND gate D. 16 The output terminal of the NOT gate is connected to the D gate. 16 The input terminal receives the predictive stimulus signal N2 (U8 in the figure), and the positive terminal of the main circuit of the pressure-controlled switch S9 is connected to the pressure-controlled switch S... 10 Connect the positive control terminal to the voltage-controlled switch S. 10 The negative control terminal is grounded, and the voltage-controlled switch S 10 The negative terminal of the main circuit of the switch is connected to the positive terminal of power supply V9, and the negative terminal of power supply V9 ​​is grounded; voltage-controlled switch S 10 The positive terminal of the main circuit of the switch is connected to the minus terminal of the memristor M4; the voltage-controlled switch S 11The positive control terminal receives the predictive stimulus signal N2 (U8 in the figure), and the pressure-controlled switch S 11 The negative control terminal is grounded, and the voltage-controlled switch S 11 The negative terminal of the main circuit of the switch is connected to the power supply V. 10 Negative terminal connection, power supply V 10 Positive terminal grounded; voltage-controlled switch S 11 The positive terminal of the main circuit of the switch is connected to the minus terminal of memristor M5; before associative memory is formed, voltage-controlled switch S9 is turned on, and NOT gate D... 15 The signal can be transmitted to the voltage-controlled switch S 10 This causes the voltage-controlled switch S 10 and S 11 Select power supply V9 ​​or V according to the input signal status. 10 The memristor M5 is modulated. Once the associative memory is formed, the voltage-controlled switch S9 is opened, and the resistance of the memristor M5 will no longer change. At this time, the resistance of M5 is used as a memory to record the interval of the stimulus signal during the learning process. The plus terminal of the memristor M5 is connected to the inverting input terminal of the operational amplifier OP8, the non-inverting input terminal of the operational amplifier OP8 is grounded, and the resistor R9 is connected between the inverting input terminal and the output terminal of the operational amplifier OP8. The memristor M5, the resistor R9, and the operational amplifier OP8 form a branch with negative feedback. The output terminal of the operational amplifier OP8 is connected to the non-inverting input terminal of the operational amplifier OP9, the inverting input terminal of the operational amplifier OP9 is connected to the positive terminal of the power supply V7, the negative terminal of the power supply V7 is grounded, and the output terminal of the operational amplifier OP9 outputs the feedback voltage U6. The output terminal of the operational amplifier OP8 is also connected to the second input terminal of the operational unit ABM3, the first input terminal of the operational unit ABM3 is connected to the minus terminal of the memristor M5, and the output terminal of the operational unit ABM3 is connected to the operational amplifier OP8. 11 The non-inverting input terminal is connected; the output terminal of operational amplifier OP8 is also connected to the input terminal of absolute value unit ABS3, and the output terminal of absolute value unit ABS3 is connected to voltage-controlled switch S. 12 The main circuit positive terminal of the switch is connected, and the voltage-controlled switch S is connected. 12 The main circuit of the switch outputs a delayed learning voltage U at the negative terminal. 10 And through resistor R 11 Grounding, delayed learning voltage U 10 The voltage summator is input to the second input terminal of the voltage summator SUM3, and the output terminal of the voltage summator SUM3 is connected to the resistor R. 12 Then connect to the output terminal of the feedback voltage U3, and the voltage-controlled switch S 12 The negative control terminal is grounded.

[0042] Furthermore, the reinforcing stimulus signal N1 (U1 in the figure) and the NOT gate D 18 The input terminals are connected to the NOT gate D. 18The output terminal of the logic AND gate D 21 The first input terminal is connected to the NOT gate D, indicating the stimulus signal N2 (U8 in the figure). 19 The input terminals are connected to the NOT gate D. 19 The output terminal of the logic AND gate D 20 The first input terminal is connected, and the output terminal of operational amplifier OP7 is connected to logic AND gate D. 20 The second input terminal is connected to the logic AND gate D. 20 The output terminal of the logic AND gate D 21 The second input terminal is connected to the logic AND gate D. 21 The output terminal is connected to the voltage-controlled switch S 13 Connect the positive control terminal to the voltage-controlled switch S. 13 The negative control terminal is grounded, and the voltage-controlled switch S 13 The negative terminal of the main circuit of the switch is connected to the power supply V. 11 Positive terminal connection, power supply V 11 Negative terminal grounded, voltage-controlled switch S 13 The positive terminal of the main circuit of the switch is connected to the minus terminal of the memristor M6, indicating that the stimulation signal N2 (U8 in the figure) is also connected to the voltage-controlled switch S. 14 Connect the positive control terminal to the voltage-controlled switch S. 14 The negative control terminal is grounded, and the voltage-controlled switch S 14 The negative terminal of the main circuit of the switch is connected to the power supply V. 12 Negative terminal connection, power supply V 12 Positive terminal grounded, voltage-controlled switch S 14 The positive terminal of the main circuit of the switch is connected to the minus terminal of the memristor M6, thereby selecting the power supply V according to the input signal state. 11 or V 12 The memristor M6 is modulated. The minus terminal of the memristor M6 is also connected to the first input terminal of the operational unit ABM4, and the plus terminal of M6 is connected to the operational amplifier OP. 10 Connect the inverting input terminal to the operational amplifier OP. 10 The non-inverting input terminal is grounded, and the resistor R 10 Connected to operational amplifier OP 10 Between the inverting input and output terminals, memristor M6 and resistor R 10 Operational amplifier (OP) 10 This forms a branch with negative feedback, creating a time decay unit to simulate the time decay process. The operational amplifier (OP) is used in this unit. 10 The output terminal is connected to the second input terminal of the operational amplifier ABM4, and the output terminal of the operational amplifier ABM4 is connected to the operational amplifier OP. 11 The inverting input terminal is connected to the operational amplifier OP. 11The output terminal of the pulse generator P1 is connected to the input terminal of the pulse generator P1. The output terminal of the pulse generator P1 outputs a feedback voltage U2. When the modulation time of the memristor M6 reaches the predetermined recording time of the memristor M5, the operational amplifier OP... 11 The output terminal is connected to the pulse generator P1 and outputs signal U2, making the learning process time-dependent, thereby realizing the delayed learning function with time encoding capability.

[0043] In the embodiments of this application, such as Figure 2 As shown, the synaptic neuron module is used to simulate biological neurons and synaptic connections. Its core is to use the resistance change of memristor M1 to represent the synaptic weight change. The reinforcement stimulation signal N1 (U1 in the figure) input from the synaptic neuron module is connected to the first input terminal of OR gate N3 via resistor R1, thereby simulating the system response after the reinforcement stimulation signal is generated. The output terminal of feedback voltage U3 is connected to the minus terminal of memristor M1 to receive modulation voltages from the other three modules. The plus terminal of memristor M1 is connected to the inverting input terminal of operational amplifier OP1, and the non-inverting input terminal of operational amplifier OP1 is grounded. Resistor R2 is connected between the inverting input terminal and the output terminal of operational amplifier OP1. The output terminal of operational amplifier OP1 is connected to the input terminal of absolute value unit ABS1, and the output terminal of absolute value unit ABS1 is connected to the non-inverting input terminal of operational amplifier OP2. ABS1 is used to eliminate the influence of signal polarity on subsequent processing. The inverting input terminal of operational amplifier OP2 is connected to the positive terminal of power supply V1, and the negative terminal of power supply V1 is grounded, forming a threshold comparison circuit. The output terminal of operational amplifier OP2 is connected to the second input terminal of OR gate N3 and the output terminal of pulse generator P1. The memristor M1 outputs a feedback voltage U2. Its resistance changes with the input voltage. When the resistance decreases, it indicates enhanced synaptic connection. When the input signal to the threshold comparison circuit exceeds the set threshold, the operational amplifier OP2 outputs a signal. This output signal serves as the feedback voltage U2, outputting to other modules and also as input to logic gate N3. Logic gate N3 combines the input signal U1 with the output signal of operational amplifier OP2 to ultimately output the neuron activation signal U0. The output of operational amplifier OP1 is also connected to the first input of operational unit ABM1. The minus terminal of memristor M1 is connected to the second input of operational unit ABM1 to calculate the functional relationship of the memristor resistance change. The output of operational unit ABM1 is connected to the non-inverting input of operational amplifier OP3. The inverting input of operational amplifier OP3 is connected to the positive terminal of power supply V2, and the negative terminal of power supply V2 is grounded. The output of operational amplifier OP3 outputs a feedback voltage U4 to adjust the operating state of other modules.

[0044] The conventional learning module generates a conventional learning control voltage related to the synchronously input reinforcement stimulus signal and predictive stimulus signal through memristor M2; the latent learning module stores the latent memory state representing the history of input stimuli under the condition of no reinforcement stimulus signal through memristor M3 and outputs the latent learning modulation voltage after the reinforcement stimulus signal appears; the time encoding module realizes time retention and time decay through memristors M4, M5, and M6 and outputs a delayed learning voltage related to the stimulation time interval of the input reinforcement stimulus signal and predictive stimulus signal; the conventional learning control voltage, the latent learning modulation voltage, and the delayed learning voltage work together to act on memristor M1 in the synaptic neuron module, so that the resistance change of memristor M1 is simultaneously affected by the correlation between reinforcement and predictive stimuli, the latent memory state, and the stimulation time interval, thereby realizing the latent learning ability and time encoding function.

[0045] The synaptic neuron module, conventional learning module, latent learning module, and time-coding module are combined to form a complete circuit to realize a memristor associative memory neural network circuit with latent learning capability and time-coding function. Its circuit structure is as follows: Figure 6 As shown in the diagram, N1 represents the reinforcing stimulus (food), N2 represents the predictive stimulus (bell), and N3 represents the neuron output signal. The output of N3 also indicates whether the dog salivates.

[0046] Learning: When input signals N1 and N2 are present simultaneously, voltage-controlled switches S1 and S5 close, and S4 opens. The voltage from power supply V2 is transmitted to the synaptic neuron module through voltage summing unit SUM2, memristor M2, operational amplifier OP3, absolute value unit ABS1, voltage-controlled switch S5, and voltage summing unit SUM3, causing the resistance of memristor M1 to decrease, thus initiating the learning process. When the resistance of memristor M1 decreases to a certain level, only a dog bell signal is provided. S1 and S4 close, and S5 opens. Power supply V2 is transmitted to memristor M1 through voltage summing unit SUM2, memristor M2, operational amplifier OP3, voltage-controlled switch S4, and voltage summing unit SUM3. For a period of time, memristor M2 is sufficiently small, causing OR gate N3 to output an activation voltage, indicating that the dog has secreted saliva. After one learning process has been completed, due to the effect of feedback voltage U2, voltage-controlled switches S1 and S2 close simultaneously, and the voltage output by SUM2 is V2 + V3. When memristor M2 receives a signal greater than the threshold voltage, the resistance of memristor M2 increases, and the output voltage of OP3 becomes -(V2+V3)*(R5 / M2). As a result, the output U4 of the voltage control module decreases, which in turn reduces the voltage U3 transmitted to memristor M1 through SUM3. This causes the resistance of memristor M1 to change faster in the next learning cycle, which in turn changes the learning rate.

[0047] The working process of latent learning: In this invention, the latent learning process is achieved collaboratively by the latent learning module and the synaptic neuron module. When only a pre-stimulus signal is input and the reinforcing stimulus signal has not appeared, the logic control unit controls the voltage-controlled switch S5 to turn on according to the input state. At this time, the power supply V5 acts on the memristor M3 through the voltage-controlled switch S5, causing the memristor M3 to undergo a slow resistance change under a small voltage amplitude. Since this change process does not directly act on the memristor M1 in the synaptic neuron module, it will not immediately trigger neuronal activation output, but the memristor M3 has already recorded the input signal, thus forming a latent memory state. When the subsequent reinforcing stimulus signal appears, the logic control unit controls the voltage-controlled switch S7 to turn on, so that the latent learning voltage output by the operational amplifier OP5 and the learning voltage output by the conventional learning module are superimposed and act together on the memristor M1 in the synaptic neuron module. Since the memristor M3 has already completed pre-adjustment, its output voltage can accelerate the resistance change rate of the memristor M1, thereby significantly accelerating the learning process, which is manifested in establishing an associative relationship with fewer training sessions. When the input signal disappears, the voltage-controlled switch S6 is turned on, and the power supply V6 applies a reverse action to the memristor M3, causing its resistance to gradually recover, thereby realizing the decay process of latent memory.

[0048] The time encoding process is implemented by a time encoding module. Its core lies in constructing time-holding and time-decay branches using multiple memristors to characterize the time interval between input signals. When the pre-stimulus signal first appears, the voltage-controlled switch is turned on under the action of the logic control circuit, causing memristors M4, M5, and M6 to enter their working states. Specifically, memristor M4 maintains its current state in the negative feedback circuit composed of operational amplifier OP6 and resistor R8, representing associative memory through delayed learning; memristor M5 gradually changes its resistance under the action of operational amplifier OP8, achieving time recording; memristor M6... 10 The opposing forces produce resistance changes, thus achieving the time decay process. As time progresses, the resistance changes of memristors M5 and M6 accumulate, and their outputs are processed by mathematical operation units ABM3 and ABM4 before being input to operational amplifier OP. 11 This process generates a time-coded voltage signal. The length of this time code varies depending on whether the reinforcing stimulus signal lags behind the predictive stimulus by different time intervals. After associative memory is formed, an output signal is generated when the time interval between the predictive stimulus events reaches the coding time. Through this process, the timing of stimulus occurrence is encoded, enabling the system to learn not only the relationships between stimuli but also the temporal characteristics of stimulus occurrence.

[0049] Figure 7The simulation results demonstrate the conventional process of this invention. (a) shows the voltage waveform of input signal N1, (b) shows the voltage waveform of input signal N2, and (c) shows the voltage waveform of the activation voltage output by the synaptic neuron module. Reinforcing and predictive stimuli occur simultaneously. After approximately 30 waveform stimuli, an output signal is generated when only the predictive stimulus signal is given, indicating the formation of associative memory. Subsequently, when only the predictive stimulus signal is given, the formed associative memory gradually deteriorates. Figure 8 Simulation results demonstrate the latent learning process of this invention. Initially, a large number of predictive stimulus signals are input, and the circuit stores the input information in advance without reinforcement stimulus signals. Subsequently, only a few combined stimuli are needed to quickly form associative memory; Figure 9 Simulation results demonstrate the time encoding capability of this invention, where the reinforcing stimulus signal lags behind the predictive stimulus signal, forming associative memory after several cycles of stimulation. Subsequently, whenever the predictive signal appears, an output signal appears after a short time interval.

[0050] This invention proposes a memristor associative memory neural network circuit with latent learning capability and time encoding function, which enables the circuit to latently store input information without reinforcement stimulation and to encode the time interval between input signals, thereby more closely resembling the actual learning behavior of biological nervous systems.

[0051] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A memristor associative memory neural network circuit with latent learning capability and time encoding function, characterized in that, It includes a conventional learning module, a latent learning module, a time-encoding module, and a synaptic neuron module. The signal input terminals of the conventional learning module, the latent learning module, and the time-encoding module are all connected to external stimulus signals, receiving reinforcement stimulus signals and predictive stimulus signals, respectively. The output terminal of the synaptic neuron module outputs a neuron activation signal as an associative memory response signal. The synaptic neuron module, the conventional learning module, the latent learning module, and the time-encoding module are connected in pairs to form a closed loop through control voltage and feedback voltage. The latent learning module is used to realize latent memory storage without reinforcement stimulus and rapid learning after reinforcement stimulus appears. The time-encoding module is used to realize the encoding and modulation of the input stimulus time interval.

2. The memristor associative memory neural network circuit with latent learning capability and time encoding function according to claim 1, characterized in that, The conventional learning module generates a conventional learning control voltage related to the synchronously input reinforcement stimulus signal and predictive stimulus signal through memristor M2; the latent learning module stores the latent memory state representing the history of input stimuli under the condition of no reinforcement stimulus signal through memristor M3 and outputs the latent learning modulation voltage after the reinforcement stimulus signal appears; the time encoding module realizes time retention and time decay through memristors M4, M5, and M6 and outputs a delayed learning voltage related to the stimulation time interval of the input reinforcement stimulus signal and predictive stimulus signal; the conventional learning control voltage, the latent learning modulation voltage, and the delayed learning voltage work together to act on memristor M1 in the synaptic neuron module, so that the resistance change of memristor M1 is simultaneously affected by the correlation between reinforcement and predictive stimuli, the latent memory state, and the stimulation time interval, thereby realizing the latent learning ability and time encoding function.

3. The memristor associative memory neural network circuit with latent learning capability and time encoding function according to claim 2, characterized in that, In the conventional learning module, the input reinforcement stimulus signal N1 is connected to the first input terminals of AND gates D1, D3, and D4, respectively; the input predictive stimulus signal N2 is connected to the first input terminal of OR gate D2 and the second input terminal of AND gate D3, respectively; the output terminal of AND gate D1 is connected to the second input terminal of OR gate D2; the output terminal of OR gate D2 is connected to the positive control terminal of pressure-controlled switch S1 for controlling pressure-controlled switch S1; the negative control terminal of pressure-controlled switch S1 is grounded; the negative terminal of the main circuit of pressure-controlled switch S1 is connected to the positive terminal of power supply V3; the negative terminal of power supply V3 is grounded; a resistor R3 is connected in parallel between the positive terminal of the main circuit of pressure-controlled switch S1 and the negative terminal of power supply V3; the positive terminal of the main circuit of pressure-controlled switch S1 is connected to the first input terminal of voltage summation unit SUM1; the feedback voltage U2 from the synaptic neuron module is connected to the positive control terminal of pressure-controlled switch S2 for controlling pressure-controlled switch S1. With switch S2 closed, the negative control terminal of voltage-controlled switch S2 is grounded. The negative terminal of the main circuit of voltage-controlled switch S2 is connected to the positive terminal of power supply V4, and the negative terminal of power supply V4 is grounded. A resistor R4 is connected in parallel between the positive terminal of the main circuit of voltage-controlled switch S2 and the negative terminal of power supply V4. The positive terminal of the main circuit of voltage-controlled switch S2 is then connected to the second input terminal of voltage summing unit SUM1. Voltage summing unit SUM1 superimposes the voltages from voltage-controlled switches S1 and S2 and outputs the result to the plus terminal of memristor M2. The minus terminal of memristor M2 is connected to the inverting input terminal of operational amplifier OP4. The non-inverting input terminal of operational amplifier OP4 is grounded. Resistor R5 is connected between the inverting input terminal and the output terminal of operational amplifier OP4. The output terminal of operational amplifier OP4 is connected to the input terminal of absolute value unit ABS2. When the input voltage exceeds the threshold of memristor M2, the resistance of memristor M2 changes, thereby changing the output voltage of operational amplifier OP4.

4. The memristor associative memory neural network circuit with latent learning capability and time encoding function according to claim 3, characterized in that, In the conventional learning module, the feedback voltage U6 from the time encoding module is connected to the second input terminals of AND gate D1 and AND gate D4, respectively. The output terminals of AND gate D3 and AND gate D4 are connected to the first and second input terminals of OR gate D5, respectively. The output terminal of OR gate D5 is connected to the input terminal of NOT gate D6. OR gate D5 outputs control voltage U7. Control signals are generated between the logic gates through combinational logic relationships. The output terminal of NOT gate D6 is connected to the positive control terminal of voltage-controlled switch S3. The negative control terminal of the voltage-controlled switch S3 is grounded, and the positive terminal of the main circuit of the voltage-controlled switch S3 is connected to the input terminal of the absolute value unit ABS2. The output terminal of the OR gate D5 is connected to the positive control terminal of the voltage-controlled switch S4, the negative control terminal of the voltage-controlled switch S4 is grounded, the negative terminal of the main circuit of the voltage-controlled switch S4 is connected to the negative terminal of the main circuit of the voltage-controlled switch S3, the negative terminal of the main circuit of the voltage-controlled switch S4 outputs the conventional learning control voltage U5, the conventional learning control voltage U5 is connected to the first input terminal of the voltage summation unit SUM2, and the positive terminal of the main circuit of the voltage-controlled switch S4 is connected to the output terminal of the absolute value unit ABS2.

5. The memristor associative memory neural network circuit with latent learning capability and time encoding function according to claim 4, characterized in that, In the latent learning module, the input reinforcement stimulus signal N1 is connected to the input terminal of NOT gate D7, and the output terminal of NOT gate D7 is connected to the logic AND gate D. 10 The first input terminal is connected to the logic AND gate D. 10 The output of the AND-OR gate D 12 The first input terminal is connected; the predictive stimulus signal N2 is connected to the input terminal of NOT gate D8, and the output terminal of NOT gate D8 is connected to the AND gate D. 10 The second input terminal and the logic AND gate D 11 The first input terminal is connected to the feedback voltage U6 from the time encoding module and the input terminal of NOT gate D9. The output terminal of NOT gate D9 is connected to the AND gate D. 11 The second input terminal is connected to the logic AND gate D. 11 The output of the AND-OR gate D 12 The second input terminal is connected.

6. The memristor associative memory neural network circuit with latent learning capability and time encoding function according to claim 5, characterized in that, In the latent learning module ； OR gate D 12 The output terminal of the signal is connected to the positive control terminal of the pressure-controlled switch S6 to control the conduction state of the pressure-controlled switch S6. The negative control terminal of the pressure-controlled switch S6 is grounded. The negative terminal of the main circuit of the pressure-controlled switch S6 is connected to the negative terminal of the power supply V6, and the positive terminal of the power supply V6 is grounded. The pre-stimulation signal N2 is connected to the positive control terminal of the pressure-controlled switch S5 to control the conduction state of the pressure-controlled switch S5. The negative control terminal of the pressure-controlled switch S5 is grounded. The negative terminal of the main circuit of the pressure-controlled switch S5 is connected to the positive terminal of the power supply V5, and the negative terminal of the power supply V5 is grounded. The positive terminals of the main circuits of both the pressure-controlled switch S6 and the pressure-controlled switch S5 are connected to the minus terminal of the memristor M3 and the output terminal of the feedback voltage U3. The memristor M... The plus terminal of 3 is connected to the inverting input terminal of operational amplifier OP5. The non-inverting input terminal of operational amplifier OP5 is grounded. Resistor R6 is connected between the inverting input terminal and the output terminal of operational amplifier OP5. The output terminal of operational amplifier OP5 is connected to the negative terminal of the main circuit of voltage-controlled switch S7 via resistor R7. The positive control terminal of voltage-controlled switch S7 receives control voltage U7, the negative control terminal of voltage-controlled switch S7 is grounded, and the positive terminal of the main circuit of voltage-controlled switch S7 outputs latent learning modulation voltage U9. The latent learning modulation voltage U9 is connected to the second input terminal of voltage summing unit SUM2. The output terminal of voltage summing unit SUM2 is connected to the first input terminal of voltage summing unit SUM3.

7. The memristor associative memory neural network circuit with latent learning capability and time encoding function according to claim 6, characterized in that, In the time encoding module shown, the input reinforcement stimulus signal N1 is ANDed with the logic gate D. 13 The first input terminal is connected to the N2 stimulus signal AND gate D. 15 The input terminals are connected to the NOT gate D. 15 The output terminal of the logic AND gate D 14 The first input terminal is connected, and the feedback voltage U6 is ANDed with the logic gate D. 14 The second input terminal is connected to the logic AND gate D. 14 The output terminal of the logic AND gate D 13 The second input terminal is connected to the logic AND gate D. 13 The output terminals are respectively connected to the voltage-controlled switch S 12 The positive control terminal of the voltage-controlled switch S7 is connected to the positive control terminal of the voltage-controlled switch S7. The negative control terminal of the voltage-controlled switch S7 is grounded. The positive terminal of the main circuit of the voltage-controlled switch S7 receives feedback voltage U3. The negative terminal of the main circuit of the voltage-controlled switch S7 is connected to the minus terminal of the memristor M4. The minus terminal of the memristor M4 is also connected to the positive terminal of the main circuit of the voltage-controlled switch S8. The negative terminal of the main circuit of the voltage-controlled switch S8 is connected to the negative terminal of the power supply V7. The positive terminal of the power supply V7 and the negative control terminal of the voltage-controlled switch S8 are both grounded. The positive control terminal of the voltage-controlled switch S8 is connected to the output terminal of the pulse generator P2. The input terminal of the pulse generator P2 receives feedback voltage U4. The plus terminal of the memristor M4 is connected to the inverting input terminal of the operational amplifier OP6. The non-inverting input terminal of the operational amplifier OP6 is grounded. The resistor R8 is connected between the inverting input terminal and the output terminal of the operational amplifier OP6.

8. The memristor associative memory neural network circuit with latent learning capability and time encoding function according to claim 7, characterized in that, In the time encoding module, the minus terminal of memristor M4 is also connected to the first input terminal of mathematical operation unit ABM2, the output terminal of operational amplifier OP6 is connected to the second input terminal of mathematical operation unit ABM2, and the output terminal of mathematical operation unit ABM2 is connected to the inverting input terminal of operational amplifier OP7; the non-inverting input terminal of operational amplifier OP7 is connected to the positive terminal of power supply V8, the negative terminal of power supply V8 is grounded, and the output terminal of operational amplifier OP7 is connected to the NAND gate D. 17 The input terminals are connected to the NOT gate D. 17 The output terminal is connected to the positive control terminal of the voltage-controlled switch S9, and the negative control terminal of the voltage-controlled switch S9 is grounded; the negative terminal of the main circuit of the voltage-controlled switch S9 is connected to the NAND gate D. 16 The output terminal of the NOT gate is connected to the D gate. 16 The input terminal receives the predictive stimulus signal N2, and the positive terminal of the main circuit of the pressure-controlled switch S9 is connected to the pressure-controlled switch S... 10 Connect the positive control terminal to the voltage-controlled switch S. 10 The negative control terminal is grounded, and the voltage-controlled switch S 10 The negative terminal of the main circuit of the switch is connected to the positive terminal of power supply V9, and the negative terminal of power supply V9 ​​is grounded; voltage-controlled switch S 10 The positive terminal of the main circuit of the switch is connected to the minus terminal of the memristor M4; the voltage-controlled switch S 11 The positive control terminal receives the predictive stimulus signal N2 (U8 in the figure), and the pressure-controlled switch S 11 The negative control terminal is grounded, and the voltage-controlled switch S 11 The negative terminal of the main circuit of the switch is connected to the power supply V. 10 Negative terminal connection, power supply V 10 Positive terminal grounded; voltage-controlled switch S 11 The positive terminal of the main circuit of the switch is connected to the minus terminal of memristor M5; the plus terminal of memristor M5 is connected to the inverting input terminal of operational amplifier OP8, the non-inverting input terminal of operational amplifier OP8 is grounded, resistor R9 is connected between the inverting input terminal and the output terminal of operational amplifier OP8, the output terminal of operational amplifier OP8 is connected to the non-inverting input terminal of operational amplifier OP9, the inverting input terminal of operational amplifier OP9 is connected to the positive terminal of power supply V7, the negative terminal of power supply V7 is grounded, and the output terminal of operational amplifier OP9 outputs feedback voltage U6; the output terminal of operational amplifier OP8 is also connected to the second input terminal of operational unit ABM3, the first input terminal of operational unit ABM3 is connected to the minus terminal of memristor M5, and the output terminal of operational unit ABM3 is connected to the operational amplifier OP8. 11 The non-inverting input terminal is connected; the output terminal of operational amplifier OP8 is also connected to the input terminal of absolute value unit ABS3, and the output terminal of absolute value unit ABS3 is connected to voltage-controlled switch S. 12 The main circuit positive terminal of the switch is connected, and the voltage-controlled switch S is connected. 12 The main circuit of the switch outputs a delayed learning voltage U at the negative terminal. 10 And through resistor R 11 Grounding, delayed learning voltage U 10 The voltage summator is input to the second input terminal of the voltage summator SUM3, and the output terminal of the voltage summator SUM3 is connected to the resistor R. 12 Then connect to the output terminal of the feedback voltage U3, and the voltage-controlled switch S 12 The negative control terminal is grounded.

9. The memristor associative memory neural network circuit with latent learning capability and time encoding function according to claim 8, characterized in that, In the time encoding module, the reinforcement stimulus signal N1 and the NOT gate D 18 The input terminals are connected to the NOT gate D. 18 The output terminal of the logic AND gate D 21 The first input terminal is connected to the N2 stimulus signal AND gate D. 19 The input terminals are connected to the NOT gate D. 19 The output terminal of the logic AND gate D 20 The first input terminal is connected, and the output terminal of operational amplifier OP7 is connected to logic AND gate D. 20 The second input terminal is connected to the logic AND gate D. 20 The output terminal of the logic AND gate D 21 The second input terminal is connected to the logic AND gate D. 21 The output terminal is connected to the voltage-controlled switch S 13 Connect the positive control terminal to the voltage-controlled switch S. 13 The negative control terminal is grounded, and the voltage-controlled switch S 13 The negative terminal of the main circuit of the switch is connected to the power supply V. 11 Positive terminal connection, power supply V 11 Negative terminal grounded, voltage-controlled switch S 13 The positive terminal of the main circuit of the switch is connected to the minus terminal of the memristor M6, indicating that the stimulation signal N2 is also connected to the voltage-controlled switch S. 14 Connect the positive control terminal to the voltage-controlled switch S. 14 The negative control terminal is grounded, and the voltage-controlled switch S 14 The negative terminal of the main circuit of the switch is connected to the power supply V. 12 Negative terminal connection, power supply V 12 Positive terminal grounded, voltage-controlled switch S 14 The positive terminal of the main circuit of the switch is connected to the minus terminal of memristor M6. The minus terminal of memristor M6 is also connected to the first input terminal of operational unit ABM4. The plus terminal of M6 is connected to operational amplifier OP. 10 The inverting input terminal is connected to the operational amplifier OP. 10 The non-inverting input terminal is grounded, and the resistor R 10 Connected to operational amplifier OP 10 Between the inverting input and output terminals, used to simulate the time decay process, operational amplifier OP 10 The output terminal is connected to the second input terminal of the operational amplifier ABM4, and the output terminal of the operational amplifier ABM4 is connected to the operational amplifier OP. 11 The inverting input terminal is connected to the operational amplifier OP. 11 The output terminal of the pulse generator is connected to the input terminal of the pulse generator P1, and the output terminal of the pulse generator P1 outputs the feedback voltage U2.

10. The memristor associative memory neural network circuit with latent learning capability and time encoding function according to claim 9, characterized in that, In the synaptic neuron module, the input reinforcement stimulation signal N1 is connected to the first input terminal of OR gate N3 via resistor R1; the output terminal of feedback voltage U3 is connected to the minus terminal of memristor M1, the plus terminal of memristor M1 is connected to the inverting input terminal of operational amplifier OP1, and the non-inverting input terminal of operational amplifier OP1 is grounded; resistor R2 is connected between the inverting input terminal and the output terminal of operational amplifier OP1, the output terminal of operational amplifier OP1 is connected to the input terminal of absolute value unit ABS1, and the output terminal of absolute value unit ABS1 is connected to the non-inverting input terminal of operational amplifier OP2; the inverting input terminal of operational amplifier OP2... The input terminal is connected to the positive terminal of power supply V1, and the negative terminal of power supply V1 is grounded; the output terminal of operational amplifier OP2 is connected to the second input terminal of OR gate N3 and the output terminal of pulse generator P1 respectively, and outputs feedback voltage U2; the output terminal of operational amplifier OP1 is also connected to the first input terminal of operational unit ABM1, the minus terminal of memristor M1 is connected to the second input terminal of operational unit ABM1, the output terminal of operational unit ABM1 is connected to the non-inverting input terminal of operational amplifier OP3, the inverting input terminal of operational amplifier OP3 is connected to the positive terminal of power supply V2, the negative terminal of power supply V2 is grounded, and the output terminal of operational amplifier OP3 outputs feedback voltage U4.

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