Hardware acceleration methods, vector acceleration units, devices, media, and software products for sparse matrix multiplication.
By optimizing sparse matrix multiplication operations through hardware acceleration methods and vector acceleration unit arrays, the problem of low efficiency in existing sparse matrix multiplication technologies is solved, enabling efficient computation of sparse matrix multiplication in financial systems and improving system stability and security.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INDUSTRIAL AND COMMERCIAL BANK OF CHINA
- Filing Date
- 2026-03-27
- Publication Date
- 2026-07-31
AI Technical Summary
Existing CPU/GPU architectures are inefficient at handling sparse matrix multiplication, leading to delays in fault location in financial operations and maintenance, affecting transaction continuity and regulatory compliance, and causing cascading service outages, especially in critical payment and risk control processes.
A hardware acceleration method for sparse matrix multiplication is adopted, which utilizes vector acceleration units in the vector acceleration unit array to perform sparse matrix multiplication operations. Through row compression storage and parallel accumulator optimization, efficient multiplication and addition operations between sparse and dense matrices are achieved.
It significantly improves the computational efficiency of sparse matrix multiplication, reduces fault location delays, minimizes transaction delays and risk control failures, avoids cascading business interruptions during critical clearing and trading periods, and enhances the stability and security of the financial system.
Smart Images
Figure CN122491372A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the fields of cloud computing and financial technology, specifically to a hardware acceleration method, vector acceleration unit, device, medium, and program product for sparse matrix multiplication operations. Background Technology
[0002] Currently, the fintech sector widely adopts microservice-based database systems (such as those supporting high-frequency trading) to handle massive business demands. These systems are typically deployed in clusters with thousands of nodes, exhibiting highly complex service call topologies. The daily processing of transaction logs, user behavior, and risk indicator data generates over ten billion call chains, and their core operations (especially ensuring transaction continuity and meeting regulatory compliance requirements) heavily rely on the real-time parsing and computation of service dependency graphs. This dependency graph computation can be abstracted as a sparse matrix multiplication (SpMM) problem.
[0003] However, existing CPU / GPU architectures face severe efficiency bottlenecks when processing sparse matrices. Due to the highly random distribution of non-zero elements in sparse matrices, GPU memory bandwidth utilization is less than 40%, and the idle rate of computing units exceeds 60%, resulting in hardware resources not being fully utilized.
[0004] This computational delay has serious consequences in financial operations: delayed fault location can easily trigger cascading service outages in critical payment, clearing, or risk control processes. A typical example is a bank's core payment and clearing system, where the SpMM computational delay prevented the real-time identification of risk propagation paths and delayed the assessment of the fault's impact range by several seconds, ultimately leading to a widening of business interruptions and causing widespread transaction delays and failures. Summary of the Invention
[0005] In view of the above problems, embodiments of this application provide a hardware acceleration method, vector acceleration unit, device, medium, and program product for sparse matrix multiplication operations.
[0006] According to a first aspect of this application, a hardware acceleration method for sparse matrix multiplication is provided, applied to any vector acceleration unit in a vector acceleration unit array. The method includes: obtaining a sparse matrix stored in any vector acceleration unit, wherein the sparse matrix is a subset of an initial matrix A. n×q The sparse matrix is obtained by row compression, where n and q are both positive integers representing the number of rows and columns of the initial matrix, respectively. The sparse matrix includes a weight array, a row pointer array, and a column index array. The weight array represents multiple non-zero elements in the initial matrix, the row pointer array represents the number of non-zero elements in any row of the initial matrix, and the column index array represents the column number of each non-zero element in the initial matrix. The dense matrix B input to any vector acceleration unit is then obtained. q×tt is a positive integer representing the number of columns in the dense matrix, for the initial matrix A. n×q Any array a in the i-th row 1×q Let i = 0, 1, ..., n-1, and let the i-th row of the array a be... 1×q The number of columns p for any non-zero element in the matrix B is used to locate the dense matrix B. q×t Read the dense matrix B from the p-th row, where p = 0, 1, ..., q-1. q×t The p-th row of array b 1×t ; the initial matrix A n×q The i-th row of array a 1×q At least one non-zero element in the p-th row of array b 1×t Perform multiplication and addition operations, and determine the resulting matrix C obtained by multiplying the sparse matrix and the dense matrix based on the operation results. n×t The i-th row of the array c 1×t Obtain the result matrix C n×t .
[0007] According to an embodiment of this application, based on the i-th row array a 1×q The number of columns p for any non-zero element in the matrix B is used to locate the dense matrix B. q×t Read the dense matrix B from the p-th row. q×t The p-th row of array b 1×t This includes: obtaining the read pointer of the dense matrix, which is used to indicate the array b to be read. 1×t The row number in the dense matrix is read by initially pointing the pointer to the first row of the dense matrix; based on the initial matrix A... n×q The column number p of any non-zero element in the i-th row will cause the read pointer to jump from the starting row to the p-th row; read the p-th row array b in the dense matrix. 1×t ; Jump the read pointer from line p to the starting line.
[0008] According to embodiments of this application, any vector acceleration unit further includes multiple parallel accumulators; the method further includes: when initializing matrix A... n×q The i-th row of array a 1×q At least one non-zero element in the p-th row of array b 1×t Before performing multiplication and addition operations, in the dense matrix B q×t The p-th row of array b 1×t In this process, multiple element groups are read sequentially with a preset step size, the preset step size being equal to the number of multiple accumulators; each element group includes multiple vector elements, and the multiple vector elements correspond one-to-one with the multiple accumulators.
[0009] According to an embodiment of this application, the initial matrix A is... n×q The i-th row of array a 1×q At least one non-zero element in the p-th row of array b 1×tPerform multiplication and addition operations, and determine the resulting matrix C obtained by multiplying the sparse matrix and the dense matrix based on the operation results. n×t The i-th row of the array c 1×t This includes performing the following operations for any target accumulator among multiple accumulators: obtaining the initial accumulated value of the target accumulator, where the initial accumulated value is a preset value or comes from the previous vector acceleration unit of any vector acceleration unit; and setting the initial matrix A... n×q The i-th row of array a 1×q The first non-zero element in the array is multiplied by the vector element corresponding to the target accumulator, and the result is added to the initial accumulated value pre-stored in the target accumulator to obtain the first current accumulated value, which is then stored in the target accumulator; the first non-zero element is the array a in the i-th row. 1×q The first non-zero element in column order; the initial matrix A n×q The i-th row of array a 1×q The second non-zero element in the matrix is multiplied by the corresponding vector element of the target accumulator, and the result is added to the first current accumulated value of the target accumulator to obtain the second current accumulated value, which is then stored in the target accumulator; when the initial matrix A is... n×q The i-th row of array a 1×q After performing multiplication and addition operations on multiple non-zero elements in the matrix, the result is used as the result matrix C. n×t The i-th row of the array c 1×t .
[0010] According to an embodiment of this application, the initial matrix A is... n×q The i-th row of array a 1×q At least one non-zero element in the p-th row of array b 1×t Perform multiplication and addition operations, and determine the resulting matrix C obtained by multiplying the sparse matrix and the dense matrix based on the operation results. n×t The i-th row of the array c 1×t It also includes performing the following operations for multiple groups of elements: For any one of the multiple groups of elements, initialize matrix A. n×q The i-th row of array a 1×q The current non-zero element in the matrix is multiplied and added with multiple vector elements in any element group to obtain the third current accumulated value, which is stored in multiple accumulators. The third current accumulated value is the sum of the next element group of any element group and the initial matrix A. n×q The i-th row of array a 1×q When multiplying the current non-zero element in the array, the current accumulated value of multiple accumulators is used; after multiplying and adding the current non-zero element with multiple element groups, the result is used as the result matrix C. n×t The i-th row of the array c 1×t Partial sum; partial sum with initial matrix A n×q The i-th row of array a1×q The results of multiplying and adding the other non-zero elements and multiple element groups in the matrix are summed to obtain the resulting matrix C. n×t The i-th row of the array c 1×t .
[0011] According to embodiments of this application, the method further includes: when in dense matrix B q×t The p-th row of array b 1×t If the number of elements in the last element group read is less than the preset step size, zeros are padded to the last element group so that it contains the number of elements of the preset step size.
[0012] According to embodiments of this application, the method further includes: when the initial matrix A n×q The i-th row of array a 1×q When there are no non-zero elements in the initial matrix A, n×q The (i+1)th row of the array a 1×q With array b in row p 1×t Perform multiplication and addition operations.
[0013] According to embodiments of this application, the method further includes: obtaining the result matrix C n×t Then, the result matrix is output to the next vector acceleration unit or the external storage unit. When the result matrix is output to the next vector acceleration unit, the next vector acceleration unit uses the received result matrix as the initial accumulation value of its multiple accumulators. When the result matrix is output to the external storage unit, the external storage unit is used to store the result matrix for subsequent processing units to read.
[0014] According to a second aspect of this application, a vector acceleration unit is provided, comprising: a first acquisition module, configured to acquire a sparse matrix stored in any vector acceleration unit, the sparse matrix being an initial matrix A. n×q The sparse matrix is obtained by row compression, where n and q are both positive integers representing the number of rows and columns of the initial matrix, respectively. The sparse matrix includes a weight array, a row pointer array, and a column index array. The weight array represents multiple non-zero elements in the initial matrix, the row pointer array represents the number of non-zero elements in any row of the initial matrix, and the column index array represents the column number of each non-zero element in the initial matrix. The second acquisition module is used to acquire the dense matrix B input to any vector acceleration unit. q×t t is a positive integer representing the number of columns in the dense matrix, for the initial matrix A. n×q Any array a in the i-th row 1×q Let i = 0, 1, ..., n-1, and let the i-th row of the array a be... 1×q The number of columns p for any non-zero element in the matrix B is used to locate the dense matrix B. q×t Read the dense matrix B from the p-th row, where p = 0, 1, ..., q-1. q×tThe p-th row of array b 1×t ; Matrix operation module, used to perform operations on the initial matrix A n×q The i-th row of array a 1×q At least one non-zero element in the p-th row of array b 1×t Perform multiplication and addition operations, and determine the resulting matrix C obtained by multiplying the sparse matrix and the dense matrix based on the operation results. n×t The i-th row of the array c 1×t Obtain the result matrix C n×t .
[0015] According to a third aspect of this application, an electronic device is provided, comprising: one or more processors; and a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the method described above.
[0016] According to a fourth aspect of this application, a computer-readable storage medium is also provided, on which a computer program or instructions are stored, wherein the computer program or instructions, when executed by a processor, implement the steps of the above-described method.
[0017] According to a fifth aspect of this application, a computer program product is also provided, including a computer program or instructions that, when executed by a processor, implement the steps of the above-described method. Attached Figure Description
[0018] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:
[0019] Figure 1 The schematic diagram illustrates a system architecture diagram of a hardware acceleration method, vector acceleration unit, device, medium, and program product for sparse matrix multiplication operations according to embodiments of this application.
[0020] Figure 2 A flowchart illustrating a hardware acceleration method for sparse matrix multiplication according to an embodiment of this application is shown schematically.
[0021] Figure 3 A schematic diagram of the structure of a vector acceleration unit according to an embodiment of this application is shown.
[0022] Figure 4 A block diagram of an electronic device suitable for implementing a hardware acceleration method for sparse matrix multiplication operations according to an embodiment of this application is illustrated. Detailed Implementation
[0023] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.
[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0025] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.
[0026] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).
[0027] In the technical solution of this application, the user information (including but not limited to user personal information, user image information, user device information, such as location information) and data (including but not limited to data used for analysis, stored data, and displayed data) involved are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, storage, use, processing, transmission, provision, disclosure, and application of related data all comply with relevant laws, regulations, and standards, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entry points for users to choose to authorize or refuse.
[0028] In scenarios where personal information is used for automated decision-making, the methods, devices, and systems provided in this application all provide users with corresponding operation entry points for users to choose to agree to or reject the automated decision results; if the user chooses to reject, the process enters the expert decision-making process.
[0029] Figure 1The diagram schematically illustrates a system architecture diagram of a hardware acceleration method, vector acceleration unit, device, medium, and program product for sparse matrix multiplication operations according to embodiments of this application. Figure 1 As shown, the system architecture 100 according to an embodiment of this application may include a vector acceleration unit array 110, a processing system 120, a programmable logic 130, and an off-chip memory 140.
[0030] The Versal Adaptive Compute Acceleration Platform (Versal ACAP) is a heterogeneous computing architecture that mainly consists of three computing units: a vector acceleration unit array (AIEngine, AIE) 110, a processing system (PS) 120, and programmable logic (PL) 130.
[0031] The Vector Acceleration Unit Array (AIE array) 110, composed of multiple vector acceleration units 111 arranged in a two-dimensional grid, is the core computing resource. The vector acceleration units (AI Engine, AIE) 111 are the core acceleration engines in Versal ACAP, specifically designed for high-throughput, low-latency matrix operations. Each vector acceleration unit 111 possesses independent computation, storage, and communication capabilities, and can perform key operations such as multiplication and accumulation in sparse matrix multiplication in parallel. The vector acceleration unit array 110 internally enables efficient on-chip interconnection and data distribution, supporting multi-core parallel computing.
[0032] The processing system 120 is responsible for system control, task scheduling, data preprocessing and postprocessing, and interaction with the external environment. It works in conjunction with the vector acceleration unit array 110 and the programmable logic 130 through a dedicated interface to manage the overall execution flow of sparse matrix multiplication.
[0033] The programmable logic 130 is composed of FPGA programmable logic resources and is directly connected to the vector acceleration unit array 110 through the PLIO interface. It undertakes tasks such as data transfer, format conversion, sparse matrix compression / decompression (such as CSR format parsing), and can also implement customized hardware acceleration logic to relieve the pressure on the vector acceleration unit array 110 and the processing system 120.
[0034] The off-chip memory 140 serves as a high-capacity storage medium for storing the original data, intermediate calculation results, and final output of the sparse matrix. The off-chip memory 140 can be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR memory). Data is efficiently transferred between the off-chip memory 140 and the vector acceleration unit array 110 via programmable logic 130, ensuring the continuity and sufficiency of data supply during computation.
[0035] It should be noted that the hardware acceleration method for sparse matrix multiplication provided in this application embodiment can generally be executed by the vector acceleration unit 111. Accordingly, the vector acceleration unit provided in this application embodiment can generally be disposed in the vector acceleration unit array 110.
[0036] Figure 2 A flowchart illustrating a hardware acceleration method for sparse matrix multiplication according to an embodiment of this application is shown schematically. Figure 2 As shown, the hardware acceleration method for sparse matrix multiplication according to the embodiments of this application is applied to any vector acceleration unit in the vector acceleration unit array, and the method 200 may include steps S210 to S230.
[0037] In step S210, the sparse matrix stored in any vector acceleration unit is obtained. The sparse matrix is a subset of the initial matrix A. n×q The sparse matrix is obtained by row compression, where n and q are both positive integers and represent the number of rows and columns of the initial matrix, respectively. The sparse matrix includes a weight array, a row pointer array, and a column index array. The weight array represents multiple non-zero elements in the initial matrix, the row pointer array represents the number of non-zero elements in any row of the initial matrix, and the column index array represents the column number of each of the multiple non-zero elements in the initial matrix.
[0038] For example, sparse matrices are stored in the storage units of any vector acceleration unit, such as in a data memory.
[0039] In a microservice-based database system, service dependencies can be represented as: Node set: multiple microservices (such as transaction service, risk control service, account service, etc.); Edge set: call relationships between services (RPC, HTTP, message queue, etc.); Weight: call frequency, response time, transaction amount, risk propagation probability, etc.
[0040] For example, the initial matrix A n×q Let A be the adjacency matrix of the service dependency graph, where row n represents the target service and column q represents the source service. The initial matrix is A. n×q The elements in the matrix represent call weights (such as transaction amount, propagation probability). Since microservice calls are far fewer than full-connection calls, the initial matrix A... n×q It is a highly sparse matrix.
[0041] For example, the sparse matrix obtained by performing row compression (CSR) on the initial matrix transforms the irregular storage of non-zero elements in the initial matrix into regular row contiguous storage. This can efficiently store the non-zero elements of the sparse matrix and their position information, effectively saving storage space and avoiding the storage of a large number of zero elements.
[0042] In step S220, the dense matrix B input to any vector acceleration unit is obtained. q×t t is a positive integer representing the number of columns in the dense matrix, for the initial matrix A. n×q Any array a in the i-th row 1×q Let i = 0, 1, ..., n-1, and let the i-th row of the array a be... 1×q The number of columns p for any non-zero element in the matrix B is used to locate the dense matrix B. q×t Read the dense matrix B from the p-th row, where p = 0, 1, ..., q-1. q×t The p-th row of array b 1×t .
[0043] For example, dense matrix B q×t The service's real-time status vector / matrix has each column representing a monitoring metric dimension (such as response time, error rate, risk score) and each row representing the current status value of a service. The dense matrix has almost no zero elements, and all locations store valid data.
[0044] For example, in a financial system, there are 5 microservices (user service, account service, transaction service, risk control service, and reporting service) and 4 monitoring metrics (response time, error rate, risk score, and current transaction volume). In this case, q=5 and t=4.
[0045] For example, for the same source service p, it is represented by the number of columns in the initial matrix A and by the number of rows in the dense matrix B. The number of rows p in the dense matrix B is determined by the number of columns p of any non-zero element in the initial matrix A, and the p-th row of the dense matrix B represents all the metrics of the source service p.
[0046] In step S230, the initial matrix A is... n×q The i-th row of array a 1×q At least one non-zero element in the p-th row of array b 1×t Perform multiplication and addition operations, and determine the resulting matrix C obtained by multiplying the sparse matrix and the dense matrix based on the operation results. n×t The i-th row of the array c 1×t Obtain the result matrix C n×t .
[0047] For example, the resulting matrix C n×tRow n represents the target service, column t represents the monitoring metric dimension, and the result matrix C represents the final state value of each target service after considering all dependencies, such as the risk score after risk propagation and the scope of failure impact.
[0048] For example, the resulting matrix C n×t The i-th row of the array c 1×t This represents the final value of the target service across all monitoring dimensions.
[0049] The hardware acceleration method for sparse matrix multiplication provided in the embodiments of this application transforms the irregular storage of non-zero elements in the sparse matrix into regular row-sequential storage. While maintaining a high compression ratio, it achieves efficient support for row traversal and row-level parallelism, effectively improving computational efficiency. By performing vector calculations using non-zero elements and dense matrices, the inner loop of sparse matrix multiplication and addition is fully vectorized, allowing multiple multiplication and addition units to work in parallel with a single instruction, further improving computational efficiency and energy efficiency. This provides a complete hardware acceleration solution for real-time parsing of massive service dependency graphs in fintech scenarios. Utilizing SpMM for millisecond-level real-time analysis of service dependencies on Versal ACAP, it can predict resource bottlenecks in financial transactions and risk control links in advance, significantly reducing the risks of payment failures, transaction delays, and risk control failures. This avoids cascading business interruptions and significant financial losses (such as the million-dollar-per-hour losses in the banking case) caused by fault propagation during critical clearing and transaction periods.
[0050] In the embodiments of this application, based on the i-th row array a 1×q The number of columns p for any non-zero element in the matrix B is used to locate the dense matrix B. q×t Read the dense matrix B from the p-th row. q×t The p-th row of array b 1×t This includes: obtaining the read pointer of the dense matrix, which is used to indicate the array b to be read. 1×t The row number in the dense matrix is read by initially pointing the pointer to the first row of the dense matrix; based on the initial matrix A... n×q The column number p of any non-zero element in the i-th row will cause the read pointer to jump from the starting row to the p-th row; read the p-th row array b in the dense matrix. 1×t ; Jump the read pointer from line p to the starting line.
[0051] For example, jumping the read pointer in a dense matrix B involves moving the read pointer from its current position to the p-th row based on the column number p of the non-zero elements. It jumps from the starting row to the p-th row to prepare for reading data from that row. After reading, the pointer is returned to the starting row to prepare for the next jump.
[0052] For example, in the real-time risk control scenario of a bank's core payment system, dense matrix B stores real-time status data for five microservices: user service, account service, transaction service, risk control service, and clearing service. Each service corresponds to one row, containing indicator values for four monitoring dimensions: response time, error rate, risk score, and transaction volume. When processing the risk assessment of the transaction service (this is the i-th row of the initial matrix A), based on the dependencies recorded in sparse matrix A, the status data of the account service (p=1) and the risk control service (p=3) need to be read sequentially. The read pointer initially points to the user service (row 0). First, based on p=1, it jumps forward to the row containing the account service, reads its status array, and immediately jumps back to the starting row; then, based on p=3, it jumps to the risk control service row, reads its status array, and jumps back. This operation of the read pointer jumping back to the starting row after reading the status array ensures that the status readings of the two source services (account service and risk control service) do not interfere with each other, providing complete input data for subsequent multiplication and addition operations.
[0053] The hardware acceleration method for sparse matrix multiplication provided by the embodiments of this application reads the entire row of data of the dense matrix at once through vector loading, enabling multiple multiplication and addition calculations in a single memory access service, which greatly improves the computation-to-memory ratio; pointer reset makes the access of each non-zero element to the dense matrix independent of each other, and the pointer jump of the current non-zero element will not affect the access of the next non-zero element, thereby supporting the continuous random access sequence of the dense matrix.
[0054] In embodiments of this application, any vector acceleration unit further includes multiple parallel accumulators; the method further includes: when initializing matrix A... n×q The i-th row of array a 1×q At least one non-zero element in the p-th row of array b 1×t Before performing multiplication and addition operations, in the dense matrix B q×t The p-th row of array b 1×t In this process, multiple element groups are read sequentially with a preset step size, the preset step size being equal to the number of multiple accumulators; each element group includes multiple vector elements, and the multiple vector elements correspond one-to-one with the multiple accumulators.
[0055] For example, the maximum processing precision of a multi-way parallel accumulator is 8-bit single-precision floating-point numbers. Therefore, during initialization, four multi-way parallel accumulators (totaling 32 bits) are used for multiply-accumulate operations. Each vector acceleration unit is responsible for calculating the dependencies of 32 services. The results are accumulated in parallel using four accumulators, and scalability to a scale of thousands of nodes can be achieved through multi-core cascading.
[0056] For example, multiple accumulators in parallel form a set of parallel registers within the vector acceleration unit, with each accumulator independently storing an intermediate accumulated value. Each accumulator is responsible for accumulating a partial sum of a monitoring dimension (such as response time, error rate, risk score, or trading volume).
[0057] For example, the preset step size is the p-th row of the dense matrix array b each time. 1×t The number of elements read forward indicates that each read processes data from four monitoring dimensions.
[0058] For example, in dense matrix B q×t The p-th row of array b 1×t The system reads multiple element groups sequentially at a preset step size. Each element group represents the real-time status value of the source service p in four monitoring dimensions.
[0059] For example, a vector element represents a specific metric value in a dense matrix, that is, a specific value of the source service in a certain monitoring dimension, such as a response time of 125ms.
[0060] Multiple vector elements correspond one-to-one with multiple accumulators, meaning each vector element is routed to a uniquely determined accumulator, typically in index order. For example, the 0th vector element (response time) is always accumulated to the 0th accumulator, and the 1st vector element (error rate) is accumulated to the 1st accumulator.
[0061] The hardware acceleration method for sparse matrix multiplication provided in the embodiments of this application divides the row data of a dense matrix into multiple element groups by setting a preset step size equal to the number of parallel accumulators. The vector elements in each element group correspond one-to-one with the accumulators, enabling parallel computation of all accumulators with a single vector loading. This achieves precise matching between storage layout and computation mode. Furthermore, it allows multiple data obtained from a single memory access operation to participate in multi-way multiply-accumulate operations simultaneously, improving the computation-to-memory ratio and reducing memory access bandwidth requirements.
[0062] In the embodiments of this application, the initial matrix A is... n×q The i-th row of array a 1×q At least one non-zero element in the p-th row of array b 1×t Perform multiplication and addition operations, and determine the resulting matrix C obtained by multiplying the sparse matrix and the dense matrix based on the operation results. n×t The i-th row of the array c 1×t This includes performing the following operations for any target accumulator among multiple accumulators: obtaining the initial accumulated value of the target accumulator, where the initial accumulated value is a preset value or comes from the previous vector acceleration unit of any vector acceleration unit; and setting the initial matrix A... n×q The i-th row of array a 1×qThe first non-zero element in the array is multiplied by the vector element corresponding to the target accumulator, and the result is added to the initial accumulated value pre-stored in the target accumulator to obtain the first current accumulated value, which is then stored in the target accumulator; the first non-zero element is the array a in the i-th row. 1×q The first non-zero element in column order; the initial matrix A n×q The i-th row of array a 1×q The second non-zero element in the matrix is multiplied by the corresponding vector element of the target accumulator, and the result is added to the first current accumulated value of the target accumulator to obtain the second current accumulated value, which is then stored in the target accumulator; when the initial matrix A is... n×q The i-th row of array a 1×q After performing multiplication and addition operations on multiple non-zero elements in the matrix, the result is used as the result matrix C. n×t The i-th row of the array c 1×t .
[0063] For example, the target accumulator can be any one of multiple parallel accumulators, responsible for accumulating partial sums of a column or block of columns in the result matrix. Each accumulator independently maintains its own accumulated value.
[0064] For example, the first current accumulated value is the latest value in the accumulator after processing the first non-zero element, which is equal to the initial accumulated value plus the result of the operation of the first non-zero element.
[0065] For example, in the risk assessment scenario of the transaction service (row i=2 in the initial matrix A), accumulator 0 is responsible for accumulating the response time dimension. When processing the first non-zero element (dependent on account service, weight 0.5), the response time of 87 is read from row 1 of dense matrix B, multiplied by the initial accumulated value of 10.0 and updated to 53.5; when processing the second non-zero element (dependent on user service, weight 0.3), the response time of 125 is read from row 0 of dense matrix B, multiplied by the initial accumulated value and updated to 91.0; when processing the third non-zero element (dependent on clearing service, weight 0.2), the response time of 312 is read from row 3, multiplied by the initial accumulated value and finally reaches 153.4, which is the comprehensive response time result of the transaction service.
[0066] The hardware acceleration method for sparse matrix multiplication provided by the embodiments of this application enables each accumulator to independently maintain the contribution accumulation of all non-zero elements in the row through iterative inheritance of accumulator values, thereby realizing continuous accumulation at the register level and completely eliminating the memory access overhead of intermediate results. At the same time, the initial accumulated value can inherit the calculation result of the previous level vector acceleration unit, realizing seamless cascading and precision preservation between multiple cores.
[0067] In the embodiments of this application, the initial matrix A is... n×q The i-th row of array a 1×qAt least one non-zero element in the p-th row of array b 1×t Perform multiplication and addition operations, and determine the resulting matrix C obtained by multiplying the sparse matrix and the dense matrix based on the operation results. n×t The i-th row of the array c 1×t It also includes performing the following operations for multiple groups of elements: For any one of the multiple groups of elements, initialize matrix A. n×q The i-th row of array a 1×q The current non-zero element in the matrix is multiplied and added with multiple vector elements in any element group to obtain the third current accumulated value, which is stored in multiple accumulators. The third current accumulated value is the sum of the next element group of any element group and the initial matrix A. n×q The i-th row of array a 1×q When multiplying the current non-zero element in the array, the current accumulated value of multiple accumulators is used; after multiplying and adding the current non-zero element with multiple element groups, the result is used as the result matrix C. n×t The i-th row of the array c 1×t Partial sum; partial sum with initial matrix A n×q The i-th row of array a 1×q The results of multiplying and adding the other non-zero elements and multiple element groups in the matrix are summed to obtain the resulting matrix C. n×t The i-th row of the array c 1×t .
[0068] For example, in a scenario where the transaction service (row i in the initial matrix A) depends on the risk control service (weight 0.7), the eight monitoring dimensions are divided into two groups of four. When processing the first group (dimensions 0-3), four accumulators receive the risk control service's response time (56), error rate (0.00), risk score (12), and transaction volume (2345) in parallel, multiplying them by the weight 0.7 to obtain an intermediate accumulated value. When processing the second group (dimensions 4-7), the accumulators use the intermediate value as a base and continue to accumulate the weighted contributions of CPU utilization (45), memory utilization (62), network latency (8), and availability (1) in parallel, ultimately obtaining the partial sum of the risk control service for all eight dimensions. This partial sum is then added to the partial sums of other dependent services (other non-zero elements) in the same row to form the complete result for one row of the transaction service.
[0069] The hardware acceleration method for sparse matrix multiplication provided by the embodiments of this application realizes the full coverage calculation of all columns in a certain row of a dense matrix by a single non-zero element: multiple vector elements in each element group are multiplied and added in parallel with multiple accumulators, and the groups are passed sequentially by the inheritance mechanism of accumulator values, so that the contribution of the current non-zero element to all columns of the dense matrix is fully accumulated as a "partial sum"; the partial sums of multiple non-zero elements are then added together through the continuous inheritance of accumulators, and finally the complete row vector of the result matrix is obtained, realizing the full coverage calculation of dense matrices with arbitrary number of columns and sparse matrices with arbitrary row length.
[0070] In embodiments of this application, the method further includes: when in dense matrix B q×t The p-th row of array b 1×t If the number of elements in the last element group read is less than the preset step size, zeros are padded to the last element group so that it contains the number of elements of the preset step size.
[0071] For example, when the number of columns t of the dense matrix is not divisible by the number of accumulators, the actual number of elements in the last element group is less than the number of accumulators, which is 4. For the last element group with less than 4 elements, the end is padded with 0s to force its length to be equal to 4.
[0072] The hardware acceleration method for sparse matrix multiplication provided in the embodiments of this application completely eliminates the hardware branch judgment and control complexity introduced by boundary cases by padding the last incomplete element group with zeros, so that all element groups have the same length: all element groups adopt a unified vector loading instruction and a fixed-length data block processing flow, and there is no need to design special length judgment and partial accumulator masking logic for the last group; the zero-padding element multiplied by any non-zero weight is 0, which does not affect the mathematical correctness of the accumulation result.
[0073] In embodiments of this application, the method further includes: when the initial matrix A n×q The i-th row of array a 1×q When there are no non-zero elements in the initial matrix A, n×q The (i+1)th row of the array a 1×q With array b in row p 1×t Perform multiplication and addition operations.
[0074] For example, the initial matrix A n×q The i-th row of array a 1×q There are no non-zero elements in the sparse matrix, meaning all elements in the i-th row are zero; skip the current empty row, increment the row index directly to the next row, and continue the multiplication and addition operation process.
[0075] For example, the row pointer array can be used to determine whether the i-th row of the initial matrix A is empty.
[0076] The hardware acceleration method for sparse matrix multiplication provided in the embodiments of this application quickly detects empty rows and skips them directly by using a row pointer array. While keeping the accumulator state unchanged, it increments the row index to proceed to the next row for processing, completely eliminating the overhead of invalid multiplication and addition operations and loop checks for empty rows. In fintech scenarios, service dependency graphs often contain a large number of leaf nodes with zero out-degree or services that have not been called, resulting in a very high proportion of empty rows. This solution can significantly improve overall computational efficiency, ensuring that computing resources are focused on service rows with actual dependencies.
[0077] In embodiments of this application, the method further includes: obtaining the result matrix C n×t Then, the result matrix is output to the next vector acceleration unit or the external storage unit. When the result matrix is output to the next vector acceleration unit, the next vector acceleration unit uses the received result matrix as the initial accumulation value of its multiple accumulators. When the result matrix is output to the external storage unit, the external storage unit is used to store the result matrix for subsequent processing units to read.
[0078] For example, the next vector acceleration unit is the next processing unit after the current vector acceleration unit in the cascaded architecture. It receives the output of the current vector acceleration unit as its initial accumulated value to realize multi-core pipelined computing.
[0079] For example, external storage units are used to persistently store the final calculation results for subsequent reading by the CPU, GPU, or other processing units.
[0080] For example, the output of the current vector acceleration unit can be directly passed to the next vector acceleration unit through the cascading interface, without going through memory, thus achieving zero-overhead inter-core communication.
[0081] The hardware acceleration method for sparse matrix multiplication provided by the embodiments of this application achieves seamless integration of multi-core pipeline computation and result persistence by providing two flexible output modes: cascaded output and external storage. In cascaded output mode, the accumulator content of the current vector acceleration unit is directly passed to the next vector acceleration unit as the initial accumulation value through a dedicated hardware interface. The inter-core communication latency is small and completely overlaps with the computation. Intermediate results always flow at the register level without needing to be written back to memory, avoiding the hundreds of nanoseconds of overhead and precision loss of accessing external data temporary storage units. This allows the computational throughput of the multi-core system (vector acceleration unit array) to scale linearly with the number of cores. In external storage mode, the final core writes the final result matrix back to off-chip memory through DMA, providing a data source for subsequent processing units such as CPU monitoring, risk control engine, and compliance reports, thus achieving complete integration between accelerated computation and business systems.
[0082] To support the demands of large-scale parallel computing, the computation of a single-core vector acceleration unit can be extended to a multi-core vector acceleration unit array. First, based on the local memory capacity of each vector acceleration unit, the first matrix and the second matrix are divided into multiple initial matrices A according to the block matrix multiplication rules. n×q and multiple dense matrices B q×t Each vector acceleration unit can hold an initial matrix and a dense matrix. Each vector acceleration unit performs multiplication and addition operations on its assigned initial matrix and dense matrix. Then, multiple vector acceleration units are cascaded according to the architecture of the first vector acceleration unit (without cascaded input) and other meta-vector acceleration units (receiving the results of the previous vector acceleration unit) to build a cascaded data flow channel. The vector acceleration units form a pipeline to work in parallel. The processing result of the first vector acceleration unit is used as the initial accumulated value of the next vector acceleration unit. Subsequent vector acceleration units accumulate their own calculation results based on the received results and transmit them, realizing complete overlap between calculation and communication. Finally, the result matrix blocks output by the last vector acceleration unit are concatenated row by row to obtain the complete final result matrix.
[0083] Based on the hardware acceleration method for sparse matrix multiplication described above, embodiments of this application also provide a vector acceleration unit. The following will combine... Figure 3 This vector acceleration unit is described in detail.
[0084] Figure 3 A schematic block diagram of a vector acceleration unit according to an embodiment of this application is shown.
[0085] like Figure 3 As shown, the vector acceleration unit 300 in this embodiment includes a first acquisition module 310, a second acquisition module 320, and a matrix operation module 330.
[0086] The first acquisition module 310 is used to acquire the sparse matrix stored in any vector acceleration unit. The sparse matrix is a subset of the initial matrix A. n×q The sparse matrix is obtained by row compression, where n and q are both positive integers representing the number of rows and columns of the initial matrix, respectively. The sparse matrix includes a weight array, a row pointer array, and a column index array. The weight array represents multiple non-zero elements in the initial matrix, the row pointer array represents the number of non-zero elements in any row of the initial matrix, and the column index array represents the column number of each non-zero element in the initial matrix. In one embodiment, the first acquisition module 310 can be used to execute step S210 described above, which will not be repeated here.
[0087] The second acquisition module 320 is used to acquire the dense matrix B input to any vector acceleration unit. q×t t is a positive integer representing the number of columns in the dense matrix, for the initial matrix A. n×q Any array a in the i-th row1×q Let i = 0, 1, ..., n-1, and let the i-th row of the array a be... 1×q The number of columns p for any non-zero element in the matrix B is used to locate the dense matrix B. q×t Read the dense matrix B from the p-th row, where p = 0, 1, ..., q-1. q×t The p-th row of array b 1×t In one embodiment, the second acquisition module 320 can be used to perform the step S220 described above, which will not be repeated here.
[0088] Matrix operation module 330 is used to perform operations on the initial matrix A. n×q The i-th row of array a 1×q At least one non-zero element in the p-th row of array b 1×t Perform multiplication and addition operations, and determine the resulting matrix C obtained by multiplying the sparse matrix and the dense matrix based on the operation results. n×t The i-th row of the array c 1×t Obtain the result matrix C n×t In one embodiment, the matrix operation module 330 can be used to perform the steps S230 described above, which will not be repeated here.
[0089] According to embodiments of this application, any plurality of modules among the first acquisition module 310, the second acquisition module 320, and the matrix operation module 330 can be merged into one module, or any one of these modules can be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules can be combined with at least part of the functionality of other modules and implemented in one module. According to embodiments of this application, at least one of the first acquisition module 310, the second acquisition module 320, and the matrix operation module 330 can be at least partially implemented as a hardware circuit, such as a field-programmable gate array, a programmable logic array, a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit, or implemented by any other reasonable means of integrating or packaging the circuit, or implemented by any one of the three implementation methods of software, hardware, and firmware, or by any appropriate combination of any of them. Alternatively, at least one of the first acquisition module 310, the second acquisition module 320, and the matrix operation module 330 can be at least partially implemented as a computer program module, which can perform corresponding functions when the computer program module is run.
[0090] Figure 4 A block diagram of an electronic device suitable for implementing a hardware acceleration method for sparse matrix multiplication operations according to an embodiment of this application is illustrated.
[0091] like Figure 4As shown, an electronic device 400 according to an embodiment of this application includes a processor 401, which can perform various appropriate actions and processes according to a program stored in a read-only memory 402 or a program loaded from a storage portion 408 into a random access memory 403. The processor 401 may include, for example, a general-purpose microprocessor, an instruction set processor and / or an associated chipset and / or a dedicated microprocessor. The processor 401 may also include onboard memory for caching purposes. The processor 401 may include a single processing unit or multiple processing units for executing different steps of the method flow according to an embodiment of this application.
[0092] Random access memory 403 stores various programs and data required for the operation of electronic device 400. Processor 401, read-only memory 402, and random access memory 403 are interconnected via bus 404. Processor 401 executes various steps of the method flow according to embodiments of this application by executing programs stored in read-only memory 402 and / or random access memory 403. It should be noted that the programs may also be stored in one or more memories other than read-only memory 402 and random access memory 403. Processor 401 may also execute various steps of the method flow according to embodiments of this application by executing programs stored in said one or more memories.
[0093] According to embodiments of this application, the electronic device 400 may further include an input / output interface 405, which is also connected to a bus 404. The electronic device 400 may also include one or more of the following components connected to the input / output interface 405: an input section 406 including a keyboard, mouse, etc.; an output section 407 including a cathode ray tube, liquid crystal display, etc., and a speaker, etc.; a storage section 408 including a hard disk, etc.; and a communication section 409 including a network interface card, such as a local area network card, modem, etc. The communication section 409 performs communication processing via a network such as the Internet. A drive 410 is also connected to the input / output interface 405 as needed. A removable medium 411, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 410 as needed so that computer programs read from it can be installed into the storage section 408 as needed.
[0094] Embodiments of this application also provide a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of this application.
[0095] According to embodiments of this application, the computer-readable storage medium can be a non-volatile computer-readable storage medium, such as including but not limited to: portable computer disks, hard disks, random access memory, read-only memory, erasable programmable read-only memory, portable compact disk read-only memory, optical storage devices, magnetic storage devices, or any suitable combination thereof. In embodiments of this application, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this application, the computer-readable storage medium may include the read-only memory 402 described above, and / or random access memory 403, and / or one or more memories other than read-only memory 402 and random access memory 403.
[0096] Embodiments of this application also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to cause the computer system to implement the methods provided in the embodiments of this application.
[0097] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and downloaded and installed via communication section 409, and / or installed from removable medium 411. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.
[0098] In embodiments of this application, the computer program can be downloaded and installed from a network via communication section 409, and / or installed from removable medium 411. When the computer program is executed by processor 401, it performs the functions defined in the system of this application embodiment. According to embodiments of this application, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.
[0099] According to embodiments of this application, program code for executing the computer programs provided in the embodiments of this application can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).
[0100] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.
[0101] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.
Claims
1. A hardware acceleration method for sparse matrix multiplication, applied to any vector acceleration unit in a vector acceleration unit array, characterized in that, The method includes: acquiring a sparse matrix stored by the any vector acceleration unit, the sparse matrix being obtained by performing row compression on an initial matrix A n×q n and q are positive integers and represent the number of rows and columns of the initial matrix respectively, the sparse matrix comprises a weight array, a row pointer array and a column index array, the weight array represents a plurality of nonzero elements in the initial matrix, the row pointer array represents the number of nonzero elements in any row of the initial matrix, and the column index array represents the respective column number of the plurality of nonzero elements in the initial matrix; Obtain the dense matrix B input to any of the vector acceleration units. q×t t is a positive integer representing the number of columns in the dense matrix, for the initial matrix A. n×q Any array a in the i-th row 1×q Let i = 0, 1, ..., n-1, and let the i-th row of the array a be... 1×q The column number p of any non-zero element in the dense matrix B is used to locate the dense matrix B. q×t Read the p-th row, p=0,1,…,q-1, from the dense matrix B. q×t The p-th row of array b 1×t ; The initial matrix A n×q The i-th row of array a 1×q At least one non-zero element in the p-th row of array b 1×t Perform multiplication and addition operations, and determine the resulting matrix C obtained by multiplying the sparse matrix and the dense matrix based on the operation results. n×t The i-th row of the array c 1×t The result matrix C is obtained. n×t .
2. The method according to claim 1, characterized in that, said according to the i-th row array a 1×q The number of columns p of any non-zero element in the i-th row of the dense matrix B q×t The p-th row of the dense matrix B q×t The p-th row array b 1×t , including: obtaining a read pointer of the dense matrix, the read pointer being used to indicate an array b to be read 1×t a number of rows in the dense matrix, an initial state of the read pointer pointing to a starting row of the dense matrix; According to the initial matrix A n×q The column number p of any non-zero element in the i-th row of the initial matrix A jumps the read pointer from the starting row to the p-th row. reading a p-th row array b in the dense matrix 1×t ; The read pointer is moved from the p-th line to the starting line.
3. The method according to claim 1, characterized in that, Each of the vector acceleration units also includes multiple parallel accumulators; The method further includes: in the process of setting the initial matrix A n×q The i-th row of array a 1×q At least one non-zero element in the p-th row of array b 1×t Before performing multiplication and addition operations, In the dense matrix B q×t The p-th row of array b 1×t In this process, multiple groups of elements are read sequentially with a preset step size, wherein the preset step size is equal to the number of multiple accumulators; Each element group includes multiple vector elements, and each vector element corresponds one-to-one with a multiple accumulator.
4. The method according to claim 3, characterized in that, The initial matrix A is... n×q The i-th row of array a 1×q At least one non-zero element in the p-th row of array b 1×t Perform multiplication and addition operations, and determine the resulting matrix C obtained by multiplying the sparse matrix and the dense matrix based on the operation results. n×t The i-th row of the array c 1×t This includes performing the following operations for any target accumulator among the plurality of accumulators: Obtain the initial accumulated value of the target accumulator, wherein the initial accumulated value is a preset value or comes from the previous vector acceleration unit of any of the vector acceleration units; The initial matrix A n×q The i-th row of array a 1×q The first non-zero element in the array is multiplied by the vector element corresponding to the target accumulator, and the result is added to the initial accumulated value pre-stored in the target accumulator to obtain the first current accumulated value, which is then stored in the target accumulator; the first non-zero element is the array a in the i-th row. 1×q The first non-zero element in column-major order; The initial matrix A n×q The i-th row of array a 1×q The second non-zero element in the target accumulator is multiplied by the vector element corresponding to the target accumulator, and the result of the operation is added to the first current accumulated value of the target accumulator to obtain the second current accumulated value, which is then stored in the target accumulator. When the multiplication-addition operation is performed on the plurality of non-zero elements in the i-th row array a n×q in the initial matrix A 1×q , the operation result is taken as the i-th row array c n×t in the result matrix C 1×t .
5. The method according to claim 3, characterized in that, The initial matrix A is... n×q The i-th row of array a 1×q At least one non-zero element in the p-th row of array b 1×t Perform multiplication and addition operations, and determine the resulting matrix C obtained by multiplying the sparse matrix and the dense matrix based on the operation results. n×t The i-th row of array c 1×t It also includes performing the following operations on the plurality of element groups: For any one of the plurality of element groups, the initial matrix A is... n×q The i-th row of array a 1×q The current non-zero element in the array is multiplied and added with multiple vector elements in any of the element groups to obtain a third current accumulated value, which is then stored in the multiple accumulators. The third current accumulated value is the next element group of any element group and the initial matrix A. n×q The i-th row of array a 1×q The current accumulated value of the multiple accumulators when multiplying the current non-zero elements in the array; After the current non-zero element is multiplied and added with all of the multiple element groups, the result is used as the result matrix C. n×t The i-th row of the array c 1×t Parts and; The portion and the initial matrix A n×q The i-th row of array a 1×q The results of multiplying and adding the other non-zero elements in the matrix and the multiple element groups are added together to obtain the result matrix C. n×t The i-th row of array c 1×t .
6. The method according to claim 3, characterized in that, The method further includes: When in the dense matrix B q×t The p-th row of array b 1×t If the number of elements in the last element group read is less than the preset step size, the last element group is padded with zeros so that the last element group contains the number of elements of the preset step size.
7. The method according to claim 1, characterized in that, The method further includes: When the initial matrix A n×q The i-th row of array a 1×q When there are no non-zero elements in the initial matrix A, n×q The (i+1)th row of the array a 1×q With the p-th row array b 1×t Perform multiplication and addition operations.
8. The method according to claim 3, characterized in that, The method further includes: obtaining the result matrix C n×t after, The resulting matrix is output to the next vector acceleration unit or external storage unit; When the result matrix is output to the next vector acceleration unit, the next vector acceleration unit uses the received result matrix as the initial accumulated value of its multiple accumulators; When the result matrix is output to the external storage unit, the external storage unit is used to store the result matrix for subsequent processing units to read.
9. A vector acceleration unit, characterized in that, include: The first acquisition module is used to acquire the sparse matrix stored in any vector acceleration unit, wherein the sparse matrix is a subset of the initial matrix A. n×q The sparse matrix is obtained by row compression, where n and q are both positive integers and represent the number of rows and columns of the initial matrix, respectively. The sparse matrix includes a weight array, a row pointer array, and a column index array. The weight array represents multiple non-zero elements in the initial matrix, the row pointer array represents the number of non-zero elements in any row of the initial matrix, and the column index array represents the column number of each of the multiple non-zero elements in the initial matrix. The second acquisition module is used to acquire the dense matrix B input to any of the vector acceleration units. q×t t is a positive integer representing the number of columns in the dense matrix, for the initial matrix A. n×q Any array a in the i-th row 1×q Let i = 0, 1, ..., n-1, and let the i-th row of the array a be... 1×q The column number p of any non-zero element in the dense matrix B is used to locate the dense matrix B. q×t Read the p-th row, p=0,1,…,q-1, from the dense matrix B. q×t The p-th row of array b 1×t ; The matrix operation module is used to perform operations on the initial matrix A. n×q The i-th row of array a 1×q At least one non-zero element in the p-th row of array b 1×t Perform multiplication and addition operations, and determine the resulting matrix C obtained by multiplying the sparse matrix and the dense matrix based on the operation results. n×t The i-th row of the array c 1×t The result matrix C is obtained. n×t .
10. An electronic device, comprising: One or more processors; Memory, used to store one or more computer programs. The characteristic feature is that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 8.
11. A computer-readable storage medium having a computer program or instructions stored thereon, characterized in that, When the computer program or instructions are executed by a processor, they implement the steps of the method according to any one of claims 1 to 8.
12. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by a processor, they implement the steps of the method according to any one of claims 1 to 8.