Bose sampling result preprocessor

Abstract

This invention discloses a preprocessor for Boson sampling results, relating to the field of optical quantum computing technology. The preprocessor includes a detector data receiving module, a hardware noise reduction module, a statistical distribution analysis module, and a result encapsulation module. All modules are purely hardware integrated circuits, with no software processor involved in the core control of the entire process. The detector data receiving module receives the raw sampling data, the hardware noise reduction module performs noise reduction processing on the raw sampling data, the statistical distribution analysis module calculates the probability distribution characteristics of the sampling data, and the result encapsulation module packages the results into standard format data frames for output. This invention implements the preprocessing of Boson sampling results through pure hardware, effectively improving processing speed and accuracy while reducing system latency.

Description

Technical Field

[0001] This invention relates to the field of optical quantum computing technology, and in particular to a Boson sampling result preprocessor. Background Technology

[0002] Boson sampling is an important prototype of quantum computing, demonstrating the superiority of quantum computing in solving specific problems. The results of boson sampling require preprocessing before subsequent analysis and verification. In current technologies, the preprocessing of boson sampling results is typically implemented in software, that is, software acquires the raw data output by the detector and performs noise reduction, statistical analysis, and other processing.

[0003] This software implementation has the following problems: First, the software processing has a large delay, making it difficult to meet the ever-increasing high-speed requirements of the Boson sampling system; second, the processing accuracy of the software implementation is low, affecting the accuracy of the results; and finally, the software processor is susceptible to interference, resulting in low reliability. Summary of the Invention

[0004] The purpose of this invention is to provide a preprocessor for Boson sampling results, so as to solve the problems of large delay, low accuracy and poor reliability in the software-based preprocessing of Boson sampling results in the prior art.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A boson sampling result preprocessor includes a detector data receiving module, a hardware noise reduction module, a statistical distribution analysis module, and a result encapsulation module. The detector data receiving module receives raw sampling data. The hardware noise reduction module, electrically connected to the detector data receiving module, performs dark count subtraction and background noise filtering on the raw sampling data. The statistical distribution analysis module, electrically connected to the hardware noise reduction module, performs statistical distribution calculations on the noise-reduced sampling data to generate probability distribution features. The result encapsulation module, electrically connected to the statistical distribution analysis module, packages the probability distribution features into a standard format data frame and outputs it. All components—the detector data receiving module, hardware noise reduction module, statistical distribution analysis module, and result encapsulation module—are pure hardware integrated circuits, with no software processor involved in the core control throughout the entire process.

[0006] Furthermore, the detector data receiving module supports no less than 1024 parallel input channels, and the data bit width of a single channel is no less than 8 bits; the raw sampling data comes from a single-photon detector array.

[0007] Furthermore, the hardware noise reduction module includes a dark count subtraction circuit and a background noise filtering circuit; the dark count subtraction circuit has a built-in dark count baseline table stored in a one-time programmable memory unit, and the hardware automatically looks up the table to subtract the dark count of each channel; the background noise filtering circuit adopts a hardware moving average filter.

[0008] Furthermore, the statistical distribution analysis module includes a hardware histogram statistical circuit, which performs real-time hardware statistics on the denoised sampled data according to the photon number distribution to generate a probability distribution histogram of the sampling results.

[0009] Furthermore, the data frame generated by the result encapsulation module includes a frame header identifier, a task identifier, photon number distribution histogram data, and a cyclic redundancy check code. The data frame is directly written to a specified memory address through a hardware direct memory access channel.

[0010] Furthermore, it also includes a result anomaly detection module, which is electrically connected to the statistical distribution analysis module. This module is used to perform hardware comparison of the probability distribution characteristics of the sampling results with the preset Boson sampling theoretical distribution. When the deviation exceeds a preset threshold, the result is marked as an anomaly and the compiler is notified.

[0011] The present invention also provides a method for using the above-mentioned preprocessor, comprising the following steps: a. receiving raw sampling data output from a single-photon detector array; b. performing hardware-level dark count subtraction and background noise filtering on the raw sampling data; c. performing hardware-level statistical distribution calculation on the noise-reduced sampling data to generate probability distribution features; d. packaging the probability distribution features into a standard format data frame and outputting it.

[0012] The present invention also provides a boson sampling chip, which integrates the above-mentioned boson sampling result preprocessor.

[0013] Furthermore, the chip also integrates a single-photon detector array and an optical interferometer network. Beneficial effects

[0014] This invention achieves preprocessing of Boson sampling results through pure hardware integrated circuits, and has the following advantages compared with the prior art: 1. Significantly reduced latency: Pure hardware processing can achieve nanosecond-level response speeds, meeting the high-speed requirements of the boson sampling system; 2. Significantly improved accuracy: By employing hardware noise reduction and statistical circuits, higher processing accuracy can be achieved; 3. Significantly improved reliability: Pure hardware circuits are not affected by software interference, resulting in higher stability and reliability; 4. Significantly enhanced parallel processing capability: Supports more than 1024 parallel input channels, enabling simultaneous processing of output data from multiple detectors; 5. Significantly improved data transmission efficiency: Data is transmitted using hardware direct memory access, eliminating the need for software processor intervention and thus improving data transmission efficiency. Detailed Implementation

[0015] The present invention will now be described in detail with reference to specific embodiments.

[0016] The Bose sampling result preprocessor provided in this embodiment includes a detector data receiving module, a hardware noise reduction module, a statistical distribution analysis module, and a result encapsulation module. All modules are implemented using pure hardware integrated circuits, with no software processor involved in the core control of the entire process.

[0017] The detector data receiving module is used to receive the raw sampled data output by the single-photon detector array. The detector data receiving module supports no fewer than 1024 parallel input channels, with a single channel data width of no less than 8 bits, and can process the output data from multiple detector channels simultaneously.

[0018] The hardware noise reduction module is electrically connected to the detector data receiving module and includes a dark count subtraction circuit and a background noise filtering circuit. The dark count subtraction circuit has a built-in one-time programmable memory unit that stores a pre-measured dark count baseline table for each channel, and the hardware automatically looks up the table to subtract the dark count for each channel. The background noise filtering circuit uses a hardware moving average filter, which can effectively filter out background noise.

[0019] The statistical distribution analysis module is electrically connected to the hardware noise reduction module and includes a hardware histogram statistical circuit. The hardware histogram statistical circuit performs real-time hardware statistics on the noise-reduced sampled data according to the photon number distribution, generating a probability distribution histogram of the sampling results.

[0020] The results encapsulation module is electrically connected to the statistical distribution analysis module and includes a hardware data frame encapsulator and a direct memory access controller. The results encapsulation module packages the probability distribution characteristics into standard format data frames. Each data frame includes a frame header identifier, a task identifier, photon number distribution histogram data, and a cyclic redundancy check (CRC) code. The data frames are written directly to a specified memory address via the hardware direct memory access channel, without the need for a software processor.

[0021] In a preferred embodiment, the preprocessor further includes a result anomaly detection module electrically connected to the statistical distribution analysis module. The result anomaly detection module performs a hardware comparison of the probability distribution characteristics of the sampling results with a preset Boson sampling theoretical distribution. When the deviation exceeds a preset threshold, it marks the result as an anomaly and notifies the compiler.

[0022] The working process of the Bose sampling result preprocessor provided in this embodiment is as follows: 1. The detector data receiving module receives the raw sampled data output by the single-photon detector array; 2. The hardware noise reduction module performs dark count subtraction and background noise filtering on the original sampled data; 3. The statistical distribution analysis module performs statistical distribution calculations on the denoised sampled data to generate probability distribution features; 4. The result encapsulation module packages the probability distribution features into a standard format data frame and outputs it; 5. The result anomaly detection module performs anomaly detection on the sampling results and notifies the compiler when an anomaly is detected.

Claims

1. A preprocessor for Boson sampling results, characterized in that, The system includes a detector data receiving module, a hardware noise reduction module, a statistical distribution analysis module, and a result packaging module. The detector data receiving module receives raw sampled data. The hardware noise reduction module, electrically connected to the detector data receiving module, performs dark count subtraction and background noise filtering on the raw sampled data. The statistical distribution analysis module, electrically connected to the hardware noise reduction module, performs statistical distribution calculations on the noise-reduced sampled data to generate probability distribution features. The result packaging module, electrically connected to the statistical distribution analysis module, packages the probability distribution features into a standard format data frame and outputs it. All components—the detector data receiving module, hardware noise reduction module, statistical distribution analysis module, and result packaging module—are pure hardware integrated circuits, with no software processor involved in the core control throughout the entire process.

2. The preprocessor according to claim 1, characterized in that, The detector data receiving module supports no less than 1024 parallel input channels, and the data bit width of a single channel is no less than 8 bits; the raw sampling data comes from a single-photon detector array.

3. The preprocessor according to claim 1, characterized in that, The hardware noise reduction module includes a dark count subtraction circuit and a background noise filtering circuit; the dark count subtraction circuit has a built-in dark count baseline table stored in a one-time programmable memory unit, and the hardware automatically looks up the table to subtract the dark count of each channel; the background noise filtering circuit adopts a hardware moving average filter.

4. The preprocessor according to claim 1, characterized in that, The statistical distribution analysis module includes a hardware histogram statistical circuit, which performs real-time hardware statistics on the denoised sampled data according to the photon number distribution to generate a probability distribution histogram of the sampling results.

5. The preprocessor according to claim 1, characterized in that, The data frame generated by the result encapsulation module includes a frame header identifier, a task identifier, photon number distribution histogram data, and a cyclic redundancy check code. The data frame is directly written to a specified memory address through a hardware direct memory access channel.

6. The preprocessor according to claim 1, characterized in that, It also includes a result anomaly detection module, which is electrically connected to the statistical distribution analysis module. This module is used to perform hardware comparison between the probability distribution characteristics of the sampling results and the preset Boson sampling theoretical distribution. When the deviation exceeds a preset threshold, it is marked as an abnormal result and the compiler is notified.

7. A method using the preprocessor of claim 1, characterized in that, Includes the following steps: a. Receive the raw sampled data output from the single-photon detector array; b. Perform hardware-level dark count subtraction and background noise filtering on the raw sampled data; c. Perform hardware-level statistical distribution calculations on the denoised sampled data to generate probability distribution features; d. Pack the probability distribution features into a standard format data frame and output it.

8. The method according to claim 7, characterized in that, In step b, the dark count subtraction uses a hardware automatic table lookup method, and the background noise filtering uses a hardware moving average filtering method; in step c, the statistical distribution calculation uses a hardware histogram statistical method.

9. A boson sampling chip, characterized in that, Integrate the Bose sampling result preprocessor as described in claim 1.

10. The chip according to claim 9, characterized in that, It also integrates a single-photon detector array and an optical interferometer network.