Chip package fan-out pad automatic allocation method, computer device and storage medium

Abstract

This invention provides an automatic fan-out pad allocation method, computer device, and storage medium for chip packages. The method includes: acquiring silicon interposer board size information and the coordinates of the pads to be fanned out; constructing and solving a nonlinear programming model with the goal of balancing pad density in sub-regions based on the coordinates of each pad to be fanned out, obtaining horizontal and vertical dividing lines that maximize the balance of pad density in each sub-region, thus completing global region segmentation; for each sub-region, sorting the set of ubump pads to be fanned out and the set of C4 pads by polar angle, and establishing line segment non-intersection constraints based on computational geometry cross-experimentation; constructing an integer programming model with the optimization objectives of minimizing trace length and the number of via crossings; and solving the model to obtain the allocation result of C4 pads for the ubump pads to be fanned out. Applying the automatic fan-out pad allocation method of this invention can improve the overall fan-out pad link quality.

Description

Technical Field

[0001] This invention relates to the field of chip technology, specifically to an automatic allocation method for fan-out pads in chip packages, a computer device using the automatic allocation method for fan-out pads in chip packages, and a computer-readable storage medium using the automatic allocation method for fan-out pads in chip packages. Background Technology

[0002] With the rapid development of advanced packaging technologies, chip sizes are constantly shrinking and I / O counts are surging. Fan-out packaging, 2.5D / 3D packaging, and chiplet integration have become mainstream solutions. In these packaging structures, microbumps are typically used on the chip side. The chip uses a bump / ubump pad as the signal output interface, while the adapter board or package substrate uses C4 solder balls (C4 bump) to achieve electrical interconnection with the outside. Signals need to be fanned out from the ubump pad of the chip through internal wiring to the C4 pad, and then connected to the external system.

[0003] Traditional fan-out design methods based on human experience or simple rules do not systematically divide the fan-out area, resulting in random distribution of signal trace distances. This can easily lead to problems such as excessively long local links, increased crosstalk, and difficulty in timing convergence. Furthermore, it is impossible to constrain the upper limit of the fan-out trace distance at a global level, which seriously affects the quality of high-speed signal transmission.

[0004] Although existing advanced packaged EDA tools have some capability to support automated design of 2.5D / 3D advanced packaged signal fan-out, their capabilities focus on the interconnect connectivity of the design, and pay insufficient attention to signal quality beyond connectivity.

[0005] Therefore, a more optimized method for automatically allocating fan-out pads in chip packages needs to be considered. Summary of the Invention

[0006] The primary objective of this invention is to provide an automatic fan-out pad allocation method for chip packages that can improve the overall fan-out pad link quality.

[0007] A second objective of this invention is to provide a computer device that can improve the overall fan-out pad link quality.

[0008] A third objective of this invention is to provide a computer-readable storage medium that can improve the overall fan-out pad link quality.

[0009] To achieve the aforementioned first objective, the chip packaging fan-out pad automatic allocation method provided by this invention includes: acquiring silicon interposer board size information and the coordinates of the pads to be fanned out; setting partition grid parameters m and n, dividing the silicon interposer board area into m rows and n columns of sub-regions, and using horizontal cutting lines and vertical dividing lines as optimization decision variables; based on the coordinates of each pad to be fanned out, calculating the number of pads in each sub-region, the pad density in each sub-region, and the global average pad density, and constructing a nonlinear programming model with the goal of balancing the pad density in the sub-regions; solving the nonlinear programming model to obtain the horizontal cutting lines and vertical dividing lines that maximize the balance of the pad density in each sub-region, thus completing the full allocation method. The process involves: local area segmentation; allocation of fan-out pads for each sub-region; the steps for allocating fan-out pads for each sub-region include: sorting the set of fan-out ubump pads A and the set of C4 pads B within each sub-region relative to the same origin using polar angles; establishing a constraint condition that the matching links between the fan-out ubump pads and C4 pads do not intersect based on computational geometry crossover experiments; constructing an integer programming model containing non-intersecting constraints and one-to-one matching constraints with the optimization objectives of minimizing trace length and the number of via crossings; solving the integer programming model to obtain the allocation result of C4 pads for the fan-out ubump pads.

[0010] As can be seen from the above scheme, the automatic allocation method for fan-out pads in chip packaging of the present invention, by constructing a nonlinear programming model with the optimization objective of balanced density of fan-out pads in sub-regions, can accurately solve for the optimal horizontal cutting line and vertical dividing line, achieving uniform division of the silicon adapter board area and avoiding excessive local pad density and signal link congestion. Simultaneously, through balanced partitioning, the upper limit of the signal fan-out trace distance is effectively constrained, avoiding signal loss and timing deviations caused by excessively long local links. Furthermore, within each partition, an integer programming model is used to optimize the automatic allocation of the C4 pad. The optimization objective is to prevent crossovers when fan-out traces are routed in a plane within this region, minimizing the overall trace length and the number of via crossings, thereby ensuring the overall quality of the fan-out link.

[0011] In a further scheme, the optimization objective of the nonlinear programming model is to minimize the deviation between the pad density of the sub-region and the global average pad density; the constraints of the horizontal cutting line and the vertical dividing line include that the horizontal cutting line and the vertical dividing line are monotonically increasing and located within the silicon adapter plate area.

[0012] In a further proposed solution, the nonlinear programming model is as follows: ;st , ;in, For the i-th horizontal cutting line, Let j be the j-th vertical dividing line. Let be the number of pads in sub-region (i,j). The width of the silicon interposer area. This refers to the height of the silicon interposer area. This represents the number of pads to be fanned out.

[0013] Therefore, by taking the minimum deviation between the pad density of the sub-region and the global average pad density as the optimization objective, and by setting the constraint that the horizontal cutting line and the vertical dividing line are monotonically increasing and located within the silicon interposer area, the optimal region segmentation result can be accurately obtained, and the uniform and balanced distribution of the pads to be fanned out in each sub-region can be achieved.

[0014] In a further scheme, the step of sorting the polar angles of the ubump pad set A to be fanned out in the sub-region and the C4 pad set B in the sub-region relative to the same origin includes: if there are points with the same polar angle in the ubump pad set A or the C4 pad set B to be fanned out, then the polar coordinate origin is translated by a random offset along the X-axis or Y-axis, the polar angle is recalculated, and the sorting is repeated.

[0015] Therefore, for each divided sub-region, if there are points with the same polar angle in set A or set B, the origin of the polar coordinates is shifted by a random offset along the X-axis or Y-axis, the polar angle is recalculated and sorted again. This can completely avoid the sorting chaos and matching logic errors caused by the same polar angle of the pad center point, and ensure that both types of pads can form an ordered and unique sorting sequence, avoiding cross-correlation conflicts caused by sorting abnormalities.

[0016] In a further scheme, the steps to establish the constraint that the matching links between the ubump pad to be fanned out and the C4 pad do not cross include: when any two matching line segments from the ubump pad to the C4 pad to the C4 pad meet the intersection condition, the matching of the same set of lines is prohibited from occurring at the same time, so that all matching links do not cross within the same plane routing layer.

[0017] In a further scheme, when any two matching line segments pointing from the ubump pad to the C4 pad satisfy the intersection condition, the intersection constraint is as follows: , Among them, line segments , The function for determining whether there is an intersection is: .

[0018] Therefore, when any two matching lines from the ubump pad to the C4 pad meet the intersection condition, the simultaneous occurrence of this set of matches is prohibited. This forces all matching links to be laid out without crossing within the same plane routing layer, which avoids signal trace crossing and short-circuit conflicts. This avoids cross-layer and routing conflicts that affect signal quality. There is no need to add additional routing layers or vias to avoid conflicts, which greatly saves packaging and routing process resources, reduces process costs and process complexity, and reduces signal loss and crosstalk risks caused by multi-layer routing and multiple vias, ensuring the quality of fan-out signal transmission.

[0019] In a further scheme, the constraints of the integer programming model include: each pad in the set A of ubump pads to be fanned out is matched once; each pad in the set B of C4 pads is matched at most once; the total number of matches is equal to the total number of ubump pads to be fanned out.

[0020] Therefore, by matching each pad in the set A of ubump pads to be fanned out once, and each pad in the set B of C4 pads to be matched at most once, and the total number of matches is equal to the total number of ubump pads to be fanned out, the uniqueness of the pad matching relationship can be guaranteed, and the crossover conflict of traces can be avoided.

[0021] In a further proposed approach, the objective function of the integer programming model is: ; where represents the ubump pad to be fanned out. Does it match C4 pad? Decision variables .

[0022] Therefore, by optimizing the objective function, the sum of the straight-line distances of all matched pad pairs can be minimized.

[0023] To achieve the second objective of the present invention, the present invention provides a computer device including a processor and a memory, the memory storing a computer program, which, when executed by the processor, implements the steps of the above-described chip package fan-out pad automatic allocation method.

[0024] To achieve the third objective of the present invention, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a controller, implements the steps of the above-described chip package fan-out pad automatic allocation method. Attached Figure Description

[0025] Figure 1 This is a flowchart of an embodiment of the chip packaging fan-out pad automatic allocation method of the present invention.

[0026] Figure 2 This is a flowchart illustrating the allocation of fan-out pads to be fanned out in each sub-region in an embodiment of the chip packaging fan-out pad automatic allocation method of the present invention.

[0027] Figure 3 This is a schematic diagram of the pad polar angle in an embodiment of the chip packaging fan-out pad automatic allocation method of the present invention.

[0028] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0029] Example of an automatic allocation method for fan-out pads in chip packaging: The automatic allocation method for fan-out pads in chip packages of the present invention is an application program in a computer device used to automatically allocate fan-out pads in chip packages.

[0030] like Figure 1 As shown, the automatic fan-out pad allocation method for chip packaging in this embodiment first executes step S1 to obtain the silicon interposer board size information and the coordinates of the pads to be fanned out. With the advanced package die placement completed, the position and orientation of each die determined, and the C4 pad freely assignable, the advanced package size is determined during the advanced package placement stage according to the package design requirements. The advanced package size information can be obtained through the GDS layout determined by the die placement, or through design exchange files (DEF), etc. Obtaining the package design size information includes: silicon interposer board size information, such as the width and height of the silicon interposer board; and the center coordinates of the pads to be fanned out.

[0031] After obtaining the silicon adapter board size information and the coordinates of the fan-out pads, step S2 is executed to set the partition grid parameters m and n, dividing the silicon adapter board area into m rows and n columns of sub-regions, and using horizontal cutting lines and vertical dividing lines as optimization decision variables. The partition grid parameters m and n can be determined according to the scale of the fan-out signals and the package size characteristics. For example, if the package is long and strip-shaped, then the number of columns is more than the number of rows. There are two purposes for partitioning: (1) the signals are fan-out in a limited area of ​​the sub-region to ensure the shortest integrated link path; (2) for large-scale integrated circuit scenarios, the scale of the subsequent mathematical model can be reduced, such as the difficulty of solving the large scale and the large computing power requirement. The silicon adapter board area is the area to be partitioned, which is generally the area of ​​the silicon adapter board or the distribution area of ​​the fan-out solder balls constrained by the process. W represents the width of the silicon adapter board area and H represents the height of the silicon adapter board area. When setting the optimization decision variables, set the horizontal cutting lines (m-1 lines): , Set vertical dividing lines (n-1 lines): , The summary decision variables are: , There are a total of m+n-2.

[0032] After setting the partition grid parameters m and n, execute step S3. Based on the coordinates of each pad to be fanned out, calculate the number of pads in each sub-region, the pad density in each sub-region, and the global average pad density, and construct a nonlinear programming model with the goal of balancing the pad density in the sub-regions.

[0033] The coordinates of each fan-out pad are set within the entire silicon interposer area. After the layout is determined in the previous stage of advanced packaging design, the coordinate positions of the fan-out pads on the chip are already determined. Assuming there are N fan-out signal pads (ubump / micro-bump), the coordinates of the fan-out pads are as follows: After setting the coordinates of each pad to be fanned out, the number of pads in each sub-region can be calculated. The number of pads is measured by whether the center point of the pad falls within the sub-region.

[0034] When calculating the pad density within each sub-region, it can be obtained from the number of pads in the sub-region and the area of ​​that sub-region. For example, the range of sub-region (i,j) is: Therefore, the area of ​​subregion (i,j) is obtained by the following formula: Number of pads in subregion (i,j): Therefore, the pad density of subregion (i,j) is obtained by the following formula: The global average pad density is calculated using the following formula: .

[0035] In this embodiment, the optimization objective of the nonlinear programming model is to minimize the deviation between the pad density of the sub-region and the global average pad density; the constraints for the horizontal cut lines and vertical dividing lines include that the horizontal cut lines and vertical dividing lines are monotonically increasing and located within the silicon interposer region. The nonlinear programming model is as follows: ; st , ; in, For the i-th horizontal cutting line, Let j be the j-th vertical dividing line. Let be the number of pads in sub-region (i,j). The width of the silicon interposer area. This refers to the height of the silicon interposer area. This represents the number of pads to be fanned out.

[0036] The optimization objective is to minimize the deviation between the pad density of the sub-region and the global average pad density. By setting constraints that the horizontal cutting line and the vertical dividing line are monotonically increasing and located within the silicon interposer area, the optimal region segmentation result can be accurately obtained, and the uniform and balanced distribution of the pads to be fanned out in each sub-region can be achieved.

[0037] After obtaining the nonlinear programming model, step S4 is executed to solve the nonlinear programming model, obtaining the horizontal cutting lines and vertical dividing lines that maximize the density of the fan-out pads in each sub-region, thus completing the global region segmentation. When solving the nonlinear programming model, a nonlinear programming solver can be called. Nonlinear programming solvers include commercial solvers such as Gurobi and CPlex, or free or open-source solvers such as SCIP. Solving nonlinear programming models is a well-known technique to those skilled in the art and will not be elaborated upon here. The horizontal dividing lines are obtained by solving the nonlinear programming model. and vertical dividing lines The density of fan-out pads in the sub-regions divided by these dividing lines is the most balanced, which can avoid congestion of the fan-out signal link.

[0038] After completing the global region segmentation, step S5 is executed to allocate the fan-out pads for each sub-region. After segmenting the silicon interposer region to obtain the optimal region segmentation, the fan-out pads for each sub-region are allocated. In this embodiment, see Figure 2 When allocating fan-out pads to each sub-region, step S51 is first executed. For each sub-region, the set of fan-out ubump pads A and the set of C4 pads B within that sub-region are sorted by polar angle relative to the same origin. Polar angle sorting is used to avoid cross-collisions between downward pad connection links caused by the allocation scheme. All fan-out ubump pad sets A within each sub-region are then sorted by polar angle. With the C4 pad set B in this sub-region Perform polar angle sorting. The number of C4 pads is greater than the number of ubump pads to be fanned out, therefore, n>m.

[0039] When performing polar angle sorting, see [link / reference]. Figure 3 First, select a point within the area as the origin. Among them, the origin Unlike the two types of pad center points, the polar angles of all points in set A and set B relative to the origin are calculated: the angle formed by the point, the origin, and the x-axis. After obtaining the polar angles of all points in set A and set B relative to the origin, they are sorted in ascending order of angle size, resulting in an ordered sequence of m+n points.

[0040] In this embodiment, the step of sorting the set of ubump pads A and the set of C4 pads B within the sub-region relative to the same origin by polar angle includes: if there are points with the same polar angle in either set of ubump pads A or set of C4 pads B, the origin of the polar coordinates is shifted by a random offset along the X-axis or Y-axis, the polar angle is recalculated, and the sorting is repeated. For each divided sub-region, if there are points with the same polar angle in set A or set B, the origin of the polar coordinates is shifted by a small random offset along the X-axis or Y-axis, the polar angle is recalculated, and the sorting is repeated. This completely avoids sorting chaos and matching logic errors caused by the same polar angle at the center point of the pads, ensuring that both types of pads can form an ordered and unique sorting sequence, and avoiding cross-correlation conflicts caused by abnormal sorting.

[0041] After polar angle sorting, step S52 is executed. Based on computational geometry crossover experiments, constraints are established to ensure that the matching links between the ubump pad to be fanned out and the C4 pad do not cross. To ensure link matching between the ubump pad to be fanned out and the C4 pad, constraints to prevent link crossing need to be set.

[0042] Based on the cross product experiment in computational geometry, the cross product function of planar vectors p and q is defined as follows: Define a directed area function: Therefore, line segment and The necessary and sufficient condition for them to intersect is: and .

[0043] Therefore, based on computational geometry crossover experiments, constraints can be set to ensure that the matching links between the ubump pad to be fanned out and the C4 pad do not cross. For example, assume there are two line segments. , ,in ;make , ;set up: , , , Then the necessary and sufficient condition for two line segments to intersect is: ; Define a function to determine whether line segments intersect: .

[0044] In this embodiment, the step of establishing the constraint condition that the matching links between the ubump pad to be fanned out and the C4 pad do not intersect includes: when any two matching line segments from the ubump pad to the C4 pad meet the intersection condition, then the simultaneous occurrence of this set of matches is prohibited, so that all matching links do not intersect within the same plane routing layer. Specifically, when two line segments , When they intersect, add constraints: The intersection constraints can be summarized as follows: , When any two matching lines from the ubump pad to the C4 pad meet the intersection condition, the simultaneous occurrence of this set of matches is prohibited. This forces all matching links to be laid out without intersection within the same plane routing layer, avoiding signal trace crossing and short-circuit conflicts. It eliminates the need to add additional routing layers or vias to avoid conflicts, significantly saving packaging and routing process resources, reducing process costs and complexity, and reducing signal loss and crosstalk risks caused by multi-layer routing and multiple vias, thus ensuring the quality of fan-out signal transmission.

[0045] After establishing the constraint that the matching links between the ubump pad to be fanned out and the C4 pad do not cross, step S53 is executed. With the optimization objectives of minimizing trace length and the number of via crossings, an integer programming model containing non-crossing constraints and one-to-one matching constraints is constructed. In this embodiment, the optimization objective function of the integer programming model is: ; where represents the ubump pad to be fanned out. Does it match C4 pad? Decision variables By optimizing the objective function, the sum of the straight-line distances of all matched pad pairs can be minimized.

[0046] In this embodiment, the constraints of the integer programming model include: each pad in the set A of ubump pads to be fanned out is matched once, as expressed in the following expression: Each pad in pad set B of C4 is matched at most once, and the expression is: The total number of matches equals the total number of ubump pads to be fanned out, expressed as: This ensures that each pad in the set A of ubump pads to be fanned out is matched once, and each pad in the set B of C4 pads is matched at most once. The total number of matches is equal to the total number of ubump pads to be fanned out, which guarantees the uniqueness of the pad matching relationship and avoids trace crossing conflicts.

[0047] After obtaining the integer programming model, step S54 is executed to solve the integer programming model, yielding the allocation result of the C4 pad for the ubump pad to be fanned out. When solving the integer programming model, commercial solvers such as Gurobi, CPlex, or the free and open-source solver SCIP can be used. Solving integer programming models is a well-known technique in the art and will not be elaborated further. By repeatedly performing polar angle sorting, non-crossing constraint construction, integer programming modeling, and solving steps (i.e., steps S51 to S54) on all sub-regions, the allocation of all fan-out pads is completed.

[0048] As described above, the automatic fan-out pad allocation method for chip packaging of the present invention, by constructing a nonlinear programming model with the optimization objective of balanced density of fan-out pads in sub-regions, can accurately solve for the optimal horizontal cutting line and vertical dividing line, achieving uniform division of the silicon adapter board area and avoiding excessive local pad density and signal link congestion. Simultaneously, through balanced partitioning, the upper limit of the signal fan-out trace distance is effectively constrained, avoiding signal loss and timing deviations caused by excessively long local links. Furthermore, within each partition, an integer programming model is used to optimize the automatic allocation of the C4 pad. The optimization objective is to prevent crossovers when fan-out traces are routed in a plane within this region, minimizing the overall trace length and the number of via crossings, thereby ensuring the overall quality of the fan-out link.

[0049] Computer device embodiment: The computer device in this embodiment includes a controller, which executes a computer program to implement the steps in the above-described embodiment of the automatic allocation method for fan-out pads in chip packaging.

[0050] For example, a computer program can be divided into one or more modules, one or more of which are stored in memory and executed by a controller to perform the present invention. One or more modules can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in a computer device.

[0051] A computer device may include, but is not limited to, a controller and memory. Those skilled in the art will understand that a computer device may include more or fewer components, or a combination of certain components, or different components; for example, a computer device may also include input / output devices, network access devices, buses, etc.

[0052] For example, a controller can be a Central Processing Unit (CPU), or other general-purpose controllers, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose controller can be a microcontroller or any conventional controller. The controller is the control center of a computer device, connecting all parts of the computer device through various interfaces and lines.

[0053] The memory can be used to store computer programs and / or modules. The controller implements various functions of the computer device by running or executing the computer programs and / or modules stored in the memory, and by accessing data stored in the memory. For example, the memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound receiving function, sound-to-text function, etc.), etc.; the data storage area may store data created based on the use of the mobile phone (such as audio data, text data, etc.). In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, RAM, plug-in hard disk, SmartMediaCard (SMC), Secure Digital (SD) card, FlashCard, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0054] Examples of computer-readable storage media: If the modules integrated into the computer device in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the above embodiments of the automatic fan-out pad allocation method for chip packages can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a controller, it can implement the steps of the above embodiments of the automatic fan-out pad allocation method for chip packages. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The storage medium can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content contained in computer-readable media may be appropriately added to or subtracted from the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media may not include electrical carrier signals and telecommunication signals.

[0055] It should be noted that the above are only preferred embodiments of the present invention, but the design concept of the invention is not limited thereto. Any non-substantial modifications made to the present invention using this concept also fall within the protection scope of the present invention.

Claims

1. A method for automatically allocating fan-out pads in a chip package, characterized in that: include: Obtain the dimensions of the silicon adapter board and the coordinates of the fan-out pads; Set the partition grid parameters m and n, divide the silicon adapter board area into m rows and n columns of sub-regions, and use the horizontal cutting line and the vertical dividing line as optimization decision variables; Based on the coordinates of each of the pads to be fanned out, the number of pads in each of the sub-regions, the pad density in each of the sub-regions, and the global average pad density are calculated, and a nonlinear programming model with the goal of balancing the pad density in the sub-regions is constructed. Solving the nonlinear programming model yields the horizontal cutting line and vertical dividing line that maximize the density of the fan-out pads in each sub-region, thus completing the global region segmentation. Assign fan-out pads to each of the sub-regions; The step of assigning fan-out pads to each of the sub-regions includes: For each sub-region, the set of ubump pads to be fanned out in the sub-region A and the set of C4 pads in the sub-region B are sorted by polar angle relative to the same origin; Based on computational geometry crossover experiments, a constraint condition is established that the matching links between the ubump pad to be fanned out and the C4 pad do not cross. With the optimization objectives of minimizing the routing length and the number of through-hole crossings, an integer programming model containing no cross-constraints and one-to-one matching constraints is constructed. Solve the integer programming model to obtain the allocation result of the C4 pad for the ubump pad to be fanned out.

2. The automatic allocation method for fan-out pads in chip packaging according to claim 1, characterized in that: The optimization objective of the nonlinear programming model is to minimize the deviation between the pad density of the sub-region and the global average pad density. The constraint conditions for the horizontal cutting line and the vertical dividing line include that the horizontal cutting line and the vertical dividing line are monotonically increasing and located within the area of ​​the silicon adapter plate.

3. The automatic allocation method for fan-out pads in chip packaging according to claim 2, characterized in that: The nonlinear programming model is as follows: ； s.t. , ; in, For the i-th horizontal cutting line, Let j be the j-th vertical dividing line. Let be the number of pads in sub-region (i,j). The width of the silicon interposer area. The height of the silicon interposer area. The number of pads to be fanned out.

4. The automatic allocation method for fan-out pads in chip packaging according to any one of claims 1 to 3, characterized in that: The steps for polar angle sorting of the set of ubump pads A to be fanned out in the sub-region and the set of C4 pads B in the sub-region relative to the same origin include: If there are points with the same polar angle in either the set of ubump pads to be fanned out (A) or the set of C4 pads (B), then the polar coordinate origin is shifted by a random offset along the X-axis or Y-axis, the polar angle is recalculated, and the pads are sorted again.

5. The automatic allocation method for fan-out pads in chip packaging according to any one of claims 1 to 3, characterized in that: The steps for establishing the constraint that the matching links between the ubump pad to be fanned out and the C4 pad do not cross include: When any two matching lines from the ubump pad to the C4 pad meet the intersection condition, the matching of the same pair is prohibited from occurring simultaneously, so that all matching links do not cross within the same plane routing layer.

6. The automatic allocation method for fan-out pads in chip packaging according to claim 5, characterized in that: When any two matching line segments pointing from the ubump pad to the C4 pad satisfy the intersection condition, the intersection constraint is as follows: ， ； Among them, line segment , The function for determining whether there is an intersection is: 。 7. The automatic allocation method for fan-out pads in chip packaging according to claim 6, characterized in that: The constraints of the integer programming model include: Each pad in the set A of ubump pads to be fanned out is matched once; Each pad in the C4 pad set B is matched at most once; The total number of matches is equal to the total number of ubump pads to be fanned out.

8. The automatic allocation method for fan-out pads in chip packaging according to claim 7, characterized in that: The objective function of the integer programming model is: ； Here, it represents the ubump pad to be fanned out. Does it match C4 pad? Decision variables .

9. A computer device comprising a processor and a memory, characterized in that: The memory stores a computer program that, when executed by the processor, implements the steps of the chip package fan-out pad automatic allocation method as described in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the controller, it implements the steps of the chip package fan-out pad automatic allocation method as described in any one of claims 1 to 8.

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