Graphics processor, instruction stream execution and generation method, electronic device and medium

Abstract

This application discloses a graphics processor, an instruction stream execution and generation method, an electronic device, and a medium. The graphics processor includes a thread bundle manager and an executor, wherein the executor includes a vector general-purpose register; the executor is configured to, when executing a target instruction stream pointed to by a target thread bundle, send a resource reclamation message to the thread bundle manager if a reclamation setting instruction is detected in the target instruction stream; wherein the reclamation setting instruction is used to instruct the reclamation of the vector general-purpose register allocated to the target thread bundle; the thread bundle manager is configured to, based on the received resource reclamation message, release the vector general-purpose register allocated to the target thread bundle. By implementing this application, the number of warps that a GPU can simultaneously launch and run can be increased, thereby improving the overall performance of the GPU.

Description

Technical Field

[0001] This application generally relates to the field of data processing technology. More specifically, this application relates to a graphics processor, an instruction stream execution and generation method, an electronic device, and a medium. Background Technology

[0002] The Vector General Purpose Register (vGPR) in a Graphics Processing Unit (GPU) serves as a high-speed storage unit. It stores the source and destination operands required when various instructions (e.g., data processing instructions, data loading instructions) pointed to by a warp are scheduled for execution, supporting tasks such as data processing and data loading. Therefore, the proper allocation of vGPR resources is crucial for ensuring GPU performance.

[0003] Currently, for kernel programs that include data processing and data loading tasks, the traditional vGPR resource allocation mechanism uses the maximum vGPR requirement of the data processing task as the standard to uniformly allocate resources to all warps under that kernel that undertake the task, ensuring that all warps are allocated the same number of vGPRs. However, for tasks such as data loading that do not require vGPRs during execution, this results in warps corresponding to these tasks occupying a large number of idle vGPRs, leading to resource waste, limiting the number of warps that the GPU can start and run simultaneously, and reducing the overall performance of the GPU.

[0004] In view of this, there is an urgent need to provide a graphics processor, instruction stream execution and generation method, electronic device and medium so that tasks that do not require vGPR during data loading and other execution processes do not occupy vGPR, thereby alleviating the pressure on vGPR in the GPU, increasing the number of warps that the GPU can start running at the same time, and improving the overall operating performance of the GPU. Summary of the Invention

[0005] In order to at least solve one or more of the technical problems mentioned above, this application proposes a graphics processor, an instruction stream execution and generation method, an electronic device, and a medium in several aspects.

[0006] In a first aspect, this application provides a graphics processor, including: a thread bundle manager and an executor, wherein the executor includes a vector general-purpose register; the executor is configured to, when executing a target instruction stream pointed to by a target thread bundle, if it is detected that the target instruction stream includes a set reclamation instruction, send a resource reclamation message to the thread bundle manager; wherein the set reclamation instruction is used to instruct the reclamation of the vector general-purpose register allocated to the target thread bundle; the thread bundle manager is configured to, based on the received resource reclamation message, release the vector general-purpose register allocated to the target thread bundle.

[0007] In some embodiments, the set reclamation instruction includes: a source operand, the source operand indicating the number of vector general-purpose registers that a single thread in the target thread bundle needs to release; the resource reclamation message carries the source operand, and the thread bundle manager releases the vector general-purpose registers allocated to the target thread bundle based on the source operand.

[0008] In some embodiments, the source operand is determined by the difference between the number of vector general-purpose registers allocated to a single thread in the target thread bundle and the actual number of vector general-purpose registers required.

[0009] In some embodiments, the executor further includes a scalar arithmetic logic unit pipeline and a vector operation unit pipeline; the executor is also configured to, when executing the target instruction stream pointed to by the target thread bundle, if it is detected that the target instruction stream includes a set scalar operation identifier, move the target instruction stream to the scalar arithmetic logic unit pipeline for execution.

[0010] In some embodiments, the graphics processor further includes: a thread bundle assembler; the thread bundle assembler, upon receiving a task execution signal, assembles threads to obtain multiple thread bundles; and sends a thread bundle runtime resource request to the thread bundle manager, the thread bundle runtime resource request carrying a vector general-purpose register configuration number, the vector general-purpose register configuration number being the number of vector general-purpose registers allocated to a single thread; the thread bundle manager is further configured to allocate vector general-purpose registers to each thread bundle based on the vector general-purpose register configuration number; wherein, the target thread bundle is one of multiple thread bundles.

[0011] In a second aspect, this application provides an instruction stream execution method applied to a graphics processor as described in the first aspect or any of the embodiments of the first aspect, the method comprising: executing a target instruction stream pointed to by a target thread bundle; and, if during execution it is detected that the target instruction stream includes a set reclamation instruction, releasing a vector general-purpose register allocated to the target thread bundle, wherein the set reclamation instruction is used to instruct the reclamation of the vector general-purpose register allocated to the target thread bundle.

[0012] In some embodiments, the set reclamation instruction includes: a source operand, the source operand being used to indicate the number of vector general-purpose registers that a single thread in the target thread bundle needs to release; releasing the vector general-purpose registers allocated to the target thread bundle includes: releasing the vector general-purpose registers allocated to the target thread bundle based on the source operand.

[0013] In some embodiments, the source operand is determined by the difference between the number of vector general-purpose registers allocated to a single thread in the target thread bundle and the actual number of vector general-purpose registers required.

[0014] In some embodiments, the graphics processor includes a scalar arithmetic logic unit pipeline and a vector arithmetic logic unit pipeline; the method further includes: if, during execution, it is detected that the target instruction stream includes a set scalar operation identifier, moving the target instruction stream to the scalar arithmetic logic unit pipeline for execution.

[0015] In some embodiments, before executing the target instruction stream in the target thread bundle, the method further includes: assembling threads to obtain multiple thread bundles after receiving a task execution signal; allocating vector general-purpose registers to each thread bundle based on the number of vector general-purpose registers configured; wherein the number of vector general-purpose registers configured is the number of vector general-purpose registers allocated to a single thread; and the target thread bundle is one of the multiple thread bundles.

[0016] In a third aspect, this application provides a method for generating instruction streams for a graphics processor, comprising: parsing a target task to obtain a vector general-purpose register configuration number and multiple instruction streams, wherein the vector general-purpose register configuration number is determined by the maximum vector general-purpose register requirement of a single thread in the target task; and identifying the multiple instruction streams obtained from the parsing, wherein if it is detected that when any instruction stream is executed, the actual number of vector general-purpose registers required by the single thread executing it is less than the vector general-purpose register configuration number, a set reclamation instruction is inserted at the front end of the instruction stream; wherein the set reclamation instruction is used to instruct the graphics processor to reclaim the allocated vector general-purpose registers when executing the instruction stream.

[0017] In some embodiments, the set reclamation instruction includes: a source operand, the source operand being used to indicate the number of vector general-purpose registers that need to be released; wherein the source operand is determined based on the difference between the configured number of vector general-purpose registers and the actual number of vector general-purpose registers required by a single thread.

[0018] In some embodiments, the method further includes: when identifying multiple instruction streams obtained from parsing, if an instruction stream is identified as a scalar operation instruction stream, then setting the scalar operation identifier in the identified scalar operation instruction stream to a set scalar operation identifier.

[0019] In a fourth aspect, this application provides an electronic device including a graphics processor as described in the first aspect or any of the embodiments of the first aspect.

[0020] In a fifth aspect, this application provides a computer-readable storage medium, which is a non-volatile or non-transient storage medium, storing a computer program thereon. When a processor runs the computer program, it performs the steps of the instruction stream execution method described in the second aspect or any of the embodiments of the second aspect, or performs the steps of the instruction stream generation method for a graphics processor described in the third aspect or any of the embodiments of the third aspect.

[0021] Based on the graphics processor, instruction stream execution and generation method, electronic device, and medium provided above, the image processor in this embodiment includes a thread bundle manager and an executor. By adding a dedicated set-reclaim instruction, the executor and thread bundle manager are linked (i.e., when the executor executes the target instruction stream pointed to by the target thread bundle, if it detects that the target instruction stream includes a set-reclaim instruction, it sends a resource reclamation message to the thread bundle manager; after receiving the resource reclamation message, the thread bundle manager releases the vector general-purpose registers allocated to the target thread bundle). For tasks that do not require vGPR during execution, such as data loading, and matrix operation tasks with low demand for vector registers, idle vector general-purpose registers (all or part of the vector general-purpose registers) can be dynamically reclaimed during the thread bundle operation. Execution can then be performed using only scalar general-purpose registers or a small portion of the vector general-purpose registers, so that the reclaimed vector general-purpose registers can be allocated to other thread bundles to execute instructions, relieving the pressure on vGPR in the GPU, increasing the number of warps that the GPU can start running simultaneously, and improving the overall GPU performance. Attached Figure Description

[0022] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, and the same or corresponding reference numerals denote the same or corresponding parts, wherein:

[0023] Figure 1 An exemplary structural block diagram of a graphics processor according to some embodiments of this application is shown; Figure 2An exemplary flowchart of an instruction stream execution method according to some embodiments of this application is shown; Figure 3 An exemplary flowchart of an instruction stream generation method for a graphics processor according to some embodiments of this application is shown; Figure 4 An exemplary structural block diagram of a data processing apparatus according to some embodiments of this application is shown; Figure 5 An exemplary structural block diagram of a data processing system according to some embodiments of this application is shown; Figure 6 An exemplary structural block diagram of an electronic device according to some embodiments of this application is shown. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] It should be understood that the terms "comprising" and "including" used in the specification and claims of this application indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0026] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this specification and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0027] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0028] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0029] Exemplary application scenarios Graphics Processing Units (GPUs), as hardware in electronic devices specifically designed for handling graphics-related computations, rely on multi-threaded parallelism to complete tasks such as graphics rendering and matrix operations. Their parallel computing capabilities enable high-quality real-time graphics computing, driving the rapid development of fields such as Virtual Reality (VR), Augmented Reality (AR), scientific computing, machine learning, and deep learning. However, with the diversification of GPU applications and the exponential growth of computing demands, GPU performance faces many challenges. Therefore, optimizing GPUs to meet the ever-increasing demands for high-performance computing has become a key focus.

[0030] The Vector General Purpose Register (vGPR), a crucial runtime resource in the GPU, serves as a high-speed storage unit. It stores the source and destination operands required for the scheduled execution of various instructions (e.g., data processing instructions, data loading instructions) pointed to by a warp, supporting tasks such as data processing and data loading. Therefore, the capacity of the vGPR directly impacts GPU performance, and the proper allocation of vGPR resources is key to ensuring optimal GPU performance.

[0031] Currently, matrix operator execution typically involves two types of tasks: data loading and data computation. Data loading refers to loading the matrices required for matrix computation from external memory to the GPU's shared memory using the Tensor Memory Accelerator (TMA) module. This only requires specifying the descriptor of the matrix to be loaded, the global memory address, the starting address of the shared memory, and necessary parameters. This information is all scalar, primarily consuming the GPU's Scalar General-Purpose Register (sGPR) resources, with very low or even zero demand on vGPR. Data computation, on the other hand, utilizes the TensorCore to execute matrix multiply-accumulate (MMA) instructions. This process consumes significant vGPR resources to store the matrices to be computed and the computation results.

[0032] For kernel programs that simultaneously include data processing and data loading tasks, the traditional vGPR resource allocation mechanism uses the maximum vGPR requirement of the data processing task as the standard to uniformly allocate resources to all warps undertaking that task within the kernel, ensuring that all warps are allocated the same number of vGPRs. However, for tasks such as data loading that do not require vGPR resources during execution, this results in warps corresponding to these tasks occupying a large number of idle vGPRs, leading to resource waste, limiting the number of warps that the GPU can launch and run simultaneously, and reducing the overall performance of the GPU.

[0033] In view of this, there is an urgent need to provide a graphics processor, instruction stream execution and generation method, electronic device and medium so that tasks that do not require vGPR during data loading and other execution processes do not occupy vGPR, thereby alleviating the pressure on vGPR in the GPU, increasing the number of warps that the GPU can start running at the same time, and improving the overall operating performance of the GPU.

[0034] Figure 1 An exemplary structural block diagram of a graphics processor according to some embodiments of this application is shown.

[0035] like Figure 1 As shown, the graphics processor includes a thread bundle assembler 101, a thread bundle manager 102, and an executor 103. The thread bundle manager 102 is communicatively connected to both the thread bundle assembler 101 and the executor 103. The thread bundle assembler 101 is used to assemble threads to obtain multiple thread bundles. The following embodiments provide a detailed description of the thread bundle assembler 101, which will not be repeated here.

[0036] The thread bundle manager 102 is used to allocate and reclaim resources for the thread bundles assembled by the thread bundle assembler 101.

[0037] The executor 103 includes a vector general-purpose register, a scalar general-purpose register, a vector arithmetic logic unit (VALU) pipeline, and a vector arithmetic logic unit (SALU) pipeline, for executing instruction streams.

[0038] The vector general-purpose register is a hardware module inside the GPU used to store the source and destination operands required when various instructions (such as data operation instructions and data loading instructions) pointed to by a thread bundle are scheduled for execution. The scalar general-purpose register is also a storage unit of the graphics processor, used to store shared control information and common data, such as the program counter, loop iteration count, address, and constants. The scalar arithmetic logic unit pipeline is a dedicated hardware pipeline inside the GPU for performing scalar operations. Scalar operations are single-data operations with small data volumes and simple logic. The vector arithmetic logic unit pipeline is a dedicated hardware pipeline inside the GPU for performing vector operations, corresponding to multi-data parallel operations, and is a core computing resource of the GPU.

[0039] The following is a detailed description of the graphics processor's executor 103 and thread bundle manager 102: Specifically, the executor 103 is configured to send a resource reclamation message to the thread bundle manager 102 when it detects that the target instruction stream includes a set reclamation instruction while executing the target instruction stream pointed to by the target thread bundle; wherein the set reclamation instruction is used to instruct the reclamation of the vector general-purpose registers allocated to the target thread bundle; the thread bundle manager 102 is configured to release the vector general-purpose registers allocated to the target thread bundle based on the received resource reclamation message.

[0040] In this embodiment, each thread bundle is assigned an independent vGPR. The aforementioned thread bundle manager 102 is a hardware structure in the GPU responsible for managing thread bundles, which can allocate runtime resources to each thread bundle and release the vector general-purpose registers allocated to the thread bundle.

[0041] The aforementioned executor 103 refers to the hardware module in the GPU that actually executes instructions, capable of decoding and performing operations such as calculations on various instructions. In this embodiment, the executor 103 is communicatively connected to the thread bundle manager 102.

[0042] The aforementioned target thread bundle refers to a thread bundle currently being scheduled and executed by executor 103. In this embodiment, a thread bundle is the basic unit of GPU parallel scheduling and execution, and it consists of multiple threads. The aforementioned target instruction stream refers to a sequence of instructions that the target thread bundle needs to execute.

[0043] It is understood that the number of threads included in each thread bundle is fixed, for example, 32. Of course, the above example of 32 is merely an example and is not intended to limit this application.

[0044] In this embodiment, when the executor 103 loads and executes the target instruction stream pointed to by the target thread bundle, it decodes, identifies, and executes each instruction in the target instruction stream. If, during the identification process, the target instruction stream is found to include a set-reclaim instruction (e.g., the first instruction in the target instruction stream is a set-reclaim instruction), a resource reclamation message is sent to the thread bundle manager 102. This resource reclamation message is hardware interaction information generated by the executor 103, used to instruct the thread bundle manager 102 to release the vector general-purpose registers allocated to the target thread bundle.

[0045] The aforementioned set-reclaim instruction is a predefined, dedicated control instruction that can be executed by the executor 103, used to instruct the reclaiming of the vector general-purpose registers allocated to the target thread bundle. As a specific embodiment of this application, the aforementioned set-reclaim instruction can be denoted as INC_VGPR.

[0046] In this embodiment, after receiving a resource reclamation message, the thread bundle manager 102 releases the vector general-purpose registers allocated to the target thread bundle based on the resource reclamation message. Specifically, all vector general-purpose registers allocated to the target thread bundle can be released, or only a portion of the vector general-purpose registers allocated to the target thread bundle can be released; this embodiment does not impose specific limitations on this.

[0047] As a specific implementation of this application, after receiving the resource reclamation message, the thread bundle manager 102 directly releases all the vector general-purpose registers allocated to the target thread bundle. This can be applied to data loading tasks that do not require vector general-purpose registers, alleviate the pressure on vGPR in the GPU, and improve the overall operating performance of the GPU.

[0048] For some matrix operation tasks, the required vector general-purpose registers are few. Based on this, the vector general-purpose registers allocated to the threads executing such matrix operation tasks can be released to further alleviate the pressure on vGPR in the GPU and improve the overall performance of the GPU.

[0049] As another specific embodiment of this application, the above-mentioned setting recycling instruction includes: a source operand, which indicates the number of vector general-purpose registers that a single thread in the target thread bundle needs to release; a resource recycling message carrying the source operand, and the thread bundle manager 102 releasing the vector general-purpose registers allocated to the target thread bundle based on the source operand.

[0050] For example, the aforementioned source operand is a parameter field embedded in the set reclamation instruction, and is a component of the set reclamation instruction. It is used to indicate the number of vector general-purpose registers that a single thread in the target thread bundle needs to release, providing a quantitative basis for resource reclamation. Here, the aforementioned single thread is the smallest unit of the thread bundle, and each thread independently uses its allocated vector general-purpose registers.

[0051] As a specific implementation of this application, the above-mentioned set reclamation instruction can be INC_VGPR void, sr0. Here, sr0 is the 0th scalar general-purpose register, representing the aforementioned source operand.

[0052] In this embodiment, the aforementioned source operand is determined by the difference between the number of vector general-purpose registers allocated to a single thread in the target thread bundle (denoted as cs_vgpr_num) and the actual number of vector general-purpose registers required (denoted as vgpr_needed). Specifically, it can be determined and written by the data processing device (such as a central processing unit (CPU)) that issues tasks to the GPU (see the description of the following embodiments for specific methods, which will not be repeated here). The executor 103 in this embodiment can directly read the set recycling instruction upon recognizing it. The number of vector general-purpose registers allocated to each thread is a predefined fixed value, and the actual number of vector general-purpose registers required by each thread is obtained by the CPU parsing the program package of the task corresponding to the target instruction stream.

[0053] Based on this, the resource reclamation message carries the source operand, and the thread bundle manager 102 releases the vector general-purpose registers allocated to the target thread bundle based on the source operand. That is, each thread in the target thread bundle releases the vector general-purpose registers of the source operand (i.e., releases a portion of the vector general-purpose registers). The total number of vector general-purpose registers that need to be released in the target thread bundle is the product of the source operand and the number of threads in the target thread bundle.

[0054] Of course, the above resource reclamation message also carries a thread bundle identifier (ID). After receiving the resource reclamation message, the thread bundle manager 102 releases the vector general-purpose registers allocated to the thread bundle ID according to the thread bundle ID in the resource reclamation message. The number of registers released is determined according to the source operand.

[0055] It is understandable that when releasing some vector general-purpose registers, the release can start from the high address of the vector general-purpose registers allocated to the target thread bundle, while retaining the vector general-purpose registers at lower addresses.

[0056] In this embodiment of the application, when releasing vector general-purpose registers, only a portion of the vector general-purpose registers are released based on the source operands in the set reclamation instruction. This can adapt to matrix operation tasks with low requirements for vector general-purpose registers, further reduce the pressure on vGPR in the GPU, and improve the overall operating performance of the GPU.

[0057] In this embodiment of the application, after the executor 103 finishes executing the target instruction stream, the executor 103 can also send a release signal to the thread bundle manager 102 so that the thread bundle manager 102 can reclaim the remaining vector general-purpose registers based on the release signal, so that the released vector general-purpose registers are in the allocated state.

[0058] The image processor in this embodiment includes a thread bundle manager 102 and an executor 103. By adding a dedicated set-reclaim instruction, the executor 103 and the thread bundle manager 102 are linked (i.e., when the executor 103 is executing the target instruction stream pointed to by the target thread bundle, if it detects that the target instruction stream includes a set-reclaim instruction, it sends a resource reclamation message to the thread bundle manager 102. After receiving the resource reclamation message, the thread bundle manager 102 releases the vector general-purpose registers allocated to the target thread bundle). For tasks that do not require vGPR during execution, such as data loading, and matrix operation tasks with low requirements for vector registers, idle vector general-purpose registers (all or part of the vector general-purpose registers) can be dynamically reclaimed during the thread bundle operation. Execution can then be performed using only scalar general-purpose registers or a small portion of vector general-purpose registers, so that the reclaimed vector general-purpose registers can be allocated to other thread bundles to execute instructions, relieving the pressure on vGPR in the GPU, increasing the number of warps that the GPU can start running simultaneously, and improving the overall performance of the GPU.

[0059] The solutions in this application can be widely applied to GPU usage scenarios (e.g., graphics rendering, matrix calculation, scientific computing, etc.), and can fully and effectively utilize the vGPR resources of the GPU to improve the overall operating performance of the GPU.

[0060] As an optional embodiment of this application, the executor 103 is further configured to, when executing the target instruction stream pointed to by the target thread bundle, if it is identified that the target instruction stream includes a scalar operation identifier, move the target instruction stream to the scalar arithmetic logic unit pipeline for execution.

[0061] For example, the aforementioned scalar operation identifier is a preset identification field that can be embedded in the scalar operation instruction stream as an identification mark for the executor 103 to distinguish between scalar instructions and non-scalar instructions.

[0062] As a specific implementation of this application, the above-mentioned scalar operation identifier can be assigned the values ​​"1" and "0", where "1" represents scalar operation (i.e., the above-mentioned set scalar operation identifier); "0" represents non-scalar operation.

[0063] In this embodiment of the application, when the executor 103 executes the target instruction stream pointed to by the target thread bundle, if it detects that the target instruction stream includes a scalar operation identifier (i.e., "1"), it moves the target instruction stream to the scalar arithmetic logic unit pipeline for execution.

[0064] This application embodiment sets a scalar operation identifier, so that after the executor 103 recognizes the set scalar operation identifier, it moves the target instruction stream to the scalar arithmetic logic unit pipeline for execution, thereby improving the execution efficiency of scalar operations, reducing the load on the vector pipeline, and optimizing the overall instruction execution efficiency and hardware division of labor of the GPU.

[0065] As an optional embodiment of this application, after receiving the task execution signal, the thread bundle assembler 101 assembles the threads to obtain multiple thread bundles; and sends a thread bundle runtime resource request to the thread bundle manager 102. The thread bundle runtime resource request carries the number of vector general-purpose registers configured, which is the number of vector general-purpose registers allocated to a single thread; the thread bundle manager 102 is also used to allocate vector general-purpose registers to each thread bundle based on the number of vector general-purpose registers configured; wherein, the target thread bundle is one of the multiple thread bundles.

[0066] For example, the thread bundle assembler 101 described above is a hardware module of the GPU front end, located upstream of the thread bundle manager 102, and communicating with the thread bundle manager 102. It is responsible for decomposing and assembling tasks submitted by the software layer (e.g., the CPU) into thread bundles that the GPU can schedule and execute.

[0067] In this embodiment of the application, the task execution signal is a task start signal ordered by the data processing device, which triggers the GPU's thread bundle assembler 101 to work.

[0068] In this embodiment, after receiving a task execution signal, the thread bundle assembler 101 initiates a thread processing flow, that is, assembles the threads to obtain multiple thread bundles. As a specific implementation of this application, the threads are assembled according to a set size (e.g., 32) to obtain multiple thread bundles. It should be noted that the aforementioned task execution signal may carry the set size.

[0069] For example, the above-mentioned thread bundle runtime resource request is a hardware resource request message sent by the thread bundle assembler 101 to the thread bundle manager 102, used to request runtime resources for the assembled thread bundle. The runtime resources here may include, but are not limited to, vector general-purpose registers.

[0070] In this embodiment, the thread bundle runtime resource request carries the vector general-purpose register configuration number. Here, the vector general-purpose register configuration number is a globally unified configuration parameter, representing the number of vector general-purpose registers allocated to a single thread.

[0071] In this embodiment of the application, after the thread bundle assembler 101 assembles the thread bundle, it sends a thread bundle runtime resource request to the thread bundle manager 102. The thread bundle manager 102 allocates a vector general-purpose register to each thread bundle based on the number of vector general-purpose registers configured. Specifically, the number of vector general-purpose registers is the product of the number of vector general-purpose registers configured and the number of threads in each thread bundle.

[0072] It should be noted that the target thread bundle mentioned above is one of multiple thread bundles.

[0073] This application embodiment introduces a thread bundle assembler 101 and a resource request, realizing a complete hardware link from thread assembly to resource request to register allocation to instruction execution to dynamic resource reclamation, and realizing closed-loop control from task issuance to execution and resource management.

[0074] Figure 2 An exemplary flowchart of an instruction stream execution method 200 according to some embodiments of this application is shown.

[0075] like Figure 2 As shown, the above instruction stream execution method 200 is applied to the above graphics processor. The above instruction stream execution method 200 includes: step S210: executing the target instruction stream pointed to by the target thread bundle; step S220: if a set reclamation instruction is detected in the target instruction stream during execution, the vector general-purpose registers allocated to the target thread bundle are released, wherein the set reclamation instruction is used to instruct the reclamation of the vector general-purpose registers allocated to the target thread bundle.

[0076] As an optional embodiment of this application, the above-mentioned setting recycling instruction includes: a source operand, which indicates the number of vector general-purpose registers that a single thread in the target thread bundle needs to release; releasing the vector general-purpose registers allocated to the target thread bundle includes: releasing the vector general-purpose registers allocated to the target thread bundle based on the source operand.

[0077] As an optional embodiment of this application, the source operand is determined by the difference between the number of vector general-purpose registers allocated to a single thread in the target thread bundle and the actual number of vector general-purpose registers required.

[0078] As an optional embodiment of this application, the graphics processor includes a scalar arithmetic logic unit pipeline and a vector arithmetic logic unit pipeline; the method further includes: if during execution, if the target instruction stream is identified to include a set scalar operation identifier, the target instruction stream is moved to the scalar arithmetic logic unit pipeline for execution.

[0079] As an optional embodiment of this application, before executing the target instruction stream in the target thread bundle, the instruction stream execution method 200 further includes: after receiving the task execution signal, assembling the threads to obtain multiple thread bundles; allocating vector general-purpose registers to each thread bundle based on the number of vector general-purpose registers configured; wherein, the number of vector general-purpose registers configured is the number of vector general-purpose registers allocated to a single thread; and the target thread bundle is one of the multiple thread bundles.

[0080] For details on the specific implementation methods and beneficial effects, please refer to the description of the graphics processor above, which will not be repeated here.

[0081] Figure 3 An exemplary flowchart of an instruction stream generation method 300 for a graphics processor according to some embodiments of this application is shown.

[0082] like Figure 3 As shown, the above-mentioned instruction stream generation method 300 for a graphics processor includes: step S310: parsing the target task to obtain the number of vector general-purpose registers configured and multiple instruction streams, wherein the number of vector general-purpose registers configured is determined by the maximum number of vector general-purpose registers required by a single thread in the target task; step S320: identifying the multiple instruction streams obtained from the parsing, and if it is detected that when any instruction stream is executed, the number of vector general-purpose registers actually required by a single thread executing it is less than the number of vector general-purpose registers configured, inserting a set reclamation instruction at the beginning of the instruction stream; wherein the set reclamation instruction is used to instruct the graphics processor to reclaim the allocated vector general-purpose registers when executing the instruction stream.

[0083] For example, in step S310 above, the target task refers to the task to be sent to the GPU for graphics processing. In this embodiment of the application, the target task can be a program package (e.g., C language, C++ language, etc.) defined by the developers, denoted as the kernel program.

[0084] In this embodiment, the data processing device includes a compilation unit and a driver unit. The compilation unit is a software tool within the data processing device that translates source code written in a high-level programming language (i.e., the aforementioned target task) into machine code executable by the computer hardware. The driver unit is also a software tool within the data processing device, running within the device's operating system and serving as a communication tool between the software and hardware.

[0085] In this embodiment, the compilation unit in the aforementioned data processing device parses the code, logic, and resource requirements of the target task to obtain multiple instruction streams and the number of vector general-purpose registers configured. The number of vector general-purpose registers configured here can be the maximum number of vector general-purpose registers required by a single thread in the target task, or it can be the sum of the maximum number of vector general-purpose registers required by a single thread in the target task and a set value (e.g., 5). This embodiment does not impose a specific limitation on this, and it can be determined according to the actual situation. In this embodiment, the number of vector general-purpose registers configured can be used as a global configuration standard for vector general-purpose registers.

[0086] In this embodiment, after parsing multiple instruction streams, each instruction stream is identified. If an instruction stream is identified as including a TMA descriptor, a TMA load instruction, and a small amount of address calculation, but not an MMA instruction, a set-reclaim instruction is inserted at the beginning of the instruction stream. Thus, when the instruction stream is executed by the GPU's executor, the presence of the set-reclaim instruction at the beginning allows the GPU to reclaim the allocated vector general-purpose registers based on this instruction, enabling the GPU to launch more warps into the execution state and achieve high-concurrency execution of thread bundles.

[0087] It is understandable that when an instruction stream includes a TMA descriptor, a TMA load instruction, and a small number of address calculations, but does not contain MMA instructions, the actual number of vector general-purpose registers required by a single thread executing it (i.e., vgpr_needed) is less than the number of vector general-purpose registers configured (i.e., cs_vgpr_num).

[0088] In this embodiment, after compiling the instruction stream, the compilation unit sends the configuration quantity of the vector general-purpose registers and the compiled instruction stream to the driver unit through the compilation unit-driver unit interface. The driver unit then writes the compiled instruction stream and the configuration quantity of the vector general-purpose registers into the graphics processor and sends a task execution signal to the graphics processor.

[0089] This application uses the maximum register requirement of a thread as the global allocation standard, which can ensure that the thread has enough registers available during peak task periods, avoiding abnormal operation due to insufficient resources. Furthermore, when it is found that the number of vector general-purpose registers actually required by a single thread is less than the number of vector general-purpose registers configured, a reclamation instruction is inserted at the front end of the instruction stream, so that the GPU reclaims the allocated idle vector general-purpose registers when executing the instruction stream, thereby relieving the pressure on vGPR in the GPU, increasing the number of warps that the GPU can start running simultaneously, and improving the overall operating performance of the GPU.

[0090] As an optional embodiment of this application, the above-mentioned set reclamation instruction includes: a source operand, which indicates the number of vector general-purpose registers that need to be released; wherein, the source operand is determined based on the difference between the number of vector general-purpose registers configured and the number of vector general-purpose registers actually required by a single thread.

[0091] In this embodiment, the definition and calculation method of the source operand can be found in the description of the above embodiment, and will not be repeated here.

[0092] It should be noted that after the compilation unit in the above data processing device obtains the number of vector general-purpose registers configured and the number of vector general-purpose registers actually required by a single thread, it can directly calculate the difference between the two to obtain sr0, that is, sr0 = cs_vgpr_num – vgpr_neede.

[0093] As an optional embodiment of this application, the above-described instruction stream generation method 300 for a graphics processor further includes: when identifying multiple instruction streams obtained from parsing, if an instruction stream is identified as a scalar operation instruction stream, then the scalar operation identifier in the identified scalar operation instruction stream is set to a set scalar operation identifier.

[0094] For example, the embodiments of this application further adjust the instruction set. Specifically, a 1-bit scalar operation identifier is added to pure scalar operation instructions such as arithmetic logic unit (ALU) operation instructions or data storage instructions.

[0095] Specifically, when the compiler identifies multiple instruction streams obtained from parsing, if it identifies an instruction stream as a scalar operation instruction stream, it sets the scalar operation identifier in the identified scalar operation instruction stream to the set scalar operation identifier (i.e., "1").

[0096] In this way, when the GPU executor executes the instruction, it recognizes the scalar operator and moves the thread executing the instruction to the scalar arithmetic logic unit pipeline for execution, without affecting the execution of the vector arithmetic logic unit pipeline.

[0097] The above embodiments describe a handling scheme for the differentiated vGPR requirements when both data processing tasks and data loading tasks are included within the same kernel. It is understood that the schemes in this application are also applicable to cross-kernel tasks. For example, for a pure data loading kernel (denoted as kernel0), kernel0 only contains TMA loading logic; the compilation unit of the data processing device configures cs_crf_num to 0; when the GPU's thread bundle manager allocates vGPR resources for the number of threads, since cs_crf_num is 0, vGPR is not allocated directly. For a data processing kernel (denoted as kernel1), kernel1 only contains MMA logic; the compilation unit of the data processing device configures cs_crf_num to the maximum value required by kernel1, and does not release vector general-purpose registers or releases only a small number of vector general-purpose registers during the execution phase.

[0098] Figure 4 An exemplary structural block diagram of a data processing apparatus 400 according to some embodiments of this application is shown. It will be understood that the data processing apparatus 400 described above is a central processing unit (CPU) of an electronic device.

[0099] like Figure 4 As shown, the data processing apparatus 400 described above is used to generate the instruction stream of the graphics processor in the above embodiment. The data processing apparatus 400 includes: a compilation unit 410; the compilation unit 410 is configured to execute the instruction stream generation method 300 of the graphics processor as described in the above embodiment; and a number of send vector general-purpose registers configured and a compiled instruction stream.

[0100] As an optional embodiment of this application, the data processing device further includes: a driving unit; the driving unit is configured to, after receiving vector general-purpose register configuration data and compiled instruction stream, write the compiled instruction stream and vector general-purpose register configuration quantity into the graphics processor, and send a task execution signal to the graphics processor.

[0101] For details on the specific implementation methods and beneficial effects, please refer to the description of the instruction stream generation method 300 for a graphics processor in the above embodiments, which will not be repeated here.

[0102] Correspondingly, embodiments of this application also provide a data processing system 500. For example... Figure 5 As shown, the data processing system 500 includes the data processing device 400 and the graphics processor 520.

[0103] Correspondingly, embodiments of this application also provide hardware structure diagrams, specifically as follows: Figure 6As shown, the electronic device 600 can be a device that implements the above-described instruction stream execution method 200 or the instruction stream generation method 300 for a graphics processor. For example... Figure 6 As shown in A, the electronic device 600 includes: a graphics processor 520. Alternatively, as... Figure 6 As shown in B, the electronic device 600 includes a graphics processing system 620.

[0104] Correspondingly, embodiments of the present invention also provide a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored. When the computer program is run by a processor, it executes the steps of the aforementioned instruction stream execution method 200 or the instruction stream generation method 300 for a graphics processor.

[0105] While numerous embodiments of this application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will arise for those skilled in the art without departing from the spirit and intent of this application. It should be understood that various alternatives to the embodiments of this application described herein may be employed in the practice of this application. The appended claims are intended to define the scope of protection of this application and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A graphics processor, comprising: include: A thread bundle manager and an executor, wherein the executor includes a vector general-purpose register; The executor is configured to send a resource reclamation message to the thread bundle manager when it detects that the target instruction stream pointed to by the target thread bundle includes a set reclamation instruction; wherein the set reclamation instruction is used to instruct the reclamation of the vector general-purpose registers allocated to the target thread bundle. The thread bundle manager is configured to release the vector general-purpose registers allocated to the target thread bundle based on the received resource reclamation message.

2. The graphics processor of claim 1, wherein, The set reclamation instruction includes: a source operand, which indicates the number of vector general-purpose registers that a single thread in the target thread bundle needs to release; the resource reclamation message carries the source operand, and the thread bundle manager releases the vector general-purpose registers allocated to the target thread bundle based on the source operand.

3. The graphics processor of claim 2, wherein, The source operand is determined by the difference between the number of vector general-purpose registers allocated to a single thread in the target thread bundle and the actual number of vector general-purpose registers required.

4. The graphics processor according to claim 1, characterized in that, The executor further includes a scalar arithmetic logic unit pipeline and a vector operation unit pipeline; the executor is also used to move the target instruction stream to the scalar arithmetic logic unit pipeline for execution if it is detected that the target instruction stream includes a set scalar operation identifier when executing the target instruction stream pointed to by the target thread bundle.

5. The graphics processor according to any one of claims 1-4, characterized in that, The graphics processor further includes: a thread bundle assembler; Upon receiving a task execution signal, the thread bundle assembler assembles the threads to obtain multiple thread bundles; and Send a thread bundle runtime resource request to the thread bundle manager. The thread bundle runtime resource request carries the number of vector general-purpose registers configured, which is the number of vector general-purpose registers allocated to a single thread. The thread bundle manager is also used to allocate a vector general-purpose register to each thread bundle based on the number of vector general-purpose registers configured; wherein the target thread bundle is one of a plurality of thread bundles.

6. An instruction stream execution method, characterized in that, The method is applied to a graphics processor as described in any one of claims 1-5, and the method includes: Execute the target instruction stream pointed to by the target thread bundle; If a set reclamation instruction is detected in the target instruction stream during execution, the vector general-purpose registers allocated to the target thread bundle are released, wherein the set reclamation instruction is used to instruct the reclamation of the vector general-purpose registers allocated to the target thread bundle.

7. The method according to claim 6, characterized in that, The set reclamation instruction includes: a source operand, which indicates the number of vector general-purpose registers that a single thread in the target thread bundle needs to release; Releasing the vector general-purpose registers allocated to the target thread bundle includes: Release the vector general-purpose register allocated to the target thread bundle based on the source operand.

8. The method according to claim 7, characterized in that, The source operand is determined by the difference between the number of vector general-purpose registers allocated to a single thread in the target thread bundle and the actual number of vector general-purpose registers required.

9. The method according to claim 6, characterized in that, The graphics processor includes a scalar arithmetic logic unit pipeline and a vector arithmetic logic unit pipeline; the method further includes: if, during execution, it is detected that the target instruction stream includes a set scalar operation identifier, the target instruction stream is moved to the scalar arithmetic logic unit pipeline for execution.

10. The method according to any one of claims 6-9, characterized in that, Before executing the target instruction stream in the target thread bundle, the method further includes: After receiving the task execution signal, the threads are assembled to obtain multiple thread bundles; Vector general-purpose registers are allocated to each thread bundle based on the number of vector general-purpose registers configured; wherein, the number of vector general-purpose registers configured is the number of vector general-purpose registers allocated to a single thread; and the target thread bundle is one of multiple thread bundles.

11. A method for generating instruction streams for a graphics processor, characterized in that, include: The target task is parsed to obtain the number of vector general-purpose registers configured and multiple instruction streams, wherein the number of vector general-purpose registers configured is determined by the maximum vector general-purpose register requirement of a single thread in the target task; and The multiple instruction streams obtained from the parsing are identified. If it is detected that when any instruction stream is executed, the number of vector general-purpose registers actually required by a single thread executing it is less than the number of vector general-purpose registers configured, a setting reclamation instruction is inserted at the beginning of the instruction stream. The setting reclamation instruction is used to instruct the graphics processor to reclaim the allocated vector general-purpose registers when executing the instruction stream.

12. The method according to claim 11, characterized in that, The set reclamation instruction includes: a source operand, which indicates the number of vector general-purpose registers that need to be released; wherein, the source operand is determined based on the difference between the configured number of vector general-purpose registers and the actual number of vector general-purpose registers required by a single thread.

13. The method according to claim 11, characterized in that, The method further includes: when identifying multiple instruction streams obtained from parsing, if an instruction stream is identified as a scalar operation instruction stream, then the scalar operation identifier in the identified scalar operation instruction stream is set to the scalar operation identifier.

14. An electronic device, characterized in that, Including the graphics processor as described in any one of claims 1-5.

15. A computer-readable storage medium, said computer-readable storage medium being a non-volatile storage medium or a non-transient storage medium, having stored thereon a computer program, characterized in that, When the computer program is run by the processor, it performs the steps of the instruction stream execution method according to any one of claims 6-10 or the steps of the instruction stream generation method for a graphics processor according to any one of claims 11-13.

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