Wafer defect detection method, system and device

Abstract

This invention discloses a wafer defect detection method, system, and apparatus, relating to the field of semiconductor defect detection technology. The method includes: acquiring a wafer defect image to be processed; enhancing the defect features of the wafer defect image to obtain a defect-enhanced wafer image; constructing a deep learning-based denoising model, inputting the defect-enhanced wafer image into the denoising model for noise suppression, and obtaining an initial denoised wafer defect image; updating the denoising model by comparing the difference between the initial denoised wafer defect image and an actual clean wafer defect image, completing the overall training process of the denoising model; inputting a test wafer defect image to be denoised into the trained denoising model to obtain a clean wafer defect image; accurately locating defects in the clean wafer defect image, and outputting a wafer defect detection result image. This method achieves effective preservation of defect signals and suppression of noise in complex noise backgrounds.

Description

Technical Field

[0001] This invention relates to the field of semiconductor defect detection technology, and specifically to a wafer defect detection method, system, and apparatus. Background Technology

[0002] In integrated circuit manufacturing, wafer surface defects directly affect chip yield and reliability. As semiconductor manufacturing process nodes continue to shrink, the allowable defect size threshold for wafers has significantly decreased. Even micrometer-level defects can cause chip malfunctions, placing unprecedentedly high demands on the sensitivity, accuracy, and reliability of wafer defect detection technology. Wafer defect detection in integrated circuit manufacturing spans both front-end and back-end processes. Front-end inspection plays a crucial role in chip manufacturing, directly impacting the yield control of core processes such as deposition, photolithography, etching, and chemical mechanical polishing (CMP), and is a core element determining the competitiveness of a chip manufacturing plant.

[0003] Current wafer front-end inspection primarily employs optical inspection and electron beam inspection technologies. Electron beam inspection, leveraging the physical properties of high-energy electron beams interacting with matter, can achieve nanometer-level resolution. However, its point-by-point scanning mechanism results in extremely low throughput, and the high cost of equipment and maintenance makes it unsuitable for the efficiency and cost-effectiveness requirements of large-scale mass production. In contrast, optical inspection, based on high-speed imaging principles, offers significant advantages in terms of high throughput and controllable cost, making it more suitable for industrial production scenarios. However, this technology is limited by the optical diffraction limit and system aberrations, resulting in a theoretical bottleneck in spatial resolution. Furthermore, it is susceptible to interference from speckle noise and uneven illumination during imaging, leading to a decrease in the contrast of defect signals. Therefore, it faces significant challenges in detecting weak defects at the nanoscale with low signal-to-noise ratios. To overcome the sensitivity limitations of optical inspection systems, existing methods typically employ short-wavelength light sources or increase the numerical aperture. However, these solutions suffer from high technical difficulty, high cost, reduced detection field of view, and decreased detection efficiency, limiting industrial applications.

[0004] In summary, existing wafer front-end inspection methods have limited ability to extract wafer defects in complex noise environments, making it difficult to effectively preserve defect signals and suppress noise. This results in low accuracy and stability of defect detection, failing to meet the requirements for high-sensitivity detection. Summary of the Invention

[0005] To address the shortcomings of existing technologies in effectively preserving defect signals and suppressing noise in complex noise environments, this invention proposes a wafer defect detection method, system, and device. By combining a deep learning-based noise reduction model, it achieves effective preservation of defect signals and suppression of noise in complex noise environments, thereby enhancing the accuracy and stability of defect detection and solving the problems existing in the prior art.

[0006] A wafer defect detection method includes the following steps: Acquire a defect image of the wafer under test, and perform defect feature enhancement on the defect image to obtain a defect-enhanced wafer image; The defect-enhanced wafer image is input into a pre-trained denoising model to obtain a clean wafer defect image; Defects are located based on images of clean wafers to obtain wafer defect detection results. The process of inputting the defect-enhanced wafer image into a pre-trained denoising model to obtain a clean wafer defect image includes the following steps: The defect-enhanced wafer image is mapped to a high-dimensional feature space through the head convolutional mapping module to obtain the initial feature map; The initial feature map is input into the encoder, and is processed hierarchically by the cascaded core noise reduction module and downsampling module to gradually extract abstract features and suppress noise, thus obtaining the encoder output feature map; The encoder output feature map is input into the decoder, which is symmetrical to the encoder structure. The feature is reconstructed step by step through the cascaded upsampling module and the core noise reduction module. In each reconstruction process, the features corresponding to the encoder level are fused to gradually restore the image details and obtain the decoder output feature map. The tail convolution mapping module maps the decoder output feature map back to the image pixel space to generate a clean wafer defect image.

[0007] Furthermore, before performing defect feature enhancement on the wafer defect image, the method includes preprocessing the wafer defect image to obtain a normalized wafer defect image; the preprocessing process includes the following steps: The wafer defect image is converted to grayscale to a single-channel grayscale image; The wafer defect image converted to a single-channel grayscale image is subtracted by the mean grayscale value of all pixels and then divided by the standard deviation to map the pixel values ​​to a standard normal distribution, thus obtaining a normalized wafer defect image.

[0008] Furthermore, a composite second-order difference algorithm is used to enhance the defect features of the wafer defect image, resulting in a defect-enhanced wafer image. This process includes the following steps: Three wafer defect images were acquired at horizontal intervals with a step size s. Each wafer defect image is divided into three image blocks of equal step size in the vertical direction to perform second-order difference operations, forming a three-level defect feature pattern in the vertical direction. A horizontal second-order difference operation was performed on three time-series images that had undergone vertical second-order difference operation to form a horizontal third-level defect feature pattern. The two types of third-level defect feature patterns in the vertical and horizontal directions are superimposed to generate the final defect-enhanced wafer image.

[0009] Furthermore, the hierarchical processing via cascaded core noise reduction modules and downsampling modules to progressively extract abstract features and suppress noise, resulting in an encoder output feature map, specifically includes sequentially inputting the initial feature map into multiple processing stages of the encoder, each stage containing at least one core noise reduction module; within each processing stage, the initial feature map undergoes noise suppression and feature cleansing sequentially through multiple cascaded core noise reduction modules, and between encoder stages, the spatial resolution of the feature map is progressively reduced in the downsampling module by combining convolution and pixel descrambling operations; wherein, the processing of the initial feature map by each core noise reduction module includes the following steps: By using a wavelet transform-based gated cross-fusion attention unit, the input features are mapped through a linear transformation layer and then divided into gated features and attention features according to the channel dimension. Deep convolution is performed on the attention features to extract the initial features, and discrete wavelet transform is used to decompose the initial features into low-frequency and high-frequency components. A channel-wide attention mechanism is used to enhance the overall image structure of low-frequency components, resulting in low-frequency enhancement features. A sliding window attention mechanism is used to perform sliding window attention calculations on high-frequency components to distinguish between real edge details and noise components, outputting high-frequency cleanup features. After concatenating the low-frequency enhancement features and the high-frequency purification features, the inverse discrete wavelet transform is applied to restore the spatial domain from the frequency domain to the spatial domain, resulting in a reconstructed spatial domain feature map. The reconstructed spatial domain feature map is fused with the initial features output by the depth convolution through skip connections to obtain wavelet post-processing denoising features; The wavelet post-processing noise reduction features and gated features are fused through a gating mechanism to control the information flow and output the fused original image structure information and noise-filtered information as output features.

[0010] Furthermore, the method includes constructing a loss function by comparing the difference between the clean wafer defect image output by the denoising model and the actual clean wafer defect image; and using the backpropagation algorithm to update the gradient of the denoising model based on the loss function to complete the training of the denoising model.

[0011] Furthermore, the construction of the loss function specifically includes using the L1 norm loss function as the optimization objective, calculating the sum of the absolute errors of each corresponding pixel between the clean wafer defect image output by the denoising model and the actual clean wafer defect image; and using the sum of the absolute errors as the loss function value to measure the degree of difference between the clean wafer defect image output by the denoising model and the actual clean wafer defect image.

[0012] Furthermore, the step of locating defects based on clean wafer defect images to obtain wafer defect detection results specifically includes the following steps: The clean wafer defect image is subjected to normalization, contrast enhancement, two-dimensional window weighting, horizontal correction, unstructured edge clipping and height mapping in sequence to obtain preprocessed image features; By scanning column by column, local extrema detection is performed on the features of the preprocessed image, and each column of data is converted into a one-dimensional height signal to identify convex areas and record peak positions. Based on statistical principles, the mean and standard deviation of local peak values ​​in each column are calculated, and peak values ​​higher than the mean are identified as defects and their coordinates are recorded. By marking all defect locations, the final wafer defect detection results are output.

[0013] The present invention also includes a wafer defect detection system, comprising: The acquisition module is used to acquire defect images of the wafer under test and perform defect feature enhancement on the wafer defect images to obtain defect-enhanced wafer images; The model building module is used to input the defect-enhanced wafer image into a pre-trained denoising model to obtain a clean wafer defect image. Specifically, inputting the defect-enhanced wafer image into the pre-trained denoising model to obtain a clean wafer defect image includes: mapping the defect-enhanced wafer image to a high-dimensional feature space through a head convolutional mapping module to obtain an initial feature map; inputting the initial feature map into the encoder, where it undergoes hierarchical processing through a cascaded core denoising module and downsampling module to progressively extract abstract features and suppress noise, resulting in an encoder output feature map; inputting the encoder output feature map into a decoder symmetrical to the encoder structure, where it undergoes step-by-step feature reconstruction through a cascaded upsampling module and core denoising module, fusing features corresponding to the encoder's level at each reconstruction stage to progressively restore image details, resulting in a decoder output feature map; and finally, mapping the decoder output feature map back to the image pixel space through a tail convolutional mapping module to generate a clean wafer defect image. The detection module is used to locate defects based on images of defects on clean wafers and obtain wafer defect detection results.

[0014] The present invention also includes a wafer defect detection computer device, comprising: a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the wafer defect detection method.

[0015] The present invention also includes a readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, are used to perform the steps of the wafer defect detection method.

[0016] This invention provides a method for detecting wafer defects, which has the following advantages: This invention proposes a deep learning denoising model based on an encoder-decoder architecture. The model employs a cascaded core denoising module and a downsampling module to extract deep abstract features and suppress noise. A symmetrical decoder then fuses the corresponding layer features from the encoder to restore image details. This achieves effective preservation of weak defect signals and precise noise suppression even in complex noise environments. Finally, by introducing an automatic defect localization algorithm, the model can automatically identify and accurately pinpoint the location of defects, thus realizing automated detection and localization of wafer defects. This method significantly improves the accuracy and stability of wafer defect detection and effectively solves the technical challenge of simultaneously preserving defect signals and suppressing noise in existing technologies. Attached Figure Description

[0017] Figure 1 This is a flowchart of the automatic wafer defect detection method based on composite second-order difference and deep learning in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the principle of the composite second-order difference algorithm in an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the overall architecture of the noise reduction model in this embodiment of the invention. Figure 4 This is a schematic diagram illustrating the principle of each functional module in the noise reduction model of this invention. Figure 5 This is a flowchart of the automatic defect location algorithm in an embodiment of the present invention; Figure 6 This is a schematic diagram of the application process in an embodiment of the present invention; Figure 7 This is a comparison chart of the processing effects of the composite second-order difference algorithm in the embodiments of the present invention; Figure 8 This is a comparison chart of the denoising performance of the denoising model on the test set in this embodiment of the invention; Figure 9 This is a comparison chart showing the localization effect of the automatic defect localization algorithm in the embodiments of the present invention. Detailed Implementation

[0018] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0019] This invention proposes a wafer defect detection method. Without changing the optical hardware architecture, this method innovatively integrates and improves differential algorithms and deep neural networks to construct a multi-level processing framework of "image preprocessing - adaptive noise reduction - precise defect localization". This significantly improves the detection rate and efficiency of nanoscale and low-contrast defects, and has strong robustness and industrial applicability.

[0020] like Figure 1 As shown, the method specifically includes the following steps: S1. Obtain the wafer defect image to be processed.

[0021] Wafer defect images are images obtained by acquiring patterned wafer samples with common defects using a bright-field or dark-field optical inspection system in the visible light band. They are suitable for wafer defect inspection tasks.

[0022] Specifically, it covers typical defect types such as parallel bridges, vertical bridges, and broken bridges, with defect sizes as small as 22 nanometers. These images exhibit significant diversity in defect morphology, scale, and background complexity, effectively supporting and validating the effectiveness of the proposed automatic wafer defect detection method based on composite second-order difference and deep learning. Unless otherwise specified, the following descriptions of wafer defect images refer to single wafer defect images containing typical defects such as parallel bridges, vertical bridges, and broken bridges, acquired using a bright-field optical phase imaging system.

[0023] S2. Preprocess the wafer defect image to obtain a normalized wafer defect image. The specific preprocessing method includes the following steps:

[0024] (1) Convert the wafer defect image into a single-channel grayscale image by grayscale processing. (2) Subtract the mean gray value of all pixels from the wafer defect image converted into a single-channel grayscale image, and then divide by the standard deviation to map the pixel values ​​to a standard normal distribution, eliminate interference factors such as uneven illumination, and obtain a normalized wafer defect image.

[0025] S3. The normalized wafer defect image is processed by a composite second-order difference algorithm to enhance the defect features and obtain a defect-enhanced wafer image.

[0026] This invention provides a novel image processing algorithm based on composite second-order difference, which aims to solve the problems of insufficient response to weak defects, susceptibility to noise interference, and inaccurate edge localization of traditional second-order difference algorithms in complex backgrounds through multi-level feature extraction and process optimization, and significantly improve the detection capability of small and low-contrast defects.

[0027] Specifically, the traditional second-order difference algorithm involves acquiring a pixel sequence sampled at step-size intervals of 's' along the current direction, calculating the difference between corresponding pixel values ​​in the sampled images to obtain a first-order difference image, and then performing a difference operation with a step-size of 's' again based on the first-order difference image to obtain a second-order difference image. This is used to enhance defect edges and high-frequency details, and suppress low-frequency background noise. Compared to the traditional second-order difference algorithm, the composite second-order difference algorithm provided in this invention first performs second-order difference operations on adjacent images acquired at equal step sizes along the vertical direction (height direction) of the wafer defect image being processed. Then, it performs second-order difference operations at the same step size along the horizontal direction (time direction) on the vertical second-order difference results, finally obtaining a composite second-order difference image. This effectively enhances the edge, texture, and local contrast information of small defects, significantly reduces the processing flow, and greatly enhances the algorithm's robustness to low signal-to-noise ratio and complex background noise images.

[0028] Specifically, based on three time-series wafer defect images acquired at horizontal intervals with a step size *s*, a composite second-order difference algorithm divides each image into three image blocks of equal step size in the vertical direction and performs second-order difference operations to form a three-level defect feature pattern in the vertical direction. This pattern is used to enhance the defect signal-to-noise ratio and extract edge and texture features in the vertical direction. Then, a horizontal second-order difference operation is performed on the three time-series images that have undergone vertical second-order difference operations to form a three-level defect feature pattern in the horizontal direction. This pattern is used to enhance the defect signal-to-noise ratio in the horizontal direction while eliminating timing noise and system noise. Finally, the two three-level defect feature patterns are superimposed to form the final defect-enhanced wafer image. A schematic diagram of the algorithm is shown below. Figure 2 As shown.

[0029] S4. Construct a deep learning-based denoising model. Input the defect-enhanced wafer image into the denoising model for noise suppression to obtain the initial denoised wafer defect image. This includes the following steps: 1) The defect-enhanced wafer image is input into the head convolutional mapping module to obtain the initial feature extraction results.

[0030] 2) The initial feature extraction results are fed into the core noise reduction module in the encoder, and the frequency domain transformation output features with low frequency information retention and high frequency noise information suppression are obtained through the gated cross-fusion attention unit based on wavelet transform.

[0031] 3) The frequency domain transformation output features are nonlinearly transformed and local feature detail enhancement extracted through gated feedforward network units, and the noise feature representation is selectively controlled and cleaned through a gated mechanism to obtain clean output features.

[0032] 4) The clean output features are input into the downsampling module to obtain the downsampled output features; the downsampled output features then pass through the four stages of the encoder to gradually extract deep abstract information and form the encoder output features.

[0033] 5) The encoder output features are further input into the core noise reduction module, which has the same structure as the encoder, to complete feature reconstruction and obtain accurate reconstructed features.

[0034] 6) The spatial resolution of the accurately reconstructed features is gradually restored by the upsampling module to form the upsampled output features.

[0035] 7) The upsampled output features are processed step by step in the four stages of the decoder and the features of the corresponding stages of the encoder are fused through skip connections to enhance the ability to reconstruct details.

[0036] 8) The decoder output features are reconstructed by the tail convolution mapping module to generate an initial denoised wafer defect image.

[0037] This invention provides a novel deep learning-based denoising model, which employs a symmetric encoder-decoder architecture within the PyTorch deep learning framework. Specifically, the deep learning-based denoising model uses a symmetric encoder-decoder architecture similar to the U-Net model. Each stage includes a convolutional mapping module at the encoder head and a convolutional mapping module at the decoder tail. Both the encoder and decoder comprise four stages, each containing multiple unified core denoising modules. A downsampling module is placed between consecutive encoder stages to reduce spatial resolution and increase channel dimensions. An upsampling module is placed between consecutive decoder stages to gradually restore the image's spatial resolution. Furthermore, skip connections are used to fuse the detailed information provided by the encoder, achieving accurate reconstruction. A schematic diagram of the overall structure of this denoising model is shown below. Figure 3 As shown, the number of core noise reduction modules in each stage of the encoder and decoder in the noise reduction model is different, and different model variants are obtained by scaling the network width (i.e., the number of channels) and depth (i.e., the number of blocks used in each stage). In this invention, the number of core noise reduction modules in the encoder is 4, 6, 6, and 8, and the number of channels is set to 48, 96, 192, and 384, while the number of core noise reduction modules and the number of channels in the decoder are exactly the opposite of those in the encoder.

[0038] The construction of a deep learning-based noise reduction model specifically includes: (1) Head Convolution Mapping Module: The head convolution mapping module is implemented through a 3×3 ordinary convolution. The 3×3 ordinary convolution calculates the weighted sum of 3×3 neighboring pixels in the local region by sliding the convolution kernel on the spatial dimension of the input feature map, and maps the input image to a high-dimensional feature space for shallow feature extraction and channel dimension adjustment, laying the foundation for subsequent deep features.

[0039] (2) Core noise reduction module: The specific structural details of each component of the core noise reduction module are as follows Figure 4 As shown, unlike traditional transformer modules, this core noise reduction module consists of a wavelet transform-based gated cross-fusion attention module and a gated feedforward network module. Specifically, the core noise reduction module first separates low-frequency and high-frequency information based on wavelet transform using the wavelet transform-based gated cross-fusion attention module. High-frequency information is then processed using a sliding window attention calculation centered on a specific pixel. Low-frequency information is processed using a channel-wide attention mechanism to extract the overall structure of the image. Finally, the two processing results are merged and inversely transformed to the spatial domain for feature fusion and interaction. Subsequently, the fused and interacted features are processed through a gated feedforward network module for nonlinear transformation and local feature detail enhancement extraction. A gating mechanism is used to control information flow and generate the next layer of features.

[0040] Formally, given the first l The input characteristics of each core noise reduction module, and the input-output relationship of the entire core noise reduction module, can be represented as follows: in, For the first The input characteristics of each core noise reduction module For the first The intermediate output features of a wavelet transform-based gated cross-fusion attention module. For the first The final output characteristics of each core noise reduction module It is layer normalization. It is a gated cross-fusion attention module based on wavelet transform. It is a gated feedforward network module.

[0041] (2a) Wavelet Transform-Based Gated Cross-Fusing Attention Unit: The wavelet transform-based gated cross-fusion attention unit first performs preliminary processing on the input features through a double convolutional layer, separating gated features and attention features. Then, the attention features are decomposed into low-frequency and high-frequency features through Discrete Wavelet Transform (DWT) and grouped convolution. Low-frequency features contain the main structural information of the image, while high-frequency features typically contain noise and detail information. For low-frequency features, a channel-wide attention mechanism is applied to focus on the overall structure of the image, enhancing important regions and suppressing some low-frequency noise. A sliding window attention mechanism is used to process high-frequency features, enabling detailed processing of small-scale features and high-frequency noise in the image. This effectively suppresses noise in high-frequency regions while preserving detail information. Then, the low-frequency and high-frequency processing results are merged and transformed back to the spatial domain through Inverse Discrete Wavelet Transform (IDWT). The features from the inverse wavelet transform are then post-processed through a channel expansion layer to ensure that image information is effectively enhanced and transformed during the restoration process, resulting in wavelet post-processing denoising features. Next, the aforementioned gating features and wavelet post-processing denoising features are fused with the original image structural features and noise-filtered features through a gating mechanism. This better preserves important image content and effectively removes noise. This operation ensures that the final output not only contains the denoised image information but also retains the key information of the input image, preventing information loss. Finally, the final denoised image is output through a projection layer.

[0042] Formally, given the first i Input features First, a linear transformation and channel partitioning are performed to obtain the gated features. With attention characteristics Then attention features Initial feature extraction is performed using depthwise convolution, followed by wavelet transform and grouped convolution to segment high-frequency features. Low-frequency characteristics The specific steps are as follows: (2) in, Indicates the first i Each input feature Indicates a linear layer. This represents a depthwise convolution operation. This represents the discrete wavelet transform operation. This represents the intermediate features output by the depthwise convolution, which will be subsequently fused with the wavelet-denoised features. This indicates a grouped convolution operation. These represent low-frequency and high-frequency characteristics, respectively.

[0043] Next, high-frequency features Applying sliding window attention For low-frequency features Global attention is obtained through application channels Then, the features are reassembled according to the partitioning order, and restored to the spatial domain through wavelet inverse transform, and then combined with the intermediate features output from the aforementioned depth convolution. The fusion is performed through skip connections, followed by a channel extension layer to obtain wavelet post-processing denoising features. These wavelet post-processing denoising features are then combined with the aforementioned gated features. Feature fusion is performed using a gating mechanism to control the information flow, prevent the loss of image detail, and obtain the final module output. The specific steps are as follows: (3) in, It's about the attention of the sliding window. It is channel global attention. It's a splicing operation. It is the inverse discrete wavelet transform operation. It is a channel extension layer operation. This indicates a linear layer.

[0044] The sliding window attention mechanism, by limiting the receptive field of each pixel to a fixed window region in its vicinity and calculating attention weights within this local area, enables the model to effectively focus on high-frequency details and local structures. This neighborhood attention mechanism not only significantly enhances the expressive power of local features but also helps to preserve key high-frequency information while suppressing noise. Specifically, by constraining the scope of attention calculation, this mechanism greatly reduces computational complexity and strengthens the modeling ability for local high-frequency details, thereby improving the model's perceptual accuracy and robustness in high-frequency information processing and noise suppression tasks.

[0045] Channel global attention is a self-attention mechanism based on covariance matrix calculation. Its core idea is to model global dependencies from the channel dimension, capturing the cross-channel correlation structure of feature maps by calculating the covariance between channels, thereby enhancing and integrating low-frequency features. Specifically, this mechanism first calculates the covariance matrix between features of each channel in the global space to measure the statistical correlation strength of different channel features, and then recalibrates and fuses the channel features based on this covariance matrix. This approach effectively emphasizes channels that play a key role in the global structure, suppresses interference from redundant or noisy channels, and thus improves the modeling ability of low-frequency components in the image (such as smooth regions, contours, and macroscopic structures). Its advantages in processing low-frequency features are mainly reflected in its ability to strengthen long-range structural dependencies through global channel covariance relationships, enhance feature consistency and smoothness, and improve the preservation and reconstruction ability of the overall structure while reducing the impact of noise.

[0046] (2b) Gated Feedforward Network Unit: Traditional feedforward neural networks consist of two linear components connected by a nonlinear activation function. In contrast, the gated feedforward network unit constructed in this invention further enhances the extraction of local feature details by adding additional deep convolution operations and a gating mechanism. Simultaneously, it utilizes the selectivity of the gating mechanism to control and purify the features, resulting in cleaner features for the next layer. The specific operation can be expressed as follows:

[0047] (4) in, This represents the output features of a wavelet transform-based gated cross-fusion attention unit. and This represents the intermediate output feature between the two branches. Represents a non-linear activation function. This represents a depthwise convolution operation. This indicates a linear layer.

[0048] (3) Encoder downsampling module: The encoder downsampling module performs channel scaling through a 3×3 ordinary convolution, and then combines pixel unshuffle operation to decompose the image into smaller blocks to reduce the computational load in high-dimensional space, thereby reducing spatial resolution, effectively filtering high-frequency noise, reducing the computational load of the denoising model, while retaining the main features of the image and suppressing the propagation of noise in high-dimensional features, thus enabling more effective subsequent image processing or denoising.

[0049] (4) Decoder upsampling module: The decoder upsampling module increases the number of channels through a 3×3 ordinary convolution, and then combines the pixel rearrangement operation (PixelShuffle) to "expand" the spatial dimension of the image by separating each pixel into multiple channels, so as to restore the spatial resolution of the image, smooth high-frequency noise, enhance local features, and improve image quality.

[0050] (5) Tail convolution mapping module: The tail convolution mapping module is implemented by a 3×3 ordinary convolution. The 3×3 ordinary convolution calculates the weighted sum of 3×3 neighboring pixels in the local region by sliding the convolution kernel on the spatial dimension of the final output feature map of the decoder, and finally maps the fused features back to the output image space.

[0051] S5. Compare the difference between the initial denoised wafer defect image and the actual clean wafer defect image to construct a loss function. Specifically, compare the initial denoised wafer defect image obtained by the denoising model with the actual clean wafer defect image. This comparison typically uses Peak Signal-to-Noise Ratio (PSNR) as the evaluation criterion. The larger the PSNR value, the smaller the difference between the image to be denoised and the clean image, and the higher the denoising effect. Considering the characteristics of wafer defect image denoising tasks, an L1 norm loss function is used to construct the loss function. The L1 norm loss enhances the model's ability to preserve details and suppress noise values ​​by directly minimizing the absolute error between the prediction and the true value.

[0052] PSNR is used to evaluate the difference between a denoised image and a clean image. The calculation formula is: (5) in, It represents the maximum possible value of an image pixel (e.g., the maximum pixel value for an 8-bit image is 255), and MSE stands for Mean Square Error. It is an actual clean image. This is the image output by the denoising model, where H and W are the height and width of the image, respectively.

[0053] L1 loss function calculation formula: (6) in, A clean image in pixels The value at that location, It is a noise-reduced image at the pixel level The value at that location.

[0054] S6. Based on the loss function, the backpropagation algorithm is used to update the gradient of the denoising model, completing the overall training process of the denoising model. Specifically, this includes: First, calculating the value of the loss function and then using the backpropagation algorithm to calculate the gradient of the loss function relative to the model parameters. Then, using an optimization algorithm (such as AdamW), the parameters of the task model are updated based on the calculated gradient, adjusting the model to reduce the value of the loss function. Finally, through multiple iterations (epochs), each including multiple batches (batch_size), the training process of the task model is completed. During training, the parameters of the denoising model are gradually optimized to improve the model's performance in image denoising.

[0055] S7. Input the test wafer defect image to be denoised into the denoising model that has been trained to obtain a clean wafer defect image.

[0056] Furthermore, the entire training process of the denoising model and the inference process of the test images to be denoised are performed on the GPU server to accelerate computation and improve efficiency.

[0057] S8. The automatic defect localization algorithm is used to process the defect image of the clean wafer to achieve accurate defect localization and output the final wafer defect detection result image.

[0058] This invention provides an effective automatic defect localization algorithm. Its core function is to identify abnormal points (defects) that deviate significantly from the normal height by analyzing the local height features of each pixel column, and to visualize and mark their locations.

[0059] Specifically, the automatic defect localization algorithm sequentially performs preprocessing operations on the input image, including normalization, contrast enhancement, two-dimensional window weighting, horizontal correction, unstructured edge cropping, and height mapping. Then, it performs local extremum detection through column-by-column scanning, calculating the mean and standard deviation of local peak values ​​in each column based on statistical principles. Protrusions significantly deviating from the normal range are accurately identified as defects, and all defect locations are automatically marked, achieving a fully automated processing flow from preprocessing to localization output. The flowchart of this automatic defect localization algorithm is shown below. Figure 5 As shown.

[0060] The process involves processing clean wafer defect images to achieve precise defect location and outputting the final wafer defect detection result image. The specific steps are as follows: (1) Clean wafer defect images are processed by a series of preprocessing operations to obtain preprocessed image features.

[0061] (2) Preprocessing image features: Local extremum detection is performed by scanning column by column, and each column of data is converted into a one-dimensional height signal to identify the protruding area and record the peak position.

[0062] (3) Perform statistical analysis and anomaly judgment on the composite three-level pattern of defects, calculate the mean and standard deviation of each column peak, and judge the peaks that are significantly higher than the mean (the standard deviation exceeds the threshold multiple) as defects and record the coordinates.

[0063] (4) Accurately mark the defect location and finally output the complete wafer defect detection results.

[0064] The following detailed description, with reference to the accompanying drawings and specific embodiments, illustrates an automatic wafer defect detection method based on composite second-order difference and deep learning provided by the present invention: like Figure 6The diagram illustrates the application process in this embodiment, including a composite second-order difference algorithm, a denoising model, an automatic defect localization algorithm, a computer device, a polarization-tunable off-axis interferometric phase imaging system (image acquisition device), and a GPU server. In the actual application of the automatic wafer defect detection method, firstly, the computer device controls the polarization-tunable off-axis interferometric phase imaging system to acquire wafer defect images, and simultaneously constructs and tests the composite second-order difference algorithm, the denoising model, and the automatic defect localization algorithm. Then, the wafer defect images are processed using the composite second-order difference algorithm to obtain defect-enhanced wafer images, and the results are output and analyzed on the computer device. Next, the defect-enhanced wafer images are denoised using the denoising model, which is trained and updated on the GPU server to obtain trained denoising model weights. Afterward, the wafer defect images to be tested are remotely controlled and managed by the computer device to the GPU server, submitting denoising model weight calls and inference tasks, and providing status feedback and monitoring to obtain clean wafer defect images. Finally, the clean wafer defect images are processed using the automatic defect localization algorithm, and the final wafer defect detection result image is output on the computer device.

[0065] To further verify the practical effectiveness of the automatic wafer defect detection method based on composite second-order difference and deep learning provided by this invention, wafer defect images were acquired and experimentally tested on wafer samples containing typical 22nm defect types such as parallel bridges, vertical bridges, and broken bridges, using the polarization-tunable off-axis interferometric phase imaging system described in the embodiments. All experimental comparisons were conducted under fair and consistent parameter conditions. Verification shows that this invention achieves excellent performance in practical wafer defect detection tasks.

[0066] like Figure 7 The image shows the processing effect of the composite second-order difference algorithm provided by this invention on wafer defect images with a linewidth of 22nm. Compared with the traditional second-order difference algorithm, this algorithm significantly enhances the detection capability of nanoscale wafer defects, enabling the same optical inspection system to have higher detection sensitivity.

[0067] like Figure 8 The image shows the processing results of the denoising model trained by this invention on images in a 22nm linewidth wafer defect test dataset. This denoising model exhibits excellent real-world noise suppression capabilities, achieving a peak signal-to-noise ratio (PSNR) of 35.5 on the test set.

[0068] like Figure 9 The figure shows the processing effect of the automatic defect localization algorithm proposed in this invention in achieving accurate defect localization on a 22nm linewidth wafer defect test dataset. This algorithm can accurately identify and locate defect positions, exhibiting excellent localization accuracy and robustness.

[0069] As demonstrated by the above experiments and embodiments, this invention provides an automatic wafer defect detection method based on composite second-order difference and deep learning, overcoming the limitations of existing technologies in detecting low-contrast, small wafer defects, and effectively solving the technical bottleneck between defect signal preservation and noise suppression. This invention enhances the feature representation of small defects by introducing a composite second-order difference algorithm, significantly improving defect distinguishability and solving the problem of traditional second-order difference algorithms in low-contrast defect detection. Simultaneously, by combining a deep learning-based denoising model, it achieves effective preservation of defect signals and suppression of noise in complex noise backgrounds, thereby enhancing the accuracy and stability of defect detection. Finally, by introducing an automatic defect localization algorithm, it can automatically identify and accurately pinpoint the location of defects, thus realizing automated detection and localization of wafer defects. Furthermore, the wafer defect detection method provided by this invention does not rely on high numerical aperture optical systems or special short-wavelength light sources, significantly improving the sensitivity and accuracy of wafer defect detection, reducing dependence on high-cost hardware equipment, effectively reducing the overall cost of the detection system, and improving its economic efficiency and applicability. Especially in complex process backgrounds and environments with variable real noise interference, this method can still achieve efficient and reliable defect identification, opening up new technical paths and providing strong technical support for semiconductor manufacturing and other high-precision industrial inspection fields.

[0070] This invention delves into methods for effectively enhancing wafer defect features and achieving high-precision detection under complex noise conditions. By constructing a multi-level processing framework of "image preprocessing - adaptive noise reduction - precise defect localization," it proposes a general wafer defect detection method applicable to nanoscale, low-contrast defects. This invention is suitable for real-world wafer defect detection scenarios, exhibiting stronger robustness, higher detection accuracy, and excellent industrial applicability. Building upon conventional visible light optical inspection systems, this invention breaks through the optical diffraction limit, achieving high-precision detection of 22-nanometer patterned wafer defects, demonstrating outstanding comprehensive performance. Therefore, this invention is not only theoretically innovative but also possesses broad application prospects in practice.

[0071] Based on the same inventive concept, this invention also proposes a wafer defect detection system, comprising: The acquisition module is used to acquire defect images of the wafer under test and perform defect feature enhancement on the wafer defect images to obtain defect-enhanced wafer images.

[0072] The model building module is used to input the defect-enhanced wafer image into a pre-trained denoising model to obtain a clean wafer defect image. Specifically, inputting the defect-enhanced wafer image into the pre-trained denoising model to obtain a clean wafer defect image includes: mapping the defect-enhanced wafer image to a high-dimensional feature space through a head convolutional mapping module to obtain an initial feature map; inputting the initial feature map into the encoder, where it undergoes hierarchical processing through a cascaded core denoising module and downsampling module to progressively extract deep abstract features and suppress noise, resulting in an encoder output feature map; inputting the encoder output feature map into a decoder symmetrical to the encoder structure, where it undergoes feature reconstruction through a cascaded upsampling module and core denoising module, fusing features corresponding to the encoder's layers to progressively restore image details, resulting in a decoder output feature map; and finally, mapping the decoder output feature map back to the image pixel space through a tail convolutional mapping module to generate a clean wafer defect image.

[0073] The detection module is used to locate defects based on images of defects on clean wafers and obtain wafer defect detection results.

[0074] The present invention also proposes a wafer defect detection computer device, comprising: a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the wafer defect detection method.

[0075] The present invention also proposes a readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, are used to perform the steps of a wafer defect detection method.

[0076] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A wafer defect detection method, characterized by, Includes the following steps: Acquire a defect image of the wafer under test, and perform defect feature enhancement on the defect image to obtain a defect-enhanced wafer image; The defect-enhanced wafer image is input into a pre-trained denoising model to obtain a clean wafer defect image; Defects are located based on images of clean wafers to obtain wafer defect detection results. The process of inputting the defect-enhanced wafer image into a pre-trained denoising model to obtain a clean wafer defect image includes the following steps: The defect-enhanced wafer image is mapped to a high-dimensional feature space through the head convolutional mapping module to obtain the initial feature map; The initial feature map is input into the encoder, and is processed hierarchically by the cascaded core noise reduction module and downsampling module to gradually extract abstract features and suppress noise, thus obtaining the encoder output feature map; The encoder output feature map is input into the decoder, which is symmetrical to the encoder structure. The feature is reconstructed step by step through the cascaded upsampling module and the core noise reduction module. In each reconstruction process, the features corresponding to the encoder level are fused to gradually restore the image details and obtain the decoder output feature map. The tail convolution mapping module maps the decoder output feature map back to the image pixel space to generate a clean wafer defect image.

2. The method of claim 1, wherein The method also includes preprocessing the wafer defect image to obtain a normalized wafer defect image before performing defect feature enhancement on the wafer defect image; Its preprocessing includes the following steps: The wafer defect image is converted to grayscale to a single-channel grayscale image; The wafer defect image converted to a single-channel grayscale image is subtracted by the mean grayscale value of all pixels and then divided by the standard deviation to map the pixel values ​​to a standard normal distribution, thus obtaining a normalized wafer defect image.

3. The wafer defect detection method according to claim 1, characterized in that, A composite second-order difference algorithm is used to enhance the defect features of the wafer defect image, resulting in a defect-enhanced wafer image. The specific steps include: Three wafer defect images were acquired at horizontal intervals with a step size s. Each wafer defect image is divided into three image blocks of equal step size in the vertical direction to perform second-order difference operations, forming a three-level defect feature pattern in the vertical direction. A horizontal second-order difference operation was performed on three time-series images that had undergone vertical second-order difference operation to form a horizontal third-level defect feature pattern. The two types of third-level defect feature patterns in the vertical and horizontal directions are superimposed to generate the final defect-enhanced wafer image.

4. The wafer defect detection method according to claim 1, characterized in that, The process involves hierarchical processing using cascaded core noise reduction modules and downsampling modules to progressively extract abstract features and suppress noise, resulting in an encoder output feature map. Specifically, this includes sequentially inputting the initial feature map into multiple processing stages of the encoder, each stage containing at least one core noise reduction module. Within each processing stage, the initial feature map undergoes noise suppression and feature cleansing sequentially through multiple cascaded core noise reduction modules. Furthermore, between encoder stages, the spatial resolution of the feature map is progressively reduced in the downsampling module by combining convolution and pixel descrambling operations. The processing of the initial feature map by each core noise reduction module includes the following steps: By using a wavelet transform-based gated cross-fusion attention unit, the input features are mapped through a linear transformation layer and then divided into gated features and attention features according to the channel dimension. Deep convolution is performed on the attention features to extract the initial features, and discrete wavelet transform is used to decompose the initial features into low-frequency and high-frequency components. A channel-wide attention mechanism is used to enhance the overall image structure of low-frequency components, resulting in low-frequency enhancement features. A sliding window attention mechanism is used to perform sliding window attention calculations on high-frequency components to distinguish between real edge details and noise components, outputting high-frequency cleanup features. After concatenating the low-frequency enhancement features and the high-frequency purification features, the inverse discrete wavelet transform is applied to restore the spatial domain from the frequency domain to the spatial domain, resulting in a reconstructed spatial domain feature map. The reconstructed spatial domain feature map is fused with the initial features output by the depth convolution through skip connections to obtain wavelet post-processing denoising features; The wavelet post-processing noise reduction features and gated features are fused through a gating mechanism to control the information flow and output the fused original image structure information and noise-filtered information as output features.

5. The wafer defect detection method according to claim 1, characterized in that, The method also includes constructing a loss function by comparing the difference between the clean wafer defect image output by the denoising model and the actual clean wafer defect image; and using the backpropagation algorithm to update the gradient of the denoising model according to the loss function to complete the training of the denoising model.

6. The wafer defect detection method according to claim 5, characterized in that, The construction of the loss function specifically includes using the L1 norm loss function as the optimization objective and calculating the sum of the absolute errors of each corresponding pixel between the clean wafer defect image output by the denoising model and the actual clean wafer defect image; The sum of the absolute errors is used as the loss function value to measure the degree of difference between the clean wafer defect image output by the denoising model and the actual clean wafer defect image.

7. The wafer defect detection method according to claim 1, characterized in that, The process of locating defects based on clean wafer defect images to obtain wafer defect detection results specifically includes the following steps: The clean wafer defect image is subjected to normalization, contrast enhancement, two-dimensional window weighting, horizontal correction, unstructured edge clipping and height mapping in sequence to obtain preprocessed image features; By scanning column by column, local extrema detection is performed on the features of the preprocessed image, and each column of data is converted into a one-dimensional height signal to identify convex areas and record peak positions. Based on statistical principles, the mean and standard deviation of local peak values ​​in each column are calculated, and peak values ​​higher than the mean are identified as defects and their coordinates are recorded. By marking all defect locations, the final wafer defect detection results are output.

8. A wafer defect detection system, characterized in that, include: The acquisition module is used to acquire defect images of the wafer under test and perform defect feature enhancement on the wafer defect images to obtain defect-enhanced wafer images; The model building module is used to input the defect-enhanced wafer image into a pre-trained denoising model to obtain a clean wafer defect image. Specifically, inputting the defect-enhanced wafer image into the pre-trained denoising model to obtain a clean wafer defect image includes: mapping the defect-enhanced wafer image to a high-dimensional feature space through a head convolutional mapping module to obtain an initial feature map; inputting the initial feature map into the encoder, where it undergoes hierarchical processing through a cascaded core denoising module and downsampling module to progressively extract abstract features and suppress noise, resulting in an encoder output feature map; inputting the encoder output feature map into a decoder symmetrical to the encoder structure, where it undergoes step-by-step feature reconstruction through a cascaded upsampling module and core denoising module, fusing features corresponding to the encoder's level at each reconstruction stage to progressively restore image details, resulting in a decoder output feature map; and finally, mapping the decoder output feature map back to the image pixel space through a tail convolutional mapping module to generate a clean wafer defect image. The detection module is used to locate defects based on images of defects on clean wafers and obtain wafer defect detection results.

9. A computer device for detecting wafer defects, characterized in that, include: A memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the wafer defect detection method according to any one of claims 1-7.

10. A readable storage medium, characterized in that, The readable storage medium stores a computer program, which includes program instructions that, when executed by a processor, perform the steps of the wafer defect detection method according to any one of claims 1-7.

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