Component circuit board defect detection method based on graph neural network

Abstract

This invention discloses a method for detecting defects in electronic component circuit boards based on graph neural networks, comprising the following steps: acquiring optical images and inventory coordinates of the circuit board; extracting features of solder joints, pins, and traces to form fine-grained entities; constructing electrical connections and spatial adjacency relationships to generate a multi-relationship structure graph and a gating matrix; encoding the multi-relationship structure graph using a graph neural network to obtain structural representations and generate anomaly evidence and complexity indices; determining the number of clusters in defect-sensitive pooling and fusing them to generate a fine-grained allocation matrix; aggregating based on the allocation matrix to form device-level structural representations and outputting device-level defect judgments; and outputting the final defect result through inter-layer mutual verification and local repooling. This invention, based on a multi-relationship perceptual graph neural network and a defect-sensitive hierarchical pooling method, achieves structured joint judgment of defects in electronic component circuit boards, possessing advantages such as high detection accuracy, strong stability, and low false detection rate.

Description

Technical Field

[0001] This invention relates to the field of circuit board inspection, and more particularly to a method for detecting defects in component circuit boards based on graph neural networks. Background Technology

[0002] Currently, defect detection of electronic components and circuit boards largely relies on automated optical inspection images to extract candidate regions and identify features of targets such as solder joints, pins, and traces. Common implementations include rule-based processes based on threshold segmentation, edge detection, and morphological screening, as well as end-to-end recognition methods represented by convolutional neural networks. In engineering applications, component lists and mounting coordinates are often combined to complete component positioning, candidate region clipping and alignment, and on this basis, component-level defect conclusions are output to meet the timeliness and consistency requirements of online inspection on production lines.

[0003] However, existing technologies often focus on visual appearance and lack a unified structured expression and collaborative constraints for electrical connection relationships and spatial adjacency relationships. This leads to prominent issues of misallocation of fine-grained entities and misaggregation across devices in scenarios with high-density mounting, complex wiring, and significant reflection and occlusion. At the same time, defect evidence lacks verifiable alignment mechanisms and closed-loop correction paths between the fine-grained layer and the device layer, making it difficult to achieve local adaptive reaggregation in conflict areas. This can easily lead to the spread of false positives and false negatives, unstable device-level judgments, and insufficient robustness to complex defect coupling.

[0004] Therefore, how to provide a method for detecting defects in components and circuit boards based on graph neural networks is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] One objective of this invention is to propose a defect detection method for component circuit boards based on graph neural networks. This invention is based on a multi-relational perceptual graph neural network and a defect-sensitive hierarchical pooling method to achieve structured joint determination of defects in component circuit boards, which has the advantages of high detection accuracy, strong stability and low false detection rate.

[0006] The component circuit board defect detection method based on graph neural network according to an embodiment of the present invention includes the following steps: Acquire automatic optical inspection images of component circuit boards, component lists and mounting coordinate information, extract solder joint feature sets, pin feature sets and trace segment feature sets to form a fine-grained inspection entity set; Based on the fine-grained detection entity set, an electrical connection relationship set and a spatial adjacency relationship set are constructed, and a fine-grained multi-relationship circuit structure diagram is generated. Based on the component list and mounting coordinate information, a circuit feasibility gating matrix is ​​generated. The fine-grained multi-relation circuit structure diagram is input into the multi-relation perceptual graph neural network encoder to obtain a set of fine-grained structure representations and generate an abnormal evidence set and an abnormal complexity index. In the defect-sensitive hierarchical pooling mechanism based on DiffPool, the number of pooling clusters is determined according to the abnormal complexity index and the defect-sensitive cluster configuration is generated. Based on the circuit feasibility gating matrix, the allocation matrix is ​​generated for the electrical connection relationship set and the spatial adjacency relationship set respectively and then fused in a consistent manner to obtain the fine-grained allocation matrix. Based on the fine-grained allocation matrix, the fine-grained structural representation set and the fine-grained multi-relation circuit structure diagram are aggregated to generate a device-level multi-relation circuit structure diagram and a device-level structural representation set, and the device-level defect judgment result is output. Based on the fine-grained allocation matrix, the set of abnormal evidence is aggregated to generate pooled cluster anomaly estimation results, and inter-layer mutual verification consistency determination is performed with the device-level defect determination results. This triggers local repooling to update the fine-grained allocation matrix and the device-level defect determination results, and outputs the component circuit board defect detection results.

[0007] Optionally, the generation of the fine-grained detection entity set specifically includes: Acquire automatic optical inspection images of component circuit boards, component list and placement coordinate information, perform consistency verification on component list and placement coordinate information, and generate a set of coordinate validity verification results and a set of component positioning baselines; Based on the set of coordinate validity verification results, geometric correction, distortion correction and illumination normalization are performed on the automatic optical inspection image to generate a set of corrected automatic optical inspection images. Background baseline map and noise suppression mask set are generated in the set of corrected automatic optical inspection images. Based on the device localization baseline set, device candidate region generation is performed in the corrected automatic optical inspection image set, and boundary clipping and rotation alignment are performed to generate an aligned device candidate region set. In the aligned device candidate region set, candidate region extraction is performed in conjunction with the noise suppression mask set to generate solder joint candidate region set, pin candidate region set and trace segment candidate region set respectively. Then, connected component decomposition and morphological consistency screening are performed to generate solder joint instance set, pin instance set and trace segment instance set. Based on the set of solder joint instances, the solder joint morphology description, reflection anomaly description, and boundary continuity description are calculated to form a solder joint feature set; Based on the set of pin instances, calculate the pin position offset descriptor, pin spacing consistency descriptor, and endpoint integrity descriptor to form a pin feature set; Based on the set of trace segment instances, calculate the trace width stability descriptor, trace direction consistency descriptor, and break gap descriptor to form a trace segment feature set; The solder joint feature set, pin feature set, and trace segment feature set are indexed and bound to the corresponding aligned device candidate region set, and coordinate backfilling is performed to generate a fine-grained detection entity set.

[0008] Optionally, the generation of the fine-grained multi-relationship circuit structure diagram and the circuit feasibility gating matrix specifically includes: Obtain a fine-grained set of detected entities, perform entity deduplication and entity consistency verification, and generate a set of entity validity verification results and a fine-grained entity index table; A set of spatial adjacency candidate pairs is generated by performing spatial retrieval of detected entities based on a fine-grained entity index table within the same aligned set of device candidate regions. The Euclidean distance, azimuth difference, and consistency of constraints of the detected entities are integrated to generate a set of spatial adjacency candidate pair attributes. Based on the set of spatial adjacency candidate pairs, perform spatial adjacency domain filtering to obtain the set of spatial adjacency relations and the set of spatial adjacency edge attributes; Obtain the component list and mounting coordinate information, combine the fine-grained entity index table to establish a set of device candidate identifiers for each detected entity, and register the theoretical pin positions, theoretical solder joint positions and device outline boundary information in the device positioning baseline set to form a set of consistency basis for device candidate attribution. Based on the consistency criteria set of device candidate attribution and the fine-grained entity index table, an electrical connection relationship set is constructed, and a connection type label, an endpoint entity type label, and endpoint geometric proximity evidence are registered for each electrical connection edge to generate an electrical connection edge attribute set. Based on the set of electrical connection edge attributes, electrical network conflict suppression is performed to obtain a set of conflict suppression results for the set of electrical connection relationships. Cross-device conflict elimination is performed on electrical connection edges in the cross-device candidate belonging set to generate a set of conflict-suppressed electrical connection relationships. Fine-grained multi-relationship circuit structure diagrams are generated based on the conflict-suppressed set of electrical connection relationships and the set of spatial adjacency relationships. A circuit feasibility gating matrix is ​​generated based on the set of consistency criteria for device candidate attribution, the set of conflict-suppressed electrical connection relationships, and the set of spatial adjacency relationships.

[0009] Optionally, the generation of the anomalous evidence set and the anomalous complexity index specifically includes: Obtain a fine-grained multi-relation circuit structure diagram, perform alignment encoding on the node feature structure and edge attribute structure based on the fine-grained entity index table, generate a fine-grained initial node representation set and a multi-relation edge attribute representation set, and write them into the fine-grained multi-relation circuit structure diagram to form the encoded fine-grained multi-relation circuit structure diagram; The encoded fine-grained multi-relation circuit structure diagram is input into the multi-relation perception graph neural network encoder. Electrical relationship message passing and spatial relationship message passing are performed on the adjacency structures corresponding to the electrical connection relationship set and the spatial adjacency relationship set, respectively. Electrical neighborhood aggregation representation and spatial neighborhood aggregation representation are generated for each detected entity, and electrical relationship update node representation set and spatial relationship update node representation set are generated. Perform multi-relation consistency fusion on the electrical relation update node representation set and the spatial relation update node representation set to generate a fine-grained fused node representation set; Based on the fine-grained fusion node representation set, multi-layer stacked encoding and normalization constraints are performed to generate a fine-grained structural representation set; Generate anomaly evidence sets based on fine-grained structural representation sets; Calculate the set of abnormal complexity indices based on the set of abnormal evidence, and bind them to the set of abnormal evidence to form the result of the abnormal complexity index.

[0010] Optionally, the generation of the fine-grained allocation matrix specifically includes: Obtain the abnormal complexity index results, read the abnormal complexity index set and determine the number of pooling clusters, and generate the defect-sensitive cluster configuration; Obtain the circuit feasible gating matrix and the fine-grained structure representation set, configure and initialize the pooling cluster candidate index set based on the number of defect-sensitive clusters, and align the indexes with the circuit feasible gating matrix to generate a gating alignment result set; In the defect-sensitive hierarchical pooling mechanism based on DiffPool, an electrical allocation matrix is ​​generated according to the set of fine-grained structural representations and the set of electrical connection relationships. In the defect-sensitive hierarchical pooling mechanism based on DiffPool, a spatial allocation matrix is ​​generated based on the set of fine-grained structural representations and the set of spatial adjacency relationships. Based on the circuit feasibility gate matrix, the electrical allocation matrix and the spatial allocation matrix are fused to generate a fine-grained allocation matrix. Based on the fine-grained allocation matrix, cluster-level feasibility verification and cluster number consistency verification are performed to generate a set of allocation feasibility verification results; The fine-grained allocation matrix is ​​indexed and bound to the set of allocation feasibility verification results to form the fine-grained allocation matrix index result and output it.

[0011] Optionally, the generation of the device-level defect determination result specifically includes: Obtain the fine-grained allocation matrix index results, fine-grained structure representation set and fine-grained multi-relation circuit structure diagram. Based on the fine-grained allocation matrix, determine the pooling cluster candidate index belonging to each detected entity on the row index of the fine-grained entity index table, and generate the cluster-in-cluster detection entity set and the cluster-in-cluster index binding result set. Based on the cluster index binding result set, perform intra-cluster aggregation on the fine-grained structural representation set, weighted convergence of the fine-grained structural representation of the detected entities within the cluster according to the pooling cluster candidate index and perform amplitude normalization to generate the pooling cluster node representation set, and register it as the device-level structural representation set. Based on the set of detected entities within a cluster and the set of electrical connection relationships in the fine-grained multi-relation circuit structure diagram, a relational mapping is performed to map cross-cluster electrical connection edges to electrical inter-cluster connection edges between pooled cluster candidate indices. The connection type label and endpoint geometric proximity evidence are aggregated to generate an electrical inter-cluster edge attribute set, resulting in a device-level electrical connection relationship set. Based on the set of detected entities within a cluster and the set of spatial adjacency relationships in the fine-grained multi-relationship circuit structure diagram, a relation mapping is performed. Cross-cluster spatial adjacency edges are mapped to spatial inter-cluster adjacency edges between pooled cluster candidate indices. Euclidean distance, azimuth angle difference, and consistency of constraints within the same device are aggregated to generate a set of spatial inter-cluster edge attributes, resulting in a device-level set of spatial adjacency relationships. A device-level multi-relationship circuit structure diagram is constructed based on the set of device-level electrical connection relationships, the set of edge attributes between electrical clusters, the set of device-level spatial adjacency relationships, and the set of edge attributes between spatial clusters. The device-level multi-relationship circuit structure diagram and the device-level structural representation set are input into the device-level defect judgment process. Based on the device-level electrical connection relationship set and the device-level spatial adjacency relationship set, the device-level structural representation set is subjected to multi-relationship consistent aggregation to generate the device-level defect judgment representation set. The device-level defect judgment result is output based on the device-level defect judgment representation set. The device-level defect determination results are bound to the cluster-specific index binding result set to which the pooling cluster candidate index belongs, thus forming the device-level defect determination index result.

[0012] Optionally, the generation of the component circuit board defect detection results specifically includes: Obtain the fine-grained allocation matrix index result, the abnormal evidence set, and the fine-grained entity index table. Based on the fine-grained allocation matrix index result, determine the pooling cluster candidate index belonging to each detected entity on the row index of the fine-grained entity index table, generate the abnormal evidence cluster belonging mapping result set, and align it with the abnormal evidence set to obtain the cluster-aligned abnormal evidence set. Based on the cluster-aligned anomaly evidence set, cluster-level aggregation is performed on the anomaly evidence set to generate a pooled cluster anomaly vector set, which is then indexed and bound to the pooled cluster candidate index to form the pooled cluster anomaly estimation result. Based on the device-level defect judgment index results, the device-level defect judgment results and the pooling cluster anomaly estimation results are aligned on the pooling cluster candidate index dimension to generate an inter-layer alignment result set. Based on the inter-layer alignment result set, inter-layer mutual verification consistency determination is performed. Consistency scores are calculated for the device-level defect status item and the pooling cluster anomaly vector item of the same pooling cluster candidate index, and a consistency score set is formed. The set is then bound to the pooling cluster candidate index to obtain the mutual verification consistency index result. Based on the mutual verification consistency index results, mutual verification trigger screening is performed. Pooling cluster candidate indices whose consistency scores do not meet the threshold interval division rules are registered as conflict cluster sets. From the conflict cluster set, their adjacent pooling cluster candidate indices in the device-level multi-relation circuit structure diagram are traced back to form a conflict expansion cluster set, generating a local repooling trigger result set. Local repooling is triggered on the result set of local repooling to obtain the locally updated fine-grained allocation matrix, and the fine-grained allocation matrix index result is written back to form the updated fine-grained allocation matrix index result; Based on the updated fine-grained allocation matrix index results, the device-level defect judgment index results are updated synchronously. The pooling cluster anomaly estimation results generation and inter-layer mutual verification consistency judgment are re-executed. The device-level defect judgment results and pooling cluster anomaly estimation results constrained by the mutual verification consistency index results are output, and the index binding is performed to form the component circuit board defect detection results.

[0013] The beneficial effects of this invention are: This invention unifies the modeling of solder joints, pins, and trace segments extracted from automated optical inspection images into fine-grained inspection entities. Based on this, it introduces a multi-relationship circuit structure expression of electrical connection relationships and spatial adjacency relationships, realizing integrated perception of the local structure and overall topology of the circuit board. This allows defect analysis to no longer be limited to isolated appearance features, but to be jointly judged under the constraints of electrical feasibility and spatial consistency. This significantly reduces the risk of false detection and misjudgment caused by visual noise, reflection interference, or local occlusion under high-density mounting and complex routing conditions.

[0014] Furthermore, this invention employs a defect-sensitive hierarchical pooling mechanism based on adaptive adjustment of anomaly complexity, enabling the aggregation granularity to dynamically change with anomaly distribution. It also constructs an inter-layer mutual verification consistency judgment and local repooling closed loop between the fine-grained layer and the device layer. When inconsistencies arise between defect evidence and device-level judgment, it can automatically trigger local structural reconstruction and result updates, thereby effectively suppressing the propagation of erroneous aggregation, improving the stability and interpretability of device-level defect judgment, and enhancing the overall detection accuracy and engineering reliability of complex coupled defects, cross-structural anomalies, and local conflict regions. Attached Figure Description

[0015] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart of the component circuit board defect detection method based on graph neural network proposed in this invention; Figure 2 This is a fine-grained multi-relation circuit structure diagram and a schematic diagram of the circuit feasible gating matrix generation process for the component circuit board defect detection method based on graph neural network proposed in this invention. Figure 3 This diagram illustrates the defect-sensitive hierarchical pooling and inter-layer consistency update process based on DiffPool in the component circuit board defect detection method based on graph neural networks proposed in this invention. Detailed Implementation

[0016] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0017] refer to Figures 1-3 A component circuit board defect detection method based on graph neural networks includes the following steps: Acquire automatic optical inspection images of component circuit boards, component lists and mounting coordinate information, extract solder joint feature sets, pin feature sets and trace segment feature sets to form a fine-grained inspection entity set; Based on the fine-grained detection entity set, an electrical connection relationship set and a spatial adjacency relationship set are constructed, and a fine-grained multi-relationship circuit structure diagram is generated. Based on the component list and mounting coordinate information, a circuit feasibility gating matrix is ​​generated. The fine-grained multi-relation circuit structure diagram is input into the multi-relation perceptual graph neural network encoder to obtain a set of fine-grained structure representations and generate an abnormal evidence set and an abnormal complexity index. In the defect-sensitive hierarchical pooling mechanism based on DiffPool, the number of pooling clusters is determined according to the abnormal complexity index and the defect-sensitive cluster configuration is generated. Based on the circuit feasibility gating matrix, the allocation matrix is ​​generated for the electrical connection relationship set and the spatial adjacency relationship set respectively and then fused in a consistent manner to obtain the fine-grained allocation matrix. Based on the fine-grained allocation matrix, the fine-grained structural representation set and the fine-grained multi-relation circuit structure diagram are aggregated to generate a device-level multi-relation circuit structure diagram and a device-level structural representation set, and the device-level defect judgment result is output. Based on the fine-grained allocation matrix, the set of abnormal evidence is aggregated to generate pooled cluster anomaly estimation results, and inter-layer mutual verification consistency determination is performed with the device-level defect determination results. This triggers local repooling to update the fine-grained allocation matrix and the device-level defect determination results, and outputs the component circuit board defect detection results.

[0018] In this embodiment, the generation of the fine-grained detection entity set specifically includes: Acquire automatic optical inspection images of component circuit boards, component list and placement coordinate information, perform consistency verification on component list and placement coordinate information, and generate a set of coordinate validity verification results and a set of component positioning baselines; Based on the set of coordinate validity verification results, geometric correction, distortion correction and illumination normalization are performed on the automatic optical inspection image to generate a set of corrected automatic optical inspection images. Background baseline map and noise suppression mask set are generated in the set of corrected automatic optical inspection images. The illumination normalization includes performing background mean elimination and background standard deviation normalization on the gray value of each pixel, and introducing a constant in the denominator to prevent the denominator from being zero to obtain the pixel value after illumination normalization. Based on the device localization baseline set, device candidate region generation is performed in the corrected automatic optical inspection image set, and boundary clipping and rotation alignment are performed to generate an aligned device candidate region set. In the aligned device candidate region set, candidate region extraction is performed in conjunction with the noise suppression mask set to generate solder joint candidate region set, pin candidate region set and trace segment candidate region set respectively. Then, connected component decomposition and morphological consistency screening are performed to generate solder joint instance set, pin instance set and trace segment instance set. The solder joint candidate region set, pin candidate region set, and trace segment candidate region set are generated by performing local adaptive threshold segmentation on the image based on the local high reflectivity and near-circular region features of the solder joint in the automatic optical inspection image within the aligned device candidate region set. The background statistics of the background baseline map at the corresponding pixel position or the corresponding pixel neighborhood are used as the threshold baseline. Isolated noise is suppressed by combining the noise suppression mask set, and the solder joint response region is generated. The solder joint candidate region set is obtained by region growing. Based on the long strip-shaped and high-contrast edge structure features of the pin in the automatic optical inspection image, directional edge detection is performed on the image and directional consistency aggregation is performed along the pin arrangement direction. After removing non-continuous edge responses by combining the noise suppression mask set, region filling is performed to generate the pin candidate region set. Based on the slender continuous linear structure features of the trace in the automatic optical inspection image, linear structure enhancement processing is performed on the image. The continuous linear response region is retained by combining the noise suppression mask set. Thinning processing and width restoration are performed to generate the trace segment candidate region set. The connected component decomposition aggregates pixels that satisfy the pixel adjacency rule into independent connected components and generates a corresponding connected component attribute set for each connected component. The morphological consistency screening performs screening based on the area distribution, outer boundary shape and boundary continuity of the connected components in the solder joint candidate region set, on the aspect ratio, directional stability and arrangement consistency of the connected components in the pin candidate region set, and on the linear continuity, width stability and directional consistency of the connected components in the trace segment candidate region set, eliminating connected components that do not satisfy the corresponding morphological consistency rule. Based on the set of solder joint instances, the solder joint morphology description, reflection anomaly description, and boundary continuity description are calculated to form a solder joint feature set; The weld point morphology description quantity takes the candidate region corresponding to each weld point instance in the weld point instance set as the calculation object, extracts its geometric contour based on the binary segmentation result of the weld point region, and calculates the area, equivalent diameter, major-minor axis ratio, roundness and contour filling rate of the weld point to characterize whether the weld point shape conforms to the expected welding form, thus forming the weld point morphology description quantity. The reflection anomaly descriptor is based on the statistical gray-level distribution characteristics of the automatic optical detection image after illumination normalization within the solder joint area. It calculates the average gray-level difference, gray-level variance difference, and high-brightness pixel ratio between the solder joint area and its neighboring background area. This is used to characterize whether there is abnormal reflection, high-brightness overflow, or insufficient diffuse reflection on the surface of the solder joint, thus forming the reflection anomaly descriptor. The boundary continuity descriptor analyzes the directional change and gradient continuity of boundary pixels along the solder joint contour, calculates the proportion of directional abrupt changes between adjacent contour points, the number of boundary gradient interruptions, and the boundary closure integrity, and is used to characterize whether there are breaks, gaps, or irregular jagged edges at the solder joint edge, thus forming the boundary continuity descriptor. Based on the set of pin instances, calculate the pin position offset descriptor, pin spacing consistency descriptor, and endpoint integrity descriptor to form a pin feature set; The pin position offset descriptor is obtained by aligning and comparing the actual geometric center position of each pin instance with its corresponding theoretical position in the device positioning baseline set. The offset distance and direction consistency of the pin instance center relative to the theoretical pin center are calculated in the device local coordinate system, and the offset distance and direction consistency are normalized and combined to form the pin position offset descriptor. The pin spacing consistency descriptor is obtained by statistically analyzing the actual spacing between adjacent pin instances within the same candidate region of the device and comparing it with the theoretical spacing distribution of the corresponding pins in the device positioning baseline set. The dispersion and deviation between the actual spacing sequence and the theoretical spacing sequence are calculated to form a pin spacing consistency descriptor that reflects the uniformity of pin arrangement. The endpoint integrity descriptor is formed by performing boundary continuity analysis and morphological integrity analysis on the endpoint region of each pin instance, calculating the degree of closure of the pin endpoint contour, the proportion of missing edges, and the degree of morphological distortion of the endpoint region, thus forming an endpoint integrity descriptor used to characterize whether the pin endpoint has defects, warping, or breakage. Based on the set of trace segment instances, calculate the trace width stability descriptor, trace direction consistency descriptor, and break gap descriptor to form a trace segment feature set; The trace width stability descriptor is based on the pixel skeleton and boundary contour of the trace segment instance. It performs multi-point sampling along the main axis of the trace in the trace normal direction with a fixed step size, calculates the trace width corresponding to each sampling position, and performs statistics on the sampled width sequence. Based on the dispersion and fluctuation amplitude of the width sequence, the trace width stability descriptor is generated. The routing direction consistency descriptor is based on the skeleton point sequence or principal axis fitting result of the routing segment instance, calculates the change of direction angle between adjacent skeleton segments, and statistically analyzes the concentration of the overall direction angle distribution. The routing direction consistency descriptor is generated based on the consistency of the direction angle change. The fracture gap descriptor detects discontinuous regions along the main axis in the trace segment instance, calculates the spatial distance between adjacent continuous trace endpoints, and generates the fracture gap descriptor by combining the number of fracture regions and the maximum gap scale. The solder joint feature set, pin feature set, and trace segment feature set are indexed and bound to the corresponding aligned device candidate region set, and coordinate backfilling is performed to generate a fine-grained detection entity set.

[0019] In this embodiment, the generation of the fine-grained multi-relationship circuit structure diagram and the circuit feasible gating matrix specifically includes: Obtain a fine-grained set of detected entities, perform entity deduplication and entity consistency verification, and generate a set of entity validity verification results and a fine-grained entity index table; The fine-grained entity index table assigns a unique entity identifier to each detected entity and records the entity type label, entity geometric position label, and the index position of the corresponding feature vector, forming a structured fine-grained entity index result; A set of spatial adjacency candidate pairs is generated by performing spatial retrieval of detected entities based on a fine-grained entity index table within the same aligned set of device candidate regions. The Euclidean distance, azimuth difference, and consistency of constraints of the detected entities are integrated to generate a set of spatial adjacency candidate pair attributes. Based on the set of spatial adjacency candidate pairs, perform spatial adjacency domain filtering to obtain the set of spatial adjacency relations and the set of spatial adjacency edge attributes; The spatial adjacency domain filtering method includes filtering candidate pairs within the same device candidate region according to Euclidean distance threshold, azimuth difference threshold and entity type matching rules, and registering the filtered candidate pairs as undirected spatial adjacency edges. Obtain the component list and mounting coordinate information, combine the fine-grained entity index table to establish a set of device candidate identifiers for each detected entity, and register the theoretical pin positions, theoretical solder joint positions and device outline boundary information in the device positioning baseline set to form a set of consistency basis for device candidate attribution. Based on the consistency criteria set of device candidate attribution and the fine-grained entity index table, an electrical connection relationship set is constructed, and a connection type label, an endpoint entity type label, and endpoint geometric proximity evidence are registered for each electrical connection edge to generate an electrical connection edge attribute set. The set of electrical connection relationships includes the nearest neighbor connection edge from the pin to the solder joint, the access connection edge from the solder joint to the trace segment, and the continuous connection edge between the trace segments; Based on the set of electrical connection edge attributes, electrical network conflict suppression is performed to obtain a set of conflict suppression results for the set of electrical connection relationships. Cross-device conflict elimination is performed on electrical connection edges in the cross-device candidate belonging set to generate a set of conflict-suppressed electrical connection relationships. The electrical network conflict suppression includes determining conflicts among multiple electrical connection edges of the same detection entity and retaining electrical connection edges that satisfy the shortest connection distance and type consistency. Fine-grained multi-relationship circuit structure diagrams are generated based on the conflict-suppressed set of electrical connection relationships and the set of spatial adjacency relationships. The fine-grained multi-relation circuit structure diagram includes a multi-relation adjacency structure constructed from the electrical connection relationship set and the spatial adjacency relationship set, respectively, and a node feature structure and edge attribute structure corresponding to the fine-grained entity index table; A circuit feasibility gating matrix is ​​generated based on the set of consistency criteria for device candidate attribution, the set of conflict-suppressed electrical connection relationships, and the set of spatial adjacency relationships. The circuit feasible gating matrix uses the detected entities in the fine-grained entity index table as row indexes and the pooled cluster candidate indexes as column indexes. Entity-cluster candidate combinations that do not meet the device candidate attribution consistency rule, electrical network conflict suppression rule, or spatial adjacency domain rule are assigned a value of zero, while entity-cluster candidate combinations that meet the three rules are assigned a value of one.

[0020] In this embodiment, the generation of the abnormal evidence set and the abnormal complexity index specifically includes: Obtain a fine-grained multi-relation circuit structure diagram, perform alignment encoding on the node feature structure and edge attribute structure based on the fine-grained entity index table, generate a fine-grained initial node representation set and a multi-relation edge attribute representation set, and write them into the fine-grained multi-relation circuit structure diagram to form the encoded fine-grained multi-relation circuit structure diagram; The encoded fine-grained multi-relation circuit structure diagram is input into the multi-relation perception graph neural network encoder. Electrical relationship message passing and spatial relationship message passing are performed on the adjacency structures corresponding to the electrical connection relationship set and the spatial adjacency relationship set, respectively. Electrical neighborhood aggregation representation and spatial neighborhood aggregation representation are generated for each detected entity, and electrical relationship update node representation set and spatial relationship update node representation set are generated. The multi-relation perception graph neural network encoder adopts a hierarchical structure with shared input alignment and parallel relation branches. It performs unified alignment encoding on the node feature structure and edge attribute structure in the fine-grained multi-relation circuit structure graph, generates a fine-grained initial node representation set, and sets up mutually independent electrical relation message passing branches and spatial relation message passing branches. The two branches work in parallel on the same node set but only perceive their respective adjacency structures. Neighborhood aggregation, normalization constraints and residual superposition are performed within each branch. The electrical relation update node representation set and the spatial relation update node representation set output by each branch maintain the same dimension and index order in structure. The electrical relationship message passing process involves retrieving only the electrical connection edges directly connected to each detected entity from the electrical connection relationship set to form an electrical neighborhood. Adjacency weights are generated based on the connection type markers recorded in the electrical connection edges and the geometric proximity evidence of the endpoints. The node representations of adjacent detected entities within the neighborhood are then weighted and aggregated to obtain the electrical neighborhood aggregated representation and update it to form the electrical relationship update node representation set. The spatial relationship message passing is for each detected entity. It only retrieves undirected adjacent edges that satisfy the spatial adjacency domain rule from the spatial adjacency relationship set to form a spatial neighborhood. Based on the Euclidean distance, azimuth difference and device constraint consistency in the spatial adjacent edge attributes, a spatial propagation weight is generated. The node representations of adjacent detected entities in the neighborhood are weighted and aggregated to obtain the spatial neighborhood aggregated representation and update to form a spatial relationship update node representation set. Perform multi-relation consistency fusion on the electrical relation update node representation set and the spatial relation update node representation set to generate a fine-grained fused node representation set; The multi-relation consistency fusion includes performing consistency calibration on the electrical neighborhood aggregation representation and the spatial neighborhood aggregation representation based on the edge attribute structure, generating a multi-relation fusion weight set based on the consistency calibration results, and performing weighted fusion on the electrical relationship update node representation and the spatial relationship update node representation of the same detected entity. Based on the fine-grained fusion node representation set, multi-layer stacked encoding and normalization constraints are performed to generate a fine-grained structural representation set; The multi-layer stacked coding performs residual superposition with the output of the previous coding layer on the set of node representations in the output layer of each coding layer, and performs scale consistency constraints on the node representation amplitude and the neighborhood aggregate response in the normalization constraint. Generate anomaly evidence sets based on fine-grained structural representation sets; The set of abnormal evidence includes visual anomaly intensity, connectivity anomaly count, and number of abnormal connected components. The visual anomaly intensity is obtained by aggregating the abnormal responses corresponding to the solder joint feature set, pin feature set, and trace segment feature set in the fine-grained structural characterization set. The connectivity anomaly count is obtained by statistically analyzing the conflict between endpoint geometric proximity evidence and connection type markers in the electrical connection relationship set. The number of abnormal connected components is obtained by statistically analyzing the connected domain decomposition of abnormal response nodes on the electrical connection relationship set and the spatial adjacency relationship set. Calculate the set of abnormal complexity indices based on the set of abnormal evidence, and bind them to the set of abnormal evidence to form the result of the abnormal complexity index. The set of anomaly complexity indices is obtained by weighted summation of visual anomaly intensity, connectivity anomaly count, and number of anomalous connected components. The weight corresponding to visual anomalies is calculated based on the mean and high quantile percentage of visual anomaly intensity in the fine-grained detection entity set. The weight corresponding to connectivity anomalies is calculated based on the proportion of anomalous connections in the electrical connection relationship set to the total number of connections. The weight corresponding to anomalous connected components is calculated based on the proportion of anomalous connected components to the total number of connected components.

[0021] In this embodiment, the generation of the fine-grained allocation matrix specifically includes: Obtain the abnormal complexity index results, read the abnormal complexity index set and determine the number of pooling clusters, and generate the defect-sensitive cluster configuration; The pooling cluster count is statistically analyzed based on the overall distribution of the abnormal complexity index set on the fine-grained detection entity set. The concentration and dispersion of the abnormal complexity index in all detection entities are calculated, and a subset of detection entities with high abnormal complexity indices are identified. Based on the connectivity distribution of the high abnormal complexity detection entity subset in the fine-grained multi-relationship circuit structure diagram, the number of abnormal connected components formed by the abnormal detection entities in the electrical connection relationship set and the spatial adjacency relationship set is counted. The number of abnormal connected components is used as the basic candidate number of pooling clusters. Combined with the distribution density of normal detection entities in the fine-grained multi-relationship circuit structure diagram, the basic candidate number is compensated and adjusted, increasing the pooling cluster count corresponding to abnormally dense regions and decreasing the pooling cluster count corresponding to abnormally sparse regions, thereby generating a target pooling cluster count that matches the abnormal spatial distribution. The defect-sensitive cluster number configuration is based on the target pooling cluster number. The consistency between the target pooling cluster number and the device candidate affiliation is verified by a consistency set to ensure that each pooling cluster candidate index only covers the detection entities within the same device candidate affiliation set, thus forming a defect-sensitive cluster number configuration that includes the target pooling cluster number, cluster capacity upper limit constraint, and cluster entity affiliation constraint. Obtain the circuit feasible gating matrix and the fine-grained structure representation set, configure and initialize the pooling cluster candidate index set based on the number of defect-sensitive clusters, and align the indexes with the circuit feasible gating matrix to generate a gating alignment result set; The set of gated alignment results is used to limit the detection entities in the fine-grained entity index table to pooling cluster candidate indices with a value of one in the circuit feasible gate matrix; In the defect-sensitive hierarchical pooling mechanism based on DiffPool, an electrical allocation matrix is ​​generated according to the set of fine-grained structural representations and the set of electrical connection relationships. The electrical assignment matrix is ​​formed by aggregating the fine-grained structural representation set of each detected entity in the electrical neighborhood corresponding to the electrical connection relationship set, thus forming an electrical neighborhood assignment preference set. Based on the electrical neighborhood assignment preference set, the support strength, connection type consistency, and overall consistency of the endpoint geometric proximity evidence of the pooling cluster candidate index set in the electrical neighborhood are comprehensively evaluated to generate an electrical assignment score set. Based on the gating alignment result set, gating suppression is performed on the electrical assignment score set, and assignment scores that do not meet the circuit feasible gating matrix constraints are set to unselectable. Normalization mapping is performed on the gating electrical assignment score set to obtain the electrical assignment matrix. In the defect-sensitive hierarchical pooling mechanism based on DiffPool, a spatial allocation matrix is ​​generated based on the set of fine-grained structural representations and the set of spatial adjacency relationships. The spatial allocation matrix is ​​formed by aggregating the fine-grained structural representation set of each detected entity in the spatial neighborhood corresponding to the spatial adjacency relationship set, forming a spatial neighborhood assignment preference set. Based on the spatial neighborhood assignment preference set, the support density, relative orientation consistency and spatial distance stability of the pooling cluster candidate index set in the spatial neighborhood are comprehensively evaluated to generate a spatial assignment score set. Based on the gating alignment result set, gating suppression is performed on the spatial assignment score set, and the assignment score that does not meet the circuit feasible gating matrix constraint is set to unselectable. Normalization mapping is performed on the gating spatial assignment score set to obtain the spatial allocation matrix. Based on the circuit feasibility gate matrix, the electrical allocation matrix and the spatial allocation matrix are fused to generate a fine-grained allocation matrix. The consistency fusion includes performing consistency judgment rule verification on the same detection entity assignment results of the electrical assignment matrix and the spatial assignment matrix, including conflict cluster prohibition merging rules and conflict edge suppression rules. When there is a cross-cluster electrical connection conflict in the electrical connection relationship set or a cross-cluster spatial adjacency conflict in the spatial adjacency relationship set, it is prohibited to assign the corresponding conflict endpoint detection entity to the same pooling cluster candidate index. When the endpoint geometric proximity evidence and connection type label in the electrical connection relationship set trigger a conflict, the assignment path that causes the conflict is suppressed and backed to the suboptimal assignment allowed by the gating alignment result set. During the fusion process, the circuit feasible gating matrix is ​​kept as the only legality constraint entry for generating the assignment matrix, and a fine-grained assignment matrix that satisfies the gating constraints and consistency judgment rules is obtained. Based on the fine-grained allocation matrix, cluster-level feasibility verification and cluster number consistency verification are performed to generate a set of allocation feasibility verification results; The cluster-level feasibility review performs device candidate attribution consistency review, electrical network conflict suppression review and spatial adjacency domain review on the cluster detection entity set of each pooling cluster candidate index. The cluster number consistency review includes consistency verification between the number of actually activated pooling cluster candidate indices in the fine-grained allocation matrix and the target number of pooling clusters in the defect-sensitive cluster number configuration. The fine-grained allocation matrix is ​​indexed and bound to the set of allocation feasibility verification results to form the fine-grained allocation matrix index result and output it.

[0022] In this embodiment, the generation of the device-level defect determination result specifically includes: Obtain the fine-grained allocation matrix index results, fine-grained structure representation set and fine-grained multi-relation circuit structure diagram. Based on the fine-grained allocation matrix, determine the pooling cluster candidate index belonging to each detected entity on the row index of the fine-grained entity index table, and generate the cluster-in-cluster detection entity set and the cluster-in-cluster index binding result set. Based on the cluster index binding result set, perform intra-cluster aggregation on the fine-grained structural representation set, weighted convergence of the fine-grained structural representation of the detected entities within the cluster according to the pooling cluster candidate index and perform amplitude normalization to generate the pooling cluster node representation set, and register it as the device-level structural representation set. Based on the set of detected entities within a cluster and the set of electrical connection relationships in the fine-grained multi-relation circuit structure diagram, a relational mapping is performed to map cross-cluster electrical connection edges to electrical inter-cluster connection edges between pooled cluster candidate indices. The connection type label and endpoint geometric proximity evidence are aggregated to generate an electrical inter-cluster edge attribute set, resulting in a device-level electrical connection relationship set. Based on the set of detected entities within a cluster and the set of spatial adjacency relationships in the fine-grained multi-relationship circuit structure diagram, a relation mapping is performed. Cross-cluster spatial adjacency edges are mapped to spatial inter-cluster adjacency edges between pooled cluster candidate indices. Euclidean distance, azimuth angle difference, and consistency of constraints within the same device are aggregated to generate a set of spatial inter-cluster edge attributes, resulting in a device-level set of spatial adjacency relationships. A device-level multi-relationship circuit structure diagram is constructed based on the set of device-level electrical connection relationships, the set of edge attributes between electrical clusters, the set of device-level spatial adjacency relationships, and the set of edge attributes between spatial clusters. The device-level multi-relation circuit structure diagram includes a multi-relation adjacency structure constructed from the device-level electrical connection relationship set and the device-level spatial adjacency relationship set, as well as a node feature structure and a device-level edge attribute structure corresponding to the device-level structure representation set; The device-level multi-relationship circuit structure diagram and the device-level structural representation set are input into the device-level defect judgment process. Based on the device-level electrical connection relationship set and the device-level spatial adjacency relationship set, the device-level structural representation set is subjected to multi-relationship consistent aggregation to generate the device-level defect judgment representation set. The device-level defect judgment result is output based on the device-level defect judgment representation set. The device-level defect determination result is obtained by using the pooling cluster candidate index in the device-level multi-relation circuit structure diagram as the index unit in the device-level defect determination characterization set. Defect determination mapping is performed on the device-level structural characterization corresponding to each pooling cluster. Based on the consistency of its electrical relationship aggregated response intensity and spatial relationship aggregated response, the corresponding device-level abnormal response value is generated. The abnormal response value is aligned and fused with the visual abnormality intensity, connectivity abnormality count and abnormal connectivity component number already indexed and bound in the abnormal evidence set to form the device-level abnormality score result. According to the relative sorting distribution of the device-level abnormality score result on all pooling cluster candidate indices and the threshold interval division rule, the device-level structural characterization is determined to have a defect status. The output device-level defect determination result includes normal status, suspected defect status and confirmed defect status. The threshold interval division rule and the abnormal complexity index result maintain consistency constraints to ensure the interlayer consistency between the device-level defect determination result and the fine-grained abnormal distribution. The device-level defect determination results are bound to the cluster-specific index binding result set to which the pooling cluster candidate index belongs, thus forming the device-level defect determination index result.

[0023] In this embodiment, the generation of the component circuit board defect detection results specifically includes: Obtain the fine-grained allocation matrix index result, the abnormal evidence set, and the fine-grained entity index table. Based on the fine-grained allocation matrix index result, determine the pooling cluster candidate index belonging to each detected entity on the row index of the fine-grained entity index table, generate the abnormal evidence cluster belonging mapping result set, and align it with the abnormal evidence set to obtain the cluster-aligned abnormal evidence set. Based on the cluster-aligned anomaly evidence set, cluster-level aggregation is performed on the anomaly evidence set to generate a pooled cluster anomaly vector set, which is then indexed and bound to the pooled cluster candidate index to form the pooled cluster anomaly estimation result. The cluster-level aggregation performs intra-cluster aggregation and amplitude normalization on the three fields of visual anomaly intensity, connectivity anomaly count, and number of anomalous connectivity components for the detected entities to which the candidate index of the same pooling cluster belongs. Based on the device-level defect judgment index results, the device-level defect judgment results and the pooling cluster anomaly estimation results are aligned on the pooling cluster candidate index dimension to generate an inter-layer alignment result set. The interlayer alignment result set includes device-level defect status items and pooling cluster anomaly vector items aligned according to pooling cluster candidate indices; Based on the inter-layer alignment result set, inter-layer mutual verification consistency determination is performed. Consistency scores are calculated for the device-level defect status item and the pooling cluster anomaly vector item of the same pooling cluster candidate index, and a consistency score set is formed. The set is then bound to the pooling cluster candidate index to obtain the mutual verification consistency index result. The consistency score is obtained by weighted aggregation of the visual consistency component, the connectivity consistency component, and the structural consistency component. The visual consistency component is obtained by the matching degree between the intensity of visual anomalies in the pooling cluster anomaly vector set and the device-level defect state item. The connectivity consistency component is obtained by the matching degree between the count of connectivity anomalies in the pooling cluster anomaly vector set and the device-level defect state item. The structural consistency component is obtained by the matching degree between the number of abnormal connectivity components in the pooling cluster anomaly vector set and the device-level defect state item. The consistency component weights inherit the weights corresponding to visual anomalies, connectivity anomalies, and abnormal connectivity components in the anomaly complexity index result and are then normalized. Based on the mutual verification consistency index results, mutual verification trigger screening is performed. Pooling cluster candidate indices whose consistency scores do not meet the threshold interval division rules are registered as conflict cluster sets. From the conflict cluster set, their adjacent pooling cluster candidate indices in the device-level multi-relation circuit structure diagram are traced back to form a conflict expansion cluster set, generating a local repooling trigger result set. Local repooling is triggered on the result set of local repooling to obtain the locally updated fine-grained allocation matrix, and the fine-grained allocation matrix index result is written back to form the updated fine-grained allocation matrix index result; The local repooling is based on extracting the corresponding conflict subgraphs from the conflict cluster set and the conflict extended cluster set in the fine-grained multi-relation circuit structure diagram. The detected entities in the conflict subgraphs are locked as the local repooling entity set. The defect sensitive cluster number configuration and circuit feasible gating matrix are called to re-execute the gating alignment result set generation, electrical allocation matrix generation, spatial allocation matrix generation and consistency fusion on the local repooling entity set to obtain the locally updated fine-grained allocation matrix. Based on the updated fine-grained allocation matrix index results, the device-level defect judgment index results are updated synchronously. The pooling cluster anomaly estimation results generation and inter-layer mutual verification consistency judgment are re-executed. The device-level defect judgment results and pooling cluster anomaly estimation results constrained by the mutual verification consistency index results are output, and the index binding is performed to form the component circuit board defect detection results.

[0024] Example 1: To verify the feasibility of this invention in practice, it was applied to a component circuit board quality inspection scenario in an electronics manufacturing company. In this scenario, the production line uses automated optical inspection equipment to continuously collect data on circuit boards that have been mounted and soldered. The circuit boards simultaneously contain high-density components, fine traces, and various soldering patterns. Traditional methods that rely on single image features or local rules are difficult to consider the structural relationships between solder joints, pins, and traces, and are prone to problems such as misjudgments concentrated in local areas or inaccurate attribution after defects spread, making it difficult to guarantee the stability and consistency of the inspection.

[0025] In practical applications, automated optical inspection images, component lists, and mounting coordinate information are simultaneously introduced into the processing flow. Image processing and feature extraction form fine-grained inspection entities, and based on this, a multi-relationship circuit structure representation reflecting electrical connections and spatial adjacency is constructed. Subsequently, a multi-relationship-aware graph neural network is used to jointly model the fine-grained structure, simultaneously characterizing visual anomalies, connectivity anomalies, and structural anomalies within the same framework, generating a comprehensive characterization result that reflects the complexity of the anomaly distribution. In subsequent processing, the pooling level is adaptively adjusted according to the anomaly distribution characteristics, rationally aggregating fine-grained information into the device-level structural space. Simultaneously, circuit feasibility constraints are used to limit the aggregation results, avoiding merging cases that do not conform to electrical or spatial logic.

[0026] During the detection process, fine-grained anomaly clues and device-level judgment results are continuously verified through an inter-layer mutual verification mechanism. When inconsistencies exist in a local area, a re-aggregation update for that area is automatically triggered, thereby achieving targeted correction of the anomaly area. Through continuous operation in actual production cycles, it can be observed that this method maintains stable judgment behavior on different batches and circuit boards with different structural complexities. It can provide consistent detection feedback for both local minor defects and structural anomalies, effectively reducing the propagation of misjudgments and the need for repeated verification, thus verifying the feasibility and practical value of this invention in real-world application environments.

[0027] Table 1. Overall Performance Comparison of Component and Circuit Board Defect Detection Methods

[0028] The defect detection accuracy shows that traditional rule-based methods are significantly limited in scenarios with complex solder joints and high-density traces, resulting in low accuracy. While the introduction of convolutional neural networks enhances image-level recognition capabilities, the lack of systematic modeling of electrical connections and spatial structures still leads to the accumulation of localized false positives. The method of this invention achieves 98.47% accuracy in this metric, an improvement of over 6 percentage points compared to traditional methods, demonstrating a significant advantage in overall reliability.

[0029] In terms of defect recall, the method of this invention shows a significant advantage, reaching 97.35%, which is 3.14 percentage points higher than the single-relationship graph neural network method. This improvement stems from the multi-relationship circuit structure modeling mechanism, which enables anomalies between solder joints, pins, and traces to propagate jointly through electrical relationships and spatial adjacency relationships, avoiding the missed detection problem caused by relying on a single neighborhood, and is particularly sensitive to structural defects.

[0030] False alarm rate is one of the key indicators for measuring engineering usability. As can be seen from the table, the false alarm rate of the method of this invention is reduced to 1.96%, which is significantly lower than other comparative methods. This is mainly due to the constraint effect of the circuit feasibility gating matrix on the allocation process, and the subsequent inter-layer mutual verification consistency mechanism for verifying and backing up abnormal results, which effectively suppresses abnormal responses that do not conform to electrical or spatial logic, thereby reducing the generation of false alarms.

[0031] In terms of device-level consistency index, the method of this invention achieves 98.12%, which is significantly better than other methods. This result shows that by using defect-sensitive hierarchical pooling and device-level multi-relation structure reconstruction, not only is a stable mapping from fine-grained to device level achieved, but logical consistency between decision results at different levels is also guaranteed, avoiding problems such as local amplification or mispropagation across devices.

[0032] From the perspective of processing latency, the method of this invention increases the single-board processing latency after introducing multi-relation modeling and mutual verification updates, but it still remains within an acceptable range. Combined with its comprehensive improvement in accuracy, recall, and consistency, this time overhead is traded for higher detection reliability and engineering stability, demonstrating a significant performance-to-price ratio advantage.

[0033] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for detecting defects in circuit boards based on graph neural networks, characterized in that, Includes the following steps: Acquire automatic optical inspection images of component circuit boards, component lists and mounting coordinate information, extract solder joint feature sets, pin feature sets and trace segment feature sets to form a fine-grained inspection entity set; Based on the fine-grained detection entity set, an electrical connection relationship set and a spatial adjacency relationship set are constructed, and a fine-grained multi-relationship circuit structure diagram is generated. Based on the component list and mounting coordinate information, a circuit feasibility gating matrix is ​​generated. The fine-grained multi-relation circuit structure diagram is input into the multi-relation perceptual graph neural network encoder to obtain a set of fine-grained structure representations and generate an abnormal evidence set and an abnormal complexity index. In the defect-sensitive hierarchical pooling mechanism based on DiffPool, the number of pooling clusters is determined according to the abnormal complexity index and the defect-sensitive cluster configuration is generated. Based on the circuit feasibility gating matrix, the allocation matrix is ​​generated for the electrical connection relationship set and the spatial adjacency relationship set respectively and then fused in a consistent manner to obtain the fine-grained allocation matrix. Based on the fine-grained allocation matrix, the fine-grained structural representation set and the fine-grained multi-relation circuit structure diagram are aggregated to generate a device-level multi-relation circuit structure diagram and a device-level structural representation set, and the device-level defect judgment result is output. Based on the fine-grained allocation matrix, the set of abnormal evidence is aggregated to generate pooled cluster anomaly estimation results, and inter-layer mutual verification consistency determination is performed with the device-level defect determination results. This triggers local repooling to update the fine-grained allocation matrix and the device-level defect determination results, and outputs the component circuit board defect detection results.

2. The component circuit board defect detection method based on graph neural network according to claim 1, characterized in that, The generation of the fine-grained detection entity set specifically includes: Acquire automatic optical inspection images of component circuit boards, component list and placement coordinate information, perform consistency verification on component list and placement coordinate information, and generate a set of coordinate validity verification results and a set of component positioning baselines; Based on the set of coordinate validity verification results, geometric correction, distortion correction and illumination normalization are performed on the automatic optical inspection image to generate a set of corrected automatic optical inspection images. Background baseline map and noise suppression mask set are generated in the set of corrected automatic optical inspection images. Based on the device localization baseline set, device candidate region generation is performed in the corrected automatic optical inspection image set, and boundary clipping and rotation alignment are performed to generate an aligned device candidate region set. In the aligned device candidate region set, candidate region extraction is performed in conjunction with the noise suppression mask set to generate solder joint candidate region set, pin candidate region set and trace segment candidate region set respectively. Then, connected component decomposition and morphological consistency screening are performed to generate solder joint instance set, pin instance set and trace segment instance set. Based on the set of solder joint instances, the solder joint morphology description, reflection anomaly description, and boundary continuity description are calculated to form a solder joint feature set; Based on the set of pin instances, calculate the pin position offset descriptor, pin spacing consistency descriptor, and endpoint integrity descriptor to form a pin feature set; Based on the set of trace segment instances, calculate the trace width stability descriptor, trace direction consistency descriptor, and break gap descriptor to form a trace segment feature set; The solder joint feature set, pin feature set, and trace segment feature set are indexed and bound to the corresponding aligned device candidate region set, and coordinate backfilling is performed to generate a fine-grained detection entity set.

3. The component circuit board defect detection method based on graph neural networks according to claim 1, characterized in that, The generation of the fine-grained multi-relational circuit structure diagram and the circuit feasible gating matrix specifically includes: Obtain a fine-grained set of detected entities, perform entity deduplication and entity consistency verification, and generate a set of entity validity verification results and a fine-grained entity index table; A set of spatial adjacency candidate pairs is generated by performing spatial retrieval of detected entities based on a fine-grained entity index table within the same aligned set of device candidate regions. The Euclidean distance, azimuth difference, and consistency of constraints of the detected entities are integrated to generate a set of spatial adjacency candidate pair attributes. Based on the set of spatial adjacency candidate pairs, perform spatial adjacency domain filtering to obtain the set of spatial adjacency relations and the set of spatial adjacency edge attributes; Obtain the component list and mounting coordinate information, combine the fine-grained entity index table to establish a set of device candidate identifiers for each detected entity, and register the theoretical pin positions, theoretical solder joint positions and device outline boundary information in the device positioning baseline set to form a set of consistency basis for device candidate attribution. Based on the consistency criteria set of device candidate attribution and the fine-grained entity index table, an electrical connection relationship set is constructed, and a connection type label, an endpoint entity type label, and endpoint geometric proximity evidence are registered for each electrical connection edge to generate an electrical connection edge attribute set. Based on the set of electrical connection edge attributes, electrical network conflict suppression is performed to obtain a set of conflict suppression results for the set of electrical connection relationships. Cross-device conflict elimination is performed on electrical connection edges in the cross-device candidate belonging set to generate a set of conflict-suppressed electrical connection relationships. Fine-grained multi-relationship circuit structure diagrams are generated based on the conflict-suppressed set of electrical connection relationships and the set of spatial adjacency relationships. A circuit feasibility gating matrix is ​​generated based on the set of consistency criteria for device candidate attribution, the set of conflict-suppressed electrical connection relationships, and the set of spatial adjacency relationships.

4. The method for detecting defects in circuit boards based on graph neural networks according to claim 1, characterized in that, The generation of the anomalous evidence set and the anomalous complexity index specifically includes: Obtain a fine-grained multi-relation circuit structure diagram, perform alignment encoding on the node feature structure and edge attribute structure based on the fine-grained entity index table, generate a fine-grained initial node representation set and a multi-relation edge attribute representation set, and write them into the fine-grained multi-relation circuit structure diagram to form the encoded fine-grained multi-relation circuit structure diagram; The encoded fine-grained multi-relation circuit structure diagram is input into the multi-relation perception graph neural network encoder. Electrical relationship message passing and spatial relationship message passing are performed on the adjacency structures corresponding to the electrical connection relationship set and the spatial adjacency relationship set, respectively. Electrical neighborhood aggregation representation and spatial neighborhood aggregation representation are generated for each detected entity, and electrical relationship update node representation set and spatial relationship update node representation set are generated. Perform multi-relation consistency fusion on the electrical relation update node representation set and the spatial relation update node representation set to generate a fine-grained fused node representation set; Based on the fine-grained fusion node representation set, multi-layer stacked encoding and normalization constraints are performed to generate a fine-grained structural representation set; Generate anomaly evidence sets based on fine-grained structural representation sets; Calculate the set of abnormal complexity indices based on the set of abnormal evidence, and bind them to the set of abnormal evidence to form the result of the abnormal complexity index.

5. The method for detecting defects in circuit boards based on graph neural networks according to claim 1, characterized in that, The generation of the fine-grained allocation matrix specifically includes: Obtain the abnormal complexity index results, read the abnormal complexity index set and determine the number of pooling clusters, and generate the defect-sensitive cluster configuration; Obtain the circuit feasible gating matrix and the fine-grained structure representation set, configure and initialize the pooling cluster candidate index set based on the number of defect-sensitive clusters, and align the indexes with the circuit feasible gating matrix to generate a gating alignment result set; In the defect-sensitive hierarchical pooling mechanism based on DiffPool, an electrical allocation matrix is ​​generated according to the set of fine-grained structural representations and the set of electrical connection relationships. In the defect-sensitive hierarchical pooling mechanism based on DiffPool, a spatial allocation matrix is ​​generated based on the set of fine-grained structural representations and the set of spatial adjacency relationships. Based on the circuit feasibility gate matrix, the electrical allocation matrix and the spatial allocation matrix are fused to generate a fine-grained allocation matrix. Based on the fine-grained allocation matrix, cluster-level feasibility verification and cluster number consistency verification are performed to generate a set of allocation feasibility verification results; The fine-grained allocation matrix is ​​indexed and bound to the set of allocation feasibility verification results to form the fine-grained allocation matrix index result and output it.

6. The method for detecting defects in circuit boards based on graph neural networks according to claim 1, characterized in that, The generation of the device-level defect determination result specifically includes: Obtain the fine-grained allocation matrix index results, fine-grained structure representation set and fine-grained multi-relation circuit structure diagram. Based on the fine-grained allocation matrix, determine the pooling cluster candidate index belonging to each detected entity on the row index of the fine-grained entity index table, and generate the cluster-in-cluster detection entity set and the cluster-in-cluster index binding result set. Based on the cluster index binding result set, perform intra-cluster aggregation on the fine-grained structural representation set, weighted convergence of the fine-grained structural representation of the detected entities within the cluster according to the pooling cluster candidate index and perform amplitude normalization to generate the pooling cluster node representation set, and register it as the device-level structural representation set. Based on the set of detected entities within a cluster and the set of electrical connection relationships in the fine-grained multi-relation circuit structure diagram, a relational mapping is performed to map cross-cluster electrical connection edges to electrical inter-cluster connection edges between pooled cluster candidate indices. The connection type label and endpoint geometric proximity evidence are aggregated to generate an electrical inter-cluster edge attribute set, resulting in a device-level electrical connection relationship set. Based on the set of detected entities within a cluster and the set of spatial adjacency relationships in the fine-grained multi-relationship circuit structure diagram, a relation mapping is performed. Cross-cluster spatial adjacency edges are mapped to spatial inter-cluster adjacency edges between pooled cluster candidate indices. Euclidean distance, azimuth angle difference, and consistency of constraints within the same device are aggregated to generate a set of spatial inter-cluster edge attributes, resulting in a device-level set of spatial adjacency relationships. A device-level multi-relationship circuit structure diagram is constructed based on the set of device-level electrical connection relationships, the set of edge attributes between electrical clusters, the set of device-level spatial adjacency relationships, and the set of edge attributes between spatial clusters. The device-level multi-relationship circuit structure diagram and the device-level structural representation set are input into the device-level defect judgment process. Based on the device-level electrical connection relationship set and the device-level spatial adjacency relationship set, the device-level structural representation set is subjected to multi-relationship consistent aggregation to generate the device-level defect judgment representation set. The device-level defect judgment result is output based on the device-level defect judgment representation set. The device-level defect determination results are bound to the cluster-specific index binding result set to which the pooling cluster candidate index belongs, thus forming the device-level defect determination index result.

7. The method for detecting defects in circuit boards based on graph neural networks according to claim 1, characterized in that, The generation of the component circuit board defect detection results specifically includes: Obtain the fine-grained allocation matrix index result, the abnormal evidence set, and the fine-grained entity index table. Based on the fine-grained allocation matrix index result, determine the pooling cluster candidate index belonging to each detected entity on the row index of the fine-grained entity index table, generate the abnormal evidence cluster belonging mapping result set, and align it with the abnormal evidence set to obtain the cluster-aligned abnormal evidence set. Based on the cluster-aligned anomaly evidence set, cluster-level aggregation is performed on the anomaly evidence set to generate a pooled cluster anomaly vector set, which is then indexed and bound to the pooled cluster candidate index to form the pooled cluster anomaly estimation result. Based on the device-level defect judgment index results, the device-level defect judgment results and the pooling cluster anomaly estimation results are aligned on the pooling cluster candidate index dimension to generate an inter-layer alignment result set. Based on the inter-layer alignment result set, inter-layer mutual verification consistency determination is performed. Consistency scores are calculated for the device-level defect status item and the pooling cluster anomaly vector item of the same pooling cluster candidate index, and a consistency score set is formed. The set is then bound to the pooling cluster candidate index to obtain the mutual verification consistency index result. Based on the mutual verification consistency index results, mutual verification trigger screening is performed. Pooling cluster candidate indices whose consistency scores do not meet the threshold interval division rules are registered as conflict cluster sets. From the conflict cluster set, their adjacent pooling cluster candidate indices in the device-level multi-relation circuit structure diagram are traced back to form a conflict expansion cluster set, generating a local repooling trigger result set. Local repooling is triggered on the result set of local repooling to obtain the locally updated fine-grained allocation matrix, and the fine-grained allocation matrix index result is written back to form the updated fine-grained allocation matrix index result; Based on the updated fine-grained allocation matrix index results, the device-level defect judgment index results are updated synchronously. The pooling cluster anomaly estimation results generation and inter-layer mutual verification consistency judgment are re-executed. The device-level defect judgment results and pooling cluster anomaly estimation results constrained by the mutual verification consistency index results are output, and the index binding is performed to form the component circuit board defect detection results.

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