Chip pin position automatic identification control optimization method and system

Abstract

This invention discloses an automatic identification and control optimization method and system for chip pin positions, relating to the field of pin position identification and control technology. The method includes establishing a first pin position set; generating an optical flow displacement field based on pad pixel displacement under adjacent illumination conditions, and applying it to a set of pad center points to generate a pad displacement set; mapping the pad displacement set to the first pin position set to generate an optical flow-corrected pin position set, and returning it to the PCB conductive space to generate a virtual pin position set; and generating an input subset by performing illumination difference elimination and updating processing on the set of pad center points, and controlling the coverage ratio of the flux-covered pad point set to participate in optical flow generation control, thereby realizing the overall construction and correction process of pin positions. This solves the problems of uncharacterizable soldering offset caused by relying solely on geometric registration for virtual positioning of invisible pins in hybrid packages, and optical loss due to high flux reflection under multiple illumination conditions.

Description

Technical Field

[0001] This invention relates to the field of pin position recognition and control technology, and more specifically, to a method and system for automatic identification and control optimization of chip pin positions. Background Technology

[0002] In the current field of BGA / QFN hybrid package chip inspection, since pins are usually located at the bottom of the chip or inside the package, their actual positions cannot be obtained through direct imaging. Industrial vision systems typically employ indirect inference methods based on package models to locate pins. This method generally uses an industrial camera to acquire images of the chip and PCB pads under multi-light source conditions, combines this with package shape features to determine the chip orientation, and utilizes the theoretical pin array structure in a standard package model library to map the theoretical pin coordinates to the PCB pad array space, thereby indirectly constructing the position of invisible pins and generating virtual pin coordinates.

[0003] Existing technologies primarily rely on a "geometric registration + model mapping" approach to pin inference, based on the core assumption of a rigid correspondence between the chip package and the PCB pads. However, in actual BGA / QFN soldering, significant local deformation and offset phenomena occur between the pads and solder, such as lateral offset caused by solder collapse, local misalignment caused by solder joint misalignment, and center offset caused by pad contamination. This leads to discrepancies between the geometric model inference results and the actual electrical connection state. Furthermore, existing methods lack the ability to model local non-uniform changes during the soldering process, resulting in virtual pin positions that, while meeting geometric alignment conditions, fail to reflect the actual conduction state.

[0004] In other fields, dense optical flow field-constrained guided reconstruction methods in computer vision construct pixel-level motion vector fields by analyzing pixel grayscale changes at different time frames or under different imaging conditions. These fields are used to characterize the relationship between minute displacements and deformation propagation of the target structure, and further, key point position correction is achieved through structural constraints. This method has strong applicability in dynamic image registration, target tracking, and deformation recovery. Its core idea lies in using local pixel changes to construct a continuous spatial displacement field, thereby correcting the offset of key points. This idea has certain structural similarities to the response changes of pad areas under multiple illumination conditions, thus providing analogy and inspiration for pin position correction.

[0005] However, applying optical flow field constraint methods to BGA / QFN pad scenarios presents new technical challenges. On one hand, the pad structure itself is not a real moving body; the grayscale changes it produces under multi-source imaging originate only from variations in illumination and differences in reflection. Therefore, the "displacement" expressed by the optical flow field is essentially a pseudo-motion field, making it difficult to directly correspond to real physical offsets. On the other hand, flux residue areas exist on the pad surface, and their high reflectivity can lead to local abrupt grayscale changes, causing discontinuous jumps in the optical flow direction. This disrupts the spatial consistency of the displacement field and may even introduce directional deviations, resulting in systematic offset errors in the correction results.

[0006] Therefore, existing BGA / QFN invisible pin location inference technology is still largely based on "model geometry mapping". It cannot effectively integrate the local response change information of the pad under multiple lighting conditions. At the same time, it lacks the ability to correct the actual electrical connection state under complex soldering conditions (such as off-center soldering, flux coverage, solder collapse). This results in a structural difference between the virtual pin position and the actual conduction state, which affects the accuracy of subsequent soldering inspection and conduction consistency judgment.

[0007] To address the above problems, this invention proposes a solution. Summary of the Invention

[0008] To overcome the aforementioned deficiencies of the prior art, embodiments of the present invention provide an automatic identification and control optimization method and system for chip pin positions. By introducing a collaborative mechanism of pin position correction based on dense optical flow field constraints and pseudo-optical flow elimination based on pad structure anchor point constraints, the present invention addresses the issues of uncharacterizable soldering offset caused by relying solely on geometric registration for virtual positioning of invisible pins in hybrid packages, and optical loss due to high flux reflection under multi-light conditions.

[0009] To achieve the above objectives, the present invention provides the following technical solution: An automatic identification and control optimization method for chip pin positions includes the following steps: acquiring multi-source image sequences, extracting pad area edges and analyzing the set of pad center points, simultaneously marking the set of flux-covered pad points, and establishing a first pin position set; generating an optical flow displacement field based on pad pixel displacement under adjacent illumination conditions, and applying it to the set of pad center points to generate a pad displacement set; mapping the pad displacement set to the first pin position set to generate an optical flow-corrected pin position set, and returning it to the PCB conductive space to generate a virtual pin position set; the set of pad center points also includes, optionally, generating an updated set of pad center points by eliminating abnormal points based on illumination differences; the set of flux-covered pad points also includes, optionally, generating an optimal pad input subset based on coverage ratio control, and optimizing the original set of pad center points to participate in optical flow generation.

[0010] An automatic identification, control, and optimization system for chip pin positions includes an imaging modeling module, an optical flow driving module, a pin reconstruction module, an illumination filtering module, and a flux control module. The imaging modeling module acquires multi-source image sequences, extracts pad area edges, analyzes the set of pad center points, and simultaneously marks the set of flux-covered pad points to establish a first pin position set. The optical flow driving module generates an optical flow displacement field based on pad pixel displacements under adjacent illumination conditions and applies it to the set of pad center points to generate a pad displacement set. The pin reconstruction module maps the pad displacement set to the first pin position set to generate an optical flow-corrected pin position set and then returns it to the PCB conductive space to generate a virtual pin position set. The illumination filtering module optionally includes removing abnormal points based on illumination differences to generate an updated set of pad center points. The flux control module optionally generates an optimal pad input subset based on coverage ratio control and optimizes the original set of pad center points for optical flow generation.

[0011] An electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform an automatic chip pin position identification control optimization method as described in one of the above methods.

[0012] A computer-readable storage medium storing a computer program, which, when executed by a processor, implements an automatic identification and control optimization method for chip pin positions. The technical effects and advantages of the automatic identification and control optimization method and system for chip pin positions of this invention are as follows: 1. This invention introduces a key point position correction mechanism based on dense optical flow field constraints, which enables the local displacement information formed by the center point of the pad under multiple illumination conditions to be converted into a continuous spatial driving correction amount. This allows for point-by-point correction of the theoretical position of standard package pins, effectively compensating for the deviation between the geometric center of the pin and the actual electrical connection center under conditions such as solder collapse, off-center soldering, and local bridging. This improves the output result from the traditional "geometric alignment position" to an "electrical connection equivalent position" that is closer to the actual conduction state, significantly improving the positioning consistency and engineering adaptability of the virtual position inference of invisible pins in complex soldering deformation scenarios.

[0013] 2. This invention introduces pad structure anchor point constraints and a pseudo-optical flow elimination mechanism to confine the optical flow disturbances induced by the differences in multiple illuminations within the pad array topology. It also suppresses and eliminates optical flow components that do not conform to the propagation law of the array structure, thereby avoiding the optical flow assumption failure problem caused by the discontinuous structure of the pads. At the same time, it weakens the directional jumps and local noise diffusion caused by the high reflectivity of the flux, so that the effective displacement information only propagates between the stable pad structure anchor points. Ultimately, it improves the structural reliability and anti-reflection interference capability of the optical flow driven pin correction process, and can still stably generate reliable virtual pin position results under complex surface conditions. Attached Figure Description

[0014] Figure 1 This is a flowchart illustrating an automatic identification and control optimization method for chip pin positions according to the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0016] Example 1, Figure 1 The present invention provides an automatic identification and control optimization method for chip pin positions, comprising the following steps: S1, acquire multi-source image sequence, extract pad area edges and analyze pad center point set, simultaneously mark flux-covered pad point set, and establish first pin position set.

[0017] In this embodiment, the steps of acquiring multi-source image sequences, extracting pad region edges and analyzing pad center point sets, simultaneously marking flux-covered pad point sets, and establishing a first pin position set are as follows: The image sequence with different lighting angles in the multi-light source image sequence is processed frame by frame to achieve uniform lighting. The average gray value of the same non-pad background area is used as the reference, and each image is scaled proportionally so that all images are output as a normalized image sequence under a uniform brightness reference. Metal response pixel set is extracted from normalized image sequence. By calculating the difference between the maximum and minimum gray values ​​of the same pixel in all illuminated images, pixels with a difference greater than the median gray value of the background texture are defined as metal response pixels, and a set of candidate pad regions is generated. Perform connected pixel aggregation processing on the set of candidate pad regions, and merge spatially continuous metal response pixels into independent pad regions using the eight-neighbor pixel connection rule; For each pad region, contour closure processing is performed. By locally extending and connecting the boundary broken pixels, each pad region forms a closed contour region. The mean value of all pixel coordinates within the closed contour area is calculated to obtain the geometric center point in two-dimensional space, and a set of pad center points is generated. Extract the set of pixels in the pad area whose grayscale variation is lower than the median value of the background texture variation, and mark the center point of the pad corresponding to the pixel set as the set of flux-covered pad points; The chip's outer contour center point is matched with the set of pad center points to obtain the chip's translation and rotation transformation parameters. The theoretical pin coordinates in the standard package pin model are then mapped to the PCB coordinate space through this transformation to generate the first set of pin positions.

[0018] In this embodiment, the multi-light source image sequence is a set of images formed by successively illuminating the same PCB area with light sources located in different spatial orientations after the chip is mounted. The light source orientations include direct vertical light, low-angle oblique light, and lateral grazing light. Each lighting condition corresponds to one frame of image, thereby making the pad metal reflection characteristics present differentiated responses in different images.

[0019] In this embodiment, the illumination unification process is a process of normalizing and adjusting the overall brightness of images from different light sources. It is implemented by selecting a background area in the image that does not contain pads and chip structures, calculating the average gray level of this area in each frame of the image, and using this average gray level as a unified benchmark to adjust the brightness ratio of the entire image so that images under different illumination conditions have a comparable gray level representation basis.

[0020] In this embodiment, the non-pad background area is the area in the PCB image that does not contain metal pads, chip packages, or flux residue. This area is usually represented by the surface of a glass fiber substrate or solder mask layer, and its texture changes are relatively stable. It is used as a reference area for illumination normalization to avoid interference from the high reflectivity of the pads on the brightness reference.

[0021] In this embodiment, the metal response pixel is a pixel with a large grayscale variation at the same spatial location in a multi-light source image sequence under different lighting conditions. This variation is obtained by comparing the difference between the maximum and minimum brightness of the pixel in all lighting images, reflecting the metal reflection characteristics of the location that are sensitive to the lighting angle, and is used to distinguish the pad from the background area.

[0022] In this embodiment, the median value of the background texture grayscale difference is the value of the middle position after sorting the grayscale change amplitude of all pixels in the non-pad background area under multi-light source conditions. This value is used to characterize the normal illumination disturbance range of the background area, and thus serves as a reference benchmark to distinguish metal response pixels from background texture changes.

[0023] In this embodiment, the set of candidate pad regions is a set of regions formed by continuously merging metal response pixels in space according to their adjacency relationship. This merging process is expanded by the connectivity of pixels in the top, bottom, left, right and diagonal directions, so that the originally scattered high reflectivity pixels are aggregated into pad regions with spatially continuous boundaries.

[0024] In this embodiment, the eight-neighbor pixel connection rule is to take a certain pixel as the center in the image coordinates and consider whether the eight adjacent pixels in the eight directions of its top, bottom, left, right and four diagonal directions belong to the same response type. This is used to determine whether the pixels form a spatial continuous structure, thereby realizing the complete merging of the pad area.

[0025] In this embodiment, contour closure processing is a process of directional extension repair of pixel boundaries with breaks or gaps in the edge of the pad area. It is implemented by connecting the broken boundaries according to the local extension direction of the edge pixels, so that the pad area forms a closed geometric contour structure.

[0026] In this embodiment, the geometric center point of the pad is the center point obtained by converging the spatial positions of all pixel coordinates within the closed contour area. This center point represents the geometric centroid of the pad in the image coordinate system and is used as the spatial reference for subsequent pin position mapping.

[0027] In this embodiment, the set of flux-covered pad points is the set of center points of the pads corresponding to areas where the local grayscale change amplitude is significantly reduced and the reflection edge is unclear within the pad area. This feature is usually formed by the weakening or diffusion of metal reflection caused by flux coverage, and is used to mark areas where the reliability of the pads is reduced.

[0028] In this embodiment, the center point of the chip's outer contour is a point obtained by extracting the external geometric boundary of the chip package and calculating its overall spatial center position. This point is used to establish the chip package coordinate reference, thereby achieving spatial alignment between the chip and the PCB pads.

[0029] In this embodiment, nearest neighbor matching is a process of taking the center point of the chip's outer contour as the reference origin, calculating the spatial distance relationship for each point in the set of pad center points, and taking the pad point with the smallest distance as the corresponding matching object, which is used to establish the spatial correspondence between the chip and the PCB.

[0030] In this embodiment, the standard package pin model is a pre-stored chip package structure data model, which contains the theoretical spatial distribution of pins under different package types. This model is used to generate the theoretical projection position of the pins in the PCB coordinate system after spatial alignment.

[0031] In this embodiment, the translation and rotation transformation parameters are spatial transformation relationships calculated based on the spatial correspondence between the outer contour of the chip and the center point of the pad. These parameters are used to describe the positional offset and angular deflection of the chip package on the PCB, thereby realizing the spatial mapping from the package model to the actual mounting state.

[0032] It should be noted that the above processing flow enhances the metal response characteristics of the pads by using multi-source image differences and combines it with the reconstruction of the structural integrity of the pad area, so that the set of pad center points can stably reflect the actual spatial distribution of the pads. At the same time, the flux coverage marking is used to identify and isolate the abnormal reflection areas, thereby avoiding interference with the subsequent pin position mapping.

[0033] It should be noted that multi-source grayscale difference analysis is introduced during the pad extraction process, so that pad recognition does not depend on a single lighting condition. This improves the stable extraction capability of pad areas under high reflection or partial occlusion conditions and provides a reliable foundation for subsequent chip and PCB space registration.

[0034] It should be noted that the beneficial effect of this technology is that by using multi-source joint modeling and pad structure reconstruction, the invisible pin problem is transformed into a spatial mapping problem based on the center point of the pad. At the same time, a flux coverage area identification mechanism is introduced to isolate abnormal reflection areas, so that the final generated first pin position set has higher reliability in terms of spatial consistency and computability.

[0035] S2 generates an optical flow displacement field based on the pixel displacement of the pads under adjacent illumination conditions, and applies it to the set of center points of the pads to generate a set of pad displacements.

[0036] In this embodiment, the step of generating an optical flow displacement field based on the pad pixel displacement under adjacent illumination conditions and applying it to the set of pad center points to generate a set of pad displacements specifically involves: Pixel-wise grayscale difference processing is performed on the first and second images corresponding to adjacent lighting conditions in the normalized image sequence to generate a difference grayscale image; Extract the direction of gray-level change in the neighborhood of each pixel position in the differential grayscale image with a preset dimension, and encode the direction of gray-level increase and gray-level decrease in the neighborhood into direction vectors respectively to generate a set of pixel direction vectors; A spatial consistency expansion process is performed on the set of pixel orientation vectors, which merges vectors with the same orientation and adjacent distances less than a preset pixel spacing threshold in the two-dimensional coordinate space to generate an initial set of optical flow vector units. The initial optical flow vector unit set is spatially pruned according to the boundary of the pad candidate region, retaining only the vector units located inside the pad candidate region, to generate the pad-constrained optical flow vector set; Calculate the geometric center position of each vector unit in the set of constrained optical flow vectors for the pads, and bind it to the nearest pad center point in the set of pad center points to generate a set of corresponding pad center points and vectors; Multiple optical flow vectors corresponding to the same pad center point are merged by direction merging, and vectors at the same spatial position are combined into a single pad center driving vector by vector superposition. Reorganize all pad center driving vectors according to the spatial arrangement order of the pad center point set to generate a pad displacement set.

[0037] In this embodiment, the normalized image sequence is a set of images of pads acquired under multi-light source conditions and adjusted with a unified brightness benchmark. Each frame of the image has eliminated the overall brightness difference caused by different light intensities, so that only the local reflection difference caused by the change of light angle is retained between adjacent images, thereby providing a comparable input basis for subsequent optical flow displacement extraction.

[0038] In this embodiment, the first image and the second image are two adjacent frames in the normalized image sequence in terms of acquisition time or light source angle. These two frames correspond to the same PCB area but there is a slight change in the direction of illumination, which is used to capture the grayscale change trajectory of the pad surface under different light incident conditions.

[0039] In this embodiment, pixel-by-pixel grayscale difference processing is a process of extracting grayscale values ​​from pixels at the same spatial location in the first image and the second image and comparing the differences. The result forms a difference grayscale image, which is used to express the brightness variation amplitude and direction characteristics of each pixel under different lighting conditions.

[0040] In this embodiment, the differential grayscale image is a two-dimensional image matrix composed of pixel grayscale change values, where each pixel value represents the intensity of brightness change at that location under adjacent lighting conditions. This intensity of change is used to subsequently determine whether the location belongs to a metal reflection-dominated area or a background texture area.

[0041] In this embodiment, the grayscale change direction within the neighborhood is obtained by extracting the grayscale increase and decrease trend of adjacent pixels within a fixed range centered on a certain pixel in the differential grayscale image, and converting it into a directional expression form to describe the reflection expansion direction of the local area under illumination changes.

[0042] In this embodiment, the pixel direction vector set is a set of vectors formed by uniformly encoding the gray-level change direction of each pixel and its neighborhood. This set of vectors is used to express the spatial response trend of each local region in the image under illumination changes.

[0043] In this embodiment, the spatial consistency expansion process is a process of adjacency expansion and merging of pixel direction vectors in two-dimensional space. The basis is that vectors with adjacent positions and similar directions are considered to originate from the same physical reflection structure, thereby merging scattered pixel-level responses into structural-level response units.

[0044] In this embodiment, the preset pixel spacing threshold is a distance constraint parameter used to limit the spatial adjacency range. Its function is to control that only pixel direction vectors within a certain spatial distance range can be merged into the same optical flow unit, thereby avoiding mis-fusion across pads or across structures.

[0045] In this embodiment, the initial optical flow vector unit set is a set of vector units formed after spatial consistency expansion. Each unit represents the illumination change-driven response with uniform directional characteristics in a local region, which is used to replace the optical flow unit definition under the traditional continuous motion assumption.

[0046] In this embodiment, the boundary of the pad candidate region is the outer contour of the pad region obtained by metal response pixel aggregation in the previous step. This boundary is used to limit the optical flow vector to be calculated and acted only inside the pad structure, thereby avoiding interference from the background region.

[0047] In this embodiment, the set of optical flow vectors constrained by the pads is a set of vectors obtained by clipping the pad candidate region boundary based on the initial set of optical flow vector units. This set only contains optical flow response units located inside the pad structure, which is used to ensure that the object of optical flow action is consistent with the physical pad structure.

[0048] In this embodiment, the geometric center position is the center point obtained by converging the spatial coordinates of all pixels inside each optical flow vector unit. This center point is used to represent the spatial position of the optical flow unit in the PCB coordinate system.

[0049] In this embodiment, the center point of the pad is the geometric centroid of the pad obtained by calculating the pad outline closure and pixel mean in the previous step, and is used as the core spatial anchor point for optical flow vector binding and action.

[0050] In this embodiment, the bonding relationship between the pad center point and the vector is a process of matching the geometric center position of each optical flow vector unit with the pad center point that is closest in space, in order to establish the spatial affiliation relationship between the optical flow response and the specific pad.

[0051] In this embodiment, the direction merging process is a process of merging multiple optical flow vectors associated with the center point of the same pad according to the consistency of spatial direction. The implementation method is to superimpose and integrate multiple vectors in spatial coordinates to form a single pad center driving vector, which is used to uniformly express the overall illumination driving displacement trend of the pad.

[0052] In this embodiment, the pad displacement set is a set of vectors formed by reorganizing the center driving vector of each pad according to the spatial arrangement order of the pad center point in the PCB array. This set is used to represent the overall displacement state of all pads under optical flow drive.

[0053] It should be noted that this step transforms the grayscale differences caused by illumination changes into structured direction vectors and performs spatial merging under the constraints of the pad structure. This converts the originally discontinuous illumination response into a driving quantity that can be used for pad-level displacement modeling, thereby achieving a unified mapping process from pixel changes to pad center driving.

[0054] It should be noted that by introducing pad candidate region constraints and center point binding mechanisms, optical flow calculation no longer relies on the assumption of overall image continuity, but instead performs local driving expression based on the pad structure, thereby improving the reliability of displacement expression in highly reflective metal regions.

[0055] It should be noted that the beneficial effect of this technology is that it transforms the traditional optical flow method based on the assumption of continuous motion into a local driving model based on pad structure anchoring, which enables the stable generation of pad-level displacement sets even in complex environments with multiple light source reflections, providing a structurally consistent input basis for subsequent pin virtual position correction.

[0056] S3 maps the pad displacement set to the first pin position set to generate the optical flow corrected pin position set, and returns it to the PCB conduction space to generate the virtual pin position set.

[0057] In this embodiment, the step of mapping the pad displacement set to the first pin position set to generate the optical flow-corrected pin position set, and then returning it to the PCB conductive space to generate the virtual pin position set, specifically involves: Spatial binding and matching are performed between the center driving vector of each pad in the pad displacement set and the corresponding pin position in the first pin position set to generate a pin-pad correspondence set. For each pin position in the pin-pad correspondence set, the corresponding pad center driving vector is superimposed to generate a pin optical flow correction position set. Perform package array constraint projection processing on the pin optical flow correction position set to restrict each pin position within a regular grid range determined by the pad array spacing, generating a grid-constrained pin position set; Perform PCB conductive pad alignment constraint processing on the set of mesh-constrained pin positions, mapping each pin position to the conductive region where the center point of the nearest PCB pad is located, and generating a set of conductive-constrained pin positions; Offset regression processing is performed on the set of conduction constraint pin positions. By analyzing the spatial offset between the pin position and the corresponding pad center point, the pin positions that exceed the effective coverage of the conduction pad are pulled back to the pad center and into the coverage boundary. The set of pin positions after conduction regression processing is rearranged according to the pin sequence order in the package model to generate a set of virtual pin positions.

[0058] In this embodiment, the pad displacement set is the set of pad-level driving results generated in the previous step, where each element corresponds to a two-dimensional spatial displacement vector of the center point of the pad under the action of multiple light source optical flow. This vector represents the equivalent offset trend of the pad under the driving of illumination change and is used as the spatial input basis for pin correction.

[0059] In this embodiment, the first pin position set is a set of theoretical pin space coordinates obtained by spatial registration of the standard package model and the PCB pad array. Each pin position corresponds one-to-one with the pin number in the package model, and the spatial mapping from the package coordinate system to the PCB coordinate system has been completed.

[0060] In this embodiment, the pin-pad correspondence set is a pair of data structures generated by spatial binding matching. Each pair consists of a pin position and a pad center driving vector. The correspondence is determined by the spatial nearest neighbor relationship and the consistency of the package array topology, and is used to establish a unique association between the pin and the pad driving change.

[0061] In this embodiment, spatial binding matching is the process of spatially corresponding the driving vector in the pad displacement set with the pin point in the first pin position set. The matching is based on the consistency constraint between the relative position of the pin in the package array and the pad array structure, so that each pin can inherit the displacement driving information of its corresponding pad.

[0062] In this embodiment, the pin optical flow correction position set is the pin space set obtained by superimposing the corresponding pad center driving vector on the original first pin position. This set reflects the corrected position of the pin under the influence of light-driven displacement and is used to replace the theoretical position calculated only based on the geometric model.

[0063] In this embodiment, the package array constraint projection processing is a process of restricting the pin optical flow correction position within a regular grid space defined by the package pin spacing and array structure. This regular grid is determined by the pin arrangement in the package standard model and is used to ensure that the corrected pins still conform to the physical structure constraints of the package.

[0064] In this embodiment, the set of grid-constrained pin positions is the set of pin positions after being projected by the package array constraint. Each pin position is restricted to a legal position neighborhood of the package standard array grid, thereby avoiding pin structure misalignment caused by optical flow correction.

[0065] In this embodiment, the PCB conductive pad is a metal soldering area on the PCB surface used to achieve electrical connection. Its position is determined by the set of center points of the pad and serves as the target area for the final conductive connection of the pin, constraining the pin spatial landing point to fall within the conductive range.

[0066] In this embodiment, the set of conduction constraint pin positions is a set of pins formed by mapping the grid constraint pin positions to the center area of ​​the nearest PCB conduction pad. Its spatial position has been restricted to the coverage area of ​​the actual conduction pad to ensure the physical feasibility of electrical connection.

[0067] In this embodiment, the offset regression process is a process of analyzing the spatial offset between the pin position and the center of the corresponding pad and then performing a position callback. The implementation method is that when the pin position exceeds the effective coverage area of ​​the pad, it is pulled back to the center position of the pad along the offset direction so that it re-enters the conductive area of ​​the pad.

[0068] In this embodiment, the virtual pin location set is the final pin spatial location set obtained after spatial binding, optical flow correction, package constraint projection and conduction regression processing. This set is used to replace the real invisible pin locations as the output result of subsequent insertion detection and location recognition.

[0069] It should be noted that this step maps the pad-level optical flow drive quantity to the pin space position, transforming the positioning of invisible pins from a static geometric inference to a dynamic drive correction process. At the same time, it introduces package array constraints and PCB conductivity constraints, so that the correction result satisfies both package structure rules and actual electrical connection conditions.

[0070] It should be noted that by introducing a package array grid constraint and a conductive pad return mechanism, the pin position after optical flow correction will not deviate from the physical package structure or the actual PCB pad range, thereby avoiding the spatial drift problem caused by relying solely on optical flow superposition.

[0071] It should be noted that the beneficial effect of this technology is that it performs structured correction of pin positions by pad driving vectors and combines package array and PCB conduction constraints for dual regression control, so that the virtual pin positions maintain both package geometry consistency and actual electrical connection feasibility, thereby significantly improving the engineering reliability of inferring the position of invisible pins.

[0072] S4, the set of pad center points also includes an optional method for generating and updating the set of pad center points by eliminating abnormal points based on illumination differences.

[0073] In this embodiment, the The set of pad center points also includes an optional method for generating and updating the set of pad center points by removing outliers based on lighting differences, specifically: Extract the set of local pixel windows corresponding to the center point of each pad in the normalized image sequence under different lighting conditions to generate a set of local observation windows for the pad; Perform grayscale extreme value difference analysis on each window in the local observation window set of the pads to obtain the grayscale fluctuation amplitude of the window under different lighting conditions; Sort the grayscale fluctuation amplitude values ​​corresponding to the center points of all pads to generate a pad fluctuation amplitude sequence. The center point of the pad whose amplitude difference between adjacent pads exceeds a preset difference threshold is marked as a pad point with a sudden change in light response. Perform a spatial neighborhood consistency check on the center point of the pad corresponding to the pad with a sudden change in light response, and compare the grayscale fluctuation amplitude of the center point of the pad corresponding to the pad with the center points of the four surrounding neighboring pads. When the grayscale fluctuation amplitude of the center point of the pad corresponding to the pad with a sudden change in light response deviates from the average fluctuation amplitude of the center points of all neighboring pads by more than a preset deviation threshold, the corresponding pad center point will be removed from the set of pad center points. The set of removed pad center points is reorganized according to the spatial order of the PCB pad array to generate an updated set of pad center points.

[0074] In this embodiment, the normalized image sequence is a set of images after multi-source brightness unification processing. Each frame of the image is proportionally corrected with the same background grayscale reference so that the difference in pad reflection under different lighting angles retains only local variation features, which can be used for subsequent pad stability judgment and anomaly screening.

[0075] In this embodiment, the center point of the pad is a two-dimensional spatial coordinate point calculated by the closure of the pad region outline and the geometric mean of the pixels. This point represents the spatial centroid position of the pad region in the PCB coordinate system and is used as a spatial anchor point for subsequent optical flow driving and pin mapping.

[0076] In this embodiment, the local observation window of the pad is a local pixel area of ​​a fixed size that is cropped from each frame of normalized image with the center point of the pad as the center. This area covers the main body of the pad and its edge transition area, and is used to capture the local grayscale change response of the pad under different lighting conditions.

[0077] In this embodiment, the pad local observation window set is a set of multiple local windows corresponding to the center point of the same pad under different lighting conditions. This set is used to describe the local reflection response trajectory of the pad during the process of lighting change.

[0078] In this embodiment, grayscale extreme value difference analysis is a process of comparing and analyzing the maximum and minimum grayscale values ​​of a local observation window of the same pad under all lighting conditions. The result is used to represent the normal lighting response level of the pad in the local area, and thus serves as an anomaly judgment benchmark.

[0079] In this embodiment, the preset difference threshold is a boundary condition used to determine whether the amplitude of the pad fluctuation is significantly separated from that of the adjacent pads. Its function is to distinguish between pads with normal illumination changes and pads with abnormal illumination responses, thereby avoiding misjudging pads with normal structure but slightly different reflections as abnormal points.

[0080] In this embodiment, the preset deviation threshold is a judgment condition used to determine whether the difference between the target pad and the average response of its neighborhood exceeds the acceptable range. Its function is to further confirm whether the pad belongs to a structural anomaly rather than a local noise fluctuation.

[0081] In this embodiment, the updated pad center point set is a set of pad center points that has been reorganized after removing pad center points with abnormal light response. This set is reordered and filled according to the PCB array structure to ensure that subsequent optical flow calculations and pin mappings are based on a stable pad structure.

[0082] It should be noted that this step involves performing cross-view consistency analysis on the pad illumination response under multi-source conditions to remove center point drift or erroneous response points caused by abnormal illumination from the pad structure, thereby preventing abnormal pads from participating in the subsequent optical flow driving process and affecting the stability of pin position inference.

[0083] It should be noted that by introducing a local observation window and a neighborhood structure comparison mechanism, the judgment of pad anomalies does not only rely on single-point grayscale changes, but also combines the local structural consistency for judgment, thereby improving the reliability of the pad center point set in complex reflection environments.

[0084] It should be noted that the beneficial effect of this technology is that by using a multi-source light source response difference screening mechanism to purify the structure of the pad center point set, the pad points participating in subsequent optical flow driving and pin mapping have more consistent illumination response characteristics, thereby improving the stability and repeatability of the virtual pin position generation process.

[0085] S5, the flux-covered pad set also includes an optional optimal pad input subset generated based on coverage ratio control, and optimization of the original pad center point set to participate in optical flow generation.

[0086] In this embodiment, the flux-covered pad set further includes an optional optimal pad input subset generated based on coverage ratio control, and optimization of the original pad center point set for optical flow generation, specifically: A two-dimensional array index matrix is ​​constructed for the set of PCB pad center points according to the row and column spatial distribution relationship. For each pad center point, the nearest neighbor row direction matching and the nearest neighbor column direction matching are performed to obtain a unique row index identifier and column index identifier for each pad center point, and a pad array index set is generated. For each center point of the pad array index set, calculate the coverage ratio between the number of flux-covered pixels and the total number of pixels in the corresponding pad area, and bind the coverage ratio as an array control parameter to the corresponding center point of the pad to generate a pad coverage control set. Based on the spatial distribution results of the coverage ratio in the pad coverage control set, the PCB two-dimensional array index matrix is ​​subjected to array compression mapping processing. The array index space corresponding to the area with a high coverage ratio is density-shrunken, while the array index space corresponding to the area with a low coverage ratio is structurally preserved, and an array compression index space is generated. Extract the set of pad center points that still maintain the continuity of row and column structure within the array compressed index space, and define it as the initial pad input control subset; The initial pad input control subset is subjected to structure preservation mapping processing. The center point of the compressed and removed pad is set as a space placeholder node in the array compression index space. A spatial continuity mapping relationship is established between the placeholder nodes based on the center points of adjacent row and column pads, so that the structure after array compression still maintains the row and column topology consistency, and a structure preservation pad input control subset is generated. The structure retains the pad input control subset and inputs it into the optical flow displacement field generation process. Only the center point of the pad retained after array compression participates in the pixel displacement driving calculation to generate a controlled pad displacement set. The controlled pad displacement set is used in the subsequent pin position mapping process to realize the generation of the optical flow-corrected pin position set.

[0087] In this embodiment, the set of PCB pad center points is the set of pad geometric center coordinates obtained from the previous pad extraction step. Each center point corresponds to an actual pad position on the PCB, which is used to describe the spatial distribution relationship of the pads in the array structure and serves as the basic input for subsequent flux coverage analysis and optical flow drive selection.

[0088] In this embodiment, the two-dimensional array index matrix is ​​a two-dimensional index structure constructed according to the actual arrangement of PCB pads. Each index position corresponds to a pad center point, and the pads are structurally numbered by row and column directions respectively, which is used to convert the spatial distribution into a regular matrix expression.

[0089] In this embodiment, nearest neighbor row direction matching is the process of searching for the center point of each pad in the pad array along the horizontal direction that is spatially closest to the center point of the pad and whose position is closest to the horizontal arrangement trend, and classifying it into the same row index sequence, which is used to establish the row structure belonging relationship of the pads.

[0090] In this embodiment, nearest neighbor column direction matching is the process of searching for the center point of each pad in the pad array along the vertical direction that is closest in spatial distance and closest in position to the vertical arrangement trend, and classifying it into the same column index sequence, which is used to establish the column structure belonging relationship of the pads.

[0091] In this embodiment, the pad array index set is a set formed by having a unique row index and column index identifier for each pad center point. It is used to transform the spatial distribution of pads into an indexable structured matrix representation, thereby supporting subsequent coverage analysis and structure compression processing.

[0092] In this embodiment, the number of flux-covered pixels is the number of pixels detected in the pad area that belong to the flux-covered feature. These feature pixels are usually characterized by local grayscale attenuation, weakened edge reflection, or blurred texture, and are used to indicate the degree of flux coverage on the pad surface.

[0093] In this embodiment, the total number of pixels in the pad area is the total number of all pixels inside the closed area of ​​a single pad outline. This value is used as a benchmark for calculating the coverage ratio, so that there is a unified coverage evaluation standard between pads of different sizes.

[0094] In this embodiment, the pad coverage control set is a set formed by binding the flux coverage ratio corresponding to the center point of each pad to its array index. This set is used to describe the distribution state of flux in the PCB array space and serves as the basis for subsequent array compression control.

[0095] In this embodiment, the array compressed index space is an index space obtained by compressing and adjusting the spatial structure based on the two-dimensional pad array index matrix according to the pad coverage ratio distribution. The high coverage area corresponds to the index density reduction treatment, while the low coverage area maintains the original index structure, which is used to reduce the participation of pads affected by flux.

[0096] In this embodiment, the initial pad input control subset is the set of pad center points that still maintain the continuity of the complete row and column structure in the array compression index space. This set only includes pad points that still retain the conditions for participating in optical flow calculation after structural compression.

[0097] In this embodiment, the space placeholder node is a structural placeholder mark reserved for the pad positions that are removed or not involved in optical flow calculation during array compression. The placeholder node does not participate in optical flow calculation, but is used to maintain the integrity of the original row and column topology.

[0098] In this embodiment, the spatial continuity mapping relationship is a structural connection relationship established by utilizing the spatial arrangement relationship between the center points of adjacent pads on the top, bottom, left, and right sides of the placeholder node. This is used to maintain the continuity of the array structure without being destroyed after the pad portion is compressed and removed.

[0099] In this embodiment, the structure-preserving pad input control subset is the set of pad center points obtained after placeholder node compensation and row and column structure reconstruction. This set still maintains the original PCB pad array topology in terms of spatial structure, but only includes the effective pad points that participate in optical flow calculation.

[0100] In this embodiment, the controlled pad displacement set is the set of pad displacement results obtained after the structure-maintaining pad input control subset participates in the optical flow displacement field calculation. This set is generated only by the selected pad and is used to avoid interference from the flux-covered area on the optical flow calculation.

[0101] In this embodiment, the optical flow correction pin position set is the pin correction position set obtained by mapping the controlled pad displacement to the pin space. Its pin position has been affected by the selective control of the pad, thereby avoiding the introduction of erroneous displacement in high coverage areas.

[0102] It should be noted that this step involves structurally compressing the range of the pads involved in optical flow calculation by introducing the flux coverage ratio, thereby changing the optical flow driving process from a full pad participation mode to a controlled pad participation mode, thus reducing the interference of the flux coverage area on the displacement field calculation.

[0103] It should be noted that by using array compression and occupancy node compensation mechanisms, the integrity of the row and column topology of the PCB pad array is maintained while high-coverage pads are removed, thereby avoiding structural breakage from affecting subsequent pin mapping.

[0104] It should be noted that the beneficial effect of this technology is that by using a pad input control mechanism based on flux coverage ratio, selective optimization of optical flow calculation objects is achieved, making the set of pads participating in displacement driving closer to the effective electrical connection area, thereby improving the accuracy and stability of virtual position generation of invisible pins.

[0105] Example 2: This invention also includes an automatic chip pin position identification and control optimization system, comprising an imaging modeling module, an optical flow driving module, a pin reconstruction module, an illumination screening module, and a flux control module. The imaging modeling module acquires multi-source image sequences, extracts pad area edges, analyzes the set of pad center points, and simultaneously marks the set of flux-covered pad points to establish a first pin position set. The optical flow driving module generates an optical flow displacement field based on pad pixel displacements under adjacent illumination conditions and applies it to the set of pad center points to generate a pad displacement set. The pin reconstruction module maps the pad displacement set to the first pin position set to generate an optical flow-corrected pin position set and returns it to the PCB conductive space to generate a virtual pin position set. The illumination screening module optionally removes abnormal points based on illumination differences to generate an updated set of pad center points. The flux control module optionally generates an optimal pad input subset based on coverage ratio control and optimizes the original set of pad center points for optical flow generation.

[0106] The present invention also includes an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform an automatic chip pin position identification control optimization method as described in one of the inventions.

[0107] The present invention also includes a computer-readable storage medium storing a computer program that, when executed by a processor, implements an automatic identification and control optimization method for chip pin positions.

[0108] In the embodiments provided by this invention, it should be understood that the disclosed system can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and other division methods may be used in actual implementation.

[0109] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0110] Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be embraced within the invention. No appended diagram markings in the claims should be construed as limiting the scope of the claims.

[0111] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0112] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0113] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the system can be divided into different functional units or modules to complete all or part of the functions described above.

[0114] In the embodiments provided in this disclosure, it should be understood that the disclosed systems and methods can also be implemented in other ways. The system embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0115] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element limited by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0116] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for automatic identification and control optimization of chip pin positions, characterized in that, Includes the following steps: Acquire multi-source image sequences, extract pad area edges and analyze pad center point set, simultaneously mark flux-covered pad point set, and establish first pin position set; An optical flow displacement field is generated based on the pixel displacement of the pads under adjacent illumination conditions, and then applied to the set of center points of the pads to generate a set of pad displacements. The pad displacement set is mapped to the first pin position set to generate the optical flow corrected pin position set, and then returned to the PCB conduction space to generate the virtual pin position set; The set of pad center points also includes an optional set of updated pad center points generated by eliminating outliers based on illumination differences; The flux-covered pad set also includes an optional optimal pad input subset generated based on coverage ratio control, and optimization of the original pad center point set to participate in optical flow generation.

2. The chip pin position automatic identification and control optimization method according to claim 1, characterized in that, The process of acquiring multi-source image sequences, extracting pad region edges and analyzing pad center point sets, simultaneously marking flux-covered pad point sets, and establishing a first pin position set specifically involves: The image sequence with different lighting angles in the multi-light source image sequence is processed frame by frame to achieve uniform lighting. The average gray value of the same non-pad background area is used as the reference, and each image is scaled proportionally so that all images are output as a normalized image sequence under a uniform brightness reference. Metal response pixel set is extracted from normalized image sequence. By calculating the difference between the maximum and minimum gray values ​​of the same pixel in all illuminated images, pixels with a difference greater than the median gray value of the background texture are defined as metal response pixels, and a set of candidate pad regions is generated. Perform connected pixel aggregation processing on the set of candidate pad regions, and merge spatially continuous metal response pixels into independent pad regions using the eight-neighbor pixel connection rule; For each pad region, contour closure processing is performed. By locally extending and connecting the boundary broken pixels, each pad region forms a closed contour region. The mean value of all pixel coordinates within the closed contour area is calculated to obtain the geometric center point in two-dimensional space, and a set of pad center points is generated. Extract the set of pixels in the pad area whose grayscale variation is lower than the median value of the background texture variation, and mark the center point of the pad corresponding to the pixel set as the set of flux-covered pad points; The chip's outer contour center point is matched with the set of pad center points to obtain the chip's translation and rotation transformation parameters. The theoretical pin coordinates in the standard package pin model are then mapped to the PCB coordinate space through this transformation to generate the first set of pin positions.

3. The automatic identification and control optimization method for chip pin positions according to claim 2, characterized in that, The process of generating an optical flow displacement field based on the pixel displacement of pads under adjacent illumination conditions and applying it to the set of pad center points to generate a set of pad displacements is as follows: Pixel-wise grayscale difference processing is performed on the first and second images corresponding to adjacent lighting conditions in the normalized image sequence to generate a difference grayscale image; Extract the direction of gray-level change in the neighborhood of each pixel position in the differential grayscale image with a preset dimension, and encode the direction of gray-level increase and gray-level decrease in the neighborhood into direction vectors respectively to generate a set of pixel direction vectors; A spatial consistency expansion process is performed on the set of pixel orientation vectors, which merges vectors with the same orientation and adjacent distances less than a preset pixel spacing threshold in the two-dimensional coordinate space to generate an initial set of optical flow vector units. The initial optical flow vector unit set is spatially pruned according to the boundary of the pad candidate region, retaining only the vector units located inside the pad candidate region, to generate the pad-constrained optical flow vector set; Calculate the geometric center position of each vector unit in the set of constrained optical flow vectors for the pads, and bind it to the nearest pad center point in the set of pad center points to generate a set of corresponding pad center points and vectors; Multiple optical flow vectors corresponding to the same pad center point are merged by direction merging, and vectors at the same spatial position are combined into a single pad center driving vector by vector superposition. Reorganize all pad center driving vectors according to the spatial arrangement order of the pad center point set to generate a pad displacement set.

4. The automatic identification and control optimization method for chip pin positions according to claim 3, characterized in that, The process of mapping the pad displacement set to the first pin position set to generate the optical flow-corrected pin position set, and then returning it to the PCB conduction space to generate the virtual pin position set, specifically involves: Spatial binding matching is performed between the center driving vector of each pad in the pad displacement set and the corresponding pin position in the first pin position set to generate a set of pin-pad pairs. For each pin position in the pin-pad correspondence set, the corresponding pad center driving vector is superimposed to generate a pin optical flow correction position set. Perform package array constraint projection processing on the pin optical flow correction position set to restrict each pin position within a regular grid range determined by the pad array spacing, generating a grid-constrained pin position set; Perform PCB conductive pad alignment constraint processing on the set of mesh-constrained pin positions, mapping each pin position to the conductive region where the center point of the nearest PCB pad is located, and generating a set of conductive-constrained pin positions; Offset regression processing is performed on the set of conduction constraint pin positions. By analyzing the spatial offset between the pin position and the corresponding pad center point, the pin positions that exceed the effective coverage of the conduction pad are pulled back to the pad center and into the coverage boundary. The set of pin positions after conduction regression processing is rearranged according to the pin sequence order in the package model to generate a set of virtual pin positions.

5. The automatic identification and control optimization method for chip pin positions according to claim 4, characterized in that, The set of pad center points also includes an optional method for generating and updating the set of pad center points based on removing outliers due to lighting differences. Specifically: Extract the set of local pixel windows corresponding to the center point of each pad in the normalized image sequence under different lighting conditions to generate a set of local observation windows for the pad; Perform grayscale extreme value difference analysis on each window in the local observation window set of the pads to obtain the grayscale fluctuation amplitude of the window under different lighting conditions; Sort the grayscale fluctuation amplitude values ​​corresponding to the center points of all pads to generate a pad fluctuation amplitude sequence. The center point of the pad whose amplitude difference between adjacent pads exceeds a preset difference threshold is marked as a pad point with a sudden change in light response. Perform a spatial neighborhood consistency check on the center point of the pad corresponding to the pad with a sudden change in light response, and compare the grayscale fluctuation amplitude of the center point of the pad corresponding to the pad with the center points of the four surrounding neighboring pads. When the grayscale fluctuation amplitude of the center point of the pad corresponding to the pad with a sudden change in light response deviates from the average fluctuation amplitude of the center points of all neighboring pads by more than a preset deviation threshold, the corresponding pad center point will be removed from the set of pad center points. The set of removed pad center points is reorganized according to the spatial order of the PCB pad array to generate an updated set of pad center points.

6. The automatic identification and control optimization method for chip pin positions according to claim 5, characterized in that, The flux-covered pad set also includes an optional optimal pad input subset generated based on coverage ratio control, and optimization of the original pad center point set for optical flow generation, specifically: A two-dimensional array index matrix is ​​constructed for the set of PCB pad center points according to the row and column spatial distribution relationship. For each pad center point, the nearest neighbor row direction matching and the nearest neighbor column direction matching are performed to obtain a unique row index identifier and column index identifier for each pad center point, and a pad array index set is generated. For each center point of the pad array index set, calculate the coverage ratio between the number of flux-covered pixels and the total number of pixels in the corresponding pad area, and bind the coverage ratio as an array control parameter to the corresponding center point of the pad to generate a pad coverage control set. Based on the spatial distribution results of the coverage ratio in the pad coverage control set, the PCB two-dimensional array index matrix is ​​subjected to array compression mapping processing. The array index space corresponding to the area with a high coverage ratio is density-shrunken, while the array index space corresponding to the area with a low coverage ratio is structurally preserved, and an array compression index space is generated. Extract the set of pad center points that still maintain the continuity of row and column structure within the array compressed index space, and define it as the initial pad input control subset; The initial pad input control subset is subjected to structure preservation mapping processing. The center point of the compressed and removed pad is set as a space placeholder node in the array compression index space. A spatial continuity mapping relationship is established between the placeholder nodes based on the center points of adjacent row and column pads, so that the structure after array compression still maintains the row and column topology consistency, and a structure preservation pad input control subset is generated. The structure retains the pad input control subset and inputs it into the optical flow displacement field generation process. Only the center point of the pad retained after array compression participates in the pixel displacement driving calculation to generate a controlled pad displacement set. The controlled pad displacement set is used in the subsequent pin position mapping process to realize the generation of the optical flow-corrected pin position set.

7. A system using the automatic chip pin position identification and control optimization method as described in any one of claims 1-6, characterized in that, It includes an imaging modeling module, an optical flow driving module, a pin reconstruction module, an illumination screening module, and an additive control module; The imaging modeling module is used to acquire multi-source image sequences, extract the edges of the pad area and analyze the set of pad center points, and simultaneously mark the set of pad points covered by flux to establish the first pin position set. The optical flow driving module is used to generate an optical flow displacement field based on the pixel displacement of the pads under adjacent illumination conditions, and to act on the set of center points of the pads to generate a set of pad displacements; The pin reconstruction module is used to map the pad displacement set to the first pin position set to generate the optical flow corrected pin position set, and return it to the PCB conduction space to generate the virtual pin position set; The illumination filtering module, used for the set of pad center points, also includes an optional method for generating and updating the set of pad center points by eliminating abnormal points based on illumination differences; The flux control module, used for the flux covering the set of solder pads, also includes an optional function to generate an optimal set of input pads based on the coverage ratio, and to optimize the original set of center points of the solder pads for optical flow generation.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform the chip pin position automatic identification control optimization method as described in any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the chip pin position automatic identification control optimization method as described in any one of claims 1 to 6.

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