Gate driver, display device, and electronic device

Abstract

This disclosure relates to gate drivers, display devices, and electronic devices. The gate driver includes multiple stages. Each of the multiple stages includes: an input transistor that transmits an input signal to a Q node in response to a clock signal; a pull-up transistor that outputs a high gate voltage as an output signal in response to a signal from a QB node; a first pull-down transistor that outputs a low gate voltage as an output signal in response to a signal from a Q node; a first control transistor that transmits the signal from the QB node of the previous stage to a B node in response to a signal from a Q node; and a second pull-down transistor that outputs a low gate voltage as an output signal in response to a signal from a B node.

Description

Technical Field

[0001] The embodiments relate to gate drivers, display devices, and electronic devices, and more specifically, to gate drivers including transistors and capacitors, display devices including said gate drivers, and electronic devices including said display devices. Background Technology

[0002] The display device may include a display panel, a gate driver, and a data driver. The display panel may include pixels, the gate driver may provide gate signals to the pixels, and the data driver may provide data voltages to the pixels.

[0003] A gate driver may include stages that output gate signals. A stage may be implemented as a shift register that generates gate signals by sequentially shifting a gate start signal. Each stage may include multiple transistors and multiple capacitors. Summary of the Invention

[0004] The embodiments provide a gate driver in which the reliability of the output signal is improved and the power consumption is reduced, a display device including the gate driver, and an electronic device including the display device.

[0005] According to embodiments of this disclosure, a gate driver includes multiple stages. Each of the multiple stages includes: an input transistor configured to transmit an input signal to a Q node in response to a clock signal; an output terminal configured to output an output signal, the output terminal being disposed between a pull-up transistor and each of a first pull-down transistor and a second pull-down transistor; a pull-up transistor configured to output a high gate voltage as an output signal in response to a signal from a QB node, the QB node being connected to the gate of the pull-up transistor; a first pull-down transistor configured to output a low gate voltage as an output signal in response to a signal from a Q node; and a second pull-down transistor configured to output a low gate voltage as an output signal in response to a signal from a B node, the B node being connected to the gate of the second pull-down transistor. Each stage may further include: a first control transistor configured to transmit a signal from the QB node of a previous stage to the B node in response to a signal from a Q node, the Q node being connected to both the gate of the first pull-down transistor and the gate of the first control transistor.

[0006] According to an embodiment, each of the plurality of stages may further include: a second control transistor including a gate configured to receive a clock signal, a first terminal configured to receive a clock signal, and a second terminal connected to a C node, wherein the voltage of the C node corresponds to the sum of the low gate voltage of the clock signal and the threshold voltage of the second control transistor, and the voltage of the C node is applied to the QB node.

[0007] According to an embodiment, each of the plurality of stages may further include: a third control transistor configured to connect the QB node to the C node in response to a signal from the B node.

[0008] According to an embodiment, in the case where the input signal has a high gate voltage and the clock signal has a low gate voltage, the voltage corresponding to the sum of the low gate voltage and the threshold voltage of the second control transistor can be applied to the QB node through the second control transistor and the third control transistor.

[0009] According to an embodiment, each of the multiple stages may further include a third capacitor connected between node B and node C.

[0010] According to an embodiment, each of the plurality of stages may further include: a fourth control transistor configured to transmit a high gate voltage to the QB node in response to a signal from the Q node.

[0011] According to an embodiment, each of the plurality of stages may further include: a first protection transistor, including a gate configured to receive a low gate voltage, a first terminal connected to a second terminal of an input transistor, and a second terminal connected to a Q node.

[0012] According to an embodiment, each of the plurality of stages may further include: a second protection transistor, including a gate configured to receive a low gate voltage, a first terminal connected to a second terminal of a first control transistor, and a second terminal connected to a B node.

[0013] According to an embodiment, each of the plurality of stages may further include: a reset transistor configured to transmit a low gate voltage to the Q node in response to a reset signal.

[0014] According to an embodiment, each of the plurality of stages may further include: a first capacitor, including a first terminal connected to the QB node and a second terminal configured to receive a high gate voltage.

[0015] According to an embodiment, each of the plurality of stages may further include: a second capacitor, including a first terminal connected to the Q node and a second terminal connected to an output terminal configured to output an output signal.

[0016] According to an embodiment, in the case where the input signal has a low gate voltage, the clock signal has a low gate voltage, and the output signal transitions from a high gate voltage to a low gate voltage, the signal of the Q node can transition from a high gate voltage to a voltage lower than the low gate voltage.

[0017] According to an embodiment, each of the plurality of stages may further include: a second control transistor, including a gate connected to the B node, a first terminal configured to receive a clock signal, and a second terminal.

[0018] According to an embodiment, each of the plurality of stages may further include: a third control transistor, including a gate connected to a second terminal of the second control transistor, a first terminal connected to the second terminal of the second control transistor, and a second terminal connected to the QB node.

[0019] According to an embodiment, each of the multiple stages may further include a third capacitor connected between node B and node QB.

[0020] According to an embodiment, the second pull-down transistor may be an N-type metal-oxide-semiconductor (NMOS) transistor, and excluding the second pull-down transistor, each of the plurality of transistors in each of the plurality of stages may be a P-type metal-oxide-semiconductor (PMOS) transistor.

[0021] The display device according to an embodiment includes: a display panel including a plurality of pixel rows, each of the plurality of pixel rows including a pixel; and a gate driver including a plurality of stages configured to output gate signals to the plurality of pixel rows. Each of the plurality of stages includes: an input transistor configured to transmit an input signal to a Q node in response to a clock signal; an output terminal configured to output an output signal, the output terminal being disposed between a pull-up transistor and each of a first pull-down transistor and a second pull-down transistor; a pull-up transistor configured to output a high gate voltage as an output signal in response to a signal from a QB node, the QB node being connected to the gate of the pull-up transistor; a first pull-down transistor configured to output a low gate voltage as an output signal in response to a signal from a Q node; and a second pull-down transistor configured to output a low gate voltage as an output signal in response to a signal from a B node, the B node being connected to the gate of the second pull-down transistor. Each stage further includes: a first control transistor configured to transmit a signal from the QB node of a previous stage to the B node in response to a signal from a Q node, the Q node being connected to both the gate of the first pull-down transistor and the gate of the first control transistor, and the first pull-down transistor and the second pull-down transistor being connected in parallel with each other.

[0022] According to an embodiment, each of the plurality of pixels may include: a first transistor including a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor configured to transmit a data voltage to the second node in response to a write gate signal; a third transistor configured to connect the first node to the third node in response to a compensation gate signal; a fourth transistor configured to transmit a first initialization voltage to the first node in response to an initialization gate signal; a fifth transistor configured to transmit a first power voltage to the second node in response to an transmit control signal; a sixth transistor configured to connect the third node to the fourth node in response to an transmit control signal; a seventh transistor configured to transmit a second initialization voltage to the fourth node in response to a bypass gate signal; a storage capacitor connected between the first node and a power line configured to transmit the first power voltage; and a light-emitting element including a first terminal connected to the fourth node and a second terminal configured to receive the second power voltage. The output signal may be one of a compensation gate signal, an initialization gate signal, a bypass gate signal, and an transmit control signal.

[0023] According to an embodiment, the first pull-down transistor and the second pull-down transistor are connected in parallel.

[0024] According to embodiments of the present disclosure, an electronic device includes: a display device; and a processor configured to control the display device according to the embodiments. The display device includes: a display panel including a plurality of pixel rows, each of the plurality of pixel rows including a plurality of pixels; and a gate driver including a plurality of stages configured to output gate signals to the plurality of pixel rows. Each of the plurality of stages includes: an input transistor configured to transmit an input signal to a Q node in response to a clock signal; an output terminal configured to output an output signal, the output terminal being disposed between a pull-up transistor and each of a first pull-down transistor and a second pull-down transistor; a pull-up transistor configured to output a high gate voltage as an output signal in response to a signal from a QB node, the QB node being connected to the gate of the pull-up transistor; a first pull-down transistor configured to output a low gate voltage as an output signal in response to a signal from a Q node; and a second pull-down transistor configured to output a low gate voltage as an output signal in response to a signal from a B node, the B node being connected to the gate of the second pull-down transistor. Each stage also includes: a first control transistor configured to transmit a signal from the previous stage's QB node to the B node in response to a signal from the Q node, the Q node being connected to both the gate of the first pull-down transistor and the gate of the first control transistor, and the first pull-down transistor and the second pull-down transistor being connected in parallel with each other.

[0025] In a gate driver, a display device including the gate driver, and an electronic device including the display device, the output signal of the gate driver does not have an intermediate voltage level between a high gate voltage and a low gate voltage, and during periods when the output signal has a low voltage level, the output signal does not rise to a level higher than the low gate voltage, thereby improving the reliability of the output signal. Furthermore, even if the signal at the Q node rises to a low gate voltage due to leakage current from the input transistor and the first protection transistor, the output signal is maintained at a low gate voltage by the second pull-down transistor, enabling low-frequency driving of the display device and reducing power consumption. Moreover, even if the second pull-down transistor operates in depletion mode, it can be turned off because the signal at the B node has a second low gate voltage, thus avoiding additional power consumption and ensuring the reliability of the oxide transistor operation. Furthermore, since the gate driver is driven by only two power voltages (high gate voltage and low gate voltage), the complexity of the power voltage generator can be reduced, and the layout complexity of the gate driver due to additional power lines can be reduced. Additionally, the reduced current flowing in the pull-up transistor and the first pull-down transistor for the output signal further reduces the power consumption of the gate driver. Attached Figure Description

[0026] The illustrative, non-limiting embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a block diagram illustrating a gate driver according to an embodiment; Figure 2 It is shown that, according to the embodiments, it includes Figure 1 A circuit diagram of an example stage in a gate driver; Figure 3 This illustrates an embodiment. Figure 2 Timing diagram of the signal at the [level]; Figures 4 to 8 It is used to describe the embodiments. Figure 2 A diagram of operations at the level; Figure 9 It is shown that, according to the embodiments, it includes Figure 1 A circuit diagram of an example stage in a gate driver; Figure 10 It is shown that, according to the embodiments, it includes Figure 1 A circuit diagram of an example stage in a gate driver; Figure 11 This is a block diagram illustrating a display device according to an embodiment; Figure 12 This illustrates an embodiment. Figure 11 The circuit diagram of the pixels; and Figure 13 This is a block diagram illustrating an electronic device according to an embodiment. Detailed Implementation

[0027] While each figure may represent one or more specific embodiments of this disclosure drawn to scale, such that relative lengths, thicknesses, and angles can be inferred from each figure, it will be understood that this disclosure is not necessarily limited to the relative lengths, thicknesses, and angles shown. For example, these values ​​may be varied within the spirit and scope of this disclosure to allow for manufacturing limitations, etc. In this disclosure, "level" and "voltage level" may have substantially the same meaning.

[0028] Embodiments of this disclosure relate to a gate driver, a display device including the gate driver, and an electronic device including the display device, wherein the gate driver includes multiple stages. Each stage may include circuitry to prevent the output from falling between a high gate voltage and a low gate voltage (intermediate voltage level), thereby improving reliability. A stage (hereinafter also referred to as a stage circuit) includes an output terminal disposed between a pull-up transistor and a pull-down transistor (a first pull-down transistor and a second pull-down transistor). A second pull-down transistor may be included to prevent the output voltage from rising above the low voltage level to reach the intermediate level; the second pull-down transistor and the first pull-down transistor are electrically connected in parallel. The stage circuit includes a QB node, a Q node, and a B node, wherein the QB node serves as a control node for the pull-up transistor (i.e., connected to the gate of the pull-up transistor), the Q node is connected to the gate of the first pull-down transistor, and the B node is connected to the gate of the second pull-down transistor.

[0029] When driven at low frequencies (where the control (or Q) node of the first pull-down transistor rises to a low gate voltage due to leakage current from the input transistor), the output signal can still be maintained at a low gate voltage. In the case where the second pull-down transistor operates in depletion mode, the signal at node B can have a second low gate voltage to turn off the second pull-down transistor, reducing the quiescent current flowing through it and saving power. Furthermore, a third voltage is not required to drive the gate driver, thus reducing the complexity of the power voltage generator.

[0030] In the following, gate drivers, display devices, and electronic devices according to embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals will be used for the same elements.

[0031] Figure 1 This is a block diagram illustrating a gate driver 10 according to an embodiment.

[0032] Reference Figure 1The gate driver 10 can receive a high gate voltage VGH, a low gate voltage VGL, a first clock signal CLK1, a second clock signal CLK2, and a gate start signal. The gate driver 10 can also output multiple output signals: ..., OUT[n-1], OUT[n], ... . The high gate voltage VGH can be the cutoff voltage of a P-type metal-oxide-semiconductor (PMOS) transistor and the turn-on voltage of an N-type metal-oxide-semiconductor (NMOS) transistor. The low gate voltage VGL can be the turn-on voltage of a PMOS transistor and the cutoff voltage of an NMOS transistor. The voltage level of the low gate voltage VGL can be lower than the voltage level of the high gate voltage VGH.

[0033] The second clock signal CLK2 can be a signal that shifts the first clock signal CLK1 by half a cycle. Each of the first clock signal CLK1 and the second clock signal CLK2 can cycle (or alternate) between a high gate voltage VGH and a low gate voltage VGL.

[0034] The gate driver 10 may include multiple stages ..., ST[n-1], ST[n], ... including stage (n-1) and stage n, ST[n], where n is a natural number greater than or equal to 2. Stages ..., ST[n-1], ST[n], ... may be implemented as shift registers for output signals ..., OUT[n-1], OUT[n], ..., where the gate start signal is shifted sequentially.

[0035] Each of stages ..., ST[n-1], ST[n], ... can receive the clock signal CLK, the high gate voltage VGH, the low gate voltage VGL, the signal QB_PR of the previous stage's QB node, and the input signal IN. Each of stages ..., ST[n-1], ST[n], ... can output the QB node signal and the output signal OUT. Stage (n-1) ST[n-1] can receive the first clock signal CLK1 as the clock signal CLK. Stage (n-1) ST[n-1] can receive the signal of the QB node of stage (n-2). Stage (n-1) ST[n-1] can receive the output signal of stage (n-2) as the input signal IN. Stage (n-1) ST[n-1] can output the signal QB[n-1] of the QB node of stage (n-1) ST[n-1]. Stage (n-1) ST[n-1] can output the (n-1)th output signal OUT[n-1]. The nth stage ST[n] can receive the second clock signal CLK2 as the clock signal CLK. The nth stage ST[n] can receive the signal QB[n-1] of the QB node of the (n-1)th stage ST[n-1]. The nth stage ST[n] can receive the (n-1)th output signal OUT[n-1] of the (n-1)th stage ST[n-1] as the input signal IN. The nth stage ST[n] can output the signal QB[n] of the QB node of the nth stage ST[n], and the nth stage ST[n] can output the nth output signal OUT[n].

[0036] Figure 2 It is shown that, according to the embodiments, it includes Figure 1 A circuit diagram of an example stage ST in gate driver 10.

[0037] Reference Figure 2 The stage ST may include an input transistor M1, a second control transistor M2, a third control transistor M3, a fourth control transistor M4, a pull-up transistor M5, a first pull-down transistor M6, a first protection transistor M7, a second protection transistor M8, a first control transistor M9, a reset transistor M10, a second pull-down transistor M11, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0038] Input transistor M1 can transmit the input signal IN to the Q node in response to the clock signal CLK. Input transistor M1 may include a gate for receiving the clock signal CLK, a first terminal for receiving the input signal IN, and a second terminal connected to the A node. The first terminal of input transistor M1 may be one of the source (or source region) and the drain (or drain region), and the second terminal of input transistor M1 may be the other of the source and the drain.

[0039] The second control transistor M2 may include a gate for receiving the clock signal CLK, a first terminal for receiving the clock signal CLK, and a second terminal connected to node C. The first terminal of the second control transistor M2 may be one of the source and drain, and the second terminal of the second control transistor M2 may be the other of the source and drain. The second control transistor M2 may be connected in a diode configuration. In the case where the clock signal CLK has a low gate voltage VGL, a voltage corresponding to the sum of the low gate voltage VGL and the threshold voltage of the second control transistor M2 may be applied to node C.

[0040] The third control transistor M3 can connect the QB node and the C node in response to a signal from the B node. The third control transistor M3 may include a gate connected to the B node, a first terminal connected to the C node, and a second terminal connected to the QB node. The first terminal of the third control transistor M3 may be one of the source and the drain, and the second terminal of the third control transistor M3 may be the other of the source and the drain.

[0041] The fourth control transistor M4 can transmit a high gate voltage VGH to the QB node in response to a signal from the Q node. The fourth control transistor M4 may include a gate connected to the Q node, a first terminal receiving the high gate voltage VGH, and a second terminal connected to the QB node. The first terminal of the fourth control transistor M4 may be one of the source and drain, and the second terminal of the fourth control transistor M4 may be the other of the source and drain.

[0042] The pull-up transistor M5 can output a high gate voltage VGH as an output signal OUT in response to the signal from the QB node. The pull-up transistor M5 may include a gate connected to the QB node, a first terminal receiving the high gate voltage VGH, and a second terminal connected to the output terminal T_OUT of the output signal OUT. The first terminal of the pull-up transistor M5 can be one of the source and drain, and the second terminal of the pull-up transistor M5 can be the other of the source and drain.

[0043] The first pull-down transistor M6 can output a low gate voltage VGL as an output signal OUT in response to the signal from the Q node. The first pull-down transistor M6 may include a gate connected to the Q node, a first terminal receiving the low gate voltage VGL, and a second terminal connected to the output terminal T_OUT. The first terminal of the first pull-down transistor M6 may be one of the source and drain, and the second terminal of the first pull-down transistor M6 may be the other of the source and drain.

[0044] The first protection transistor M7 may include a gate that receives a low gate voltage VGL, a first terminal connected to node A, and a second terminal connected to node Q. The first terminal of the first protection transistor M7 may be one of the source and drain, and the second terminal of the first protection transistor M7 may be the other of the source and drain. In the case where a second low gate voltage, lower than the low gate voltage VGL, is applied to node Q, the first protection transistor M7 can protect the input transistor M1 by allowing a voltage higher than the second low gate voltage to be applied to node A.

[0045] The second protection transistor M8 may include a gate receiving a low gate voltage VGL, a first terminal connected to the second terminal of the first control transistor M9, and a second terminal connected to node B. The first terminal of the second protection transistor M8 may be one of the source and drain, and the second terminal of the second protection transistor M8 may be the other of the source and drain. In the case where the second low gate voltage is applied to node B, the second protection transistor M8 can protect the first control transistor M9 by applying a voltage higher than the second low gate voltage to the second terminal of the first control transistor M9.

[0046] The first control transistor M9 can transmit the signal QB_PR from the previous stage's QB node to the B node in response to the signal from the Q node. The first control transistor M9 may include a gate connected to the Q node, a first terminal receiving the signal QB_PR from the previous stage's QB node, and a second terminal connected to the first terminal of the second protection transistor M8. The first terminal of the first control transistor M9 may be one of the source and drain, and the second terminal of the first control transistor M9 may be the other of the source and drain.

[0047] The reset transistor M10 can transmit a low gate voltage VGL to the Q node in response to a reset signal RST. The reset transistor M10 may include a gate for receiving the reset signal RST, a first terminal for receiving the low gate voltage VGL, and a second terminal connected to the Q node. The first terminal of the reset transistor M10 may be one of the source and drain, and the second terminal of the reset transistor M10 may be the other of the source and drain.

[0048] The second pull-down transistor M11 can output a low gate voltage VGL as an output signal OUT in response to the signal from node B. The second pull-down transistor M11 may include a gate connected to node B, a first terminal receiving the low gate voltage VGL, and a second terminal connected to the output terminal T_OUT. The first terminal of the second pull-down transistor M11 may be one of the source and drain, and the second terminal of the second pull-down transistor M11 may be the other of the source and drain.

[0049] In one embodiment, the second pull-down transistor M11 may be an NMOS transistor, and excluding the second pull-down transistor M11, each of the transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10 included in the stage ST may be a PMOS transistor. In another embodiment, the second pull-down transistor M11 may be an oxide semiconductor transistor, and excluding the second pull-down transistor M11, each of the transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10 included in the stage ST may be a polysilicon transistor.

[0050] A first capacitor C1 can be connected between the QB node and the line transmitting the high gate voltage VGH. The first capacitor C1 may include a first terminal connected to the QB node and a second terminal receiving the high gate voltage VGH. The first capacitor C1 can store the signal of the QB node.

[0051] A second capacitor C2 can be connected between the Q node and the output terminal T_OUT. The second capacitor C2 may include a first terminal connected to the Q node and a second terminal connected to the output terminal T_OUT. The second capacitor C2 can store the signal of the Q node. Furthermore, in cases where the voltage level of the output signal OUT (e.g., the output voltage) changes, the second capacitor C2 can bootstrap the signal of the Q node.

[0052] A third capacitor C3 can be connected between node B and node C. The third capacitor C3 may include a first terminal connected to node B and a second terminal connected to node C. When the signal at node C changes, the third capacitor C3 can bootstrap the signal at node B.

[0053] Figure 3 This illustrates an embodiment. Figure 2 Timing diagram of the ST signal.

[0054] Reference Figure 2 and Figure 3 The operating cycle of a ST (Stationary ST) can include a first cycle P1, a second cycle P2, and a third cycle P3. The first cycle P1 can include a first-first cycle P1-1 and a first-second cycle P1-2, and the second cycle P2 can include a second-first cycle P2-1 and a second-second cycle P2-2.

[0055] The input signal IN can have a low gate voltage VGL in the first cycle P1-1, a high gate voltage VGH in the first cycle P1-2 and the second cycle P2-1, and a low gate voltage VGL in the second cycle P2-2 and the third cycle P3. The clock signal CLK can have alternating high gate voltage VGH and low gate voltage VGL. The signal QB_PR of the previous stage QB node can have a high gate voltage VGH in the first cycle P1-1, and the signal QB_PR of the previous stage QB node can have a low gate voltage VGL and a threshold voltage VGL of the second control transistor M2 in the first cycle P1-2 and the second cycle P2-1. TH The sum and corresponding voltage VGL+|V TH The signal QB_PR of the previous stage QB node can have a high gate voltage VGH in the second-second cycle P2-2 and the third cycle P3.

[0056] Figures 4 to 8 It is used to describe the embodiments. Figure 2 A diagram of ST operations at the level of ST.

[0057] Reference Figure 3 and Figure 4 In the first cycle P1-1, input transistor M1, second control transistor M2, fourth control transistor M4, first pull-down transistor M6, first protection transistor M7, second protection transistor M8, first control transistor M9, and second pull-down transistor M11 can be turned on. A low gate voltage VGL can be applied to nodes A and Q through input transistor M1 and first protection transistor M7. Through the first pull-down transistor M6, the output signal OUT can have a low gate voltage VGL. Through the bootstrapping of the second capacitor C2, the signal at node Q can have a second low gate voltage 2VGL, which is lower than the low gate voltage VGL. A high gate voltage VGH can be applied to node B through first control transistor M9 and second protection transistor M8. A high gate voltage VGH can be applied to node QB through fourth control transistor M4.

[0058] Reference Figure 3 and Figure 5 During the first-second cycle P1-2, the third control transistor M3, the fourth control transistor M4, the first pull-down transistor M6, the first protection transistor M7, the second protection transistor M8, the first control transistor M9, and the second pull-down transistor M11 can be turned on. The output signal OUT can be maintained at a low gate voltage VGL. This is related to the low gate voltage VGL and the threshold voltage V of the second control transistor M2. TH The sum and corresponding voltage VGL+|V THA high gate voltage VGH can be applied to node B via the first control transistor M9 and the second protection transistor M8. A high gate voltage VGH can be applied to node C via the fourth control transistor M4 and the third control transistor M3.

[0059] Reference Figure 3 and Figure 6 In the second-first cycle P2-1, input transistor M1, second control transistor M2, third control transistor M3, pull-up transistor M5, and first protection transistor M7 can be turned on. A high gate voltage VGH can be applied to nodes A and Q through input transistor M1 and first protection transistor M7. This is related to the low gate voltage VGL and the threshold voltage V of the second control transistor M2. TH The sum and corresponding voltage VGL+|V TH The control can be applied to nodes C and QB via the second control transistor M2 and the third control transistor M3. Through the bootstrapping of the third capacitor C3, the signal at node B can have a second low gate voltage of 2VGL. Through the pull-up transistor M5, the output signal OUT can have a high gate voltage of VGH.

[0060] Reference Figure 3 and Figure 7 In the second-second cycle P2-2, the third control transistor M3, the pull-up transistor M5, and the first protection transistor M7 can be turned on. Since the input signal IN transitions to a low gate voltage VGL, but the clock signal CLK has a high gate voltage VGH, the input transistor M1 can be turned off, and therefore, the signals of nodes Q, QB, A, B, and C, as well as the output signal OUT, can maintain their states in the second-first cycle P2-1.

[0061] Reference Figure 3 and Figure 8 In the third cycle P3, input transistor M1, second control transistor M2, fourth control transistor M4, first pull-down transistor M6, first protection transistor M7, second protection transistor M8, first control transistor M9, and second pull-down transistor M11 can be turned on. A low gate voltage VGL can be applied to nodes A and Q through input transistor M1 and first protection transistor M7. The output signal OUT can have a low gate voltage VGL through the first pull-down transistor M6. Through the bootstrapping of the second capacitor C2, the signal at node Q can have a second low gate voltage 2VGL. A high gate voltage VGH can be applied to node B through first control transistor M9 and second protection transistor M8. A high gate voltage VGH can be applied to node QB through fourth control transistor M4.

[0062] In this embodiment, during the third cycle P3, the signal at the Q node can transition from a high gate voltage VGH to a second low gate voltage 2VGL in one step, and therefore, the output signal OUT (e.g., the output voltage) can transition from the high gate voltage VGH to the low gate voltage VGL in one step. Therefore, the output signal OUT may not have an intermediate voltage between the high gate voltage VGH and the low gate voltage VGL, and thus, the reliability of the output signal OUT can be improved.

[0063] In this embodiment, during the second cycle P2, a voltage level higher than the low gate voltage VGL is compared with the low gate voltage VGL and the threshold voltage V of the second control transistor M2. TH The sum and corresponding voltage VGL+|V TH This can be applied to the QB node, and therefore, the quiescent current flowing from the pull-up transistor M5 to the first pull-down transistor M6 can be reduced. Consequently, the power consumption of stage ST can be reduced.

[0064] In this embodiment, the lengths of the first period P1 and the third period P3 can vary depending on the gate driver 10 (see [link]). Figure 1 The driving frequency of the display device decreases, and the leakage current of the input transistor M1 and the first protection transistor M7 increases with the length of the first cycle P1 and the third cycle P3. During the first cycle P1 and the third cycle P3, even if the signal at the Q node rises from the second low gate voltage 2VGL to the low gate voltage VGL due to the leakage current of the input transistor M1 and the first protection transistor M7, the output signal OUT can be maintained at the low gate voltage VGL by the second pull-down transistor M11. Therefore, the reliability of the output signal OUT of the display device under low-frequency driving can be improved, and the power consumption caused by low-frequency driving can be reduced. Furthermore, since the output signal OUT is stably maintained at the low gate voltage VGL, the stability of the operation of the gate driver 10 can be ensured.

[0065] In oxide semiconductor transistors (OSTs), threshold voltage shift due to stress may occur, and therefore, OSTs may operate in depletion mode. In the case where the second pull-down transistor M11, which is an OST, operates in depletion mode, the second pull-down transistor M11 may be turned on, causing a change in the output signal OUT or an increase in power consumption. In the embodiment, during the second cycle P2, due to the bootstrapping of the third capacitor C3, the signal at node B may have a second low gate voltage 2VGL, and even if the second pull-down transistor M11 operates in depletion mode, the second pull-down transistor M11 may be turned off. Therefore, the second pull-down transistor M11 can operate stably. Furthermore, the requirement to supply a voltage level below the low gate voltage VGL to the gate driver 10 to prevent the second pull-down transistor M11 from operating in depletion mode can be omitted, thereby preventing an increase in the number of power lines supplying voltage to the gate driver 10.

[0066] In the case where a low gate voltage VGL is applied to the Q node via a reset transistor M10 that is turned on in response to a reset signal RST, the output signal OUT can have a voltage corresponding to the sum of the low gate voltage VGL and the threshold voltage of the first pull-down transistor M6. In an embodiment, the low gate voltage VGL can be transmitted to the output terminal T_OUT via a second pull-down transistor M11, and therefore, the output signal OUT can be reduced to the low gate voltage VGL. Thus, when the gate driver 10 is reset, the output signal OUT can have a low gate voltage VGL.

[0067] exist Figures 2 to 8 In this embodiment, in addition to the first pull-down transistor M6, a second pull-down transistor M11 is included to improve the reliability of the output signal OUT. In this embodiment, the voltages at both the control (or Q) node of the first pull-down transistor M6 and the control (or QB) node of the pull-up transistor M5 can also be modified. The result is a reliable output signal OUT (where the output is not at an intermediate level between the low gate voltage VGL and the high gate voltage VGH), even under low-frequency drive, with reduced power consumption and no need for additional input voltages at each stage.

[0068] Figure 9 It is shown that, according to the embodiments, it includes Figure 1 A circuit diagram of an example stage ST' in gate driver 10.

[0069] Reference Figure 9Stage ST' may include input transistor M1, second control transistor M2, third control transistor M3, fourth control transistor M4, pull-up transistor M5, first pull-down transistor M6, first protection transistor M7, second protection transistor M8, first control transistor M9, reset transistor M10, second pull-down transistor M11, first capacitor C1, second capacitor C2, and third capacitor C3. (Note: The last sentence appears to be incomplete and possibly refers to a different stage or stage.) Figure 9 The detailed description of level ST' will make it understandable that, within this disclosure, level ST' is at least related to Figure 2 Similar to ST.

[0070] The second control transistor M2 can transmit a clock signal CLK to the gate and first terminal of the third control transistor M3 in response to a signal from node B. The second control transistor M2 may include a gate connected to node B, a first terminal for receiving the clock signal CLK, and a second terminal connected to the gate and first terminal of the third control transistor M3.

[0071] The third control transistor M3 may include a gate connected to the second terminal of the second control transistor M2, a first terminal connected to the second terminal of the second control transistor M2, and a second terminal connected to the QB node. The third control transistor M3 may be connected in a diode configuration. In the case where the clock signal CLK has a low gate voltage VGL, a voltage corresponding to the sum of the low gate voltage VGL and the threshold voltage of the third control transistor M3 may be applied to the QB node.

[0072] Gate parasitic capacitance can exist at the gate of the transistor, and first terminal parasitic capacitance can exist at the first terminal of the transistor. (Refer to...) Figure 2 In the described embodiment, the line transmitting the clock signal CLK can be connected to the gate and the first terminal of the second control transistor M2, and therefore, the parasitic capacitance observed in the clock signal CLK can correspond to the sum of the gate parasitic capacitance of the second control transistor M2 and the first terminal parasitic capacitance of the second control transistor M2.

[0073] In reference Figure 9 In the described embodiment, the line transmitting the clock signal CLK can be connected only to the first terminal of the second control transistor M2, and therefore, the parasitic capacitance observed in the clock signal CLK can correspond to the parasitic capacitance of the first terminal of the second control transistor M2. Thus, the parasitic capacitance observed in the clock signal CLK can be reduced, and therefore, the power consumption caused by the clock signal CLK can be reduced.

[0074] A third capacitor C3 can be connected between node B and node QB. The third capacitor C3 may include a first terminal connected to node B and a second terminal connected to node QB. When the signal at node QB changes, the third capacitor C3 can bootstrap the signal at node B.

[0075] In reference Figure 2 In the described embodiment, only the first capacitor C1 can be connected to the QB node. In the case where the clock signal CLK is transmitted to the QB node via the second control transistor M2 and the third control transistor M3, the parasitic capacitance observed in the clock signal CLK corresponds to the capacitance of the first capacitor C1.

[0076] In reference Figure 9 In the described embodiment, the first capacitor C1 and the third capacitor C3 can be connected to the QB node. In the case where the clock signal CLK is transmitted to the QB node via the second control transistor M2 and the third control transistor M3, the parasitic capacitance observed in the clock signal CLK corresponds to the sum of the capacitances of the first capacitor C1 and the third capacitor C3. Therefore, the parasitic capacitance observed in the clock signal CLK can increase, and the fall time of the clock signal CLK can increase.

[0077] and Figure 2 Compared to the previous embodiment, in Figure 9 In one embodiment, the parasitic capacitance of the clock signal CLK can be reduced to reduce power consumption, while the parasitic capacitance observed in the clock signal CLK can be increased to increase the fall time of the clock signal CLK.

[0078] Figure 10 It is shown that, according to the embodiments, it includes Figure 1 A circuit diagram of an example stage ST'' in gate driver 10.

[0079] Reference Figure 10 Stage ST'' may include input transistor M1, second control transistor M2, third control transistor M3, fourth control transistor M4, pull-up transistor M5, first pull-down transistor M6, first protection transistor M7, second protection transistor M8, first control transistor M9, reset transistor M10, first capacitor C1, second capacitor C2, and third capacitor C3. (Note: The last sentence appears to be incomplete and possibly refers to a different stage or stage.) Figure 10 The detailed description of level ST'' will make it understandable that, within this disclosure, level ST'' is at least related to Figure 9 Similar to ST'.

[0080] The reset transistor M10 can transmit a low gate voltage VGL to the QB node in response to a reset signal RST. The reset transistor M10 may include a gate for receiving the reset signal RST, a first terminal for receiving the low gate voltage VGL, and a second terminal connected to the QB node.

[0081] A third capacitor C3 can be connected between node B and node C. The third capacitor C3 may include a first terminal connected to node B and a second terminal connected to node C. When the signal at node C changes, the third capacitor C3 can bootstrap the signal at node B.

[0082] If the leakage current of the input transistor M1 and the first protection transistor M7 is small, even if the driving frequency of the display device is reduced, the output signal OUT can still be maintained. Figure 3 The first period P1 and Figure 3 The gate voltage VGL is maintained low during the third cycle P3. In an embodiment, stage ST'' may not include... Figure 2 and Figure 9 The second pull-down transistor M11 holds the output signal OUT at a low gate voltage VGL. Stage ST'' can consist only of PMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10, which are polysilicon transistors, and therefore, the number of masks used to manufacture stage ST'' can be reduced. Consequently, the manufacturing time and cost of the display device can be reduced.

[0083] Figure 11 This is a block diagram illustrating a display device 100 according to an embodiment.

[0084] Reference Figure 11 The display device 100 may include a display panel 110, a first gate driver 121, a second gate driver 122, a third gate driver 123, a fourth gate driver 124, a fifth gate driver 125, a data driver 130, and a controller 140.

[0085] Display panel 110 may include pixel rows PR. Each pixel row PR may include a pixel PX.

[0086] The first gate driver 121 may include a stage that outputs a write gate signal GW to the pixel row PR. The first gate driver 121 may be referred to as a write gate driver. The first gate driver 121 may generate the write gate signal GW based on a first gate control signal GCS1. The first gate control signal GCS1 may include a write gate start signal, a write gate clock signal, etc.

[0087] The second gate driver 122 may include a stage that outputs a compensation gate signal GC to the pixel row PR. The second gate driver 122 may be referred to as a compensation gate driver. The second gate driver 122 may generate the compensation gate signal GC based on the second gate control signal GCS2. The second gate control signal GCS2 may include a compensation gate start signal, a compensation gate clock signal, etc.

[0088] The third gate driver 123 may include a stage that outputs an initialization gate signal GI to the pixel row PR. The third gate driver 123 may be referred to as an initialization gate driver. The third gate driver 123 may generate the initialization gate signal GI based on the third gate control signal GCS3. The third gate control signal GCS3 may include an initialization gate start signal, an initialization gate clock signal, etc.

[0089] The fourth gate driver 124 may include a stage that outputs a bypass gate signal GB to pixel row PR. The fourth gate driver 124 may be referred to as a bypass gate driver. The fourth gate driver 124 may generate the bypass gate signal GB based on the fourth gate control signal GCS4. The fourth gate control signal GCS4 may include a bypass gate start signal, a bypass gate clock signal, etc.

[0090] The fifth gate driver 125 may include a stage that outputs a transmit control signal EM to the pixel row PR. The fifth gate driver 125 may be referred to as a transmit control driver. The fifth gate driver 125 may generate the transmit control signal EM based on the fifth gate control signal GCS5. The fifth gate control signal GCS5 may include a transmit control start signal, a transmit control clock signal, etc.

[0091] In an embodiment, Figure 1 The gate driver 10 may be one of the second gate driver 122, the third gate driver 123, the fourth gate driver 124, and the fifth gate driver 125.

[0092] The data driver 130 can output a data voltage VDAT to the pixel PX. The data driver 130 can generate the data voltage VDAT based on the output image data IMD2 and the data control signal DCS. The data driver 130 can convert the digital output image data IMD2 into the analog data voltage VDAT. The data control signal DCS may include a load signal, a data clock signal, an output data enable signal, etc.

[0093] The controller 140 can control the first gate driver 121, the second gate driver 122, the third gate driver 123, the fourth gate driver 124, the fifth gate driver 125, and the data driver 130. The controller 140 can output a first gate control signal GCS1 to the first gate driver 121, a second gate control signal GCS2 to the second gate driver 122, a third gate control signal GCS3 to the third gate driver 123, a fourth gate control signal GCS4 to the fourth gate driver 124, a fifth gate control signal GCS5 to the fifth gate driver 125, and output image data IMD2 and data control signal DCS to the data driver 130. The controller 140 can generate a first gate control signal GCS1, a second gate control signal GCS2, a third gate control signal GCS3, a fourth gate control signal GCS4, a fifth gate control signal GCS5, output image data IMD2, and a data control signal DCS based on the input image data IMD1 and the control signal CTRL. The controller 140 can convert the input image data IMD1 into the output image data IMD2. The control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc.

[0094] Figure 12 This illustrates an embodiment. Figure 11 The circuit diagram of the pixel PX.

[0095] Reference Figure 12 Pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST, and a light-emitting element EL. In an embodiment, pixel PX may also include an eighth transistor T8.

[0096] The first transistor T1 may include a gate connected to a first node N1, a first terminal connected to a second node N2, and a second terminal connected to a third node N3. In an embodiment, the first transistor T1 may also include a body (or back gate) that receives a first power voltage ELVDD. The first terminal of the first transistor T1 may be one of the source and drain, and the second terminal of the first transistor T1 may be the other of the source and drain.

[0097] The second transistor T2 can transmit a data voltage VDAT to the second node N2 in response to a write gate signal GW. The second transistor T2 may include a gate for receiving the write gate signal GW, a first terminal for receiving the data voltage VDAT, and a second terminal connected to the second node N2. The first terminal of the second transistor T2 may be one of the source and the drain, and the second terminal of the second transistor T2 may be the other of the source and the drain.

[0098] The third transistor T3 can connect the first node N1 to the third node N3 in response to the compensation gate signal GC. The third transistor T3 may include a gate for receiving the compensation gate signal GC, a first terminal connected to the first node N1, and a second terminal connected to the third node N3. The first terminal of the third transistor T3 may be one of the source and the drain, and the second terminal of the third transistor T3 may be the other of the source and the drain.

[0099] The fourth transistor T4 can transmit a first initialization voltage VINT to the first node N1 in response to an initialization gate signal GI. The fourth transistor T4 may include a gate for receiving the initialization gate signal GI, a first terminal for receiving the first initialization voltage VINT, and a second terminal connected to the first node N1. The first terminal of the fourth transistor T4 may be one of the source and the drain, and the second terminal of the fourth transistor T4 may be the other of the source and the drain.

[0100] The fifth transistor T5 can transmit a first power voltage ELVDD to the second node N2 in response to a transmit control signal EM. The fifth transistor T5 may include a gate for receiving the transmit control signal EM, a first terminal for receiving the first power voltage ELVDD, and a second terminal connected to the second node N2. The first terminal of the fifth transistor T5 may be one of the source and drain, and the second terminal of the fifth transistor T5 may be the other of the source and drain.

[0101] The sixth transistor T6 can connect the third node N3 to the fourth node N4 in response to the transmit control signal EM. The sixth transistor T6 may include a gate for receiving the transmit control signal EM, a first terminal connected to the third node N3, and a second terminal connected to the fourth node N4. The first terminal of the sixth transistor T6 may be one of the source and drain, and the second terminal of the sixth transistor T6 may be the other of the source and drain.

[0102] The seventh transistor T7 can transmit a second initialization voltage VAINT to the fourth node N4 in response to the bypass gate signal GB. The seventh transistor T7 may include a gate for receiving the bypass gate signal GB, a first terminal for receiving the second initialization voltage VAINT, and a second terminal connected to the fourth node N4. The first terminal of the seventh transistor T7 may be one of the source and drain, and the second terminal of the seventh transistor T7 may be the other of the source and drain.

[0103] The eighth transistor T8 can transmit a bias voltage VBIAS to the second node N2 in response to the bypass gate signal GB. The eighth transistor T8 may include a gate for receiving the bypass gate signal GB, a first terminal for receiving the bias voltage VBIAS, and a second terminal connected to the second node N2. The first terminal of the eighth transistor T8 may be one of the source and drain, and the second terminal of the eighth transistor T8 may be the other of the source and drain.

[0104] A storage capacitor CST can be connected between the first node N1 and the power line transmitting the first power voltage ELVDD. The storage capacitor CST may include a first terminal connected to the first node N1 and a second terminal receiving the first power voltage ELVDD. The storage capacitor CST can store the signal of the first node N1.

[0105] The light-emitting element EL may include a first terminal (or anode) connected to the fourth node N4 and a second terminal (or cathode) receiving the second power voltage ELVSS. The light-emitting element EL may emit light with a brightness corresponding to the magnitude of the drive current generated from the first transistor T1.

[0106] Figure 13 This is a block diagram illustrating an electronic device 1000 according to an embodiment.

[0107] Reference Figure 13 The electronic device 1000 can output various information via the display module 1040 through the operating system. In the case where the processor 1010 executes an application stored in the memory 1020, the display module 1040 can provide application information to the user via the display panel 1041. In other words, the processor 1010 can control the display module 1040. In this embodiment, the processor 1010 can provide information to the display module 1040. Figure 11 Input image data IMD1 and Figure 11 The control signal CTRL.

[0108] Processor 1010 can obtain external input via input module 1030 or sensor module 1061, and processor 1010 can execute an application corresponding to the external input. For example, in the case where the user selects a camera icon displayed on display panel 1041, processor 1010 can obtain user input via input sensor 1061-2, and processor 1010 can activate camera module 1071. Processor 1010 can transmit image data corresponding to a captured image, which is obtained through camera module 1071, to display module 1040. Display module 1040 can display the image corresponding to the captured image via display panel 1041. Some of the components of electronic device 1000 may be provided as a single, continuous structure as one (e.g., a single) component, or components may be provided individually as two or more components.

[0109] Electronic device 1000 can communicate with external electronic device 1002 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). In embodiments, electronic device 1000 may include processor 1010, memory 1020, input module 1030, display module 1040, power module 1050, internal module 1060, and external module 1070. In embodiments, electronic device 1000 may omit at least one of the above-mentioned components, or may add one or more other components. In embodiments, some of the above-mentioned components (e.g., sensor module 1061, antenna module 1062, or sound output module 1063) may be integrated into another component (e.g., display module 1040).

[0110] Processor 1010 can execute software to control at least one other component (e.g., hardware or software component) of electronic device 1000 connected to processor 1010, and processor 1010 can perform various data processing or calculations. In an embodiment, as at least part of data processing or calculation, processor 1010 can store commands or data received from another component (e.g., input module 1030, sensor module 1061, or communication module 1073) in volatile memory 1021, processor 1010 can process the commands or data stored in volatile memory 1021, and processor 1010 can store result data in non-volatile memory 1022.

[0111] Processor 1010 may include a main processor 1011 and a coprocessor 1012. Main processor 1011 may include one or more of a central processing unit (CPU) 1011-1 and an application processor (AP). Main processor 1011 may also include one or more of a graphics processing unit (GPU) 1011-2, a communication processor (CP), and an image signal processor (ISP). At least two of the aforementioned processing units and processors may be implemented as a single, uninterrupted structure (e.g., a single chip), or the aforementioned processing units and processors may each be implemented as independent components (e.g., multiple chips).

[0112] The coprocessor 1012 may include a controller 1012-1. The controller 1012-1 may include interface conversion circuitry and timing control circuitry. The controller 1012-1 can receive image signals from the main processor 1011, convert the data format of the image signals to suit the interface specifications of the display module 1040, and output image data. The controller 1012-1 can output various control signals required to drive the display module 1040.

[0113] The coprocessor 1012 may also include a data conversion circuit 1012-2, a gamma correction circuit 1012-3, a rendering circuit 1012-4, etc. The data conversion circuit 1012-2 can receive image data from the controller 1012-1, and can compensate the image data to display the image at the required brightness according to the characteristics of the electronic device 1000 or user settings, or it can convert the image data to reduce power consumption or compensate for afterimages. The gamma correction circuit 1012-3 can convert the image data or gamma reference voltage so that the image displayed in the electronic device 1000 has the required gamma characteristics. The rendering circuit 1012-4 can receive image data from the controller 1012-1, and can render the image data by taking into account the pixel arrangement of the display panel 1041 applied to the electronic device 1000. At least one of the data conversion circuit 112-2, the gamma correction circuit 1012-3, and the rendering circuit 1012-4 may be integrated into another component (e.g., the main processor 1011 or the controller). At least one of the data conversion circuit 1120-2, the gamma correction circuit 1012-3, and the rendering circuit 1120-4 may be integrated into the data driver 1043, which will be described below.

[0114] The memory 1020 may store various data used by at least one component of the electronic device 1000 (e.g., processor 1010 or sensor module 1061), as well as input or output data for commands related to the various data. The memory 1020 may include at least one of volatile memory 1021 and non-volatile memory 1022.

[0115] The input module 1030 can receive commands or data from outside the electronic device 1000 (e.g., from a user or external electronic device 1002) that will be used in components of the electronic device 1000 (e.g., processor 1010, sensor module 1061, or sound output module 1063).

[0116] Input module 1030 may include a first input module 1031 and a second input module 1032. Commands or data from the user are input via the first input module 1031, and commands or data from an external electronic device 1002 are input via the second input module 1032. The first input module 1031 may include a microphone, mouse, keyboard, buttons (e.g., keypads), or pen (e.g., a passive or active pen). The second input module 1032 may support a specified protocol that can be connected to the external electronic device 1002 via wired or wireless means. In embodiments, the second input module 1032 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, or an audio interface. The second input module 1032 may include a connector (e.g., an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector)) that can be physically connected to the external electronic device 1002.

[0117] Display module 1040 can provide visual information to a user. Display module 1040 may include a display panel 1041, a gate driver 1042, and a data driver 1043. Display module 1040 may also include a window, a base, and a bracket for protecting the display panel 1041. Display module 1040 can be used with... Figure 11 The display device 100 corresponds to the display panel 1041. Figure 11 Corresponding to the display panel 110, the gate driver 1042 can be connected to... Figure 11 First gate driver 121 Figure 11 The second gate driver 122 Figure 11 The third gate driver 123 Figure 11 The fourth gate driver 124 and / or Figure 11 The fifth gate driver 125 corresponds to it, and the data driver 1043 can be connected to it. Figure 11 The data drive 130 is compatible.

[0118] Power module 1050 can supply power to components of electronic device 1000. Power module 1050 may include a battery that can be charged with a power voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power module 1050 may include power management circuitry 1051. Power management circuitry 1051 can supply optimized power to each of the modules described above and below. Power module 1050 may include a wireless power transmitting / receiving component electrically connected to the battery. The wireless power transmitting / receiving component may include multiple coil-shaped antenna radiators.

[0119] The electronic device 1000 may also include an internal module 1060 and an external module 1070. The internal module 1060 may include a sensor module 1061, an antenna module 1062, and a sound output module 1063. The external module 1070 may include a camera module 1071, an optical module 1072, and a communication module 1073.

[0120] Sensor module 1061 can detect input via the user's body or via a pen in the first input module 1031, and sensor module 1061 can generate an electrical signal or data value corresponding to the input. Sensor module 1061 may include at least one of fingerprint sensor 1061-1, input sensor 1061-2, and digitizer 1061-3.

[0121] The processor 1010 can output commands or data to the display module 1040, the sound output module 1063, the camera module 1071, or the optical module 1072 based on input data received from the input module 1030. For example, the processor 1010 can generate image data and output the image data to the display module 1040 in response to input data applied by a mouse or active pen, or the processor 1010 can generate command data in response to input data to output the command data to the camera module 1071 or the optical module 1072. In cases where no input data is received from the input module 1030 for a certain period of time, the processor 1010 can switch the operating mode of the electronic device 1000 to a low-power mode or a sleep mode to reduce the power consumption of the electronic device 1000.

[0122] The processor 1010 can output commands or data to the display module 1040, the sound output module 1063, the camera module 1071, or the optical module 1072 based on the sensing data received from the sensor module 1061. For example, the processor 1010 can compare the authentication data authenticated by the fingerprint sensor 1061-1 with the authentication data stored in the memory 1020, and then the processor 1010 can execute an application based on the comparison result. The processor 1010 can execute commands or output corresponding image data to the display module 1040 based on the sensing data detected by the input sensor 1061-2 or the digitizer 1061-3. In the case where the sensor module 1061 includes a temperature sensor, the processor 1010 can receive temperature data about the temperature measured from the sensor module 1061, and the processor 1010 can further perform brightness correction on the image data, etc., based on the temperature data.

[0123] The display device according to the embodiment can be applied to display devices including computers, laptops, mobile phones, smartphones, smartboards, smartwatches, portable media players (PMPs), personal digital assistants (PDAs), or Motion Picture Experts Compression Standard Audio Layer 3 (MP3) players.

[0124] Reference Figure 1 , Figure 2 , Figure 3 , Figure 9 and Figure 10 Embodiments of this disclosure relate to a gate driver 10, a display device 100 including the gate driver 10, and an electronic device 1000 including the display device 100, wherein the gate driver 10 includes a plurality of stages ST / ST' / ST''. Each of the stages ST / ST' / ST'' may include circuitry to prevent the output from reaching an intermediate voltage between a high gate voltage VGH and a low gate voltage VGL, thereby improving reliability. The stage circuitry includes an output terminal T_OUT disposed between a pull-up transistor M5 and pull-down transistors M6 and M11. A second pull-down transistor M11 may be included to prevent the output voltage from rising above a low voltage level to reach an intermediate level. The second pull-down transistor M11 and the first pull-down transistor M6 are electrically connected in parallel. The stage circuitry includes a QB node, a Q node, and a B node, wherein the QB node is a control node for the pull-up transistor M5 (i.e., connected to the gate of the pull-up transistor M5), the Q node is connected to the gate of the first pull-down transistor M6, and the B node is connected to the gate of the second pull-down transistor M11.

[0125] When driven at low frequencies (where the control (or Q) node of the first pull-down transistor M6 rises to a low gate voltage VGL due to leakage current from the input transistor M1 and the first protection transistor M7), the output signal OUT can still be maintained at a low gate voltage VGL. In the case where the second pull-down transistor M11 operates in depletion mode, the signal at node B can have a second low gate voltage 2VGL to turn off the second pull-down transistor M11, reducing the quiescent current flowing through it and saving power. Furthermore, a third voltage is not required to drive the gate driver, thus reducing the complexity of the power voltage generator.

[0126] Although the gate driver, display device, and electronic device according to embodiments have been described with reference to the accompanying drawings, the illustrated embodiments are examples, and modifications and changes can be made to the illustrated embodiments by those skilled in the art without departing from the spirit of the technology described in the claims.

Claims

1. A gate driver, wherein, The gate driver includes multiple stages. Each of the plurality of levels includes: The input transistor is configured to transmit an input signal to the Q node in response to a clock signal; An output terminal is configured to output an output signal, the output terminal being disposed between a pull-up transistor and each of a first pull-down transistor and a second pull-down transistor; The pull-up transistor is configured to output a high gate voltage as the output signal in response to a signal from a QB node, wherein the QB node is connected to the gate of the pull-up transistor. The first pull-down transistor is configured to output a low gate voltage as the output signal in response to a signal from the Q node; The second pull-down transistor is configured to output the low gate voltage as the output signal in response to a signal from node B, wherein node B is connected to the gate of the second pull-down transistor; and A first control transistor is configured to transmit a signal from a previous stage QB node to the B node in response to the signal from the Q node, the Q node being connected to both the gate of the first pull-down transistor and the gate of the first control transistor.

2. The gate driver according to claim 1, wherein, Each of the plurality of levels also includes: The second control transistor includes a gate configured to receive the clock signal, a first terminal configured to receive the clock signal, and a second terminal connected to the C node. The voltage of the C node corresponds to the sum of the low gate voltage of the clock signal and the threshold voltage of the second control transistor, and the voltage of the C node is applied to the QB node.

3. The gate driver according to claim 2, wherein, Each of the plurality of levels also includes: A third control transistor is configured to connect the QB node to the C node in response to the signal from the B node.

4. The gate driver according to claim 3, wherein, When the input signal has the high gate voltage and the clock signal has the low gate voltage, the voltage corresponding to the sum of the low gate voltage and the threshold voltage of the second control transistor is applied to the QB node through the second control transistor and the third control transistor.

5. The gate driver according to claim 3, wherein, Each of the plurality of levels also includes: A third capacitor is connected between node B and node C.

6. The gate driver according to any one of claims 1 to 5, wherein, Each of the plurality of levels also includes: A fourth control transistor is configured to transmit the high gate voltage to the QB node in response to the signal from the Q node.

7. The gate driver according to any one of claims 1 to 5, wherein, Each of the plurality of levels also includes: The first protection transistor includes a gate configured to receive the low gate voltage, a first terminal connected to a second terminal of the input transistor, and a second terminal connected to the Q node.

8. The gate driver according to claim 7, wherein, Each of the plurality of levels also includes: The second protection transistor includes a gate configured to receive the low gate voltage, a first terminal connected to the second terminal of the first control transistor, and a second terminal connected to the B node.

9. The gate driver according to any one of claims 1 to 5, wherein, Each of the plurality of levels also includes: A reset transistor is configured to transmit the low gate voltage to the Q node in response to a reset signal.

10. The gate driver according to any one of claims 1 to 5, wherein, Each of the plurality of levels also includes: The first capacitor includes a first terminal connected to the QB node and a second terminal configured to receive the high gate voltage.

11. The gate driver according to any one of claims 1 to 5, wherein, Each of the plurality of levels also includes: The second capacitor includes a first terminal connected to the Q node and a second terminal connected to the output terminal configured to output the output signal.

12. The gate driver according to claim 11, wherein, When the input signal has the low gate voltage, when the clock signal has the low gate voltage, and when the output signal transitions from the high gate voltage to the low gate voltage, the signal of the Q node transitions from the high gate voltage to a voltage lower than the low gate voltage.

13. The gate driver according to claim 1, wherein, Each of the plurality of levels also includes: The second control transistor includes a gate connected to the B node, a first terminal configured to receive the clock signal, and a second terminal.

14. The gate driver of claim 13, wherein, Each of the plurality of levels also includes: The third control transistor includes a gate connected to the second terminal of the second control transistor, a first terminal connected to the second terminal of the second control transistor, and a second terminal connected to the QB node.

15. The gate driver according to claim 14, wherein, Each of the plurality of levels also includes: A third capacitor is connected between node B and node QB.

16. The gate driver according to any one of claims 1 to 5 and 13 to 15, wherein, The second pull-down transistor is an N-type metal-oxide-semiconductor transistor, and Excluding the second pull-down transistor, each of the multiple transistors in each of the multiple stages is a P-type metal-oxide-semiconductor transistor.

17. A display device, wherein, The display device includes: A display panel comprising multiple pixel rows, each of the multiple pixel rows comprising multiple pixels; and The gate driver according to any one of claims 1 to 16, wherein the plurality of stages are configured to output gate signals to the plurality of pixel rows.

18. The display device according to claim 17, wherein, Each of the plurality of pixels includes: The first transistor includes a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; The second transistor is configured to transmit a data voltage to the second node in response to a write gate signal; A third transistor is configured to connect the first node to the third node in response to a compensation gate signal; A fourth transistor is configured to transmit a first initialization voltage to the first node in response to an initialization gate signal; The fifth transistor is configured to transmit a first power voltage to the second node in response to a transmit control signal; A sixth transistor is configured to connect the third node to the fourth node in response to the transmit control signal; The seventh transistor is configured to transmit a second initialization voltage to the fourth node in response to a bypass gate signal; A storage capacitor is connected between the first node and a power line configured to transmit the first power voltage; and The light-emitting element includes a first terminal connected to the fourth node and a second terminal configured to receive a second electrical voltage. The output signal is one of the compensation gate signal, the initialization gate signal, the bypass gate signal, and the transmit control signal.

19. The display device according to claim 17, wherein, In each of the plurality of stages, the first pull-down transistor and the second pull-down transistor are connected in parallel.

20. An electronic device, wherein, The electronic device includes: Display device; and The processor is configured to control the display device. The display device includes: A display panel comprising multiple pixel rows, each of the multiple pixel rows comprising multiple pixels; and The gate driver according to any one of claims 1 to 16, wherein the plurality of stages are configured to output gate signals to the plurality of pixel rows.

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