Variable frequency display device

Abstract

A frequency-variable display device is disclosed. The display device includes: a sub-pixel, the sub-pixel including: a driving transistor having a gate electrode connected to a first node and a source electrode connected to a second node; a light-emitting element having an anode electrode connected to the second node; a storage capacitor having one electrode connected to the first node and another electrode connected to the second node; a data line configured to transmit a data voltage to the first node during a gate-source setting period; and a reference voltage line configured to transmit an initialization voltage to the second node during the gate-source setting period. The voltage level of the initialization voltage increases as the light-emitting element deteriorates.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit and priority of Korean Patent Application No. 10-2025-0008786, filed on January 21, 2025, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates to frequency-variable display devices. Background Technology

[0004] A variable frequency display device changes the frame rate of the image displayed on the screen based on the properties of video data received from an external video source. The variable frequency display device supports a variable refresh rate (VRR) function, which changes the frame rate within a predetermined frequency range.

[0005] When the frame rate changes rapidly from a low-speed frame to a high-speed frame or vice versa via VRR operation, flickering caused by perceived brightness deviation may be perceived by the user. To reduce perceived brightness deviation, brightness algorithms that adjust the data gain based on the frame rate are known. However, in such techniques, since the data gain of the current frame is determined based on frequency information about previous frames, there are limitations in reducing the perceived brightness deviation (i.e., VRR flicker) between the first frame immediately following the rapid frame rate change and the frame immediately preceding that first frame.

[0006] The description of related technologies should not be construed as prior art simply because it is mentioned or associated with this section. The description of related technologies includes information describing one or more aspects of the subject matter, and the description in this section does not limit the scope of this disclosure. Summary of the Invention

[0007] In order to overcome the problems of the related technologies, one or more aspects of this disclosure may provide a frequency-variable display device that can reduce VRR flicker that occurs under conditions of rapid changes in frame frequency.

[0008] To achieve these and other advantages, and for the purposes of this disclosure, as embodied and broadly described herein, in one or more aspects, a frequency-variable display device includes: a sub-pixel comprising: a driving transistor having a gate electrode connected to a first node and a source electrode connected to a second node; a light-emitting element having an anode electrode connected to the second node; a storage capacitor having one electrode connected to the first node and another electrode connected to the second node; a data line configured to transmit a data voltage to the first node during a gate-source setup period; and a reference voltage line configured to transmit an initialization voltage to the second node during the gate-source setup period, wherein the voltage level of the initialization voltage increases as the light-emitting element deteriorates.

[0009] In another aspect of this disclosure, a frequency-variable display device includes: a first sub-pixel disposed in a first pixel row and including a first driving transistor and a first light-emitting element, the first driving transistor having a gate electrode connected to a first node and a source electrode connected to a second node, and the first light-emitting element having an anode electrode connected to the second node; a second sub-pixel disposed in a second pixel row and including a second driving transistor and a second light-emitting element, the second driving transistor having a gate electrode connected to a third node and a source electrode connected to a fourth node, and the second light-emitting element having an anode electrode connected to the fourth node; a data line configured to transmit a first data voltage to the first node during a first gate-source setting period and to transmit a second data voltage to the third node during a second gate-source setting period; and a reference voltage line configured to transmit a first initialization voltage to the second node during the first gate-source setting period and to transmit a second initialization voltage to the fourth node during the second gate-source setting period, wherein the first initialization voltage is different from the second initialization voltage.

[0010] The implementation of this disclosure can achieve the following effects.

[0011] One or more aspects of this disclosure can increase the voltage level of the initialization voltage as the light-emitting element deteriorates. Therefore, one or more aspects of this disclosure can reduce low grayscale recognition brightness deviations occurring under conditions of rapid changes in frame frequency, thereby improving VRR flicker and abnormal flash, and thus enhancing display quality.

[0012] Additional features, advantages, and aspects of this disclosure are set forth in part in the description which follows, and in part will be obvious from this disclosure, or may be learned by practicing the inventive concept provided herein. Other features, advantages, and aspects of this disclosure may be realized and obtained by means of the description provided in or derived from this disclosure, as well as the claims and drawings herein. All such features, advantages, and aspects are intended to be included in this specification, within the scope of this disclosure, and protected by the appended claims. Nothing in this section should be construed as limiting these claims. Other features, advantages, and aspects are discussed below in conjunction with embodiments of this disclosure.

[0013] It should be understood that both the foregoing description and the following description of this disclosure are examples and are intended to provide further illustration of the claimed disclosure. Attached Figure Description

[0014] The accompanying drawings are included to provide a further understanding of this disclosure. The drawings are incorporated into and constitute a part of this disclosure. The drawings illustrate aspects and embodiments of this disclosure and, together with the specification, serve to illustrate the principles and examples of this disclosure. In the drawings:

[0015] Figure 1 This is a block diagram illustrating a frequency-variable display device according to an example embodiment of the present disclosure;

[0016] Figure 2 This is a diagram illustrating the connection configuration of pixels according to an exemplary embodiment of the present disclosure;

[0017] Figure 3 This is a diagram illustrating the arrangement of multiple stacks of organic light-emitting diodes (OLEDs) and color filters in a pixel according to an exemplary embodiment of this disclosure;

[0018] Figure 4 This is a diagram illustrating an example of an OLED multi-stack according to an exemplary embodiment of the present disclosure;

[0019] Figure 5 This is a diagram illustrating the vertical active period and vertical blanking period configured for a frame time;

[0020] Figure 6 This is a diagram illustrating an example of how the length of the vertical leading edge included in the vertical blanking period varies horizontally based on the frame frequency;

[0021] Figure 7 This is a diagram illustrating an example of how the perceived brightness level changes based on the frame rate;

[0022] Figure 8This is a diagram illustrating VRR flicker that occurs under conditions of rapid changes in frame frequency;

[0023] Figure 9 and Figure 10 This is a diagram illustrating an example where the visibility of VRR flicker is higher at low gray levels than at high gray levels;

[0024] Figure 11 and Figure 12 This is a diagram illustrating a concept for reducing VRR flicker;

[0025] Figure 13 This is a diagram illustrating another concept for reducing VRR flicker;

[0026] Figure 14 This is a diagram illustrating the equivalent circuit of a sub-pixel according to an exemplary embodiment of the present disclosure;

[0027] Figure 15 This is a graph illustrating an example where the initial voltage increases proportionally to the degradation of the OLED;

[0028] Figure 16 This is a graph illustrating an example of how the Coled charging time decreases by increasing the initial voltage;

[0029] Figure 17 This is a graph showing the change in Vgs when the initial voltage is applied at the default level;

[0030] Figure 18 This is a graph showing the change in Vgs when the initial voltage is applied at a voltage level higher than the default level;

[0031] Figure 19 This is a figure illustrating an example of the decrease in peak brightness in the low grayscale region when the initialization voltage VpreR is increased and / or the DTG coupling effect increases;

[0032] Figure 20A and Figure 20B This diagram illustrates why the abnormal flash phenomenon is severe when representing low gray levels rather than high gray levels;

[0033] Figure 21 and Figure 22 This is a diagram illustrating an example of abnormal flickering caused by capacitance deviation in the configuration of multiple stacked capacitors in an OLED.

[0034] Figure 23 This is a diagram illustrating an example where ΔVgs decreases as the initial voltage increases, thus reducing the over-luminescence current level and preventing flashing.

[0035] Figure 24 This is a graph showing the extent to which VRR flicker is improved with increasing initialization voltage and / or enhanced DTG coupling;

[0036] Figure 25 This is a diagram illustrating an example of adjusting the initial voltage in units of pixel rows;

[0037] Figure 26 and Figure 27 This is a diagram illustrating an example of a drive used to supply different initialization voltages to a first sub-pixel and a second sub-pixel located in adjacent pixel rows;

[0038] Figure 28 It is a driving waveform diagram used to sense the degradation of OLED; and

[0039] Figure 29A , Figure 29B and Figure 29C These are diagrams illustrating subpixel operations during the charging, discharging, and sensing periods, respectively.

[0040] Throughout the accompanying drawings and detailed embodiments, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and / or convenience, the dimensions, lengths, and thicknesses of layers, areas, and elements, and their depictions, may be exaggerated. Detailed Implementation

[0041] Implementations of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known methods, functions, structures, or configurations may be omitted for brevity where such descriptions might unnecessarily obscure aspects of this disclosure. Furthermore, repeated descriptions may be omitted for brevity. The described processing steps and / or the progression of operations are non-limiting examples.

[0042] The order of steps and / or operations is not limited to the order set forth herein and may be altered to occur in a different order than that described herein, except for steps and / or operations that must occur in a specific order. In one or more examples, two consecutive operations may be performed substantially simultaneously, or, depending on the functions or operations involved, they may be performed in reverse or a different order.

[0043] Unless otherwise stated, similar reference numerals may always refer to similar elements, even when they are shown in different figures. Unless otherwise stated, the same reference numerals may be used throughout the specification and figures to refer to the same or substantially the same elements. In one or more aspects, unless otherwise stated, the same elements (or elements with the same name) in different figures may have the same or substantially the same function and characteristics. The names of the various elements used in the following description are chosen for convenience only and may therefore differ from the names used in actual products.

[0044] The advantages and features of this disclosure, and its implementation methods, are illustrated by means of embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are exemplary and provided to make this disclosure detailed and complete to aid those skilled in the art in understanding the inventive concept, without limiting the scope of protection of this disclosure.

[0045] The shapes, dimensions (e.g., size, length, width, height, thickness, position, radius, diameter, and area), proportions, ratios, angles, numbers, number of elements, etc., disclosed herein (including those shown in the accompanying drawings) are merely examples, and therefore, this disclosure is not limited to the details shown. However, it should be noted that the relative dimensions of the components shown in the accompanying drawings are part of this disclosure.

[0046] When the terms “comprising,” “having,” “including,” “containing,” “constituting,” “made of,” “formed by,” “comprising,” “composed of,” etc., are used for one or more elements (e.g., layers, films, components, electrodes, structures, transistors, segments, members, parts, regions, areas, sections, steps, operations, etc.), one or more other elements may be added unless terms such as “only” are used. The terminology used in this disclosure is merely for describing particular exemplary embodiments and is not intended to limit the scope of this disclosure. Any reference to the singular may include the plural unless explicitly stated otherwise. In one or more examples, an element may be one or more elements, and an element may include multiple elements, unless explicitly stated otherwise. The word “exemplary” is used to mean used as an example or illustration. An implementation is an exemplary implementation. An aspect is an exemplary aspect. In one or more implementations, “implementation,” “example,” “aspect,” etc., should not be construed as preferred or superior to other implementations. Unless otherwise stated, implementation, example, exemplary implementation, aspect, etc., may refer to one or more implementations, one or more examples, one or more example implementations, one or more aspects, etc. Furthermore, the term “can” encompasses all the meanings of the term “able to”.

[0047] In one or more respects, unless otherwise expressly stated, components, features, or corresponding information (e.g., level, range, dimension, size, etc.) are interpreted as including a range of errors or tolerances, even when no explicit description of such a range of errors or tolerances is provided. Ranges of errors or tolerances can be caused by a variety of factors (e.g., process factors, internal or external influences, noise, etc.). When interpreting numerical values, unless otherwise expressly stated, the value is interpreted as including the range of errors.

[0048] When using any of the terms indicating location or position, such as “on top of,” “above,” “on the top of,” “above,” “below,” “on the top of,” “above,” “below,” “under,” “below,” “near,” “close to,” “adjacent to,” “next to,” “beside,” “at the side of,” “at the location of,” or “on one side of,” to describe the positional relationship between two elements (e.g., layers, films, components, electrodes, structures, transistors, segments, components, sections, areas, regions, parts, etc.), one or more other elements may be located between the two elements, unless more restrictive terms such as “immediately,” “directly,” or “closely” are used. For example, when any of the foregoing terms is used to describe one element and another element, the description should be interpreted to include cases where the elements are in direct contact with each other and cases where one or more additional elements are disposed or inserted therebetween. Furthermore, spatial relative terms such as the aforementioned terms and other terms like "front," "back," "back," "left," "right," "top," "bottom," "upper," "lower," "downward," "upward," "upper," "lower," "column," "row," "vertical," "horizontal," and "diagonal" refer to any frame of reference. For example, these terms can be used to illustrate the relative relationships between elements (including any correlations as shown in the accompanying drawings). However, embodiments of this disclosure are not limited to or restricted by this. Spatial relative terms should be understood to include different orientations of elements in use or operation, in addition to those depicted in the drawings or described herein. The terminology used is complex. For example, when a lower element or an element located below another element is flipped, that element can be referred to as the upper element or the element located above the other element. Therefore, for example, the terms "below" or "under" can semantically encompass the terms "above" or "over". Example terms such as "below" can include all directions, including the directions of "below," "above," and diagonal directions. Similarly, example terms such as "above," "on," etc., can include all directions, including the directions of "above," "on," "below," and diagonal directions.

[0049] When describing temporal relationships, when the temporal sequence is described as such as “after,” “following,” “after,” “next,” “before,” “previously,” “in front of,” etc., it may include cases that are not consecutive or sequential, and therefore one or more other events may occur in between, unless more restrictive terms such as “just,” “immediately,” or “directly” are used.

[0050] It should be understood that although the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used herein to describe various elements (e.g., layer, film, component, electrode, structure, transistor, segment, member, part, region, area, section, step, operation, etc.), these elements should not be limited by these terms to, for example, any particular order, priority, or number of elements. Furthermore, these terms are not used to define the nature or basis of an element. These terms are used only to refer to an element separately from another element. For example, without departing from the scope of this disclosure, a first element may refer to a second element, and similarly, a second element may refer to a first element. Furthermore, without departing from the scope of this disclosure, first elements, second elements, etc., may be named arbitrarily as is convenient for those skilled in the art. For clarity, the function or structure of these elements (e.g., first element, second element, etc.) is not limited by the ordinal number or name preceding the element. Furthermore, a first element may include one or more first elements. Similarly, a second element, etc., may include one or more second elements, etc.

[0051] The expression "joining" of an element (e.g., layer, film, component, electrode, structure, transistor, segment, member, part, region, area, section, etc.) with another element can be understood as, for example, that the element can be joined directly or indirectly to the other element. The term "joining" or similar expressions can refer to terms such as "covering," "surrounding," "contacting," "overlapping," "crossing," "intersecting," "connecting," "coupling," "attaching," "combining," "linking," "providing," "setting," "interacting," etc. Unless otherwise stated, joining can involve setting or inserting one or more intermediate elements between an element and another element. Furthermore, unless otherwise stated, an element can be joined at least partially or wholly (or completely) to another element. Additionally, an element can be included in at least one of two or more elements joined to each other. Similarly, another element can be included in at least one of two or more elements joined to each other. When an element joins with another element, at least a portion of the element can be joined with at least a portion of the other element. The term “with another element” or similar expression may be understood, depending on the context, as “another element” or “and another element, to another element, in another element, or on another element.” Similarly, the term “each other” may be understood, depending on the context, as “mutually” or “with each other, to each other, or on each other.”

[0052] The phrase “through” can be understood, for example, as passing through at least partially or completely.

[0053] Terms such as “line” or “direction” should not be interpreted solely based on the geometric relationships in which the individual lines or directions are parallel, perpendicular, diagonal, or inclined relative to each other, but may mean a line or direction with broad directionality within the scope in which the components of this disclosure can be functionally operated. For example, terms such as “first direction,” “second direction,” “X-axis direction,” and “Y-axis direction” should not be interpreted solely based on the geometric relationships in which the individual directions are parallel, perpendicular, diagonal, or inclined relative to each other, but may mean a direction with broad directionality within the scope in which the components of this disclosure can be functionally operated.

[0054] The term "at least one" should be understood to include any and all combinations of one or more of the associated enumerated items. For example, each of the phrases "at least one of the first, second, or third items" and "at least one of the first, second, and third items" can mean (i) a combination of items provided by two or more of the first, second, and third items, or (ii) only one of the first, second, or third items. Furthermore, "at least one of a plurality of elements" can mean (i) one element of a plurality of elements, (ii) some elements of a plurality of elements, or (iii) all elements of a plurality of elements. Additionally, "at least some," "some," "at least some parts," "at least some sections," "at least a portion," "at least one or more parts," "at least one section," "at least one or more sections," "at least some elements," "one or more," etc., in the context of a plurality of elements can mean (i) one element of a plurality of elements, (ii) a part (or section) of a plurality of elements, (iii) one or more parts (or sections) of a plurality of elements, (iv) one or more elements of a plurality of elements; (v) a plurality of elements of a plurality of elements, or (vi) all elements of a plurality of elements. In addition, the terms “at least some,” “some,” “at least some parts,” “at least some sections,” “at least a portion,” “at least one or more parts,” “at least one section,” “at least one or more sections,” etc., in the context of an element can mean (i) a part (or section) of an element, (ii) one or more parts (or sections) of an element, (iii) an element, or (iv) all parts of an element.

[0055] The expression "first element," "second element," and " / or" "third element" should be understood as any one of the first, second, and third elements, or any or all combinations of the first, second, and third elements. A similar interpretation applies to "and / or" used with two elements or with more than three. By way of example, A, B, and / or C can refer to only A; only B; only C; any one of A, B, and C (e.g., A, B, or C); some combinations of A, B, and C (e.g., A and B; A and C; or B and C); or all of A, B, and C. Furthermore, the expression "A / B" can be understood as A and / or B. For example, the expression "A / B" can refer to only A; only B; A or B; or A and B.

[0056] In one or more aspects, unless otherwise stated, for convenience, the terms "between" and "among" may be used interchangeably. For example, the expression "between multiple elements" can be understood as "among multiple elements." In another example, the expression "among multiple elements" can be understood as "between multiple elements." In one or more examples, the number of elements may be two. In one or more examples, the number of elements may be more than two. Furthermore, when an element is referred to as being "between" at least two elements, the element may be the only element between at least two elements, or there may be one or more intermediate elements.

[0057] In one or more aspects, unless otherwise stated, for convenience, the phrases “each other” and “mutually” may be used interchangeably. For example, the expression “different from each other” can be understood as “different from each other”. In another example, the expression “different from each other” can be understood as “different from each other”. In one or more examples, the number of elements involved in the foregoing expression may be two. In one or more examples, the number of elements involved in the foregoing expression may be more than two.

[0058] In one or more respects, unless otherwise stated, for convenience, the phrases “one or more of them” and “one or more of them” may be used interchangeably.

[0059] The term "or" means "inclusive or" rather than "exclusive or". That is, unless otherwise stated or clear from the context, the expression "x uses a or b" means any of the natural inclusive permutations. For example, "a or b" can mean "a", "b", or "a and b". For example, "a, b, or c" can mean "a", "b", "c", "a and b", "b and c", "a and c", or "a, b, and c".

[0060] The phrases “substantially identical” or “nearly identical” can indicate the degree to which minor differences due to errors in the manufacturing process are considered equivalent to each other.

[0061] Features of the various embodiments of this disclosure may be partially or completely coupled or combined with each other, may be technically related to each other, and may operate, link, or drive together in a variety of ways. Embodiments of this disclosure may be implemented or performed independently of each other, or may be implemented or performed together in a mutually dependent or related relationship. In one or more aspects, components of each apparatus and device according to the various embodiments of this disclosure are operatively coupled and configured.

[0062] Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, the terms “section” or “unit” can be applied to, for example, circuits, components, integrated circuits, computational blocks of circuit devices, or structures configured to perform the described functions, as would be understood by one of ordinary skill in the art.

[0063] The terminology used herein has been selected as that commonly used in the relevant technical fields; however, other terms may exist depending on technological developments and / or changes, conventions, preferences of those skilled in the art, etc. Therefore, the terminology used herein should not be construed as limiting the technical ideas, but rather as examples of terms used to describe exemplary embodiments.

[0064] Furthermore, in certain circumstances, the terminology may be arbitrarily chosen by the applicant, and in such cases, its detailed meaning is described herein. Therefore, the terminology used herein should not be understood solely based on its name, but also on its meaning and content.

[0065] In the following description, various exemplary embodiments of the present disclosure are described in more detail with reference to the accompanying drawings. Reference numerals for each element in the drawings may be used to indicate the same or similar elements in other drawings, and similar reference numerals may refer to similar or similar elements unless otherwise stated. The same or similar elements may be represented by the same reference numerals, even if they are depicted in different drawings. For brevity, repeated descriptions of the same or similar elements may be omitted, and unless otherwise stated, the descriptions provided for elements in one or more figures may also apply to elements in other figures using the same or similar reference numerals. Furthermore, for ease of description, the scale, dimensions, size, and thickness of each element shown in the drawings may differ from actual scale, dimensions, size, and thickness, and therefore, embodiments of the present disclosure are not limited to the scale, dimensions, size, and thickness shown in the drawings.

[0066] In the description of signal flow, for example, when a signal is provided (e.g., transmitted or sent) from node A to node B, this may include cases where the signal is provided from node A to node B via one or more nodes, unless phrases such as "provided immediately" or "provided directly" are used.

[0067] In one or more examples, the source electrode of a transistor can be referred to as the drain electrode of the transistor, and vice versa.

[0068] Figure 1 This is a block diagram illustrating a frequency-variable display device according to an example embodiment of the present disclosure.

[0069] Reference Figure 1 The display panel 100 may include a screen AA for displaying an input image. The screen AA may include a pixel array for displaying pixel data (hereinafter referred to as "image data") DATA of the input image. The pixel array may include multiple data lines DL, multiple gate lines GL intersecting the data lines DL, multiple reference voltage lines, and multiple pixels.

[0070] Pixels can be arranged on the screen AA in a matrix type defined by data lines DL, gate lines GL, and reference voltage lines. Pixels can be arranged on the screen AA in various types, such as stripe type, diamond type, and matrix type.

[0071] A pixel array may include multiple pixel columns and multiple pixel rows L1 to Ln intersecting the pixel columns. Each pixel column may include pixels arranged in the Y-axis direction. A pixel row may include pixels arranged in the X-axis direction. A vertical time period may be a frame time period required to write a frame of image data DATA across all pixels on the screen. A horizontal time period may be the time obtained by dividing a frame time period by the number of pixel rows L1 to Ln. A horizontal time period may be the time required to write image data DATA of a pixel row sharing a gate line GL across the pixels of a pixel row.

[0072] Each of the pixels may include a red (R) subpixel 101, a green (G) subpixel 101, a blue (B) subpixel 101, and a white (W) subpixel 101 for implementing the color.

[0073] The frequency-variable display device according to one or more aspects of this disclosure can be implemented as an electroluminescent display device. In this case, the pixel circuit of the frequency-variable display device may include a light-emitting element, a driving element, one or more switching elements, and a capacitor. The light-emitting element may be implemented as an organic light-emitting diode (OLED). The driving current Ioled that allows the light-emitting element to emit light can be adjusted based on the gate-source voltage of the driving element. Each of the driving element and the switching element may be implemented as a transistor. The semiconductor layer of the transistor may include amorphous silicon or polycrystalline silicon. At least some of the semiconductor layers of the transistor may include oxide. The pixel circuit may be connected to a data line DL and a gate line GL. Figure 1 In the diagram, "D1 to D3" shown in the circles can be data lines, and "Gn-2 to Gn" can be gate lines. Figure 1 Each of the sub-pixels 101 may include the same pixel circuitry.

[0074] A touch sensor can be mounted on the display panel 100. The touch sensor can be arranged on the screen AA of the display panel 100 in an on-cell or add-on manner, or it can be implemented as an in-cell touch sensor embedded in a pixel array. Touch input can be sensed by the touch sensor, or it can be sensed by pixels alone even without a touch sensor.

[0075] The source driver 110 can generate a data voltage by converting image data DATA received from the timing controller 130 into a gamma-compensated voltage using a digital-to-analog converter (DAC). The source driver 110 can supply the data voltage to the data line DL. The data voltage can be supplied to the data line DL and can be applied to the gate electrode of the driving element through the switching elements of the sub-pixel 101. The source driver 110 can supply an initialization voltage VpreR received from the power circuit 200 to a reference voltage line connected to the sub-pixel. The initialization voltage VpreR can be supplied to the reference voltage line and can be applied to the source electrode of the driving element through the switching elements of each sub-pixel 101.

[0076] The source driver 110 can be implemented using one or more source driver integrated circuits (ICs). The source driver ICs can be connected to the timing controller 130 via internal interface circuitry. This internal interface circuitry can be implemented as an embedded point-to-point clock interface (EPI). The source driver ICs may also include a touch driver. The touch driver can generate touch sensor drive signals and convert touch sensor charge changes into raw touch data. The touch driver can transmit the raw touch data to the host system (not shown) via a separate interface circuit. This separate interface circuit can be implemented as a Serial Peripheral Interface (SPI).

[0077] Gate driver 120 can be disposed in a bezel area BZ outside the screen AA in display panel 100. The bezel area BZ may not display an image. Gate driver 120 can sequentially supply gate signals synchronized with data voltages to gate lines GL under the control of timing controller 130. The gate signals can simultaneously activate pixels in the same pixel row charged with data voltages. Gate driver 120 can output gate signals using one or more shift registers and can shift the gate signals. The gate signals can be referred to as scan signals. Scan signals may include the gate on-voltage VON and gate off-voltage VOFF received from power circuit 200.

[0078] The timing controller 130 can receive video data DATA and timing signals synchronized with the video data DATA from a host system (not shown). The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The vertical synchronization signal Vsync can define a vertical time period (i.e., one frame). The horizontal synchronization signal Hsync can define a horizontal time period. The data enable signal DE can define the time during which data voltage is input to a sub-pixel within the vertical time period (i.e., the vertical active time period). Other times within the vertical active time period may be vertical blanking periods. The data enable signal DE can oscillate during the vertical active time period and may not oscillate during the vertical blanking periods.

[0079] The timing controller 130 can generate a source timing control signal DDC for controlling the operating timing of the source driver 110 and a gate timing control signal GDC for controlling the operating timing of the gate driver 120 based on the timing signals Vsync, Hsync and DE received from the host system.

[0080] The host system can be one of a television (TV), set-top box, navigation system, personal computer (PC), home theater, automotive display system, mobile device, and wearable device. In mobile devices and wearable devices, the source driver 110, timing controller 130, and level shifter 140 can be integrated into a single driver IC.

[0081] Level shifter 140 can shift the logic voltage level of the gate timing control signal GDC output from timing controller 130 to either the gate on-voltage VON or the gate off-voltage VOFF, to supply to gate driver 120. The low logic voltage of the gate timing control signal GDC can be shifted down to the gate off-voltage VOFF, and the high logic voltage of the gate timing control signal GDC can be shifted up to the gate on-voltage VON.

[0082] The power circuit 200 can generate various source voltages required for panel driving. The power circuit 200 can generate the gate on voltage VON and gate off voltage VOFF required to generate the scan signal, generate the high-level source voltage EVDD and low-level source voltage EVSS to be supplied to each sub-pixel 101, and generate the initialization voltage VpreR to be supplied to the reference voltage line.

[0083] The timing controller 130, source driver 110, gate driver 120, and power circuit 200 may be elements configuring a flicker compensation circuit according to an exemplary embodiment of the present disclosure. The flicker compensation circuit can increase the initialization voltage VpreR applied to the sub-pixels in proportion to the degradation of the OLED light-emitting element, and therefore can reduce inter-frame recognition brightness deviations that occur under conditions of rapid changes in frame frequency. In particular, when the data voltage is low based on a low gray level, the charging time of the internal capacitor (hereinafter referred to as Coled) of the OLED light-emitting element may increase, and as a result, VRR flicker may occur. On the other hand, the flicker compensation circuit according to an exemplary embodiment of the present disclosure can increase the voltage level of the initialization voltage VpreR, and therefore can shorten the charging time of Coled and reduce VRR flicker.

[0084] Figure 2 This is a diagram illustrating the connection configuration of pixels according to an example embodiment of the present disclosure.

[0085] Reference Figure 2 A pixel may include four sub-pixels SP1 to SP4 that share a reference voltage line RL. The four sub-pixels SP1 to SP4 may be R, G, B, and W sub-pixels used to constitute the same pixel. Each of the sub-pixels SP1 to SP4 may include, for example, a light-emitting element OLED, a driving transistor DT, a first switching transistor ST1 and a second switching transistor ST2, and a storage capacitor Cst.

[0086] An OLED (Optical Display Panel) emits light using a drive current supplied from a driving transistor DT to achieve brightness. The anode of the OLED can be connected to a second node N2, and its cathode can be connected to the input terminal of a low-level source voltage EVSS.

[0087] The driving transistor DT can generate a driving current Ioled based on its gate-source voltage to supply the driving current Ioled to the light-emitting element OLED. The gate electrode of the driving transistor DT can be connected to the first node N1, its drain electrode can be connected to the input terminal of the high-level source voltage EVDD, and its source electrode can be connected to the second node N2.

[0088] The gate electrode of the first switching transistor ST1 can be connected to the gate line GL. The first electrode of the first switching transistor ST1 can be connected to the data line DL, and its second electrode can be connected to the first node N1.

[0089] The gate electrode of the second switching transistor ST2 can be connected to the gate line GL. The first electrode of the second switching transistor ST2 can be connected to the reference voltage line RL, and its second electrode can be connected to the second node N2.

[0090] One electrode of the storage capacitor Cst can be connected to the first node N1, and its other electrode can be connected to the second node N2.

[0091] The first switching transistor ST1 and the second switching transistor ST2 can be turned on during the vertical active period based on the scan signal SCAN of the gate on-state voltage VON. Therefore, the gate electrode of the driving transistor DT can be connected to the data line DL, and the source electrode of the driving transistor DT can be connected to the reference voltage line RL. Thus, a data programming operation corresponding to image data can be performed. This data programming operation can be referred to as the gate-source voltage Vgs setting operation of the driving transistor DT. The gate-source voltage Vgs can be the voltage difference "Vdata-VpreR" between the data voltage Vdata and the initialization voltage VpreR. When the data programming operation is completed during the vertical active period, the first switching transistor ST1 and the second switching transistor ST2 can be turned off based on the scan signal SCAN of the gate off-state voltage VOFF.

[0092] The first switch SW1, the second switch SW2, and the third switch SW3 can also be connected to the reference voltage line RL. The first switch SW1 connects the input terminal of the initialization voltage VpreR to the reference voltage line RL. The second switch SW2 connects the reference voltage line RL to the tracking voltage VK for sensing OLED degradation. The third switch SW3 connects the reference voltage line RL to the sensing circuit SU for sensing OLED degradation. Since the second switch SW2 and the third switch SW3 are used to sense OLED degradation, components SW2, SW3, and SU can be omitted in the model that predicts OLED degradation based on data counting.

[0093] The first switch SW1 can be connected to the reference voltage line RL in the display driver. The second switch SW2 and the third switch SW3 can be connected to the reference voltage line RL in either a power-off sequence or a power-on sequence without executing the display driver. When the second switch SW2 is connected to the reference voltage line RL, the electrical connection between the first switch SW1, the third switch SW3, and the reference voltage line RL can be disconnected. Conversely, when the third switch SW3 is connected to the reference voltage line RL, the electrical connection between the first switch SW1, the second switch SW2, and the reference voltage line RL can be disconnected. When the third switch SW3 is connected to the reference voltage line RL, the OLED sensing operation of the sensing circuit SU can be performed.

[0094] The first switch SW1, the second switch SW2, the third switch SW3, and the sensing circuit SU can be included in the source driver 110.

[0095] Figure 3This is a diagram illustrating the arrangement of OLED multi-stacks of pixels and color filters according to an exemplary embodiment of this disclosure. Figure 4 This is a diagram illustrating an example of an OLED multi-stack according to an exemplary embodiment of the present disclosure.

[0096] Reference Figure 3 and Figure 4 The OLED, with light-emitting elements for each of the R, G, B, and W sub-pixels SP1 to SP4, can be implemented using a multi-stack structure (M-STACK). As an example of the M-STACK structure, a four-stack structure can exist. This four-stack structure can be configured with R stacks, B1 stacks, G stacks, and B2 stacks, which are sequentially and in series connected to each other. Internal capacitors C1, C2, C3, and C4 can be formed at the anode-cathode ends of the R stack, B1 stacks, G stacks, and B2 stacks, respectively.

[0097] The light-emitting elements of each of the R, G, B, and W subpixels SP1 to SP4 in an OLED may include a 4-stacked structure to generate white (W) light. The white (W) light can be converted into red (R), green (G), or blue (B) light in a color filter array disposed on a multi-stacked array.

[0098] In the R sub-pixel SP1, white (W) light generated by the OLED can pass through the R color filter CF-R and is thus converted into red (R) light, which can then be output to the outside. In the G sub-pixel SP2, white (W) light generated by the OLED can pass through the G color filter CF-G and is thus converted into green (G) light, which can then be output to the outside. In the B sub-pixel SP3, white (W) light generated by the OLED can pass through the B color filter CF-B and is thus converted into blue (B) light, which can then be output to the outside. Furthermore, in the W sub-pixel SP4, white (W) light generated by the OLED can bypass the color filter CF and can be output to the outside.

[0099] Figure 5 This is a diagram showing the vertical active period and vertical blanking period that constitute a frame time. Figure 6 This is a diagram illustrating an example of how the length of the vertical leading edge included in the vertical blanking period varies horizontally based on the frame frequency.

[0100] Reference Figure 5 A frame time (vertical segment) can be defined by the vertical synchronization signal Vsync. A frame time (vertical segment) can be defined as the time interval between adjacent falling (or rising) edges of the vertical synchronization signal Vsync.

[0101] The vertical active period ACT and the vertical blanking period BLK within a frame time (vertical period) can be defined by the data enable signal DE. The vertical active period ACT can be the period during which the data enable signal DE swings, and the vertical blanking period BLK can be the period during which the data enable signal DE does not swing.

[0102] A frequency-variable display device according to one or more aspects of this disclosure can operate in a VRR mode where the length of a frame varies. In VRR mode, as in... Figure 6 In this configuration, the frame rate can be changed to A, B, and C Hz. When the frame rate changes, the length of a frame duration can vary accordingly. In VRR mode, the length of the vertical active period (ACT) can be fixed to a predetermined value, and the length of the vertical blanking period (BLK) can vary based on the frame rate. Based on a frame rate of A Hz, the length of the vertical blanking period can be BLK1; based on a frame rate of B Hz, the length of the vertical blanking period can be BLK2; and based on a frame rate of C Hz, the length of the vertical blanking period can be BLK3. Here, when A>B>C, BLK1... <BLK2<BLK3。

[0103] During the fixed-length vertical active period (ACT), a gate-source voltage setting (i.e., data programming) operation can be performed in the pixel based on the data voltage corresponding to the image data (DATA). During the variable-length vertical blanking period (BLK), the gate-source voltage set in the pixel can be maintained.

[0104] Figure 7 This is a diagram illustrating an example of how brightness levels change based on frame rate. Figure 8 This is a diagram illustrating VRR flicker that occurs under conditions of rapid changes in frame rate. Figure 9 and Figure 10 This is a graph illustrating an example where the visibility of VRR flickering is higher at low gray levels than at high gray levels.

[0105] Figure 7 and Figure 8 The peak low brightness point can be the point where data programming operations are performed. While performing data programming operations, the OLED's light emission operation can be stopped, and after performing data programming operations, the OLED's light emission operation can be resumed.

[0106] Data programming operations and emission operations can be performed sequentially within a single frame. As the number of frames arranged within a predetermined time increases, i.e., the frame frequency increases, the number of data programming operations may increase, and therefore, the recognition brightness may decrease. For example, at a frame frequency of 240 Hz, the number of data programming operations within a predetermined time may be 12; at a frame frequency of 120 Hz, the number of data programming operations within a predetermined time may be 6; and at a frame frequency of 60 Hz, the number of data programming operations within a predetermined time may be 3. As a result, the real-time brightness integral value (i.e., recognition brightness) at a frame frequency of 240 Hz may be L1, the real-time brightness integral value (i.e., recognition brightness) at a frame frequency of 120 Hz may be L2, which is higher than L1, and the real-time brightness integral value (i.e., recognition brightness) at a frame frequency of 60 Hz may be L3, which is higher than L2.

[0107] As mentioned above, assuming a constant grayscale level for the displayed image, the recognition brightness may be relatively higher at a low frame rate compared to a high frame rate. Therefore, when the frame rate changes from high to low, VRR flicker may occur due to the change in recognition brightness.

[0108] like Figure 9 and Figure 10 VRR flicker in images may be perceived relatively more strongly during low grayscale periods than during high grayscale periods. When the time taken from data programming until reaching the target brightness saturation level is defined as the brightness transition rate, the brightness transition rate of a high grayscale image may be relatively greater than that of a low grayscale image. Therefore, VRR flicker caused by frequency variations may not be a significant problem in high grayscale images, but it may be clearly identifiable when displaying low grayscale images.

[0109] Figure 11 and Figure 12 This is a diagram illustrating a concept for reducing VRR flicker.

[0110] Reference Figure 11 and Figure 12 According to an example embodiment of this disclosure, the flicker compensation circuit can sense the degradation of the light-emitting element (OLED) in step S1. As the degree of degradation of the OLED increases, the capacitive and resistive components of the OLED may increase. The flicker compensation circuit can sense the OLED threshold voltage charged in the capacitor Coled of the OLED to determine the degradation of the OLED. Figure 12 In the figure, the vertical axis “Coled” represents the OLED threshold voltage charged into the capacitor Coled of the OLED light-emitting element, and the horizontal axis “Stress” represents the degree of degradation in the OLED light-emitting element.

[0111] The flicker compensation circuit can sense all sub-pixels of the screen, or it can sense only some sub-pixels. In step S2, the flicker compensation circuit can determine the average or most frequent value of the sensed values ​​as the representative sensed values, and can increase the voltage level of the initialization voltage VpreR based on the representative sensed values.

[0112] The increased initial voltage VpreR can be supplied to all sub-pixels of the screen for data programming operations.

[0113] As the degradation of the OLED light-emitting element increases, the flicker compensation circuit can increase the initialization voltage VpreR. For example, the flicker compensation circuit can adjust the initialization voltage VpreR to a first voltage level based on a first degradation sensing value, and can further adjust it to a second voltage level higher than the first voltage level based on a second degradation sensing value greater than the first voltage level. When the initialization voltage VpreR is increased based on the degradation of the OLED light-emitting element, VRR flicker can be reduced, and abnormal flash phenomena can be improved.

[0114] Figure 13 This is a diagram illustrating another concept for reducing VRR flicker.

[0115] Reference Figure 13 According to the example embodiment of this disclosure, the flicker compensation circuit can predict the degradation of the OLED element in step S11 based on the cumulative emission history of the OLED element. The cumulative emission history of the OLED element may include image display time and image display grayscale levels. The cumulative emission history of the OLED element can be examined based on a data counting accumulation technique. The data counting accumulation technique can be a degradation prediction modeling technique that converts input image data into stress values ​​for storage in memory. Figure 1 The accumulated stress value in 150). As the driving time of high grayscale images increases, the memory ( Figure 1 The accumulated stress value in 150 may increase.

[0116] The flicker compensation circuit can predict the degradation of the OLED light-emitting element based on data counts of at least some sub-pixels of the screen. In step S12, the flicker compensation circuit can increase the voltage level of the initialization voltage VpreR based on the predicted degradation value of the OLED light-emitting element.

[0117] The increased initial voltage VpreR can be supplied to all sub-pixels of the screen for data programming operations.

[0118] As the degradation of the OLED light-emitting element increases, the flicker compensation circuit can increase the initialization voltage VpreR. For example, the flicker compensation circuit can adjust the initialization voltage VpreR to a first voltage level based on a first degradation prediction value, and can further adjust it to a second voltage level higher than the first voltage level based on a second degradation prediction value greater than the first voltage level. When the initialization voltage VpreR is increased based on the degradation of the OLED light-emitting element, VRR flicker can be reduced, and abnormal flash phenomena can be improved.

[0119] In the following text, reference will be made to Figures 14 to 19 The principle of reducing VRR flicker by increasing the initial voltage VpreR is described. Furthermore, reference will be made to... Figures 20A to 23 The principle of improving abnormal flashing phenomena by increasing the initial voltage VpreR is described.

[0120] Figure 14 This is a diagram illustrating the equivalent circuit of a sub-pixel according to an exemplary embodiment of the present disclosure. Figure 15 This is a graph illustrating an example where the initial voltage increases proportionally to the degradation of the OLED. Figure 16 This is a diagram illustrating an example where the initial voltage increases as the capacitance of the capacitor Coled increases.

[0121] Reference Figure 14 and Figure 15 As the OLED light-emitting element degrades, the capacitance of the coil can increase from C1 to C2 and C3. As the capacitance of the coil increases, the OLED threshold voltage charged into the coil can also increase. Therefore, by sensing the voltage of the coil, the degree of OLED degradation can be determined.

[0122] The initialization voltage VpreR can be increased from V1 to V2 and V3 proportionally to the degradation of the OLED light-emitting element. As the initialization voltage VpreR increases, the charging time (non-light-emitting time) of the OLED can be shortened, or the DTG coupling effect can be increased, thereby reducing VRR flicker.

[0123] The DTG coupling effect can be described as the gate potential of the driving transistor DT changing based on the voltage variation of the data line DL. The DTG coupling effect can be achieved using a coupling capacitor Cpr, where one electrode of Cpr is connected to the first node N1, and the other electrode is connected to the data line DL. The DTG coupling ratio can be determined as "Cpr capacitance / (Cst capacitance + Cpr capacitance)". As Cpr capacitance increases, or Cst capacitance decreases, the coupling ratio can increase, and therefore, the DTG coupling effect can increase.

[0124] For a suitable DTG coupling effect, the capacitance of the coupling capacitor Cpr can be set to 0.1% to 0.5% of the capacitance of the storage capacitor Cst.

[0125] When the capacitance of the coupling capacitor Cpr is less than 0.1% of the capacitance of the storage capacitor Cst, there may be a problem where the desired coupling effect is insufficient when the capacitance of the coupling capacitor Cpr is greater than 0.5% of the capacitance of the storage capacitor Cst; and when the capacitance is excessively increased, the brightness during the vertical blanking period changes significantly. In one or more aspects, to obtain a suitable coupling effect, it is preferable to set the capacitance of the coupling capacitor Cpr to 0.1% to 0.5% of the capacitance of the storage capacitor Cst.

[0126] Figure 16 This is a diagram illustrating an example of shortening the charging time of a coil by increasing the initial voltage.

[0127] Reference Figure 16 When the initialization voltage VpreR is increased from 2 V to 6 V, the OLED charging time can be shortened from CT2 to CT1 due to the degradation of the OLED element. This shortened charging time indicates an earlier OLED turn-on time, and therefore, an increased emission time. The VRR flicker problem in low grayscale levels may be related to the luminance transition rate. When the initialization voltage VpreR is increased from 2 V to 6 V, the emission time of the OLED element in a frame can be increased, and therefore, the time required to reach the target brightness can be proportionally shortened. In other words, the luminance transition rate required to reach the target brightness can be increased, and thus, the VRR flicker problem in low grayscale levels can be improved.

[0128] Figure 17 This is a graph showing the change in Vgs when the initial voltage is applied at the default level. Figure 18 This is a graph showing the change in Vgs when the initial voltage is applied at a voltage level higher than the default level.

[0129] Reference Figure 14 and Figure 17When the driving transistor DT operates with the initialization voltage VpreR applied as a default level of 2 V to the second node N2 and the data voltage Vdata applied to the first node N1, the source voltage Vs can increase from 2 V to 8 V, which is the OLED turn-on voltage Vf, based on the current flowing through the driving transistor DT. At this time, the gate voltage Vg can also be increased from the data voltage Vdata to "Vdata + boost voltage" through a capacitor boost based on the storage capacitor Cst. The capacitor boost ratio can be defined as "Cst capacitance / (Cst capacitance + Cx parasitic capacitance)". In this example, the Cx parasitic capacitance can be the parasitic capacitance between the gate and source of the driving transistor DT. When the capacitor boost ratio is 80%, the boost voltage can be 6V * 0.8, which is 4.8 V. That is, the gate voltage Vg can increase to "Vdata + 4.8 V". Therefore, the voltage difference ΔVgs between the initial Vgs and the final Vgs can be 1.2 V. The initial Vgs can be the gate-source voltage of the driving transistor DT based on data programming. Ultimately, Vgs can be the gate-source voltage of the driving transistor DT, which controls the emission time of the OLED element. As mentioned above, when ΔVgs is high, the drain-source current deviation ΔIds of the driving transistor DT may increase. When the drain-source current deviation ΔIds of the driving transistor DT increases, the perceived brightness variation may increase, and as a result, VRR flicker may be easily detected at low gray levels.

[0130] Reference Figure 14 and Figure 18 When the driving transistor DT operates with the initialization voltage VpreR applied as an increased 6 V to the second node N2 and the data voltage Vdata applied to the first node N1, the source voltage Vs can increase from 6 V to 8 V, which is the OLED turn-on voltage Vf, based on the current flowing through the driving transistor DT. At this time, the gate voltage Vg can also be increased from the data voltage Vdata to "Vdata + boost voltage" through a capacitor boost based on the storage capacitor Cst. When the capacitor boost ratio is 80%, the boost voltage can be 2V * 0.8, which is 1.6 V. That is, the gate voltage Vg can be increased to "Vdata + 1.6 V". As a result, the voltage difference ΔVgs between the initial Vgs and the final Vgs can be 0.4 V. As described above, when ΔVgs decreases by increasing the initialization voltage VpreR, the drain-source current deviation ΔIds of the driving transistor DT can be reduced. When the drain-source current deviation ΔIds of the driving transistor DT decreases, the change in recognition brightness can be reduced, and therefore, VRR flicker can be prevented in low grayscale levels.

[0131] Figure 19This is a figure illustrating an example of reduced peak brightness in the low grayscale region when the initialization voltage VpreR is increased and / or the DTG coupling effect increases.

[0132] Reference Figure 19 With the increase of the harmonic / or DTG coupling ratio on the initial voltage VpreR, the peak brightness of the low grayscale region may be reduced even when the frame frequency changes rapidly from 480 Hz to 40 Hz, and thus VRR flicker can be improved.

[0133] Figure 20A and Figure 20B This diagram illustrates why the abnormal flash phenomenon is severe when representing low gray levels rather than high gray levels.

[0134] Reference Figure 20A and Figure 20B Because the transmission loss of the capacitor boost converter is greater when achieving low grayscale levels than when achieving high grayscale levels, the voltage difference ΔVgs between the initial Vgs and the final Vgs can be relatively large. When ΔVgs is large, abnormal flashing may occur at low grayscale levels.

[0135] Figure 21 and Figure 22 This is a diagram illustrating an example of abnormal flashing caused by capacitance deviation in the configuration of multiple stacked capacitors in an OLED.

[0136] Reference Figure 21 The capacitance of a G-stack can be 75% larger than that of an R-stack, B1-stack, or B2-stack.

[0137] When achieving high grayscale levels, R stacking, B1 stacking, G stacking, and B2 stacking can divide the 12V high-current OLED turn-on voltage Vf into 3V units.

[0138] Subsequently, when achieving black grayscale, the R stack, B1 stack, G stack, and B2 stack can divide the voltage based on 1 / capacitance. The R stack, B1 stack, G stack, and B2 stack can divide the initial voltage VpreR of 2 V into 0.2 V, 0.2 V, 1.4 V, and 0.2 V, respectively.

[0139] Subsequently, in the initial time of low grayscale implementation, the R stack, B1 stack, G stack, and B2 stack can divide 2 V into 0.2 V, 0.2 V, 1.4 V, and 0.2 V, respectively.

[0140] Subsequently, at the low grayscale level, the R stack, B1 stack, G stack, and B2 stack can divide the 3.8 V into 0.6 V, 0.6 V, 2 V, and 0.6 V, respectively. In this case, the emission time of the G stack can be earlier than that of the R stack, B1 stack, and B2 stack. As the emission time of the G stack shortens, the current may increase, and as a result, abnormal over-emission (i.e., flashing) may occur.

[0141] As mentioned above, the abnormal flashing phenomenon may be caused by an imbalance in the capacitance of each stack.

[0142] Figure 23 This is a diagram illustrating an example where ΔVgs decreases as the initial voltage increases, thus reducing the over-luminescence current level and preventing flashing.

[0143] Reference Figure 23 When the initial voltage VpreR is increased from 2 V to 6 V, the over-luminescence current level of the early luminescence time TTo, which is earlier than the normal luminescence time TTn, can be reduced, and thus, abnormal flashing can be effectively prevented despite early luminescence.

[0144] Figure 24 This is a graph showing the extent to which VRR flicker is improved with increasing initialization voltage and / or enhanced DTG coupling.

[0145] Reference Figure 24 Waveform WF1 represents the brightness change in the prior art, waveform WF2 represents the improved brightness change when the DTG coupling ratio increases, waveform WF3 represents the improved brightness change when the initialization voltage VpreR increases, and waveform WF4 represents the improved brightness change when the DTG coupling ratio increases and the initialization voltage VpreR increases by 2 V.

[0146] In terms of improving VRR flicker, waveform WF4 is the best, waveform WF3 is the second best, and waveform WF2 is the third best.

[0147] Figure 25 This is a diagram illustrating an example of adjusting the initial voltage in units of pixel rows. Figure 26 and Figure 27 This is a diagram illustrating a driving example for supplying different initialization voltages to the first and second sub-pixels located in adjacent pixel rows.

[0148] Reference Figure 25 The initial voltage VpreR can be adjusted independently per pixel row L1 to Ln. Therefore, the degradation of the OLED light-emitting element can be sensed per pixel row L1 to Ln, or it can be predicted based on data counts.

[0149] Since the initial voltage VpreR is adjusted independently in units of pixel rows L1 to Ln, therefore, as in Figure 26 and Figure 27 In this process, different initialization voltages VpreR1 and VpreR2 can be supplied to the first sub-pixel SPa and the second sub-pixel SPb respectively located in adjacent pixel rows L1 and L2.

[0150] In detail, as in Figure 27 In the first sub-pixel SPa, the first driving transistor DT1 may include a first driving transistor DT1 and a first light-emitting element OLED1. The first driving transistor DT1 includes a gate electrode connected to a first node N1 and a source electrode connected to a second node N2. The first light-emitting element OLED1 includes an anode electrode connected to the second node N2. The first sub-pixel SPa may be disposed in the first pixel row L1. The first sub-pixel SPa may also include a switching transistor ST11 connected to a data line DL and a first node N1 and turned on or off based on a first scan signal SCANa; a switching transistor ST12 connected to a reference voltage line RL and a second node N2 and turned on or off based on the first scan signal SCANa; a first coupling capacitor Cpr1 connected to a data line DL and a first node N1; and a first storage capacitor Cst1 connected to a first node N1 and a second node N2.

[0151] The second sub-pixel SPb may include a second driving transistor DT2 and a second light-emitting element OLED2. The second driving transistor DT2 includes a gate electrode connected to a third node N3 and a source electrode connected to a fourth node N4. The second light-emitting element OLED2 includes an anode electrode connected to the fourth node N4. The second sub-pixel SPb may be disposed in the second pixel row L2. The second sub-pixel SPb may also include a switching transistor ST21 connected to the data line DL and the third node N3 and turned on or off based on the second scan signal SCANb; a switching transistor ST22 connected to the reference voltage line RL and the fourth node N4 and turned on or off based on the second scan signal SCANb; a second coupling capacitor Cpr2 connected to the data line DL and the third node N3; and a second storage capacitor Cst2 connected to the third node N3 and the fourth node N4.

[0152] The first sub-pixel SPa and the second sub-pixel SPb can share the data line DL and the reference voltage line RL.

[0153] The data line DL can transmit the first data voltage Vdata1 to the first node N1 via the switching transistor ST11 during the first gate-source voltage setting period Tgs1 corresponding to the conduction period of the first scan signal SCANa, and can transmit the second data voltage Vdata2 to the third node N3 via the switching transistor ST21 during the second gate-source voltage setting period Tgs2 corresponding to the conduction period of the second scan signal SCANb.

[0154] The reference voltage line RL can transmit the first initialization voltage VpreR1 to the second node N2 through the switching transistor ST12 during the first gate-source voltage setting period Tgs1, and can transmit the second initialization voltage VpreR2 to the fourth node N4 through the switching transistor ST22 during the second gate-source voltage setting period Tgs2.

[0155] When the second light-emitting element OLED2 deteriorates more than the first light-emitting element OLED1, the second initialization voltage VpreR2 can be greater than the first initialization voltage VpreR1. Therefore, VRR flicker and over-emission phenomena occurring in the second sub-pixel SPb can be improved.

[0156] When the capacitance of the first coupling capacitor Cpr1 is set to 0.1% to 0.5% of the capacitance of the first storage capacitor Cst1, the VRR flicker improvement effect of the first sub-pixel SPa can be increased.

[0157] Similarly, when the capacitance of the second coupling capacitor Cpr2 is set to 0.1% to 0.5% of the capacitance of the second storage capacitor Cst2, the VRR flicker improvement effect of the second sub-pixel SPb can be increased.

[0158] Figure 28 This is a driving waveform diagram used to sense the degradation of OLEDs. Figure 29A , Figure 29B and Figure 29C These are diagrams illustrating subpixel operations during the charging, discharging, and sensing periods, respectively.

[0159] Reference Figure 28 This allows for the execution of OLED degradation sensing sequences without executing the power-on or power-off sequences of the display driver. (See reference...) Figure 28 The OLED degradation sensing sequence may include a charging period Xc, a discharging period Xd, and a sensing period Xs.

[0160] Reference Figure 29ADuring the charging period Xc, a tracking voltage VK for sensing OLED degradation can be applied to the anode electrode of the OLED via switch SW2 and switching transistor ST2. The tracking voltage VK applied to the anode electrode of the OLED can become the source voltage Vs. The tracking voltage VK can be sufficiently higher than the turn-on voltage of the OLED, and therefore, after the OLED is charged, the drive current Ioled can flow through the OLED. The voltage applied to the OLED can be the threshold voltage of the OLED used to turn on the OLED. As the OLED degrades, the threshold voltage of the OLED may increase.

[0161] Reference Figure 29B During the discharge period Xd, switch SW2 can be turned off, and therefore, discharge can be performed in the light-emitting element OLED. The discharge operation can continue until the potential of the reference voltage line RL equals the potential of the coil (i.e., the threshold voltage of the light-emitting element OLED). When the potential of the reference voltage line RL equals the potential of the coil, the discharge operation based on the light-emitting element OLED can stop. During the discharge period Xd, the threshold voltage of the light-emitting element OLED can be the Voled stored in the coil.

[0162] Reference Figure 29C During the sensing period Xs, switch SW3 can be turned on, and therefore, the Coled can be connected to the sensing circuit SU via switching transistor ST2 and switch SW3. The sensing circuit SU can sample the threshold voltage Voled of the light-emitting element OLED stored in the Coled.

[0163] In the example, the control circuit may include a flicker compensation circuit. In the example, the control circuit may include or may be a timing controller 130. In the example, the control circuit may include or may be a timing controller 130 and a source driver 110. In the example, the control circuit may include or may be a timing controller 130, a source driver 110, and a level shifter 140. In the example, the control circuit may include a flicker compensation circuit. In the example, the timing controller 130 may include a flicker compensation circuit.

[0164] In one or more examples, the display device may include: a sub-pixel including a driving transistor DT and a light-emitting element OLED connected to the driving transistor; a data line DL coupled to the sub-pixel and configured to apply a data voltage to the sub-pixel during a gate-source setting period; a reference voltage line RL coupled to the sub-pixel and configured to apply an initialization voltage VpreR to the sub-pixel during a gate-source setting period; and control circuitry coupled to the sub-pixel, configured to determine a degradation of the light-emitting element OLED or another light-emitting element, and configured to adjust the initialization voltage based on the degradation.

[0165] In one or more examples, to determine degradation, the control circuitry may sense a threshold voltage stored in an internal capacitor of the light-emitting element or another light-emitting element during a sensing period that may differ from the gate-source setting period and during which display driving is not performed.

[0166] In one or more examples, the control circuit can increase the initial voltage as degradation increases.

[0167] In one or more examples, the control circuit can determine the degradation of the light-emitting element of the sub-pixel and the degradation of the second light-emitting element of the second sub-pixel, and the control circuit can provide the sub-pixel with an initialization voltage at a first level and the second sub-pixel with a second initialization voltage at a second level.

[0168] In one or more examples, the control circuit can sense the degradation of the light-emitting element of the sub-pixel independently of sensing the degradation of the second light-emitting element of the second sub-pixel, and the control circuit can adjust the initialization voltage to the first level independently of adjusting the second initialization voltage to the second level.

[0169] In one or more examples, in order to determine degradation, the control circuitry may predict degradation based at least on the cumulative luminescence history of the light-emitting element or another light-emitting element.

[0170] In one or more examples, the subpixel may also include a storage capacitor coupled to the driving transistor and a coupling capacitor coupled to the data line.

[0171] In one or more examples, the capacitance of the coupling capacitor is 0.1% to 0.5% of the capacitance of the storage capacitor.

[0172] The implementation of this disclosure can achieve the following effects.

[0173] One or more aspects of this disclosure can increase the voltage level of the initialization voltage as the light-emitting element deteriorates. Therefore, one or more aspects of this disclosure can reduce low grayscale recognition brightness deviations occurring under conditions of rapid changes in frame frequency, thereby improving VRR flicker and abnormal flash, and thus enhancing display quality.

[0174] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0175] The description herein has been presented to enable any person skilled in the art to make, use, and practice the technical features of this disclosure, and has been provided in the context of one or more specific example applications and their example claims. Various modifications, additions, and substitutions to the described embodiments will be readily apparent to those skilled in the art, and the principles described herein can be applied to other embodiments and applications without departing from the scope of this disclosure. The description and accompanying drawings herein provide non-limiting examples of the technical features of this disclosure for illustrative purposes. In other words, the disclosed embodiments illustrate the scope of the technical features of this disclosure and are not intended to be limiting in any way. Therefore, the scope of this disclosure is not limited to the illustrated embodiments but is consistent with the widest scope consistent with the claims and their equivalents.

Claims

1. A display device, comprising: The sub-pixel includes: a driving transistor having a gate electrode connected to a first node and a source electrode connected to a second node; a light-emitting element having an anode electrode connected to the second node; and a storage capacitor having one electrode connected to the first node and another electrode connected to the second node. Data lines configured to transmit data voltage to the first node during a gate-source setup period; and A reference voltage line is configured to deliver an initialization voltage to the second node during the gate-source setup period. The voltage level of the initialization voltage increases as the light-emitting element deteriorates.

2. The display device according to claim 1, wherein When the degradation sensing value of the light-emitting element, sensed based on the threshold voltage of the light-emitting element, increases from a first value to a second value, The initialization voltage has a first voltage level based on the degradation sensing value of the first value, and a second voltage level higher than the first voltage level based on the degradation sensing value of the second value.

3. The display device according to claim 1, wherein When the predicted degradation value of the light-emitting element, based on its cumulative luminescence history, increases from a first value to a second value, The initial voltage level has a first voltage level based on the degradation prediction value of the first value, and a second voltage level higher than the first voltage level based on the degradation prediction value of the second value.

4. The display device according to claim 1 further includes a coupling capacitor having one electrode connected to the first node and another electrode connected to the data line.

5. The display device of claim 4, wherein, The capacitance of the coupling capacitor is 0.1% to 0.5% of the capacitance of the storage capacitor.

6. A display device, comprising: A first sub-pixel is disposed in a first pixel row and includes a first driving transistor and a first light-emitting element. The first driving transistor has a gate electrode connected to a first node and a source electrode connected to a second node, and the first light-emitting element has an anode electrode connected to the second node. The second sub-pixel is disposed in the second pixel row and includes a second driving transistor and a second light-emitting element. The second driving transistor has a gate electrode connected to a third node and a source electrode connected to a fourth node, and the second light-emitting element has an anode electrode connected to the fourth node. A data line configured to transmit a first data voltage to the first node during a first gate-source setup period, and a second data voltage to the third node during a second gate-source setup period; as well as A reference voltage line is configured to transmit a first initialization voltage to the second node during the first gate-source setup period, and a second initialization voltage to the fourth node during the second gate-source setup period. The voltage level of the first initialization voltage is independent of the voltage level of the second initialization voltage.

7. The display device of claim 6, wherein, When the second light-emitting element deteriorates more than the first light-emitting element, the voltage level of the second initialization voltage is greater than the voltage level of the first initialization voltage.

8. The display device of claim 6, wherein, The first sub-pixel further includes a first storage capacitor and a first coupling capacitor. The first storage capacitor has one electrode connected to the first node and another electrode connected to the second node. The first coupling capacitor has one electrode connected to the first node and another electrode connected to the data line. The second sub-pixel further includes a second storage capacitor and a second coupling capacitor. The second storage capacitor has one electrode connected to the third node and another electrode connected to the fourth node. The second coupling capacitor has one electrode connected to the third node and another electrode connected to the data line.

9. The display device of claim 8, wherein, The capacitance of the first coupling capacitor is 0.1% to 0.5% of the capacitance of the first storage capacitor, and The capacitance of the second coupling capacitor is 0.1% to 0.5% of the capacitance of the second storage capacitor.

10. A display device, comprising: A sub-pixel includes a driving transistor and a light-emitting element connected to the driving transistor; A data line coupled to the sub-pixel and configured to apply a data voltage to the sub-pixel during a gate-source setup period; A reference voltage line, coupled to the sub-pixel, is configured to apply an initialization voltage to the sub-pixel during the gate-source setup period; as well as A control circuit, coupled to the sub-pixel, is configured to determine the degradation of the light-emitting element and / or one or more other light-emitting elements, and is configured to adjust the initialization voltage based on the degradation.

11. The display device of claim 10, wherein, To determine degradation, the control circuit is configured to sense a threshold voltage stored in the internal capacitors of the light-emitting element and / or one or more other light-emitting elements during the sensing period. The sensing period is different from the gate-source setting period, and During the sensing period, the display driver is not executed.

12. The display device of claim 10, wherein, The control circuit is configured to increase the voltage level of the initialization voltage as degradation increases.

13. The display device of claim 10, wherein, The control circuit is configured to determine the degradation of the light-emitting element of the sub-pixel and the degradation of the second light-emitting element of the second sub-pixel among the one or more other light-emitting elements, and The control circuit is configured to provide the sub-pixel with an initialization voltage at a first level according to the degradation of the light-emitting element, and to provide the second sub-pixel with a second initialization voltage at a second level according to the degradation of the second light-emitting element.

14. The display device of claim 13, wherein, The control circuit is configured to sense the degradation of the light-emitting element of the sub-pixel independently of sensing the degradation of the second light-emitting element of the second sub-pixel, and The control circuit is configured to adjust the initialization voltage to the first level independently of adjusting the second initialization voltage to the second level.

15. The display device of claim 10, wherein, In order to determine degradation, the control circuit is configured to predict degradation based at least on the cumulative luminescence history of the light-emitting element and / or one or more other light-emitting elements.

16. The display device of claim 10, wherein, The sub-pixel also includes a storage capacitor coupled to the driving transistor and a coupling capacitor coupled to the data line.

17. The display device of claim 16, wherein, The capacitance of the coupling capacitor is 0.1% to 0.5% of the capacitance of the storage capacitor.

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