Display panel and display device

Abstract

This application discloses a display panel and display device. By making each pixel include a first sub-pixel to a fourth sub-pixel, and setting a selection module between at least one pixel and a first data source and a first power supply, the selection module controls the first sub-pixel or the fourth sub-pixel in the at least one pixel to receive the corresponding data signal, and controls the signal transmission between the first sub-pixel and the fourth sub-pixel and the first power supply, so that the first sub-pixel displays according to the corresponding data signal or displays a fixed grayscale according to the first power signal, and the fourth sub-pixel displays according to the corresponding data signal or displays a fixed grayscale according to the first power signal, thereby increasing the display data sources and display methods corresponding to the pixels, which is beneficial to broadening the application range of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Multiple sub-pixels in a display panel can display images and text based on corresponding data signals, presenting information to the user in a visual form. However, the display panel's display method is relatively simple, which is not conducive to broadening the application range of the display panel. Summary of the Invention

[0003] This application provides a display panel and display device, which enables the display panel to have multiple application modes, thereby expanding the application range of the display panel.

[0004] This application provides a display panel including multiple pixels and multiple selection modules. Each pixel includes multiple sub-pixels, each sub-pixel is configured to display according to a corresponding data signal, and the multiple sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The emission color of the first sub-pixel is different from the emission colors of the second and third sub-pixels. The first and fourth sub-pixels in the same pixel are electrically connected to a first data source. Each selection module is electrically connected between the first data source and the first and fourth sub-pixels of at least one pixel, and the selection module is electrically connected to a first power supply terminal. Each selection module is configured to control the signal transmission between at least one pixel and the first data source and the first power supply terminal, so as to control the first or fourth sub-pixel in the corresponding pixel to receive the data signal supplied by the first data source, and to control the signal transmission between the first and fourth sub-pixels in the corresponding pixel and the first power supply terminal. The first power signal supplied by the first power supply terminal is used to control at least one of the first and fourth sub-pixels to display a fixed grayscale.

[0005] This application also provides a display device, including any of the above-described display panels and a source driver. The source driver is electrically connected to the display panel and includes a plurality of output terminals configured to transmit corresponding data signals to a plurality of sub-pixels. Some of the output terminals serve as a first data source and are electrically connected to a corresponding selection module.

[0006] The above technical solution includes a first sub-pixel to a fourth sub-pixel in each pixel, and a selection module is set between at least one pixel and the first data source and the first power supply. The selection module controls the first sub-pixel or the fourth sub-pixel in the at least one pixel to receive the corresponding data signal, and controls the signal transmission between the first sub-pixel and the fourth sub-pixel and the first power supply. This allows the first sub-pixel to display according to the corresponding data signal or to display a fixed grayscale according to the first power signal, and the fourth sub-pixel to display according to the corresponding data signal or to display a fixed grayscale according to the first power signal. This increases the display data sources and display methods corresponding to the pixels, which is beneficial to broadening the application range of the display panel. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0008] Figures 1A-1B This is a schematic diagram of the structure of a display panel provided in an exemplary embodiment of the present disclosure; Figure 2 A schematic diagram illustrating the connection between the selection module and the first sub-pixel and the fourth sub-pixel, provided as an exemplary embodiment of this disclosure; Figure 3 A schematic diagram of the circuit structure of a sub-pixel provided in an exemplary embodiment of this disclosure; Figure 4 A schematic diagram illustrating the connection between a sub-pixel and a gating driver provided in an exemplary embodiment of this disclosure; Figures 5A-5C This is a timing diagram of sub-pixels provided in an exemplary embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of a display device provided in an exemplary embodiment of the present disclosure; The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0009] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0010] It should be noted that the electrical connection referred to in this application can refer to a direct connection or an indirect connection. An indirect connection can be a connection between connected sub-circuits, devices, or nodes achieved through electrical components, wired or wireless media, etc. An electrical connection can refer to a physically existing connection or a connection established through signals. The descriptions of "first," "second," etc., involved in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" or "second" can explicitly or implicitly include at least one of those features. Furthermore, the various technical features in this application can be applied to achieve different combinations, and are not limited to the technical solutions formed by the combinations listed in the embodiments. The technical solutions between various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application. The terms "optionally" and "in some embodiments" used in this application indicate that the technical content they refer to can be selectively configured.

[0011] Furthermore, the descriptions provided in the Background section should not be presumed to be prior art simply because they are mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter, and the description in this section does not limit the invention.

[0012] Figures 1A-1B This is a schematic diagram of the structure of a display panel provided in an exemplary embodiment of this disclosure. This application provides a display panel. The display panel may be a self-emissive display panel or a quantum dot display panel, etc.

[0013] The display panel may include multiple pixels (PX), which are used to realize the display function of the display panel.

[0014] Each pixel PX can include multiple sub-pixels Spx, and each sub-pixel Spx is configured to be displayed according to the corresponding data signal.

[0015] Optionally, at least one pixel PX may include multiple sub-pixels Spx, such as a first sub-pixel Spx1, a second sub-pixel Spx2, a third sub-pixel Spx3, and a fourth sub-pixel Spx4. Figure 1B As shown. The emission colors of the first sub-pixel Spx1 to the fourth sub-pixel Spx4 can be the same or different.

[0016] It should be noted that, in Figure 1BThe display panel shown is illustrated using only one example, with each pixel PX including the first sub-pixels Spx1 to the fourth sub-pixels Spx4. However, in practical applications, it is not limited to this example. Figure 1B The design shown. In some embodiments, each of a subset of pixels PX may include a first sub-pixel Spx1 through a fourth sub-pixel Spx4, while a subset of pixels PX may include one, two, or all three of the first sub-pixels Spx1 through the fourth sub-pixel Spx4. The shape and arrangement of the multiple sub-pixels Spx are not limited to... Figures 1A-1B As shown in the figure.

[0017] In some embodiments, to achieve multi-color display of pixel PX, the emission color of the first sub-pixel Spx1 can be different from the emission color of the second sub-pixel Spx2 and the emission color of the third sub-pixel Spx3.

[0018] Optionally, the first sub-pixel Spx1 and the fourth sub-pixel Spx4 in the same pixel PX are electrically connected to a first data source D1, so as to use the same first data source D1 to provide the required data signals for the first sub-pixel Spx1 and the fourth sub-pixel Spx4 in the same pixel PX, thereby reducing the number of data sources for the application corresponding to the display panel.

[0019] Optionally, to facilitate the sharing of a data source between the first sub-pixel Spx1 and the fourth sub-pixel Spx4, and to allow the first sub-pixel Spx1 and the fourth sub-pixel Spx4 to receive corresponding data signals as needed, the display panel may further include at least one selection module 10. Each selection module 10 may be electrically connected between a first data source D1 and the first sub-pixel Spx1 and the fourth sub-pixel Spx4 of at least one pixel PX, and the selection module 10 is electrically connected to the first power supply terminal VGH. Each selection module 10 is configured to control the signal transmission between at least one pixel PX and the first data source D1 and the first power supply terminal VGH, so as to control the first sub-pixel Spx1 or the fourth sub-pixel Spx4 in the corresponding pixel PX to receive the data signal supplied by the first data source D1, and to control the signal transmission between the first sub-pixel Spx1 and the fourth sub-pixel Spx4 in the corresponding pixel PX and the first power supply terminal VGH; wherein, the first power signal supplied by the first power supply terminal VGH is used to control at least one of the first sub-pixel Spx1 and the fourth sub-pixel Spx4 to display a fixed grayscale, so that the first sub-pixel Spx1 and the fourth sub-pixel Spx4 can also be displayed under the action of the first power signal, thereby increasing the display data source and display mode corresponding to the pixel PX, which is beneficial to broadening the application range of the display panel. The display data source corresponding to the pixel PX includes the first data source D1 and the first power supply terminal VGH corresponding to the pixel PX.

[0020] Compared to Figure 1AThe design shown, in which each sub-pixel Spx includes only the first sub-pixel Spx1, the second sub-pixel Spx2, and the third sub-pixel Spx3, allows the display panel to support more display modes by making at least one pixel PX also include a fourth sub-pixel Spx4, and by controlling the first sub-pixel Spx1 and the fourth sub-pixel Spx4 in the same pixel PX to share a first data source D1 and a first power signal, which is beneficial to broadening the application range of the display panel.

[0021] Optionally, to improve the display uniformity of the display panel, the first sub-pixel Spx1 to the fourth sub-pixel Spx4 can be distributed alternately.

[0022] In some embodiments, the display panel may include a plurality of first pixel groups PU1 and a plurality of second pixel groups PU2, wherein the first pixel groups PU1 and second pixel groups PU2 are alternately arranged along a first direction Dr1, each first pixel group PU1 includes a first sub-pixel Spx1 and a fourth sub-pixel Spx4 alternately arranged along a second direction Dr2, and each second pixel group PU2 includes a second sub-pixel Spx2 and a third sub-pixel Spx3 alternately arranged along a second direction Dr2. The first direction Dr1 and the second direction Dr2 intersect.

[0023] In some embodiments, to further improve the display uniformity of the display panel, the first sub-pixel Spx1 in two adjacent first pixel groups PU1 along the first direction Dr1 and the fourth sub-pixel Spx4 along the first direction Dr1 can be adjacent; the second sub-pixel Spx2 in two adjacent second pixel groups PU2 along the first direction Dr1 and the third sub-pixel Spx3 along the first direction Dr1 can be adjacent, so that the first sub-pixels Spx1 to the fourth sub-pixels Spx4 are evenly arranged.

[0024] Optionally, the first direction Dr1 is one of the row direction and the column direction, and the second direction Dr2 is the other of the row direction and the column direction. It should be noted that in... Figure 1B The display panel shown is illustrated using only the first direction Dr1 as the row direction and the second direction Dr2 as the column direction as an example. However, this is not intended to limit the first direction Dr1 and the second direction Dr2 of this application to be... Figure 1B As shown. Those skilled in the art can still set the first direction Dr1 and the second direction Dr2 to other directions besides the row direction and column direction, depending on different actual needs.

[0025] It should be understood that, Figure 1B The example only illustrates the case where the first pixel group PU1 is located in an even-numbered column and the second pixel group PU2 is located in an odd-numbered column. In some embodiments, the first pixel group PU1 may be located in an odd-numbered column and the second pixel group PU2 may be located in an even-numbered column.

[0026] Optionally, to further reduce the number of data sources used in the display panel, the same first data source D1 can be electrically connected to multiple pixels PX, so that the first data source D1 provides corresponding data signals to the first sub-pixel Spx1 and the fourth sub-pixel Spx4 among the multiple pixels PX.

[0027] Optionally, in order to further reduce the number of data sources used in the display panel and reduce signal interference between multiple first data sources D1, each first data source D1 can be electrically connected to the first sub-pixel Spx1 and the fourth sub-pixel Spx4 of multiple pixels PX in the same first pixel group PU1, so that the first data source and the first pixel group PU1 are set in a one-to-one correspondence.

[0028] Optionally, in order to further reduce the number of data sources used in the display panel and reduce the number of selection modules 10 included in the display panel, multiple first sub-pixels Spx1 and multiple fourth sub-pixels Spx4 of the same first pixel group PU1 can be electrically connected to a selection module 10, so that the selection module 10 can control the multiple first sub-pixels Spx1 and multiple fourth sub-pixels Spx4 of the same first pixel group PU1 to share the signal provided by the same first data source D1.

[0029] Optionally, the required data signals can be provided to multiple second sub-pixels Spx2 through multiple second data sources D2, and the required data signals can be provided to multiple third sub-pixels Spx3 through multiple third data sources D3.

[0030] In some embodiments, in order to reduce the number of second data sources D2 corresponding to the application of the display panel, multiple second sub-pixels Spx2 of the same second pixel group PU2 can be electrically connected to a second data source D2 so as to use a second data source D2 to provide the required data signals to multiple second sub-pixels Spx2 of the same second pixel group PU2.

[0031] In some embodiments, in order to reduce the number of third data sources D3 for the application corresponding to the display panel, multiple third sub-pixels Spx3 of the same second pixel group PU2 can be electrically connected to a third data source D3 so as to use a third data source D3 to provide the required data signals to multiple third sub-pixels Spx3 of the same second pixel group PU2.

[0032] In some embodiments, to reduce the impact of the selection module 10 on the display panel resolution, the selection module 10 can be set in the non-display area of ​​the display panel, while the multiple sub-pixels Spx are located in the display area of ​​the display panel.

[0033] Optionally, to enable signal transmission between the data source and the corresponding sub-pixel Spx, the display panel may also include multiple data lines, which are arranged along a first direction Dr1 and each data line extends along a second direction Dr2. Each data line is electrically connected between a data source and at least one sub-pixel Spx to enable signal transmission between a data source and the corresponding sub-pixel Spx.

[0034] like Figure 2 This diagram illustrates the connection between the selection module and the first and fourth sub-pixels, as provided in an exemplary embodiment of this disclosure. The multiple data lines include multiple first data lines DL1, multiple second data lines DL2, multiple third data lines DL3, and multiple fourth data lines DL4, as shown below. Figure 1B and Figure 2 As shown. Each first data line DL1 is electrically connected between a selection module 10 and a plurality of first sub-pixels Spx1 of a first pixel group PU1. Each second data line DL2 is electrically connected between a selection module 10 and a plurality of fourth sub-pixels Spx4 of a first pixel group PU1. Each third data line DL3 is electrically connected between a second data source D2 and a plurality of second sub-pixels Spx2 of a second pixel group PU2. The second data source D2 is configured to transmit data signals to the corresponding second sub-pixel Spx2. Each fourth data line DL4 is electrically connected between a third data source D3 and a plurality of third sub-pixels Spx3 of a second pixel group PU2. The third data source D3 is configured to transmit data signals to the corresponding third sub-pixel Spx3. By using the first data lines DL1 to the fourth data lines DL4 to supply the signals supplied by the first data source D1 to the third data source D3 to the first sub-pixels Spx1 to the fourth sub-pixels Spx4 located in different pixel groups, it is beneficial to reduce the mutual interference between the signals supplied by the first data source D1 to the third data source D3, and to improve the working stability of the display panel.

[0035] It should be noted that, Figure 2 The example shown only shows the case where the first pixel group PU1 is located to the right of the second pixel group PU2. However, in actual applications, the second pixel group PU2 can be provided on at least one of the two opposite sides of the first pixel group PU1 along the first direction Dr1.

[0036] In some embodiments, the first data line DL1 and the second data line DL2 can be positioned on opposite sides of the corresponding first pixel group PU1 along the first direction Dr1, and the third data line DL3 and the fourth data line DL4 can be positioned on opposite sides of the corresponding second pixel group PU2 along the first direction Dr1, in order to reduce the interference of the data signal transmitted by the first data line DL1 on the working state of the fourth sub-pixel Spx4, reduce the interference of the data signal transmitted by the second data line DL2 on the working state of the first sub-pixel Spx1, reduce the interference of the data signal transmitted by the third data line DL3 on the working state of the second sub-pixel Spx2, and reduce the interference of the data signal transmitted by the fourth data line DL4 on the working state of the third sub-pixel Spx3.

[0037] Optionally, in the second direction Dr2, multiple first sub-pixels Spx1 in the same first pixel group PU1 can be arranged along the same extension direction, and multiple fourth sub-pixels Spx4 can be arranged along the same extension direction. The extension directions of the arrangement of the multiple first sub-pixels Spx1 and the extension directions of the arrangement of the multiple fourth sub-pixels Spx4 can overlap or be parallel.

[0038] Optionally, to control the formation of current paths between the first sub-pixel Spx1 and the fourth sub-pixel Spx4 in the same pixel PX and their corresponding first data source D1, the selection module 10 can include a first switching unit 101 and a second switching unit 102, such as... Figure 2 As shown. A first switching unit 101 is electrically connected between a corresponding first data source D1 and a first data line DL1, and is configured to control signal transmission between the first data source D1 and the corresponding first data line DL1. A second switching unit 102 is electrically connected between a corresponding first data source D1 and a second data line DL2, and is configured to control signal transmission between the first data source D1 and the corresponding second data line DL2.

[0039] In some embodiments, the first switching unit 101 is configured to receive a first selection control signal SW1, and the second switching unit 102 is configured to receive a second selection control signal SW2. The first switching unit 101 is configured to control the signal transmission between the first data source and the corresponding first data line DL1 according to the first selection control signal SW1, and the second switching unit 102 is configured to control the signal transmission between the first data source and the corresponding second data line DL2 according to the second selection control signal SW2. By enabling the first switching unit 101 and the second switching unit 102 to receive different selection control signals, independent control of the first sub-pixel Spx1 and the fourth sub-pixel Spx4 receiving the corresponding data signals can be achieved.

[0040] Optionally, to control the formation of current paths between the first sub-pixel Spx1 and the fourth sub-pixel Spx4 in the same pixel PX and the first power supply terminal VGH, at least one selection module 10 may include a third switching unit 103 and a fourth switching unit 104, such as... Figure 2 As shown. A third switch unit 103 is electrically connected between a corresponding first power supply terminal VGH and a first data line DL1. The third switch unit 103 is configured to control the signal transmission between the first power supply terminal VGH and the corresponding first data line DL1. A fourth switch unit 104 is electrically connected between a corresponding first power supply terminal VGH and a second data line DL2. The fourth switch unit 104 is configured to control the signal transmission between the first power supply terminal VGH and the corresponding second data line DL2.

[0041] In some embodiments, the third switching unit 103 is configured to receive a third selection control signal SW3, and the fourth switching unit 104 is configured to receive a fourth selection control signal SW4. The third switching unit 103 is configured to control the signal transmission between the first power supply terminal VGH and the corresponding first data line DL1 according to the third selection control signal SW3, and the fourth switching unit 104 is configured to control the signal transmission between the first power supply terminal VGH and the corresponding second data line DL2 according to the fourth selection control signal SW4, so as to realize independent control of the first sub-pixel Spx1 and the fourth sub-pixel Spx4 receiving the corresponding first power supply signal.

[0042] Optionally, at least one of the first switching unit 101 to the fourth switching unit 104 can be implemented by a switching device or the like. The switching device includes, but is not limited to, transistors or other devices that implement switching functions.

[0043] To facilitate understanding of this application, a transistor is used as an example for illustration when describing the switching device. In some embodiments, the first switching unit 101 may include a first transistor T1, the second switching unit 102 may include a second transistor T2, the third switching unit 103 may include a third transistor T3, and the fourth switching unit 104 may include a fourth transistor T4, such as... Figure 2 As shown.

[0044] The first transistor T1 includes a control terminal configured to receive a first selection control signal SW1, a first source-drain terminal electrically connected to a corresponding first data source D1, and a second source-drain terminal electrically connected to a corresponding first data line DL1.

[0045] The second transistor T2 includes a control terminal configured to receive a second selection control signal SW2, a first source-drain terminal electrically connected to a corresponding first data source D1, and a second source-drain terminal electrically connected to a corresponding second data line DL2.

[0046] The third transistor T3 includes a control terminal configured to receive a third selection control signal SW3, a first source-drain terminal electrically connected to a first power supply terminal VGH, and a second source-drain terminal electrically connected to a corresponding first data line DL1.

[0047] The fourth transistor T4 includes a control terminal configured to receive a fourth selection control signal SW4, a first source-drain terminal electrically connected to a first power supply terminal VGH, and a second source-drain terminal electrically connected to a corresponding second data line DL2.

[0048] It should be understood that the first transistor T1 through the fourth transistor T4 can be either P-type or N-type transistors. The first transistor T1 through the fourth transistor T4 can be implemented as bipolar junction transistors, field-effect transistors, or thin-film transistors, respectively. When the transistor is implemented as a field-effect transistor or a thin-film transistor, the aforementioned control terminal can be the gate, the first source-drain terminal can be one of the source and drain, and the second source-drain terminal can be the other of the source and drain. When the transistor is implemented as a bipolar junction transistor, the aforementioned control terminal can be the base, the first source-drain terminal can be one of the collector and emitter, and the second source-drain terminal can be the other of the collector and emitter. Each transistor can employ a single-gate or dual-gate design. The active layer of each transistor can include silicon semiconductor materials or oxide semiconductor materials. The silicon semiconductor materials include monocrystalline silicon, polycrystalline silicon, or amorphous silicon, etc. The oxide semiconductor materials include indium gallium zinc oxide or indium zinc oxide, etc.

[0049] Optionally, multiple first switch units 101 may share the same first selection control signal SW1, thereby reducing the number of selection control signals used by the display panel and reducing the control complexity of multiple first switch units 101.

[0050] In some embodiments, when multiple first switching units 101 share the same first selection control signal SW1, the operating states of the multiple first switching units 101 can remain synchronized. However, it should be understood that the operating states of some of the multiple first switching units 101 can be desynchronized by having the multiple first switching units 101 each include transistors of different types. The transistors of different types can be P-type transistors or N-type transistors.

[0051] It should be noted that a first selection control signal SW1 can also be set for each first switch unit 101, and the level changes of multiple first selection control signals SW1 are independent of each other, so as to support the asynchronous design of the working states of at least two first switch units 101.

[0052] Similarly, multiple second switch units 102 can share the same second selection control signal SW2, thereby reducing the number of selection control signals used by the display panel and reducing the control complexity of the multiple second switch units 102. Furthermore, each second switch unit 102 can be assigned a corresponding second selection control signal SW2, and the level changes of the multiple second selection control signals SW2 can be independent of each other, supporting asynchronous design of the operating states of at least two second switch units 102.

[0053] Similarly, multiple third switch units 103 can share the same third selection control signal SW3, or each third switch unit 103 can be provided with a corresponding third selection control signal SW3. Multiple fourth switch units 104 can share the same fourth selection control signal SW4, or each fourth switch unit 104 can be provided with a corresponding fourth selection control signal SW4.

[0054] In some embodiments, when multiple first switching units 101 share a first selection control signal SW1, each first selection control signal SW1 can maintain the same level state within a frame, so that the first selection control signal SW1 has no level jump within a frame, which is beneficial to reducing the power consumption of the display panel. Similarly, when multiple second switching units 102 share a second selection control signal SW2, each second selection control signal SW2 can maintain the same level state within a frame. When multiple third switching units 103 share a third selection control signal SW3, each third selection control signal SW3 can maintain the same level state within a frame. When multiple fourth switching units 104 share a fourth selection control signal SW4, each fourth selection control signal SW4 can maintain the same level state within a frame.

[0055] In some embodiments, the display panel employs a line scanning design, and the time periods during which sub-pixels Spx located in different rows receive the corresponding data signals can be different. Therefore, within a single frame, the first switching unit 101 can be controlled to have different level states corresponding to the time periods during which sub-pixels Spx in different rows receive the corresponding data signals, thereby allowing pixels PX located in different rows within the same first pixel group PU1 to be displayed in different display modes.

[0056] Since the first switch unit 101 to the fourth switch unit 104, together with the first selection control signal SW1 to the fourth selection control signal SW4, can control the display of the first sub-pixel Spx1 and the fourth sub-pixel Spx4, the display panel can be designed with different display modes by corresponding to different combinations of the working states of the first switch unit 101 to the fourth switch unit 104.

[0057] In some embodiments, the display panel has a first display mode. When the display panel is in the first display mode, each first switching unit 101 connects a first data source D1 and a corresponding first data line DL1 to a current path, and each fourth switching unit 104 connects a first power supply terminal VGH and a corresponding second data line DL2 to a current path. Each second sub-pixel Spx2 and each third sub-pixel Spx3 are displayed according to their respective data signals, so that the first sub-pixels Spx1 to the third sub-pixels Spx3 in the corresponding pixel PX are displayed according to their respective data signals, while the fourth sub-pixel Spx4 displays a fixed grayscale according to the first power supply signal.

[0058] In other embodiments, the display panel has a second display mode. When the display panel is in the second display mode, each second switch unit 102 connects a first data source D1 and a corresponding second data line DL2 to a current path, and each third switch unit 103 connects a first power supply terminal VGH and a corresponding first data line DL1 to a current path. Each second sub-pixel Spx2 and each third sub-pixel Spx3 are displayed according to their respective data signals, so that the second sub-pixels Spx2 to the fourth sub-pixels Spx4 in the corresponding pixel PX are displayed according to their respective data signals, while the first sub-pixel Spx1 displays a fixed grayscale according to the first power supply signal.

[0059] In some other embodiments, the display panel has a third display mode. When the display panel is in the third display mode, each second switch unit 102 connects a first data source D1 and a corresponding second data line DL2 to a current path, and each third switch unit 103 connects a first power supply terminal VGH and a corresponding first data line DL1 to a current path. Furthermore, each second sub-pixel Spx2 and each third sub-pixel Spx3 displays 0 grayscale, so that the fourth sub-pixel Spx4 in the corresponding pixel PX is displayed according to the corresponding data signal, while the first sub-pixels Spx1 to the third sub-pixels Spx3 display a fixed grayscale.

[0060] In some other embodiments, the display panel has a fourth display mode. When the display panel is in the fourth display mode, each selection module 10 alternately connects a first data source D1 with the current path between the corresponding first data line DL1 and the second data line DL2, and each second sub-pixel Spx2 and each third sub-pixel Spx3 are displayed according to the corresponding data signal, so that the first sub-pixel Spx1 to the fourth sub-pixel Spx4 in the corresponding pixel PX are displayed according to the corresponding data signal.

[0061] It should be noted that the fixed grayscale can be one of the multiple grayscale levels that the display panel can support. For example, in some embodiments, the fixed grayscale is grayscale 0, grayscale 128, or grayscale 255, etc. Understandably, the fixed grayscale displayed by the first sub-pixel Spx1 and the fourth sub-pixel Spx4 can also be different depending on the voltage of the first power signal.

[0062] In some embodiments, when the display panel is in the first display mode, the fourth sub-pixel Spx4 displays a fixed gray level of 0 according to the first power signal, so as to reduce the power consumption of the display panel while realizing the display using the first sub-pixels Spx1 to the third sub-pixels Spx3.

[0063] In some embodiments, when the display panel is in the second display mode and the third display mode, the first sub-pixel Spx1 displays a fixed gray level of 0 according to the first power signal, so as to reduce the power consumption of the display panel.

[0064] It should be understood that the above four display modes are exemplified by simulating the synchronized operation of multiple first switch units 101, multiple second switch units 102, multiple third switch units 103, and multiple fourth switch units 104. However, in some embodiments, multiple first selection control signals SW1 can be used to control the asynchronous operation of multiple first switch units 101, multiple second selection control signals SW2 can be used to control the asynchronous operation of multiple second switch units 102, multiple third selection control signals SW3 can be used to control the asynchronous operation of multiple third switch units 103, or multiple fourth selection control signals SW4 can be used to control the asynchronous operation of multiple fourth switch units 104, so that the display panel can achieve display designs with more display modes.

[0065] To facilitate understanding of this application, various display modes of the display panel will be illustrated below in conjunction with sub-pixels (Spx).

[0066] Optionally, each sub-pixel Spx may include a light-emitting device LE and a pixel driving circuit. The pixel driving circuit is electrically connected to the light-emitting device LE and is used to drive the light-emitting device LE to emit light so as to realize the display function of the sub-pixel Spx.

[0067] Optionally, the light-emitting device LE may include at least one of organic light-emitting diodes, sub-millimeter light-emitting diodes, and micro light-emitting diodes.

[0068] Optionally, the pixel driving circuit includes a driving unit and a data writing unit. The driving unit is electrically connected to the light-emitting device (LE) and is configured to generate a driving current to drive the LE to emit light. The data writing unit is electrically connected to the driving unit and is configured to transmit a data signal to the corresponding driving unit, so that the driving unit generates a driving current according to the corresponding data signal.

[0069] In some embodiments, the driving unit and the data writing unit are implemented using components such as switching devices.

[0070] like Figure 3 This is a schematic diagram of the circuit structure of a sub-pixel provided in an exemplary embodiment of this disclosure. The driving unit may include a driving transistor Tdr, and the data writing unit may include a data transistor Tda. The driving transistor Tdr includes a control terminal, a control terminal electrically connected to a second power supply terminal VDD, and a second source-drain terminal electrically connected to a light-emitting device LE. The data transistor Tda includes a control terminal configured to receive a first scan signal Scan1, a first source-drain terminal electrically connected to a corresponding data line DL, and a second source-drain terminal electrically connected to one of the control terminal of the driving transistor Tdr, the first source-drain terminal of the driving transistor Tdr, and the second source-drain terminal of the driving transistor Tdr.

[0071] It should be noted that, Figure 3 This embodiment only shows an implementation where the first source-drain terminal of the data transistor Tda is electrically connected to the driving transistor Tdr, but in practical applications, it is not limited to this.

[0072] Optionally, the pixel driving circuit may also include a storage unit configured to maintain the potential of the control terminal of the driving transistor Tdr.

[0073] In some embodiments, the storage unit includes a first storage capacitor Cst, such as Figure 3 As shown, the first storage capacitor Cst is electrically connected between the control terminal of the driving transistor Tdr and the second power supply terminal VDD.

[0074] Optionally, when the second source-drain terminal of the data transistor Tda is electrically connected to the first source-drain terminal of the driving transistor Tdr, the pixel driving circuit may further include a second storage capacitor Cbt, which is electrically connected between the control terminal of the data transistor Tda and the control terminal of the driving transistor Tdr.

[0075] Optionally, to reduce the impact of the threshold voltage of the driving transistor Tdr on the driving current, the pixel driving circuit may also include a compensation unit, which is electrically connected to the driving transistor Tdr. The compensation unit is configured to compensate the threshold voltage of the driving transistor Tdr according to the corresponding second scan signal Scan2.

[0076] In some embodiments, the compensation unit includes a compensation transistor Tc, such as Figure 3 As shown, the compensation transistor Tc includes a control terminal configured to receive the corresponding second scan signal Scan2, a first source-drain terminal electrically connected to one of the first source-drain terminal and the second source-drain terminal of the driving transistor Tdr, and a second source-drain terminal electrically connected to the control terminal of the driving transistor Tdr.

[0077] In some embodiments, the second source-drain terminal of the data transistor Tda is electrically connected to one of the first source-drain terminal and the second source-drain terminal of the driving transistor Tdr, and the second source-drain terminal of the compensation transistor Tc is electrically connected to the other of the first source-drain terminal and the second source-drain terminal of the driving transistor Tdr.

[0078] Optionally, to reduce the influence of residual charge at the control terminal of the driving transistor Tdr on the driving current, the pixel driving circuit may further include a first reset unit, which is electrically connected to the driving transistor Tdr and configured to reset the potential of the control terminal of the driving transistor Tdr according to the corresponding third scan signal Scan3.

[0079] In some embodiments, the first reset unit includes a first reset transistor Tr1, such as... Figure 3 As shown, the first reset transistor Tr1 includes a control terminal configured to receive the corresponding third scan signal Scan3, a first source-drain terminal electrically connected to the control terminal of the drive transistor Tdr, and a second source-drain terminal configured to receive the first reset signal Vi1.

[0080] Optionally, to reduce the impact of residual charge on the anode of the light-emitting device (LE) on the brightness of the LE, the pixel driving circuit may include a second reset unit, which is electrically connected to the anode of the LE and configured to reset the potential of the anode of the LE according to the corresponding fourth scan signal Scan4.

[0081] In some embodiments, the second reset unit includes a second reset transistor Tr2, such as... Figure 3 As shown, the second reset transistor Tr2 includes a control terminal configured to receive the corresponding fourth scan signal Scan4, a first source-drain terminal electrically connected to the anode of the light-emitting device LE, and a second source-drain terminal configured to receive the second reset signal Vi2.

[0082] Optionally, to achieve controllable emission period of the light-emitting device (LE), the pixel driving circuit may further include a light-emitting control unit, which is electrically connected to the driving unit and the light-emitting device (LE). The light-emitting control unit is configured to control the on / off state of the driving current flow path according to the light-emitting control signal EM.

[0083] In some embodiments, the light-emitting control unit includes a first light-emitting control transistor Ts1, such as Figure 3 As shown, the first light-emitting control transistor Ts1 includes a control terminal configured to receive the light-emitting control signal EM, a first source-drain terminal electrically connected to the second power supply terminal VDD, and a second source-drain terminal electrically connected to the first source-drain terminal of the driving transistor Tdr.

[0084] In some embodiments, the light-emitting control unit includes a second light-emitting control transistor Ts2, such as Figure 3 As shown, the second light-emitting control transistor Ts2 includes a control terminal configured to receive the light-emitting control signal EM, a first source-drain terminal electrically connected to the second source-drain terminal of the driving transistor Tdr, and a second source-drain terminal electrically connected to the light-emitting device LE.

[0085] Optionally, the cathode of the light-emitting device LE is electrically connected to the third power supply terminal VSS, and the voltage value of the second power supply signal supplied by the second power supply terminal VDD may be different from the voltage value of the third power supply signal supplied by the third power supply terminal VSS.

[0086] Optionally, to reduce the probability of flickering and other problems, the pixel driving circuit may also include a third reset unit, which is electrically connected to the first source-drain terminal of the driving transistor Tdr. The third reset unit is configured to control the transmission of the third reset signal Vi3 to the first source-drain terminal of the driving transistor Tdr according to the corresponding fourth scan signal Scan4.

[0087] In some embodiments, the third reset unit includes a third reset transistor, such as Figure 3 As shown, the third reset transistor includes a control terminal configured to receive the corresponding fourth scan signal Scan4, a first source-drain terminal electrically connected to the first source-drain terminal of the driving transistor Tdr, and a second source-drain terminal configured to receive the third reset signal Vi3.

[0088] It should be noted that the transistors included in the pixel driving circuit can be P-type transistors or N-type transistors, and the transistors can be silicon transistors or oxide transistors. It should be understood that... Figure 3 The pixel driving circuit shown is for illustrative purposes only to facilitate understanding of this application. In practical applications, those skilled in the art can modify the specific implementation of each unit in the pixel driving circuit, or modify the connection form of each unit, or selectively configure some units according to different actual needs.

[0089] Optionally, the display panel may apply signals generated by multiple gating drivers to serve as the first scan signal Scan1 to the fourth scan signal Scan4, respectively.

[0090] Figure 4 This diagram illustrates the connection between a sub-pixel and a gating driver, provided as an exemplary embodiment of this disclosure. Multiple gating driver circuits can be integrated into the display panel using gate driving on the array substrate.

[0091] In some embodiments, the plurality of gating drivers may include a first gating driver GM1, the first gating driver GM1 including a plurality of cascaded first gating driving circuits GA, each first gating driving circuit GA being electrically connected to a data writing unit of at least one sub-pixel Spx, and each first gating driving circuit GA being configured to output a corresponding first scan signal Scan1 to the corresponding sub-pixel Spx.

[0092] Optionally, to reduce the number of first gating drive circuits GA included in the first gating driver GM1, each first gating drive circuit GA can be electrically connected to the data writing units of multiple sub-pixels Spx of at least one third pixel group PU3. Each first gating drive circuit GA is configured to output a corresponding first scan signal Scan1 to the multiple sub-pixels Spx of the corresponding third pixel group PU3. The multiple third pixel groups PU3 are arranged along the second direction Dr2, and each third pixel group PU3 includes multiple sub-pixels Spx arranged along the first direction Dr1.

[0093] It should be noted that the same third pixel group PU3 may include multiple first sub-pixels Spx1, multiple second sub-pixels Spx2, multiple fourth sub-pixels Spx4, or multiple fourth sub-pixels Spx4. In some embodiments, in some third pixel groups PU3, the first sub-pixels Spx1 and the second sub-pixels Spx2 are arranged alternately along the first direction Dr1. In other third pixel groups PU3, the second sub-pixels Spx2 and the fourth sub-pixels Spx4 are arranged alternately along the first direction Dr1. A third pixel group including the second sub-pixels Spx2 and the fourth sub-pixels Spx4 may be arranged alternately with a third pixel group including the first sub-pixels Spx1 and the third sub-pixels Spx3 along the second direction Dr2.

[0094] In some embodiments, to improve the data writing capability of each sub-pixel Spx, each first gating driving circuit GA can be electrically connected to the data writing units of multiple sub-pixels Spx in a third pixel group PU3. Each first gating driving circuit GA is configured to output a corresponding first scan signal Scan1 to the multiple sub-pixels Spx in a third pixel group PU3. For example, the m-th level first gating driving circuit is electrically connected to the data writing units of multiple sub-pixels Spx in the m-th third pixel group PU3. The m-th level first gating driving circuit outputs the m-th level first scan signal, where m ≥ 1. In some embodiments, the m-th third pixel group PU3 can be the m-th pixel row.

[0095] Optionally, to provide the required second scan signal Scan2 to the compensation unit, multiple gating drivers may include a second gating driver GM2. The second gating driver GM2 includes multiple cascaded second gating driving circuits GB. Each second gating driving circuit GB is electrically connected to the compensation unit of at least one sub-pixel Spx. Each second gating driving circuit GB is configured to output the corresponding second scan signal Scan2 to the corresponding sub-pixel Spx.

[0096] Optionally, to reduce the number of second gating drive circuits GB included in the second gating driver GM2, each second gating drive circuit GB can be electrically connected to the compensation unit of a plurality of sub-pixels Spx in at least one third pixel group PU3, and each second gating drive circuit GB is configured to output a corresponding second scan signal Scan2 to the plurality of sub-pixels Spx in the corresponding third pixel group PU3.

[0097] In some embodiments, each second gating drive circuit GB is electrically connected to the compensation units of multiple sub-pixels Spx in two adjacent third pixel groups PU3 along the second direction Dr2. For example, the s-th level second gating drive circuit is electrically connected to the compensation units of multiple sub-pixels Spx in the 2s-1th third pixel group, and the s-th level second gating drive circuit is electrically connected to the compensation units of multiple sub-pixels Spx in the 2s-th third pixel group. The s-th level second gating drive circuit is configured to output an s-th level second scan signal, where s ≥ 1.

[0098] Optionally, to provide the required third scan signal Scan3 to the first reset unit, multiple gating drivers may include a third gating driver GM3, the third gating driver GM3 including multiple cascaded third gating driver circuits GC, each third gating driver circuit GC being electrically connected to the first reset unit of at least one sub-pixel Spx, and each third gating driver circuit GC being configured to output the corresponding third scan signal Scan3 to the corresponding sub-pixel Spx.

[0099] Optionally, to reduce the number of third gating drive circuits GC included in the third gating driver GM3, each third gating drive circuit GC can be electrically connected to the first reset unit of a plurality of sub-pixels Spx in at least one third pixel group PU3, and each third gating drive circuit GC is configured to output a corresponding third scan signal Scan3 to the plurality of sub-pixels Spx of the corresponding third pixel group PU3.

[0100] In some embodiments, each third gating drive circuit GC is electrically connected to the first reset unit of a plurality of sub-pixels Spx in two adjacent third pixel groups PU3 along the second direction Dr2. For example, the u-th level third gating drive circuit is electrically connected to the first reset unit of a plurality of sub-pixels Spx in the (2u-1)th third pixel group, and the u-th level third gating drive circuit is electrically connected to the first reset unit of a plurality of sub-pixels Spx in the (2u)th third pixel group. The u-th level third gating drive circuit is configured to output a u-th level third scan signal, where u ≥ 1.

[0101] Optionally, to provide the required fourth scan signal Scan4 to the second reset unit, multiple gating drivers may include a fourth gating driver GM4. The fourth gating driver GM4 includes multiple cascaded fourth gating driving circuits GD. Each fourth gating driving circuit GD is electrically connected to the second reset unit of at least one sub-pixel Spx. Each fourth gating driving circuit GD is configured to output the corresponding fourth scan signal Scan4 to the corresponding sub-pixel Spx.

[0102] Optionally, to reduce the number of fourth gating drive circuits GD included in the fourth gating driver GM4, each fourth gating drive circuit GD can be electrically connected to the second reset unit of a plurality of sub-pixels Spx in at least one third pixel group PU3, and each fourth gating drive circuit GD is configured to output a corresponding fourth scan signal Scan4 to the plurality of sub-pixels Spx in the corresponding third pixel group PU3.

[0103] In some embodiments, each fourth gating drive circuit GD is electrically connected to the second reset unit of a plurality of sub-pixels Spx in two adjacent third pixel groups PU3 along the second direction Dr2. For example, the v-th level fourth gating drive circuit is electrically connected to the second reset unit of a plurality of sub-pixels Spx in the 2v-1th third pixel group, and the v-th level fourth gating drive circuit is electrically connected to the second reset unit of a plurality of sub-pixels Spx in the 2vth third pixel group. The v-th level fourth gating drive circuit is configured to output a v-th level fourth scan signal, where v ≥ 1.

[0104] In some embodiments, the second reset unit and the third reset unit in the same sub-pixel Spx are electrically connected to the same level fourth gating drive circuit so that the working states of the second reset transistor Tr2 and the third reset transistor Tr3 in the same sub-pixel Spx are synchronized, thereby reducing the control complexity of the sub-pixel Spx.

[0105] Optionally, to provide the required light emission control signal EM to the light emission control unit, multiple gating drivers may include a fifth gating driver GM5, the fifth gating driver GM5 including multiple cascaded fifth gating driver circuits GE, each fifth gating driver circuit GE being electrically connected to the light emission control unit of at least one sub-pixel Spx, and each fifth gating driver circuit GE being configured to output a corresponding light emission control signal EM to the corresponding multiple sub-pixels Spx.

[0106] Optionally, to reduce the number of fifth gating drive circuits GE included in the fifth gating driver GM5, each fifth gating drive circuit GE can be electrically connected to the light emission control unit of a plurality of sub-pixels Spx in at least one third pixel group PU3, and each fifth gating drive circuit GE is configured to output a corresponding light emission control signal EM to the plurality of sub-pixels Spx in the corresponding third pixel group PU3.

[0107] In some embodiments, each fifth gating drive circuit GE is electrically connected to the light-emitting control units of multiple sub-pixels Spx in two adjacent third pixel groups PU3 along the second direction Dr2. For example, the w-th level fifth gating drive circuit is electrically connected to the light-emitting control units of multiple sub-pixels Spx in the (2w-1)th third pixel group, and the w-th level fifth gating drive circuit is electrically connected to the light-emitting control units of multiple sub-pixels Spx in the (2w)th third pixel group. The w-th level fifth gating drive circuit is configured to output a w-th level light-emitting control signal, where w ≥ 1.

[0108] In some embodiments, two first gating drivers GM1 are disposed on opposite sides of the display area, a second gating driver GM2 and a third gating driver GM3 are disposed on opposite sides of the display area, and a fourth gating driver GM4 and a fifth gating driver GM5 are disposed on opposite sides of the display area, so as to reduce the impact of the gating drivers on the layout space of sub-pixels Spx in the display area of ​​the display panel.

[0109] Figures 5A-5C This is a timing diagram of the sub-pixel corresponding to an exemplary embodiment of this disclosure. For ease of understanding, the first transistor T1 to the fourth transistor T4, the driving transistor Tdr, the data transistor Tda, the first light-emitting control transistor Ts1, the second light-emitting control transistor Ts2, the second reset transistor Tr2, and the third reset transistor Tr3 are P-type transistors, and the compensation transistor Tc and the first reset transistor Tr1 are N-type transistors. Figure 2 , Figure 3 and Figures 5A-5C Taking the design as an example, this paper explains the design of using the first switch unit 101 to the fourth switch unit 104 to control the pixel PX to achieve the switching of multiple display modes, thereby enabling the display panel to have multiple display modes.

[0110] Among them, firstly Figure 3 This corresponds to a first sub-pixel Spx1. Figure 5A The first scan signal Scan1 to the fourth scan signal Scan4 and the light emission control signal EM shown are used as examples to illustrate the first sub-pixel Spx1.

[0111] Please continue reading. Figure 2 , Figure 3 and Figure 5A During the first time period t1, the first scan signal Scan1 and the light emission control signal EM corresponding to the first sub-pixel Spx1 are at a high level, while the second scan signal Scan2, the third scan signal Scan3, and the fourth scan signal Scan4 corresponding to the first sub-pixel Spx1 are at a low level. The first selection control signal SW1 and the fourth selection control signal SW4 are at a low level, while the second selection control signal SW2 and the third selection control signal SW3 are at a high level. The second reset transistor Tr2 and the third reset transistor Tr3 in the first sub-pixel Spx1 are turned on to reset the potential of the anode of the light-emitting device LE and the first source-drain terminal of the driving transistor Tdr. In the selection module 10 corresponding to the pixel PX, including the first sub-pixel Spx1, the first transistor T1 and the fourth transistor T4 are turned on.

[0112] During the second time period t2, the first scan signal Scan1 to the fourth scan signal Scan4 and the light emission control signal EM corresponding to the first sub-pixel Spx1 are at a high level. The first selection control signal SW1 and the fourth selection control signal SW4 are at a low level, and the second selection control signal SW2 and the third selection control signal SW3 are at a high level. The first reset transistor Tr1 and the compensation transistor Tc in the first sub-pixel Spx1 are turned on to reset the control terminal and the second source-drain terminal of the driving transistor Tdr. In the selection module 10 corresponding to the pixel PX of the first sub-pixel Spx1, the first transistor T1 and the fourth transistor T4 are turned on.

[0113] During the third time period t3, the first scan signal Scan1 and the third scan signal Scan3 corresponding to the first sub-pixel Spx1 are at a low level, while the second scan signal Scan2, the fourth scan signal Scan4, and the light emission control signal EM are at a high level. The first selection control signal SW1 and the fourth selection control signal SW4 are at a low level, while the second selection control signal SW2 and the third selection control signal SW3 are at a high level. In the selection module 10 corresponding to the pixel PX including the first sub-pixel Spx1, the first transistor T1 and the fourth transistor T4 are turned on. The data transistor Tda and the compensation transistor Tc in the first sub-pixel Spx1 are turned on to store the information of the data signal supplied by the first data source D1 to the control terminal of the driving transistor Tdr.

[0114] In the fourth time period t4, the first sub-pixel Spx1 has the same working state as in the first time period t1.

[0115] During the fifth time period t5, the first scan signal Scan1 and the fourth scan signal Scan4 corresponding to the first sub-pixel Spx1 are at a high level, while the second scan signal Scan2, the third scan signal Scan3, and the light emission control signal EM are at a low level. The first selection control signal SW1 and the fourth selection control signal SW4 are at a low level, while the second selection control signal SW2 and the third selection control signal SW3 are at a high level. In the selection module 10 corresponding to the pixel PX including the first sub-pixel Spx1, the first transistor T1 and the fourth transistor T4 are turned on. The first light emission control transistor Ts1 and the second light emission control transistor Ts2 in the first sub-pixel Spx1 are turned on, and the driving current generated by the driving transistor Tdr flows through the light-emitting device LE to drive the light-emitting device LE to emit light.

[0116] when Figure 3 When representing a fourth sub-pixel Spx4, Figure 5A The first scan signal Scan1 to the fourth scan signal Scan4 and the light emission control signal EM shown are signals applied to the fourth sub-pixel Spx4. The fourth sub-pixel Spx4 corresponds to... Figure 5A The working principle of the first time period t1 can be referenced to the working principle of the first sub-pixel Spx1 corresponding to the first time period t1, and the fourth sub-pixel Spx4 corresponding to... Figure 5A The working principle of the second time period t2 can be referenced to the working principle of the first sub-pixel Spx1 corresponding to the second time period t2, and the fourth sub-pixel Spx4 corresponding to... Figure 5A The working principle of the fourth time period t4 can be referred to the working principle of the first sub-pixel Spx1 corresponding to the fourth time period t4.

[0117] The fourth sub-pixel Spx4 corresponds to Figure 5ADuring the third time period t3, the first scan signal Scan1 and the third scan signal Scan3 corresponding to the third sub-pixel Spx3 are at a low level, while the second scan signal Scan2, the fourth scan signal Scan4, and the light emission control signal EM are at a high level. The first selection control signal SW1 and the fourth selection control signal SW4 are at a low level, while the second selection control signal SW2 and the third selection control signal SW3 are at a high level. In the selection module 10 corresponding to the pixel PX including the fourth sub-pixel Spx4, the first transistor T1 and the fourth transistor T4 are turned on. The data transistor Tda and the compensation transistor Tc in the fourth sub-pixel Spx4 are turned on to store the information of the first power signal supplied by the first power supply terminal VGH to the control terminal of the driving transistor Tdr.

[0118] The fourth sub-pixel Spx4 corresponds to Figure 5A During the fifth time period t5, the first scan signal Scan1 and the fourth scan signal Scan4 corresponding to the fourth sub-pixel Spx4 are at a high level, while the second scan signal Scan2, the third scan signal Scan3, and the light emission control signal EM are at a low level. The first selection control signal SW1 and the fourth selection control signal SW4 are at a low level, while the second selection control signal SW2 and the third selection control signal SW3 are at a high level. In the selection module 10 corresponding to the pixel PX including the fourth sub-pixel Spx4, the first transistor T1 and the fourth transistor T4 are turned on. The first light emission control transistor Ts1 and the second light emission control transistor Ts2 in the fourth sub-pixel Spx4 are turned on, and the driving current generated by the driving transistor Tdr flows through the light emission device LE to drive the light emission device LE to emit light, so that the fourth sub-pixel Spx4 displays a fixed grayscale.

[0119] when Figure 3 When representing a second sub-pixel Spx2, Figure 5A The first scan signal Scan1 to the fourth scan signal Scan4 and the light emission control signal EM shown are the signals applied to the second sub-pixel Spx2. When Figure 3 When representing a third sub-pixel Spx3, Figure 5A The first scan signal Scan1 to the fourth scan signal Scan4 and the light emission control signal EM shown are signals applied to the third sub-pixel Spx3. Since the second sub-pixel Spx2 is electrically connected to the corresponding second data source D2, and the third sub-pixel Spx3 is electrically connected to the corresponding third data source D3, therefore, the second sub-pixel Spx2 corresponds to... Figure 5A During the third time period t3, the data transistor Tda and compensation transistor Tc in the second sub-pixel Spx2 are turned on to store the information of the data signal supplied by the second data source D2 to the control terminal of the driving transistor Tdr. The third sub-pixel Spx3 corresponds to... Figure 5ADuring the third time period t3, the data transistor Tda and compensation transistor Tc in the third sub-pixel Spx3 are turned on to store the information of the data signal supplied by the third data source D3 to the control terminal of the driving transistor Tdr. The second sub-pixel Spx2 and the third sub-pixel Spx3 correspond to... Figure 5A The working principles of the first time period t1, the second time period t2, the fourth time period t4, and the fifth time period t5 can be referenced from the first sub-pixel Spx1. Figure 5A The working principles of the first time period t1, the second time period t2, the fourth time period t4, and the fifth time period t5 are similar, and will not be elaborated here.

[0120] Therefore, corresponding Figure 5A The design shown allows the first sub-pixel Spx1 to the third sub-pixel Spx3 to be displayed according to the corresponding data signal, and the fourth sub-pixel Spx4 to be displayed with a fixed grayscale.

[0121] Within at least one frame, the first sub-pixel Spx1 and the fourth sub-pixel Spx4 of each pixel PX each have Figure 5A During the working states shown in the first time period t1 to the fifth time period t5, the display panel implements the first display mode described above. Within at least one frame, the first sub-pixel Spx1 or the fourth sub-pixel Spx4 in any pixel PX is distinguished from... Figure 5A If the first time period t1 to the fifth time period t5 shown is used, then the display panel will have a display mode that is different from the first display mode for that frame.

[0122] Please continue reading. Figure 2 , Figure 3 and Figure 5B , Figure 3 When representing a first sub-pixel Spx1, Figure 5B The first scan signal Scan1 to the fourth scan signal Scan4 and the light emission control signal EM shown are the signals corresponding to the first sub-pixel Spx1. Similarly, we can also obtain... Figure 3 When corresponding to the second sub-pixel Spx2 to the fourth sub-pixel Spx4, Figure 5B The diagram shows the correspondence between each signal and the sub-pixel Spx.

[0123] The transistors in the first sub-pixel Spx1 to the fourth sub-pixel Spx4 correspond to Figure 5B The working status of the first time period t1 to the fifth time period t5 shown can be referred to Figure 5A The diagram shows the working status from the first time period t1 to the fifth time period t5. Corresponding to... Figure 5BDuring the first time period t1 to the fifth time period t5, the first selection control signal SW1 and the fourth selection control signal SW4 are at a high level, while the second selection control signal SW2 and the third selection control signal SW3 are at a low level. In the selection module 10 corresponding to pixel PX, including the first sub-pixel Spx1, the second transistor T2 and the third transistor T3 are turned on.

[0124] Corresponding to the first sub-pixel Spx1 Figure 5B During the third time period t3, as shown, the data transistor Tda and compensation transistor Tc in the first sub-pixel Spx1 are turned on to store the information of the first power signal supplied by the first power supply terminal VGH to the control terminal of the driving transistor Tdr. The first sub-pixel Spx1 corresponds to... Figure 5B During the fifth time period t5, the first sub-pixel Spx1 displays a fixed grayscale.

[0125] Corresponding to the fourth sub-pixel Spx4 Figure 5B During the third time period t3, as shown, the data transistor Tda and compensation transistor Tc in the fourth sub-pixel Spx4 are turned on to store the information of the data signal supplied by the first data source D1 to the control terminal of the driving transistor Tdr. The fourth sub-pixel Spx4 corresponds to... Figure 5B During the fifth time period t5, the driving transistor Tdr generates a driving current based on the corresponding data signal to drive the fourth sub-pixel Spx4 for display.

[0126] The second sub-pixel Spx2 corresponds to Figure 5B During the third time period t3, as shown, the data transistor Tda and compensation transistor Tc in the second sub-pixel Spx2 are turned on to store the information of the data signal supplied by the second data source D2 to the control terminal of the driving transistor Tdr. The second sub-pixel Spx2 corresponds to... Figure 5B During the fifth time period t5, the driving transistor Tdr generates a driving current based on the corresponding data signal to drive the second sub-pixel Spx2 for display.

[0127] Corresponding to the third sub-pixel Spx3 Figure 5B During the third time period t3, as shown, the data transistor Tda and compensation transistor Tc in the third sub-pixel Spx3 are turned on to store the information of the data signal supplied by the third data source D3 to the control terminal of the driving transistor Tdr. The third sub-pixel Spx3 corresponds to... Figure 5B During the fifth time period t5, the driving transistor Tdr generates a driving current based on the corresponding data signal to drive the third sub-pixel Spx3 for display.

[0128] Therefore, corresponding Figure 5BThe design shown allows the second sub-pixels Spx2 to the fourth sub-pixels Spx4 to be displayed according to the corresponding data signals, while the first sub-pixel Spx1 displays a fixed grayscale.

[0129] Within at least one frame, the first sub-pixel Spx1 and the fourth sub-pixel Spx4 of each pixel PX each have Figure 5B During the working states shown in the first time period t1 to the fifth time period t5, the display panel implements the second display mode described above. Within at least one frame, the first sub-pixel Spx1 or the fourth sub-pixel Spx4 in any pixel PX is distinguished from... Figure 5B If the first time period t1 to the fifth time period t5 is used, then the display panel will have a display mode that is different from the second display mode for the corresponding frame.

[0130] exist Figure 5B In the above, if each second sub-pixel Spx2 and each third sub-pixel Spx3 displays a fixed grayscale based on their respective data signals, then the corresponding... Figure 5B The design shown allows the first sub-pixels Spx1 to the third sub-pixels Spx3 to display a fixed grayscale, while the fourth sub-pixel Spx4 displays according to the corresponding data signal. Accordingly, the display panel implements the aforementioned third display mode.

[0131] Please continue reading. Figure 2 , Figure 3 and Figure 5C , Figure 3 When representing a first sub-pixel Spx1, Figure 5C The second scan signal Scan2 to the fourth scan signal Scan4 and the light emission control signal EM shown are signals applied to the first sub-pixel Spx1. The first scan signal Scan1 corresponding to the first sub-pixel Spx1 is the first sub-scan signal Scan11, and the first scan signal Scan1 corresponding to the fourth sub-pixel Spx4 is the second sub-scan signal Scan12. Similarly, we can also obtain... Figure 3 When corresponding to the second sub-pixel Spx2 to the fourth sub-pixel Spx4, Figure 5C The diagram shows the correspondence between the second scan signal Scan2 to the fourth scan signal Scan4 and the light emission control signal EM and the sub-pixel Spx. Specifically, the first scan signal Scan1 corresponding to the second sub-pixel Spx2 can be set with reference to either the first sub-scan signal Scan11 or the second sub-scan signal Scan12, and the first scan signal Scan1 corresponding to the third sub-pixel Spx3 can also be set with reference to either the first sub-scan signal Scan11 or the second sub-scan signal Scan12.

[0132] The transistors in the first sub-pixel Spx1 to the fourth sub-pixel Spx4 correspond to Figure 5C The working status of the first time period t1 to the fifth time period t5 shown can be referred to Figure 5A The diagram shows the working status from the first time period t1 to the fifth time period t5. Corresponding to... Figure 5C During the first time period t1 to the fifth time period t5, the third selection control signal SW3 and the fourth selection control signal SW4 are at a high level. The first selection control signal SW1 is at a high level during the third time period corresponding to the first sub-pixel Spx1 (i.e., Figure 5C The second selection control signal SW2 is at a low level during the third time period (i.e., the time period t31) corresponding to the fourth sub-pixel Spx4. Figure 5C During time period t32, the signal level is low. In the selection module 10 corresponding to pixel PX, including the first sub-pixel Spx1, the first transistor T1 is turned on when the corresponding electrically connected first sub-pixel Spx1 is in the corresponding third time period, so as to transmit the data signal provided by the first data source D1 to the control terminal of the driving transistor Tdr in the corresponding first sub-pixel Spx1. The second transistor T2 is turned on when the corresponding electrically connected fourth sub-pixel Spx4 is in the corresponding third time period, so as to transmit the data signal provided by the first data source D1 to the control terminal of the driving transistor Tdr in the corresponding fourth sub-pixel Spx4, thereby enabling both the first sub-pixel Spx1 and the fourth sub-pixel Spx4 to be displayed according to the corresponding data signal during the corresponding fifth time period t5.

[0133] Reference Figure 5A or Figure 5B The relevant explanations also provide the working principle of the second sub-pixel Spx2 and the third sub-pixel Spx3 when displayed with corresponding data signals or fixed gray levels, which will not be elaborated here.

[0134] Therefore, corresponding Figure 5C The design shown allows the first sub-pixel Spx1 to the fourth sub-pixel Spx4 to be displayed according to the corresponding data signals.

[0135] Within at least one frame, the first sub-pixel Spx1 and the fourth sub-pixel Spx4 of each pixel PX each have Figure 5C During the first time period t1 to the fifth time period t5, the display panel implements the aforementioned fourth display mode. Within at least one frame, the first sub-pixel Spx1 or the fourth sub-pixel Spx4 in any pixel PX is distinguished from... Figure 5C If the first time period t1 to the fifth time period t5 is used, then the display panel will have a display mode that is different from the fourth display mode for that frame.

[0136] It should be noted that by adjusting the duration of the first selection control signal SW1 remaining low during the third time period corresponding to the first sub-pixel Spx1, and by adjusting the duration of the second selection control signal SW2 remaining low during the third time period corresponding to the fourth sub-pixel Spx4, the first sub-pixel Spx1 and the fourth sub-pixel Spx4 can have the same or different brightness. The duration of the first selection control signal SW1 and the second selection control signal SW2 remaining low can be adjusted based on factors such as the luminous efficiency of the first sub-pixel Spx1 and the fourth sub-pixel Spx4.

[0137] Understandably, referring to Figures 5A-5C As can be seen from the relevant explanations, in the third time period corresponding to different first sub-pixels Spx1 and fourth sub-pixels Spx4, controlling the level of the corresponding first selection control signal SW1 to fourth selection control signal SW4 can realize the display control of the first sub-pixel Spx1 and the fourth sub-pixel Spx4, thereby obtaining more mode designs that are different from the first display mode to the fourth display mode, which will not be elaborated here.

[0138] It should be understood that, Figures 5A-5C Only with Figure 3 The pixel driving circuit design and selection module 10, which includes P-type transistors, will be used as an example for illustration. However, the above description is not intended to limit this application, and those skilled in the art can refer to it for further information. Figures 5A-5C The design corresponds to the design when the transistors in the selection module 10 are N-type transistors and the pixel driving circuit is configured in other ways. Furthermore, the design of the selection module 10 can be implemented in more complex or simpler ways, and is not limited to these methods. Figure 2 As shown, the selection module 10 only needs to be able to control the data signal received by the sub-pixel Spx and the signal used to display a fixed grayscale.

[0139] Optionally, the emission color of the fourth sub-pixel Spx4 may be different from or the same as the emission color of each of the first sub-pixels Spx1 to the third sub-pixels Spx3.

[0140] In some embodiments, the colorimetric parameters of the first sub-pixel Spx1 are different from those of the fourth sub-pixel Spx4. These colorimetric parameters include at least one of color point, emitted color, luminous efficiency, and wavelength, enabling the display panel to support designs such as a wider color gamut and higher display efficiency.

[0141] In some embodiments, the emission color of the first sub-pixel Spx1 is red, green, or blue, and the emission color of the first sub-pixel Spx1 is the same as the emission color of the fourth sub-pixel Spx4.

[0142] For example, the first sub-pixel Spx1 could emit a vermilion color, and the fourth sub-pixel Spx4 could emit an orange-red color. Alternatively, the first sub-pixel Spx1 could emit a dark red color, and the fourth sub-pixel Spx4 a light red color, and so on. Another example is that the first sub-pixel Spx1 could emit a blue color, and the fourth sub-pixel Spx4 a cyan color. Yet another example is that the first sub-pixel Spx1 could emit a dark blue color, and the fourth sub-pixel Spx4 a light blue color, and so on. Another example is that the first sub-pixel Spx1 could emit a grass green color, and the fourth sub-pixel Spx4 a dark green color. Yet another example is that the first sub-pixel Spx1 could emit a dark green color, and the fourth sub-pixel Spx4 a light green color, and so on.

[0143] In this application, controlling the fourth sub-pixel Spx4 to participate in the display can improve the display efficiency of the display panel and enable the display panel to be used in scenarios such as auxiliary therapy. As in the first display mode described above, the display panel can display the first sub-pixels Spx1 to the third sub-pixels Spx3. As in the second display mode described above, the fourth sub-pixel Spx4 can alleviate the display pressure on the first sub-pixel Spx1, which helps extend the lifespan of the first sub-pixel Spx1 and improves display efficiency. As in the third display mode described above, the display panel can be used for auxiliary therapy, etc. As in the fourth display mode described above, the display panel can support a wider color gamut display, etc.

[0144] In some embodiments, when the fourth sub-pixel Spx4 is controlled to display and emits blue light, the display of the fourth sub-pixel Spx4 can be used in adjunctive treatments such as improving skin inflammation and regulating sebum secretion.

[0145] In some embodiments, when the fourth sub-pixel Spx4 emits blue light, the light-emitting layer of the light-emitting device LE in the fourth sub-pixel Spx4 may include materials such as blue phosphorescence. In some embodiments, the wavelength of the light emitted by the fourth sub-pixel Spx4 may be 410 nm to 450 nm.

[0146] In some embodiments, when controlling the display of the fourth sub-pixel Spx4, the fourth sub-pixel Spx4 can emit infrared light, so that the display of the fourth sub-pixel Spx4 can be used in infrared light-assisted therapy. The light-emitting layer of the light-emitting device LE in the fourth sub-pixel Spx4 may include a light-emitting material that emits infrared light.

[0147] In some embodiments, when controlling the display of the fourth sub-pixel Spx4, the fourth sub-pixel Spx4 can emit green light, so that the display of the fourth sub-pixel Spx4 can be used in scenarios such as assisting treatment and relieving visual fatigue. The light-emitting layer of the light-emitting device LE in the fourth sub-pixel Spx4 may include a fluorescent material that emits green light.

[0148] In some embodiments, when the display panel is in a third display mode and each fourth sub-pixel Spx4 is used to display red light, the signals supplied by the display control module to the first data source D1 to the third data source D3 are signals used to control the display panel to display a pure red image. When the display panel is in the third display mode and each fourth sub-pixel Spx4 is used to display green light, the signals supplied by the display control module to the first data source D1 to the third data source D3 are signals used to control the display panel to display a pure green image. When the display panel is in the third display mode and each fourth sub-pixel Spx4 is used to display blue light, the signals supplied by the display control module to the first data source D1 to the third data source D3 are signals used to control the display panel to display a pure blue image. The display control module may include at least one of a graphics processor and a timing controller.

[0149] In some embodiments, the emission color of the second sub-pixel Spx2 can be one of red, green, and blue. The emission color of the third sub-pixel Spx3 can be one of red, green, and blue.

[0150] In some embodiments, the emission color of the second sub-pixel Spx2 is different from the emission color of the third sub-pixel Spx3.

[0151] Figure 6 This is a schematic diagram of the structure of a display device provided in an exemplary embodiment of this disclosure. This application also provides a display device including any of the above-described display panels.

[0152] In some embodiments, the display device further includes a source driver electrically connected to the display panel. The source driver includes a plurality of output terminals configured to transmit corresponding data signals to a plurality of sub-pixels Spx. Some of the output terminals serve as a first data source D1 and are electrically connected to a corresponding selection module 10 to provide the required data signals to the plurality of first sub-pixels Spx1 or the plurality of fourth sub-pixels Spx4 using the source driver.

[0153] In some embodiments, a portion of the output terminals serve as a second data source D2 to provide the required data signals to a plurality of second sub-pixels Spx2 using a source driver.

[0154] In some embodiments, a portion of the output terminals serve as a third data source D3 to provide the required data signals to a plurality of third sub-pixels Spx3 using a source driver.

[0155] In some embodiments, the display device may further include a timing controller electrically connected to a gating driver and a source driver. The timing controller is configured to output corresponding control signals to the gating driver and the source driver to control the gating driver to generate a scan signal or a light emission control signal EM, and to control the source driver to generate a data signal.

[0156] Optionally, the display panel may also include components not shown, such as a graphics processor and a power management chip.

[0157] Since the display device of this application includes any of the above-mentioned display panels, the display device has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0158] This application also provides an electronic device including any of the above-described display panels and a data generator, the data generator including multiple data sources configured to transmit corresponding data signals to multiple sub-pixels. In some embodiments, the data generator includes, but is not limited to, at least one of a source driver and a programmable logic controller.

[0159] Since the electronic device of this application includes any of the above-mentioned display panels, the electronic device has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0160] The above description is merely an optional embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A display panel, characterized in that, include: Multiple pixels, each pixel including multiple sub-pixels, each sub-pixel being configured to display according to a corresponding data signal, the multiple sub-pixels including a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel, the emission color of the first sub-pixel being different from the emission color of the second sub-pixel and the emission color of the third sub-pixel, the first sub-pixel and the fourth sub-pixel in the same pixel being electrically connected to a first data source; Multiple selection modules are provided, each electrically connected between a first data source and at least one first sub-pixel and a fourth sub-pixel of a pixel, and each selection module is electrically connected to a first power supply terminal. Each selection module is configured to control the signal transmission between at least one pixel and the first data source and the first power supply terminal, so as to control the first sub-pixel or the fourth sub-pixel of the corresponding pixel to receive the data signal supplied by the first data source, and to control the signal transmission between the first sub-pixel and the fourth sub-pixel of the corresponding pixel and the first power supply terminal; wherein, the first power signal supplied by the first power supply terminal is used to control at least one of the first sub-pixel and the fourth sub-pixel to display a fixed grayscale.

2. The display panel according to claim 1, characterized in that, The display panel includes a plurality of first pixel groups and a plurality of second pixel groups, the first pixel groups and the second pixel groups are arranged alternately along a first direction, each first pixel group includes a first sub-pixel and a fourth sub-pixel arranged alternately along a second direction, and each second pixel group includes a second sub-pixel and a third sub-pixel arranged alternately along a second direction. Wherein, the first direction and the second direction intersect, and multiple first sub-pixels and multiple fourth sub-pixels of the same first pixel group are electrically connected to a selection module.

3. The display panel according to claim 2, characterized in that, The display panel includes: Multiple first data lines, each first data line being electrically connected between a selection module and multiple first sub-pixels of a first pixel group; Multiple second data lines, each second data line being electrically connected between a selection module and multiple fourth sub-pixels of a first pixel group; Multiple third data lines, each of which is electrically connected between a second data source and multiple second sub-pixels of a second pixel group, wherein the second data source is configured to transmit the data signal to the corresponding second sub-pixel; and Multiple fourth data lines, each of which is electrically connected between a third data source and multiple third sub-pixels of a second pixel group, wherein the third data source is configured to transmit the data signal to the corresponding third sub-pixel.

4. The display panel according to claim 3, characterized in that, Each of the selection modules includes: The first switching unit is electrically connected between the corresponding first data source and a first data line, and is configured to control the signal transmission between the first data source and the corresponding first data line according to the first selection control signal. The second switching unit is electrically connected between the corresponding first data source and a second data line, and is configured to control the signal transmission between the first data source and the corresponding second data line according to the second selection control signal. A third switching unit, electrically connected between a corresponding first power supply terminal and a first data line, is configured to control signal transmission between the first power supply terminal and the corresponding first data line according to a third selection control signal; and The fourth switching unit is electrically connected between the corresponding first power supply terminal and a second data line, and is configured to control the signal transmission between the first power supply terminal and the corresponding second data line according to the fourth selection control signal.

5. The display panel according to claim 4, characterized in that, When the display panel is in the first display mode, each of the first switch units connects the current path between the first data source and the corresponding first data line, each of the fourth switch units connects the current path between the first power supply terminal and the corresponding second data line, and each of the second sub-pixels and each of the third sub-pixels are displayed according to the corresponding data signals. When the display panel is in the second display mode, each second switch unit connects a current path between a first data source and the corresponding second data line, each third switch unit connects a current path between the first power supply terminal and the corresponding first data line, and each second sub-pixel and each third sub-pixel are displayed according to the corresponding data signal. When the display panel is in the third display mode, each second switch unit connects the current path between the first data source and the corresponding second data line, each third switch unit connects the current path between the first power supply terminal and the corresponding first data line, and each second sub-pixel and each third sub-pixel display 0 grayscale. When the display panel is in the fourth display mode, each selection module alternately connects a first data source to the current path between the corresponding first data line and the second data line, and each second sub-pixel and each third sub-pixel are displayed according to the corresponding data signal.

6. The display panel according to claim 5, characterized in that, When the display panel is in the first display mode, the fixed gray level displayed by the fourth sub-pixel according to the first power signal is 0 gray level; When the display panel is in the second display mode and the third display mode, the fixed gray level displayed by the first sub-pixel according to the first power signal is 0 gray level.

7. The display panel according to claim 4, characterized in that, Multiple first switch units share the same first selection control signal, multiple second switch units share the same second selection control signal, multiple third switch units share the same third selection control signal, and multiple fourth switch units share the same fourth selection control signal.

8. The display panel according to any one of claims 1 to 7, characterized in that, The light color characteristic parameters of the first sub-pixel are different from those of the fourth sub-pixel; wherein, the light color characteristic parameters include at least one of color point, emission color, luminous efficiency and wavelength.

9. The display panel according to claim 8, characterized in that, The first sub-pixel emits light in red, green, or blue, and the light emission color of the first sub-pixel is the same as that of the fourth sub-pixel.

10. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 9; as well as A source driver, electrically connected to the display panel, includes multiple output terminals, which are configured to transmit corresponding data signals to multiple sub-pixels; Among them, some of the output terminals serve as the first data source and are electrically connected to the corresponding selection module.

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