Display panel and display device

Abstract

This invention discloses a display panel and a display device. The display panel includes a driving circuit; the driving circuit includes N-stage shift registers cascaded together; in the same shift register: a first node control module is used to receive an input signal and a first clock signal to control the signal of the first node; a second node control module is used to receive a first level signal and a first clock signal to control the signal of the second node; a first output module is used to receive the signal of the first node and a second clock signal to control the gate driving signal; in the second output module, the gates of the first output transistor and the second output transistor are both electrically connected to the second node, the first output transistor receives the second level signal and is electrically connected to the first terminal of the second output transistor to a third node, and the second terminal of the second output transistor outputs a gate control signal; an output voltage regulator module is used to transmit the regulated signal to the third node under the control of the first control signal, which can significantly improve the display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In current display panel designs, GOA (Gate Driver on Array) technology has become mainstream to achieve narrow bezels and low costs. With the maturity of oxide thin-film transistor (Oxide TFT) technology, some display panels now use a full oxide design, where both the pixel circuits and the peripheral GOA driving circuits are made of oxide TFTs to reduce costs and achieve lower leakage current and better image sticking performance.

[0003] However, the threshold voltage of oxide thin-film transistors (TFTs) has a very small allowable fluctuation range. When the threshold voltage is negatively biased, the off-state leakage current increases significantly. Excessive off-state leakage current of key transistors in the GOA drive circuit can lead to abnormal effective pulse output of the gate drive signal, preventing the gate drive signal from being transmitted normally step by step and affecting the display effect. Summary of the Invention

[0004] This invention provides a display panel and display device to solve the problem of abnormal gate drive signal output caused by leakage current, which can effectively improve the display effect.

[0005] According to one aspect of the present invention, a display panel is provided, comprising: a driving circuit; The driving circuit includes N cascaded shift registers; the shift registers include: a first node control module, a second node control module, a first output module, a second output module, and an output voltage regulator module; In the same shift register: The first node control module is used to receive input signals and a first clock signal, and to control the signals of the first node; The second node control module is used to receive the first level signal and the first clock signal, and to control the signals of the second node; The first output module is used to receive the signal from the first node and the second clock signal, and to control the gate drive signal; The second output module is used to receive the signal from the second node and the second level signal, and control the gate drive signal; the second output module includes a first output transistor and a second output transistor, the gates of the first output transistor and the second output transistor are electrically connected to the second node, the first terminal of the first output transistor receives the second level signal, the second terminal of the first output transistor is electrically connected to the first terminal of the second output transistor and the third node, and the second terminal of the second output transistor outputs the gate control signal; The output voltage regulator module is electrically connected to the third node, and the output voltage regulator module receives a first control signal and a voltage regulator signal; the output voltage regulator module is used to transmit the voltage regulator signal to the third node under the control of the first control signal; Wherein, the gate drive signal of the shift register of the i-th stage is the input signal of the shift register of the j-th stage; i, j and N are all positive integers, i ≠ j and i and j are both less than or equal to N.

[0006] According to one aspect of the present invention, a display device is provided, characterized in that it includes: the display panel described above.

[0007] The display panel provided in this embodiment of the invention includes a first node control module to control the signal of the first node according to the input signal and the first clock signal, a second control module to control the signal of the second node according to the first level signal and the first clock signal, a first output module to control the gate drive signal according to the signal of the first node and the second clock signal, and a second output module to control the gate drive signal according to the signal of the second node and the second level signal. The second output module includes a first output transistor and a second output transistor connected in series, so that the first output transistor and the second output transistor are synchronously turned on or off under the control of the second node, thereby controlling the signal transmission path of the second level signal to the scan output terminal through the third node. On this basis, an output voltage regulator module is electrically connected to the third node. When the second node is at an enabled level, the output voltage regulator module controls the third node to keep consistent with the voltage regulator signal according to the first control signal. This can effectively suppress the off-state leakage current of the second output transistor, ensure the stability and accuracy of the effective pulse output of the gate drive signal, and thus ensure the normal step-by-step transmission of the gate drive signal, thereby improving display uniformity and significantly improving the display effect of the display panel.

[0008] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a shift register provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. Figure 11 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. Figure 14 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. Figure 15 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 17 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 18 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 19 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 20 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 21 This is a timing diagram of a shift register driver provided in an embodiment of the present invention; Figure 22 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0011] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0012] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0013] As described in the background section, display panels using an all-oxide thin-film transistor (TFT) design have a simpler manufacturing process, reducing the number of photomasks and lowering costs, while also achieving lower leakage current and better image sticking performance. However, TFTs have a very small threshold voltage fluctuation range, resulting in relatively low interference resistance and stability. Especially in high-temperature and high-brightness applications, they are prone to characteristic shifts after prolonged operation, leading to a significant increase in off-state leakage current. Excessive off-state leakage current in key transistors of the GOA (Gate Actuation Optimizer) drive circuit can cause abnormal effective pulse output of the gate drive signal, preventing the gate drive signal from being transmitted normally step by step. This ultimately results in problems such as horizontal stripes, bright lines, or display disorder on the screen, severely affecting the display effect.

[0014] To address the aforementioned technical problems, embodiments of the present invention provide a display panel, comprising: a driving circuit; the driving circuit includes N cascaded shift registers; the shift registers include: a first node control module, a second node control module, a first output module, a second output module, and an output voltage regulator module; within the same shift register: the first node control module receives an input signal and a first clock signal to control the signal of the first node; the second node control module receives a first level signal and a first clock signal to control the signal of the second node; the first output module receives the signal of the first node and a second clock signal to control the gate drive signal; the second output module receives the signal of the second node and a second level signal to control the gate drive signal. The second output module includes a first output transistor and a second output transistor. The gates of both the first and second output transistors are electrically connected to the second node. The first terminal of the first output transistor receives a second level signal. The second terminal of the first output transistor and the first terminal of the second output transistor are electrically connected to the third node. The second terminal of the second output transistor outputs a gate control signal. The output voltage regulator module is electrically connected to the third node and receives a first control signal and a regulated signal. The output voltage regulator module is used to transmit the regulated signal to the third node under the control of the first control signal. The gate drive signal of the i-th stage shift register is the input signal of the j-th stage shift register. i, j, and N are all positive integers, i ≠ j, and i and j are both less than or equal to N.

[0015] By adopting the above technical solution, a first node control module is set to control the signal of the first node according to the input signal and the first clock signal; a second control module is set to control the signal of the second node according to the first level signal and the first clock signal; a first output module is set to control the gate drive signal according to the signal of the first node and the second clock signal; a second output module is set to control the gate drive signal according to the signal of the second node and the second level signal; the second output module includes a first output transistor and a second output transistor connected in series, so that the first output transistor and the second output transistor are synchronously turned on or off under the control of the second node, thereby controlling the signal transmission path of the second level signal to the scanning output terminal through the third node. On this basis, an output voltage regulator module is set to be electrically connected to the third node. When the second node is at an enabled level, the output voltage regulator module controls the third node to be consistent with the voltage regulator signal according to the first control signal. This can effectively suppress the off-state leakage current of the second output transistor, ensure the stability and accuracy of the effective pulse output of the gate drive signal, and thus ensure the normal step-by-step transmission of the gate drive signal, thereby improving the display uniformity and significantly improving the display effect of the display panel.

[0016] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0017] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a shift register provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 1 and Figure 2The display panel 10 includes a driving circuit 100; the driving circuit 10 includes N cascaded shift registers G (G1, G2, ..., Gi, ..., Gj, ..., Gn-1, Gn); the shift register G includes: a first node control module 101, a second node control module 102, a first output module 103, a second output module 104, and an output voltage regulator module 105; in the same shift register G: the first node control module 101 is used to receive the input signal Vin and the first clock signal ck1, and control the signal of the first node N1; the second node control module 102 is used to receive the first level signal Vgh and the first clock signal ck1, and control the signal of the second node N2; the first output module 103 is used to receive the signal of the first node N1 and the second clock signal ck2, and control the gate drive signal Gout; the second output module 104 is used to receive the signal of the second node N2 and the second level signal Vgl, and control the gate drive signal Gout. Gout; The second output module 104 includes a first output transistor M1 and a second output transistor M2. The gates of the first output transistor M1 and the second output transistor M2 are electrically connected to the second node N2. The first terminal of the first output transistor M1 receives a second level signal Vgl. The second terminal of the first output transistor M1 and the first terminal of the second output transistor M2 are electrically connected to the third node N3. The second terminal of the second output transistor M2 outputs a gate control signal Gout; The output voltage regulator module 105 is electrically connected to the third node N3, and the output voltage regulator module 105 receives a first control signal Vct and a regulated signal Vm; The output voltage regulator module 105 is used to transmit the regulated signal Vm to the third node N3 under the control of the first control signal Vct; Wherein, the gate drive signal Gout of the i-th stage shift register Gi is the input signal Vin of the j-th stage shift register Gj; i, j and N are all positive integers, i ≠ j and i and j are both less than or equal to N.

[0018] For example, the display panel 100 may also include an array of pixel circuits 20 to display images under the line-by-line driving of the driving circuit 10. The driving circuit 10 may be located in the non-display area A1 of the display panel 100, and the pixel circuits 20 may be located in the display area A2. This allows the display area A2 to have a higher pixel density, which is beneficial to improving the display effect.

[0019] Continue to refer to Figure 1 and Figure 2The scan output terminal GOUT of the i-th stage shift register Gi, which outputs the gate drive signal Gout, can be electrically connected to the signal input terminal VIN of the y-th stage shift register Gj. This allows the gate drive signal Gout of the i-th stage shift register Gi to be the input signal Vin of the j-th stage shift register Gj. The i-th stage shift register Gi and the j-th stage shift register Gj can be two adjacent shift registers, in which case j can be equal to i+1. Alternatively, the i-th stage shift register Gi and the j-th stage shift register Gj can also be two non-adjacent shift registers, in which case ji can be a positive integer greater than or equal to 2. Under the premise of achieving the core inventive points of this embodiment, the values ​​of i and j are not specifically limited in this embodiment.

[0020] For ease of description, unless otherwise specified, the embodiments of the present invention will use the i-th level shift register Gi and the j-th level shift register Gj as two adjacent shift registers as examples to illustrate the technical solutions of the embodiments of the present invention.

[0021] Continue to refer to Figure 1 and Figure 2In the same shift register G, the first node control module 101 and the first output module 103 are electrically connected to the first node N1. The first node control module 101 is electrically connected to the signal input terminal VIN to receive the input signal Vin, and to the first clock terminal CK1 to receive the first clock signal ck1. For the first-stage shift register G1, its signal input terminal VIN can be electrically connected to the start signal terminal STV, so that its input signal Vin can be the start signal Stv provided by the start signal terminal STV, so that the first-stage shift register G1 can at least respond to the start signal Stv and the first clock signal ck1 to provide corresponding signals to the first node N1. For other shift registers G besides the first-stage shift register G1, their signal input terminal VIN can be electrically connected to the scan output terminal GOUT of the previous stage shift register G, so that its input signal Vin is the gate drive signal Gout output by the previous stage shift register G, so that each stage shift register G can at least respond to the gate drive signal Gout of the previous stage shift register G and the first clock signal ck1 to provide corresponding signals to the first node N1. In an exemplary embodiment, the first node control module 101, under the control of the first clock signal ck1, controls the signal transmission path between the signal input terminal VIN and the first node N1. When the first clock signal ck1 is at an enable level, the first node control module 101 controls the signal transmission path between the signal input terminal VIN and the first node N1 to be open, and the input signal Vin can be transmitted to the first node N1 through the first node control module 101, so that the signal of the first node N1 is the same as the input signal Vin. When the first clock signal ck1 is at a de-enabled level, the first node control module 101 controls the signal transmission path between the signal input terminal VIN and the first node N1 to be closed, and the input signal Vin cannot be transmitted to the first node N1, so that the input signal Vin of the signal input terminal VIN will not affect the potential of the first node N1.

[0022] The second node control module 102 and the second output module 104 are electrically connected to the second node N2. The second node control module 102 is also electrically connected to the first clock terminal CK1 and the first level terminal VGH, respectively, to receive the first clock signal ck1 provided by the first clock terminal CK1 and the first level signal Vgh provided by the first level terminal VGH, and can provide corresponding signals to the second node N2 in response to the first clock signal ck1 and the first level signal Vgh. In an exemplary embodiment, the second node control module 102, under the control of the first clock signal ck1, controls the signal transmission path between the first level terminal VGH and the second node N2. When the first clock signal ck1 is at an enabled level, the second node control module 102 controls the signal transmission path between the first level terminal VGH and the second node N2 to be open, and the first level signal Vgh can be transmitted to the second node N2 through the second node control module 102, so that the signal of the second node N2 is the same as the first level signal Vgh. When the first clock signal ck1 is at an disabled level, the second node control module 102 controls the signal transmission path between the first level terminal VGH and the second node N2 to be closed, and the first level signal Vgh cannot be transmitted to the second node N2, so that the first level signal Vgh of the first level terminal VGH will not affect the potential of the first node N1.

[0023] The first output module 103 is electrically connected to the first node N1, the second clock terminal CK2, and the scan output terminal GOUT, respectively, to receive the signal from the first node N1 and the second clock signal ck2 provided by the second clock terminal CK2, and can control the gate drive signal Gout of the scan output terminal GOUT in response to the signal from the first node N1 and the second clock signal ck2. In an exemplary embodiment, the first output module 103, under the potential control of the first node N1, controls the signal transmission path between the second clock terminal CK2 and the scan output terminal GOUT. When the signal of the first node N1 is at the enable level, the first output module 103 controls the signal transmission path between the second clock terminal CK2 and the scan output terminal GOUT to be turned on, and the second clock signal ck2 can be transmitted to the scan output terminal GOUT through the first output module 103, so that the gate drive signal Gout is the same as the second clock signal ck2. When the signal of the first node N1 is at the disable level, the first output module 103 controls the signal transmission path between the second clock terminal CK2 and the scan output terminal GOUT to be turned off, and the second clock signal ck2 cannot be transmitted to the scan output terminal GOUT. Therefore, the second clock signal ck2 of the second clock terminal CK2 will not affect the gate drive signal Gout output by the scan output terminal GOUT.

[0024] The second output module 104 is electrically connected to the second node N2, the second level terminal VGL, and the scan output terminal GOUT, respectively, to receive the signal from the second node N2 and the second level signal Vgl provided by the second level terminal VGL, and to control the gate drive signal Gout of the scan output terminal GOUT in response to the signal from the second node N2 and the second level signal Vgl. In an exemplary embodiment, the second output module 104, under the potential control of the second node N2, controls the signal transmission path between the second level terminal VGL and the scan output terminal GOUT. When the signal of the second node N2 is at the enable level, the second output module 104 controls the signal transmission path between the second level terminal VGL and the scan output terminal GOUT to be turned on, and the second level signal Vgl can be transmitted to the scan output terminal GOUT through the second output module 104, so that the gate drive signal Gout is the same as the second level signal Vgl. When the signal of the second node N2 is at the disable level, the second output module 104 controls the signal transmission path between the second level terminal VGL and the scan output terminal GOUT to be turned off, and the second level signal Vgl cannot be transmitted to the scan output terminal GOUT. Therefore, the second level signal Vgl of the second level terminal VGL will not affect the gate drive signal Gout output by the scan output terminal GOUT.

[0025] The second output module 104 includes a first output transistor M1 and a second output transistor M2. The first output transistor M1 and the second output transistor M2 are connected in series between the second level terminal VGL and the scan output terminal GOUT. The gates of both the first output transistor M1 and the second output transistor M2 are electrically connected to the second node N2, allowing the first output transistor M1 and the second output transistor M2 to be synchronously turned on or off under the control of the second node N2. When the signal at the second node N2 is at an enable level, the first output transistor M1 and the second output transistor M2 are synchronously turned on, allowing the second level signal Vgl provided by the second level terminal VGL to be transmitted sequentially through the first output transistor M1 and the second output transistor M2 to the scan output terminal GOUT, making the gate drive signal Gout the second level signal Vgl. When the signal at the second node N2 is at a de-enabled level, the first output transistor M1 and the second output transistor M2 are synchronously turned off, preventing the second level signal Vgl from being transmitted to the scan output terminal GOUT. By connecting the first output transistor M1 and the second output transistor M2 in series between the second level terminal VGL and the scan output terminal GOUT, the equivalent off-state resistance between the second level terminal VGL and the scan output terminal GOUT is equal to the sum of the off-state resistances of the first output transistor M1 and the second output transistor M2. This significantly reduces the overall conduction capability of the leakage current path. Even if the threshold voltage of one transistor drifts, leading to an increase in off-state leakage current, the other transistor can still effectively block the leakage current path, forming dual protection. In addition, the series structure can also share voltage stress, preventing a single transistor from bearing a large source-drain voltage difference, which is beneficial for suppressing threshold drift and improving device reliability.

[0026] The gate drive signal Gout is provided to the pixel circuit 20 in the display area A2 through the scan signal line. When the gate drive signal Gout is enabled, it can control the corresponding transistor in the pixel circuit 20 to turn on, and when the gate drive signal Gout is disabled, it can control the corresponding transistor in the pixel circuit 20 to turn off, so that the pixel circuit 20 can drive the light-emitting element to emit light at least in response to the gate drive signal Gout.

[0027] It is understood that when the transistor electrically connected to the scan output terminal of the shift register G is an NMOS transistor, the enable level of the gate drive signal Gout is a high voltage signal, and the disable level of the gate drive signal Gout is a low voltage signal. Conversely, when the transistor electrically connected to the scan output terminal of the shift register G is a PMOS transistor, the enable level of the gate drive signal Gout is a low voltage, and the disable level of the gate drive signal Gout is a high voltage. This embodiment of the invention does not specifically limit this. Accordingly, the enable levels of each signal mentioned in this embodiment of the invention can be signals capable of controlling the conduction of modules or transistors electrically connected to that signal, while the disable levels of each signal are signals controlling the conduction and deactivation of modules or transistors electrically connected to that signal. These will not be elaborated further below.

[0028] It is understandable that both the first clock signal ck1 and the second clock signal ck2 can be pulse signals, allowing both to include high and low levels. The pulse frequencies of the first clock signal ck1 and the second clock signal ck2 can be the same. In this case, the phases of the first clock signal ck1 and the second clock signal ck2 are different; that is, when the first clock signal ck1 is enabled, the second clock signal ck2 is disabled; conversely, when the second clock signal ck2 is enabled, the first clock signal ck1 is disabled. The input signal Vin is the gate drive signal Gout of the previous stage shift register unit G, allowing Vin to also include high and low levels. The first level signal Vgh and the second level signal Vgl are both fixed voltage signals, one being a high-level signal and the other a low-level signal. For example, the first level signal Vgh can be a high-level signal, and the second level signal Vgl can be a low-level signal.

[0029] Since the display panel of the present invention adopts the design of all-oxide thin film transistors, all transistors in the driving circuit and pixel circuit of the present invention are NMOS. Therefore, in the present invention, the enable level of each module in the shift register and pixel circuit is high level, and the disable level is low level.

[0030] During one working cycle of the shift register G, its second node N2 remains enabled for an extended period after the output module 106 outputs an enable level. This ensures that within a display frame, the second output module 104 can maintain the gate drive signal Gout at a disabled level after outputting the enable level. Consequently, the first output transistor M1 and the second output transistor M2 remain in a conducting state for an extended period, ensuring that the gate drive signal Gout is consistent with the second level signal Vgl. However, the fact that the first output transistor M1 and the second output transistor M2 are in the on state for a long time causes their threshold voltages to shift. This shift is particularly severe under high temperature and high brightness operating conditions. As a result, when the second node N2 jumps to the disabled level in the next display frame, the first output transistor M1 and the second output transistor M2 cannot be properly turned off. In other words, the leakage current of the first output transistor M1 and the second output transistor M2 in the off state will increase significantly. This causes the gate drive signal Gout at the scan output terminal GOUT to discharge sequentially through the second output transistor M2 and the first output transistor M1 to the second level terminal VGL when outputting a high-level signal (i.e., the enabled level). This results in abnormal effective pulse output of the gate drive signal Gout, preventing the gate drive signal Gout from being transmitted normally step by step. Ultimately, this causes problems such as horizontal stripes, bright lines, or display disorder in the display image, seriously affecting the display effect.

[0031] Based on the aforementioned technical issues, the output voltage regulator module 105 is electrically connected to the third node N3. The third node N3 is the connection node between the first output transistor M1 and the second output transistor M2, i.e., the intermediate node between the second level terminal VGL and the scan output terminal GOUT. The output voltage regulator module 105 is also electrically connected to the first control terminal VCT and the regulated signal terminal VM, so as to receive the first control signal Vct provided by the first control terminal VCT and the regulated signal Vm provided by the regulated signal terminal VM, respectively. It can control the signal transmission path between the regulated signal terminal VM and the third node N3 in response to the first control signal Vct. When the first control signal Vct is enabled, the output voltage regulator module 105 controls the signal transmission path between the regulated signal terminal VM and the third node N3 to be open, and the regulated signal Vm provided by the regulated signal terminal VM can be transmitted to the third node N3 through the output voltage regulator module 105. When the first control signal Vct is disabled, the output voltage regulator module 105 controls the signal transmission path between the regulated signal terminal VM and the third node N3 to be closed, and the regulated signal Vm provided by the regulated signal terminal VM cannot be transmitted to the third node N3. Thus, the potential of the third node N3 can be controlled by the output voltage regulator module 105. Therefore, when the second node N2 is disabled, the first control signal Vct can be set to enabled, and the output voltage regulator module 105 can be turned on to transmit the regulated signal Vm to the third node N3, so that the signal of the third node N3 is consistent with the regulated signal Vm. The regulated signal Vm can be set according to the channel type of the transistor. According to the design of the all-oxide transistor of the present invention, the regulated signal Vm is a voltage signal greater than 0V.

[0032] In this configuration, the first terminal of both the first output transistor M1 and the second output transistor M2 can be the source, and the second terminal can be the drain. The source of the second output transistor M2 is electrically connected to the third node N3. After the regulated voltage signal Vm is transmitted to the third node N3, the potential of the third node N3 can be clamped to match the regulated voltage signal Vm, making the gate-source voltage Vgs of the second output transistor M2 less than its threshold voltage Vth. Therefore, even if the threshold voltage of the second output transistor M2 is negatively offset, it can still be completely turned off, effectively suppressing the leakage current from the scan output terminal GOUT to the second level terminal VGL.

[0033] For example, when the gate drive signal Gout is at the enable level, the first control signal Vct is at the enable level, and the regulated signal Vm has the opposite polarity to the signal of the second node N2.

[0034] Specifically, when the gate drive signal Gout is enabled, setting the first control signal Vct to enabled can control the output voltage regulator module 105 to be turned on, so that the regulated signal Vm can be transmitted to the third node N3 through the output voltage regulator module 105. When the gate drive signal Gout is enabled, the signal of the second node N2 is disabled (i.e., low level). The voltage regulation signal Vm is set to have the opposite polarity to the signal of the second node N2, making Vm a high-level signal. This reduces the potential difference between the second node N2 and the third node N3, meaning the gate-source voltage Vgs of the second output transistor M2 decreases and becomes much smaller than the threshold voltage Vth of the second output transistor M2. Therefore, even with a negative shift in the threshold voltage of the second output transistor M2, it can be completely turned off. This effectively suppresses the leakage current from the scan output terminal GOUT to the second level terminal VGL, ensuring the stability and accuracy of the effective pulse output by the gate drive signal Gout. This allows the gate drive signal Gout to be transmitted normally step-by-step, driving each row of pixel circuits 20 to display the image correctly, effectively improving the display effect.

[0035] The display panel provided in this embodiment of the invention includes a first node control module to control the signal of the first node according to the input signal and the first clock signal, a second control module to control the signal of the second node according to the first level signal and the first clock signal, a first output module to control the gate drive signal according to the signal of the first node and the second clock signal, and a second output module to control the gate drive signal according to the signal of the second node and the second level signal. The second output module includes a first output transistor and a second output transistor connected in series, so that the first output transistor and the second output transistor are synchronously turned on or off under the control of the second node, thereby controlling the signal transmission path of the second level signal to the scan output terminal through the third node. On this basis, an output voltage regulator module is electrically connected to the third node. When the second node is at an enabled level, the output voltage regulator module controls the third node to keep consistent with the voltage regulator signal according to the first control signal. This can effectively suppress the off-state leakage current of the second output transistor, ensure the stability and accuracy of the effective pulse output of the gate drive signal, and thus ensure the normal step-by-step transmission of the gate drive signal, thereby improving display uniformity and significantly improving the display effect of the display panel.

[0036] Optional, Figure 3 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, as shown below. Figure 3As shown, the output voltage regulator module 105 includes an output voltage regulator transistor M3; the first terminal of the output voltage regulator transistor M3 receives a voltage regulation signal Vm, the gate of the output voltage regulator transistor M3 receives a first control signal Vct, and the second terminal of the output voltage regulator transistor M3 is electrically connected to the third node N3.

[0037] Specifically, the first terminal of the output Zener transistor M3 can be electrically connected to the regulated signal VM to receive the regulated signal Vm, the gate of the output Zener transistor M3 can be electrically connected to the first control terminal VCT to receive the first control signal Vct, and the second terminal of the output Zener transistor M3 can be electrically connected to the third node N3. The output Zener transistor M3 can then be turned on or off under the control of the first control signal Vct. When the first control signal Vct is enabled, the output Zener transistor M3 is turned on, allowing the regulated signal Vm to be transmitted from its first terminal to its second terminal, thus transmitting the regulated signal Vm to the third node N3. When the first control signal Vct is disabled, the output Zener transistor M3 is turned off, preventing the regulated signal Vm from being transmitted to the third node N3. One of the first and second terminals of the output Zener transistor M3 is the source, and the other is the drain; for example, the first terminal of the output Zener transistor M3 can be set to be the source, and the second terminal to be the drain. Furthermore, based on the design of the all-oxide thin-film transistor for the display panel, the output voltage regulator transistor M3 can be an oxide thin-film transistor, so its enable level is high and its disable level is low.

[0038] For example, refer to Figure 3The first output module 103 includes a third output transistor M4. The gate of the third output transistor M4 is electrically connected to the first node N1, the first electrode of the third output transistor M4 is electrically connected to the second clock terminal CK2 to receive the second clock signal ck2, and the second electrode of the third output transistor M4 is electrically connected to the scan output terminal GOUT. The third output transistor M4 can be turned on or off under the control of the first node N1. When the signal of the first node N1 is at an enable level, the third output transistor M4 is turned on, and the second clock signal ck2 of the second clock terminal CK2 can be transmitted to the scan output terminal GOUT through the third output transistor M4, so that the second clock signal ck2 is output to the pixel circuit 20 as the gate drive signal Gout. When the signal of the first node N1 is at an enable level, the third output transistor M4 is turned off, and the second clock signal ck2 of the second clock terminal CK2 cannot be transmitted to the scan output terminal GOUT, so the transition of the second clock signal ck2 will not affect the gate drive signal Gout. In this design, one of the first and second terminals of the third output transistor M4 is the source, and the other is the drain. Based on the design of the all-oxide thin-film transistor of this invention, the third output transistor M4 is an oxide thin-film transistor with a high enable level and a low disable level.

[0039] For example, Figure 4 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 4 As shown, the shift register G may also include a first capacitor C1 and a second capacitor C2. The first capacitor C1 is electrically connected between the gate and the second terminal of the third output transistor M4. When the gate potential of the third output transistor M4 and the second clock signal ck2 are both high, the bootstrap effect of the first capacitor C1 can pull the gate potential of the third output transistor M4 high, ensuring that the third output transistor M4 is stably in the on state, thereby improving the stability of the gate drive signal Gout. The first plate of the second capacitor C2 is electrically connected to the gate of the first output transistor M1, and the second plate of the second capacitor C2 receives a fixed voltage signal. Figure 4 An example is shown where the second plate of the second capacitor C2 is electrically connected to the second level terminal VGL. The second capacitor C2 can store the gate potential of the first output transistor M1 and can keep the gate drive signal Gout output by the scan output terminal GOUT stable when the gate potential of the first output transistor M1 (i.e. the potential of the second node N2) is at the enabled level.

[0040] For example, refer to Figure 4The first node control module 101 includes a first node control transistor M5. The first electrode of the first node control transistor M5 is electrically connected to the signal input terminal VIN to receive the input signal Vin. The gate of the first node control transistor M5 is electrically connected to the first clock terminal CK1 to receive the first clock signal ck1. The second electrode of the first node control transistor M5 is electrically connected to the first node N1. The first node control transistor M5 can be turned on or off under the control of the first clock signal ck1. When the first clock signal ck1 is at an enabled level, the first node control transistor M5 is turned on, and the input signal Vin provided by the signal input terminal VIN can be transmitted to the first node N1 through the first node control transistor M5. When the first clock signal ck1 is at an disabled level, the first node control transistor M5 is turned off, and the input signal Vin provided by the signal input terminal VIN cannot be transmitted to the first node N1. In this design, one of the first and second terminals of the first node control transistor M5 is the source and the other is the drain. Based on the design of the all-oxide thin film transistor of this invention, the first node control transistor M5 is an oxide thin film transistor with an enable level of high and an disable level of low.

[0041] For example, continue to refer to Figure 4 The second node control module 102 includes a second node control transistor M6. The first electrode of the second node control transistor M6 is electrically connected to a first level terminal VGH to receive a first level signal Vgh. The gate of the second node control transistor M6 is electrically connected to a first clock terminal CK1 to receive a first clock signal ck1. The second electrode of the second node control transistor M6 is electrically connected to the second node N2. The second node control transistor M6 can be turned on or off under the control of the first clock signal ck1. When the first clock signal ck1 is at an enable level, the second node control transistor M6 is turned on, and the first level signal Vgh provided by the first level terminal VGH can be transmitted to the second node N2 through the second node control transistor M6. When the first clock signal ck1 is at a de-enabled level, the second node control transistor M6 is turned off, and the first level signal Vgh provided by the first level terminal VGH cannot be transmitted to the second node N2. In this design, one of the first and second terminals of the second node control transistor M6 is the source, and the other is the drain. Based on the design of the all-oxide thin-film transistor of this invention, the second node control transistor M6 is an oxide thin-film transistor with an enable level of high and an disable level of low.

[0042] Optional, Figure 5 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 5 As shown, the first control signal Vct is the first level signal Vgh, and the regulated signal Vm is multiplexed from the signal of the first node N1.

[0043] Specifically, the first level signal Vgh is used as the first control signal Vct. The output voltage regulator module 105 can maintain the first control signal Vct in the on state, transmitting the high-level signal of the first node N1 as the regulated signal Vm to the third node N3. During the stage when the second node N2 is low, the first node N1 is high, so that when the second clock signal ck2 outputs a high level, the gate drive signal Gout is high. Thus, during the stage when the first node N1 is high, the high-level signal of the first node N1 can be transmitted to the third node N3 through the output voltage regulator module 105, making the potential of the third node N3 consistent with the potential of the first node N1, and clamped to a high level. For the second output transistor M2, its gate is connected to the second node N2 and its source is connected to the third node N3, so its gate-source voltage Vgs is negative. Thus, even if the threshold voltage of the second output transistor M2 has shifted negatively, as long as the negative value Vgs is less than the threshold voltage after the negative shift (for example, Vth has shifted from +1V to -1V, while Vgs is -5V), the second output transistor M2 can be ensured to be completely turned off. Similarly, the gate of the first output transistor M1 is also electrically connected to the second node N2, and its source is connected to the second level signal Vgl, making its gate-source voltage 0V, and it is also in a reliable off state after the threshold voltage shifts negatively. This effectively suppresses the leakage path from the scan output terminal GOUT to the second level terminal VGL. Furthermore, by reusing the first node N1 as the voltage regulation signal source, the input terminal of the output voltage regulation module 105 is electrically connected to the first node N1, so that there is no need to set up an additional independent voltage regulation signal terminal VM and its routing. The voltage regulation function can be achieved using the existing first node N1 in the shift register G, which saves chip area and wiring resources, avoids the introduction of additional parasitic effects, and helps to simplify the layout, reduce parasitic capacitance and wiring complexity.

[0044] Optional, Figure 6 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 6 As shown, both the first control signal Vct and the voltage regulation signal Vm reuse the signals from the first node N1.

[0045] Specifically, the input and control terminals of the output voltage regulator module 105 can be electrically connected to the first node N1, that is, the gate and first electrode of the output voltage regulator transistor M3 can be electrically connected to the first node N1. Thus, when the first node N1 is high, it can simultaneously act as the first control signal Vct to control the output voltage regulator module 105 to pass through, and as the regulated signal Vm to be transmitted to the third node N3, clamping N3 to a high level. Similarly, it can create a negative gate-source voltage between the gate and source of the second output transistor M2, so that even if its threshold voltage has shifted negatively due to prolonged conduction, it can be forcibly turned off, effectively ensuring the accuracy of the gate drive signal Gout. Furthermore, without any additional control signals or voltage regulator sources, only the first node N1 is reused to simultaneously achieve the functions of "when to regulate voltage" and "to what potential to regulate voltage," solving the leakage problem caused by threshold drift with minimal hardware overhead and maximum timing synchronization, making it particularly suitable for the design of high-density drive circuits.

[0046] Optional, Figure 7 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 7 As shown, the first control signal Vct reuses the gate drive signal Gout, and the regulated signal Vm reuses the signal of the first node N1.

[0047] Specifically, the control terminal of the output voltage regulator module 105 can be electrically connected to the scan output terminal Gout to receive the gate drive signal Gout, so that the first control signal Vct multiplexes the gate drive signal Gout. The input terminal of the output voltage regulator module 105 can be electrically connected to the first node N1, so that the regulated signal Vm multiplexes the signal of the first node N1. Thus, when the gate drive signal Gout is high (i.e., enabled), this high level can act as the first control signal Vct to control the output voltage regulator module 105 to turn on. Simultaneously, the first node N1 is also high during this stage, and this high level, as the regulated signal Vm, is transmitted to the third node N3 through the turned-on output voltage regulator module 105, clamping N3 to a high level. This also allows a negative gate-source voltage to be formed between the gate and source of the second output transistor M2. Even if its threshold voltage has shifted negatively due to prolonged conduction (the gate drive signal Gout was continuously pulled low in the previous display frame), it can be forcibly turned off, effectively ensuring the accuracy of the gate drive signal Gout. Furthermore, by using the gate drive signal Gout as the first control signal Vct, the output voltage regulator module 105 is turned on only when the gate drive signal Gout is high, and automatically turned off during other stages. This ensures that the voltage regulation control and the high-level output stage of the gate drive signal Gout are naturally aligned in timing, eliminating the need for a dedicated control clock and avoiding timing matching adjustments between the first control signal Vct and the gate drive signal Gout, thus simplifying circuit design and timing convergence. Simultaneously, the regulated signal Vm reuses the signal from the first node N1, eliminating the need for an additional voltage source. This approach solves the leakage problem caused by threshold drift with extremely low hardware overhead and natural timing synchronization, making it suitable for high-density drive circuit designs.

[0048] Optional, Figure 8 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 8 As shown, the shift register G also includes: an isolation voltage regulator module 106; the first pole of the isolation voltage regulator module 106 is electrically connected to the first node N1, the gate of the isolation voltage regulator module 106 receives the first level signal Vgh, and the second pole of the isolation voltage regulator module 106 is electrically connected to the control terminal of the first output module 103 at the fourth node N4.

[0049] Specifically, the input terminal of the isolation voltage regulator module 106 can be electrically connected to the first node N1, the output terminal of the isolation voltage regulator module 106 can be electrically connected to the fourth node N4, and the control terminal of the isolation voltage regulator module 106 can be electrically connected to the first level terminal VGH. Then, the isolation voltage regulator module 106 can remain continuously conducting under the control of the first level signal Vgh, and transmit the signal from the first node N1 to the fourth node N4. Furthermore, it can isolate the first node N1 from the fourth node N4, preventing potential changes in the fourth node N4 from affecting the potential of the first node N1. For example, when the first node N1 is at a high level (let's say Vgh), this high level is transmitted to the fourth node N4 through the isolation regulator module 106, making the fourth node N4 also at a high level. At this time, due to the bootstrap effect of the first capacitor C1, the potential of the fourth node N4 can be pulled up to a voltage greater than Vgh (e.g., 2×Vgh). At this time, the isolation regulator module 106 can isolate the fourth node N4 from the first node N1, preventing the potential of the first node N1 from rising, so that the voltage of the first node N1 is maintained at Vgh, thus preventing the potential of the first node N1 from rising and flowing back to the driver chip.

[0050] For example, Figure 9 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 9 As shown, the isolation voltage regulator module 106 includes an isolation voltage regulator transistor M7. The first terminal of the isolation voltage regulator transistor M7 is electrically connected to the first node N1, and the second terminal of the isolation voltage regulator transistor M7 is electrically connected to the control terminal of the first output module 103 at the fourth node N4. The gate of the isolation voltage regulator transistor M7 is electrically connected to the first level terminal VGH to receive the first level signal Vgh. Therefore, the isolation voltage regulator module 106 can remain in the on state under the control of the first level signal Vgh, can transmit the signal from the first node N1 to the fourth node N4, and can prevent the potential change of the fourth node N4 from affecting the first node N1, thus isolating and regulating the potential of the first node N1. In this module, one of the first and second terminals of the isolation voltage regulator transistor M7 is the source, and the other is the drain. Based on the design of the all-oxide thin-film transistor of this invention, the isolation voltage regulator transistor M7 is an oxide thin-film transistor, with an enable level of high and a disable level of low.

[0051] Optional, Figure 10 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 10 As shown, the first control signal Vct reuses the first level signal Vgh, and the regulated signal Vm reuses the signal of the fourth node N4.

[0052] Specifically, the fourth node N4 is electrically connected to the first node N1 through the isolation voltage regulator module 106, so the potential of the fourth node N4 is consistent with that of the first node N1. When the first node N1 is high, the fourth node N4 is also high. At this time, the first control signal Vct is multiplexed with the first level signal Vgh, so that the first control signal Vct remains high, and the output voltage regulator module 105 is always in the conducting state. Based on this, by electrically connecting the input terminal of the output voltage regulator module 105 to the fourth node N4, that is, by multiplexing the voltage regulator signal Vm with the signal of the fourth node N4, the signal of the third node N3 is always consistent with the signal of the fourth node N4, that is, consistent with the signal of the first node N1. Therefore, when the second node N2 is at a low level, if the first node N1 is at a high level, the high level of the fourth node N4 is transmitted as a regulated signal Vm to the third node N3, clamping N3 to a high level. This creates a negative gate-source voltage between the gate (low level) and source (high level) of the second output transistor M2, forcibly turning off the threshold-biased second output transistor M2 and effectively suppressing leakage current. Thus, by multiplexing the constant first level signal Vgh with the first control signal, no additional timing control is needed. Furthermore, the regulated signal Vm is multiplexed with the fourth node N4, and N4 follows the first node N1 through the always-on isolation regulator module 106, indirectly achieving synchronization with the first node N1. At this time, the presence of the isolation regulator module 106 also prevents the potential fluctuations of the third node N3 from being reverse-coupled to the first node N1, enhancing circuit stability, reducing additional wiring, facilitating layout, reducing parasitic capacitance and wiring complexity, and effectively solving the leakage current problem caused by threshold drift.

[0053] Optional, Figure 11 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 11 As shown, the first control signal Vct and the regulated signal Vm both reuse the signals of the fourth node N4.

[0054] Specifically, when the third node N3 is clamped to a high level due to the conduction of the output voltage regulator module 105, this high level may be reverse-coupled to its control terminal or input terminal through the parasitic capacitance of the output voltage regulator module 105. Therefore, when the shift register G includes the isolation voltage regulator module 106, the control terminal and input terminal of the output voltage regulator module 105 can be electrically connected to the fourth node N4, so that the first control signal Vct and the regulated signal Vm both reuse the signal of the fourth node N4. In this way, the isolation voltage regulator module 106 can prevent the potential change of the fourth node N4 from affecting the potential of the first node N1, thereby effectively suppressing the potential fluctuation of the third node N3 from affecting the first node N1 in reverse, avoiding interference to other modules connected to the first node N1 (such as the first node control module 101), thereby effectively suppressing the off-state current of the second output transistor M2, and further improving the stability and anti-interference capability of the shift register G.

[0055] Optional, Figure 12 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 12 As shown, the first control signal Vct reuses the gate drive signal Gout, and the regulated signal Vm reuses the signal of the fourth node N4.

[0056] Specifically, based on a principle similar to the above embodiments, when the shift register G includes the isolation voltage regulator module 106, the control terminal of the output voltage regulator module 105 can be electrically connected to the scan output terminal GOUT to receive the gate drive signal Gout, so that the first control signal Vct multiplexes the gate drive signal Gout. Furthermore, the input terminals of the output voltage regulator module 105 are all electrically connected to the fourth node N4, so that the regulated signal Vm multiplexes the signal of the fourth node N4. This allows the output voltage regulator module 105 to be turned on only during the period when the gate drive signal Gout is high, and automatically turned off during other stages. This ensures that the voltage regulation control and the high-level output stage of the gate drive signal Gout are naturally aligned in timing, eliminating the need for an additional dedicated control clock. This avoids timing matching and debugging between the first control signal Vct and the gate drive signal Gout, simplifying circuit design and timing convergence. Meanwhile, the regulated signal Vm reuses the signal of the first node N1, eliminating the need for an additional voltage regulator. This solves the leakage problem caused by threshold drift with extremely low hardware overhead and natural timing synchronization. Furthermore, it effectively suppresses the potential fluctuations of the third node N3 from affecting the first node N1 in reverse, avoiding interference to other modules connected to the first node N1 (such as the first node control module 101). Thus, while effectively suppressing the off-state current of the second output transistor M2, it further enhances the stability and anti-interference capability of the shift register G.

[0057] Optional, Figure 13This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 13 As shown, the shift register G further includes: a first voltage regulation control module 107 and a second voltage regulation control module 108; the first voltage regulation control module 107 receives the signal of the first node N1 and the second clock signal ck2, and controls the signal of the fifth node N5; the second voltage regulation control module 108 receives the signal of the second node N2 and the second level signal Vgl, and controls the signal of the fifth node N5; the first control signal Vct multiplexes the signal of the fifth node N5.

[0058] Specifically, the first voltage regulator control module 107 is electrically connected to the first node N1, the second clock terminal CK2, and the fifth node N5, respectively, to receive the signal from the first node N1 and the second clock signal ck2 provided by the second clock terminal CK2, and to control the signal of the fifth node N5 in response to the signal from the first node N1 and the second clock signal ck2. In an exemplary embodiment, the input terminal of the first voltage regulator control module 107 can be electrically connected to the second clock terminal CK2, the control terminal of the first voltage regulator control module 107 can be electrically connected to the first node N1, and the output terminal of the first voltage regulator control module 107 can be electrically connected to the fifth node N5. Then, the first voltage regulator control module 107 can control the signal transmission path between the second clock terminal CK2 and the fifth node N5 under the control of the signal from the first node N1. When the signal of the first node N1 is at the enable level, the first voltage regulation control module 107 is turned on, and the second clock signal ck2 provided by the second clock terminal CK2 can be transmitted to the fifth node N5 through the first voltage regulation control module 107; when the signal of the first node N1 is at the non-enable level, the first voltage regulation control module 107 is turned off, and the second clock signal ck2 provided by the second clock terminal CK2 cannot be transmitted to the fifth node N5.

[0059] The second voltage regulation control module 108 is electrically connected to the second node N2, the second level terminal VGL, and the fifth node N5, respectively, to receive the signal from the second node N2 and the second level signal Vgl provided by the second level terminal VGL, and to control the signal of the fifth node N5 in response to the signal from the second node N2 and the second level signal Vgl. In an exemplary embodiment, the input terminal of the second voltage regulation control module 108 is electrically connected to the second level terminal VGL, the control terminal of the second voltage regulation control module 108 is electrically connected to the second node N2, and the output terminal of the second voltage regulation control module 108 is electrically connected to the fifth node N5. Under the potential control of the second node N2, the second voltage regulation control module 108 controls the signal transmission path between the second level terminal VGL and the fifth node N5. When the signal of the second node N2 is at the enable level, the second voltage regulation control module 108 controls the signal transmission path between the second level terminal VGL and the fifth node N5 to be turned on, and the second level signal Vgl can be transmitted to the fifth node N5 through the second voltage regulation control module 108, so that the gate drive signal Gout is the same as the second level signal Vgl. When the signal of the second node N2 is at the disable level, the second voltage regulation control module 108 controls the signal transmission path between the second level terminal VGL and the fifth node N5 to be turned off, and the second level signal Vgl cannot be transmitted to the fifth node N5. Therefore, the second level signal Vgl of the second level terminal VGL will not affect the signal of the fifth node N5.

[0060] Therefore, the input and control terminals of the first voltage regulation control module 107 have the same connection relationship with the first output module 103, and the input and control terminals of the second voltage regulation control module 108 have the same connection relationship with the second output module 104. Thus, the signal of the fifth node N5 has the same transition condition as the gate drive signal Gout. Based on the synchronization characteristics of the signal of the fifth node N5 and the gate drive signal Gout, the control terminal of the output voltage regulation module 105 can be electrically connected to the fifth node N5, so that the first control signal Vct reuses the signal of the fifth node N5 without additional timing matching and debugging. It also avoids the load on the first node N1 or the gate drive signal Gout caused by directly reusing the signal of the first node N1 or the gate drive signal Gout. This can effectively reduce the driving burden of key nodes (such as the first node N1 and the scan output terminal Gout), improve the rise / fall speed, noise immunity and level establishment integrity of the key node signals, and thus, while effectively regulating the voltage of the third node N3, further improve the overall working stability and output accuracy of the shift register.

[0061] Specifically, when the first control signal Vct multiplexes the signal of the fifth node N5, during the stage when the second node N2 is at an inactive level (i.e., low level) and the first output transistor M1 and the second output transistor M2 are turned off, the signal of the fifth node N5 can synchronously jump to a high level with the gate drive signal Gout. This allows the high-level signal of the fifth node N5 to control the output voltage regulator module 105 to turn on, thereby enabling the regulated signal Vm to be transmitted to the third node N3 through the output voltage regulator module 105 to regulate the signal of the third node N3. During the non-regulated stage (such as when the second node N2 is at a high level and the gate drive signal Gout is at a low level), the potential of the fifth node N5 is forcibly pulled down by the second voltage regulation control module 108 to be consistent with the second level signal Vgl, thereby controlling the output voltage regulator module 105 to remain off and not to interfere with the third node N3.

[0062] Optional, Figure 14 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 14 As shown, the first voltage regulation control module 107 includes: a first voltage regulation control transistor M8; the first terminal of the first voltage regulation control transistor M8 receives the second clock signal ck2, the gate of the first voltage regulation control transistor M8 is electrically connected to the first node N1, and the second terminal of the first voltage regulation control transistor M8 is electrically connected to the fifth node N5.

[0063] Specifically, using the above configuration, the first voltage regulator transistor M8 can be controlled to be turned on or off by the first node N1. When the signal at the first node N1 is at an enable level, the first voltage regulator transistor M8 is turned on, allowing the second clock signal ck2 provided by the second clock terminal CK2 to be transmitted to the fifth node N5 through the first voltage regulator transistor M8; when the signal at the first node N1 is at a de-enabled level, the first voltage regulator transistor M8 is turned off, and the second clock signal ck2 provided by the second clock terminal CK2 cannot be transmitted to the fifth node N5, thus the transition of the second clock signal ck2 will not affect the potential of the fifth node N5. In this configuration, one of the first and second terminals of the first voltage regulator transistor M8 is the source, and the other is the drain. Based on the design of the all-oxide thin-film transistor of this invention, the first voltage regulator transistor M8 is an oxide thin-film transistor, with an enable level of high and a de-enabled level of low.

[0064] Optional, see reference Figure 14 The second voltage regulation control module 108 includes: a second voltage regulation control transistor M9; the first terminal of the second voltage regulation control transistor M9 receives a second level signal Vgl, the gate of the second voltage regulation control transistor M9 is electrically connected to the second node N2, and the second terminal of the second voltage regulation control transistor M9 is electrically connected to the fifth node N5.

[0065] Specifically, using the above configuration, the second voltage regulator control transistor M9 can be controlled to be turned on or off by the second node N2. When the signal at the second node N2 is at an enable level, the second voltage regulator control transistor M9 is turned on, allowing the second level signal Vgl provided by the second level terminal VGL to be transmitted to the fifth node N5 through the second voltage regulator control transistor M9; when the signal at the second node N2 is at a de-enabled level, the second voltage regulator control transistor M9 is turned off, and the second level signal Vgl provided by the second level terminal VGL cannot be transmitted to the fifth node N5. In this configuration, one of the first and second terminals of the second voltage regulator control transistor M9 is the source, and the other is the drain. Based on the design of the all-oxide thin-film transistor of this invention, the second voltage regulator control transistor M9 is an oxide thin-film transistor, with its enable level being high and its de-enabled level being low.

[0066] Optional, Figure 15 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 15 As shown, the second voltage regulation control module 108 includes: a second voltage regulation control transistor M9 and a third voltage regulation control transistor M10; the first terminal of the second voltage regulation control transistor M9 receives a second level signal Vgl, the gates of the second voltage regulation control transistor M9 and the third voltage regulation control transistor M10 are both electrically connected to the second node N2, the second terminal of the second voltage regulation control transistor M9 is electrically connected to the first terminal of the third voltage regulation control transistor M10, and the second terminal of the third voltage regulation control transistor M10 is electrically connected to the fifth node N5.

[0067] Specifically, using the above configuration, the second voltage regulator transistor M9 and the third voltage regulator transistor M10 are connected in series between the second level terminal VGL and the fifth node N5. The gates of both transistors are electrically connected to the second node N2, allowing them to be simultaneously turned on or off under the control of the second node N2. When the signal at the second node N2 is at the enable level, the second voltage regulator transistors M9 and M10 are simultaneously turned on, allowing the second level signal Vgl provided by the second level terminal VGL to be transmitted to the fifth node N5 sequentially through the second and third voltage regulator transistors M9 and M10, ensuring that the signal at the fifth node N5 is consistent with the second level signal Vgl. Conversely, when the signal at the second node N2 is at the disable level, the second voltage regulator transistors M9 and M10 are simultaneously turned off, preventing the second level signal Vgl from being transmitted to the fifth node N5. By connecting the second voltage regulator control transistor M9 and the third voltage regulator control transistor M10 in series between the second level terminal VGL and the fifth node N5, the equivalent off-state resistance between the second level terminal VGL and the fifth node N5 is equal to the sum of the off-state resistances of the second voltage regulator control transistor M9 and the third voltage regulator control transistor M10, significantly reducing the overall conduction capability of the leakage current path. Even if the threshold voltage of one transistor drifts, leading to an increase in off-state leakage current, the other transistor can still effectively block the leakage current path, forming dual protection. Furthermore, the series structure can share voltage stress, preventing a single transistor from bearing a large source-drain voltage difference, which is beneficial for suppressing threshold drift and improving device reliability. In this design, one of the first and second terminals of the second voltage regulator control transistor M9 and the third voltage regulator control transistor M10 is the source, and the other is the drain. Based on the all-oxide thin-film transistor design of this invention, the second voltage regulator control transistor M9 and the third voltage regulator control transistor M10 are oxide thin-film transistors, with an enable level of high and a disable level of low.

[0068] Optional, Figure 16 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 16 As shown, the shift register G also includes: a first node inter-control module 109; the first node inter-control module 109 receives at least the signal of the second node N2, the second level signal Vgl, and the second clock signal ck2, and controls the signal of the first node N1.

[0069] Specifically, the control terminal of the first node inter-control module 109 can be electrically connected to the second node N2, the input terminal of the first node inter-control module 109 can be electrically connected to the second level terminal VGL to receive the second level signal Vgl, and the output terminal of the first node inter-control module 109 can be electrically connected to the first node N1. Then, the first node inter-control module 109 can control the signal transmission path between the second level terminal VGL and the first node N1 under the control of the second node N2. When the signal of the second node N2 is at the enable level (i.e., high level), the first node inter-control module 109 is turned on, so that the second level signal Vgl provided by the second level terminal VGL can be transmitted to the first node N1 through the first node inter-control module 109, so that the first node N1 is a low level second level signal Vgl. This ensures that when the second node N2 is at the enable level, the first node N1 remains at the disabled level, so that the polarity of the signal of the first node N1 is opposite to that of the signal of the second node N2, so as to avoid the first node N1 from being falsely raised due to capacitive coupling or leakage, thereby preventing the first output module 103 from turning on at an unexpected time and outputting an incorrect high level pulse.

[0070] Optional, Figure 17 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 17 As shown, the first node inter-control module 109 includes a first inter-control transistor M11 and a second inter-control transistor M12; the first terminal of the first inter-control transistor M11 receives a second level signal Vgl, the gate of the first inter-control transistor M11 is electrically connected to the second node N2, and the second terminal of the first inter-control transistor M11 is electrically connected to the sixth node N6; the first terminal of the second inter-control transistor M12 is electrically connected to the sixth node N6, the gate of the second inter-control transistor M12 receives a second clock signal ck2, and the second terminal of the second inter-control transistor M12 is electrically connected to the first node N1.

[0071] Specifically, the first inter-controlling transistor M11 and the second inter-controlling transistor M12 can be connected in series between the second level terminal VGL and the first node N1. One of the first inter-controlling transistors M11 and M12 is controlled by the second node N2, and the other is controlled by the second clock signal ck2. An exemplary embodiment of the present invention shows the case where the gate of the first inter-controlling transistor M11 is electrically connected to the second node N2, and the gate of the second inter-controlling transistor M12 is electrically connected to the second clock terminal CK2. That is, the first inter-controlling transistor M11 is controlled to be turned on or off by the second node N2, and the second inter-controlling transistor M12 is controlled to be turned on or off by the second clock signal ck2. In this embodiment, one of the first and second terminals of the second inter-controlling transistor M12 is the source, and the other is the drain. Based on the design of the all-oxide thin-film transistor of the present invention, the second inter-controlling transistor M12 is an oxide thin-film transistor, with an enable level of high and a disable level of low.

[0072] Therefore, when the second node N2 is enabled, when the second clock signal ck2 jumps to the enabled level, the second level signal Vgl provided by the second level terminal VGL can be transmitted to the first node N1 through the first inter-control transistor M11 and the second inter-control transistor M12 in sequence, so that the potential of the first node N1 is opposite to the potential polarity of the second node N2; and when the second clock signal ck2 jumps to the disabled level, the second inter-control transistor M12 is turned off, so that the sixth node N6 and the first node N1 are disconnected, so that the potentials of the sixth node N6 and the first node N1 do not affect each other.

[0073] When the second node N2 is disabled, the first inter-control transistor M11 remains off, preventing the second-level signal Vgl provided by the second-level terminal VGL from being transmitted to the sixth node N6. At this time, the potential of the sixth node N6 is unaffected by the second-level signal Vgl. During this stage, if the second clock signal ck2 is enabled (high level), the second inter-control transistor M12 is turned on. However, since the first inter-control transistor M11 is off, the second-level signal Vgl cannot be transmitted to the sixth node N6 through the first inter-control transistor M11. Therefore, although the sixth node N6 and the first node N1 are electrically connected through the turned-on second inter-control transistor M12, the sixth node N6 itself is in a floating state, and its potential is determined by the potential of the first node N1. Specifically, when the first node N1 is high, this high level is transmitted in reverse to the sixth node N6 through the turned-on second inter-control transistor M12, charging the potential of the sixth node N6 to a high level; while when the first node N1 is low, the sixth node N6 is pulled low. Since the second inter-control transistor M12 is a unidirectional conducting device (usually an NMOS transistor, whose source and drain are directional in actual operation), this reverse transmission may be affected by transistor body effect or threshold loss, causing the high level of the sixth node N6 to not fully reach the full amplitude of the first node N1, but it can still be maintained within a recognizable logic high level range. This can prevent the sixth node N6 from being in an uncertain floating state, effectively suppressing the noise caused by capacitive coupling, thereby improving the anti-interference capability and working stability of the entire circuit.

[0074] Optional, see reference Figure 16 The shift register G also includes: a second node inter-control module 110; the first terminal of the second node inter-control module 110 receives the first clock signal ck1, the control terminal of the second node inter-control module 110 is electrically connected to the first node N1, and the second terminal of the second node inter-control module 110 is electrically connected to the second node N2; the second node inter-control module 110 is used to control the signal transmission path from the first clock signal ck1 to the second node N2 according to the signal from the first node N1.

[0075] Specifically, when the signal of the first node N1 is at an enable level (i.e., high level), the second node inter-control module 110 is turned on, allowing the first clock signal ck1 provided by the first clock terminal CK1 to be transmitted to the second node N2 through the second node inter-control module 110, ensuring that the signal of the second node N2 is consistent with the first clock signal ck1. When the signal of the first node N1 is at a non-enable level (i.e., low level), the second node inter-control module 110 is turned off, preventing the first clock signal ck1 provided by the first clock terminal CK1 from being transmitted to the second node N2. Therefore, the potential of the second node N2 is not affected by the first clock signal ck1, and the potential of the second node N2 is determined by the second node control module 120. The second node inter-control module 110 implements unidirectional interlock control of the first node N1 on the second node N2. The first clock signal ck1 is used as the charging source for the second node N2, ensuring that the high level of the second node N2 is naturally aligned with the rising edge of the first clock signal ck1, facilitating timing matching with the output of the preceding shift register G and simplifying the cascade design.

[0076] Through the aforementioned connection, the second node inter-control module 110 and the first node inter-control module 109 can achieve bidirectional interlocking, forming a complete interlocking logic. Specifically, when the first node N1 is high, the second node inter-control module 110 is turned on, transmitting the first clock signal ck1 to the second node N2. If the first clock signal ck1 is high at this time, the second node N2 is pulled high, and then the first node inter-control module 109 (controlled by the second node N2 and the second clock signal ck2) pulls the first node N1 low, thus preventing both nodes from being high simultaneously. Conversely, when the second node N2 is high, the first node N1 is pulled low, causing the second node inter-control module 110 to turn off, cutting off the charging path of the first clock signal ck1 to the second node N2, ensuring that the high-level state of the second node N2 is not disturbed by subsequent transitions of the first clock signal ck1. The first node mutual control module 109 and the second node mutual control module 110 cooperate to ensure that the first node N1 and the second node N2 will never be enabled at the same time, effectively avoiding abnormal output of the gate drive signal Gout due to node potential conflict, and improving the stability and reliability of the shift register G in the multi-level cascade transmission process.

[0077] For example, refer to Figure 17The second node inter-control module 110 includes a third inter-control transistor M13. The first terminal of the third inter-control transistor M13 is electrically connected to the first clock terminal CK1 to receive the first clock signal ck1. The second terminal of the third inter-control transistor M13 is electrically connected to the second node N2, and the gate of the third inter-control transistor M13 is electrically connected to the first node N1. The third inter-control transistor M13 can be controlled to be turned on or off by the first node N1. When on, it can transmit the first clock signal ck1 provided by the first clock terminal CK1 to the second node N2. When off, it can disconnect the circuit between the first clock terminal CK1 and the second node N2, so that the transition of the first clock signal ck1 does not affect the potential of the second node N2. One of the first and second terminals of the third inter-control transistor M13 is the source, and the other is the drain. Based on the design of the all-oxide thin-film transistor of this invention, the third inter-control transistor M13 is an oxide thin-film transistor, with an enable level of high and a disable level of low.

[0078] Optional, see reference Figures 13-15 In any of the accompanying figures, when the shift register G includes a first voltage regulation control module 107 and a second voltage regulation control module 108, the input terminal of the output voltage regulation control module 105 can be electrically connected to the first node N1, so that the regulated signal Vm multiplexes the signal of the first node N1. Alternatively, refer to... Figure 16 or Figure 17 In the embodiment where the shift register G includes a first voltage regulation control module 107 and a second voltage regulation control module 108, or in the embodiment where the shift register G includes a first voltage regulation control module 107, a second voltage regulation control module 108, a first node mutual control module 109, and a second node mutual control module 110, the input terminal of the output voltage regulation control module 105 can be electrically connected to the first node N1 so that the regulated signal Vm multiplexes the signal of the first node N1.

[0079] Optional, Figure 18 This is a schematic diagram of another shift register provided in an embodiment of the present invention, see reference. Figure 18 When the shift register G includes a first voltage regulation control module 107 and a second voltage regulation control module 108, the input terminal of the output voltage regulation control module 105 can be electrically connected to the fifth node N5, so that the regulated signal Vm multiplexes the signal of the fifth node N5. Alternatively, Figure 19 This is a schematic diagram of another shift register provided in an embodiment of the present invention, see reference. Figure 19 In an embodiment where the shift register G includes a first voltage regulation control module 107, a second voltage regulation control module 108, a first node mutual control module 109, and a second node mutual control module 110, the input terminal of the output voltage regulation control module 105 can be electrically connected to the fifth node N5 so that the regulated signal Vm multiplexes the signal of the fifth node N5.

[0080] Optional, Figure 20 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 20 As shown, when the shift register G includes the first node mutual control module 109, the input terminal of the output voltage regulation control module 105 can be electrically connected to the sixth node N6 so that the regulated signal Vm multiplexes the signal of the sixth node N6.

[0081] Specifically, when the second node N2 is enabled (high level) and the second clock signal ck2 is enabled (high level), the first inter-controller M11 and the second inter-controller M12 are simultaneously turned on, and the sixth node N6 is pulled down to the second level signal Vgl (low level). When the second node N2 is disabled (low level) and the second clock signal ck2 is enabled (high level), the first inter-controller M11 is turned off and the second inter-controller M12 is turned on. The sixth node N6 is electrically connected to the first node N1 through the second inter-controller M12, and its potential follows the change of the first node N1. Therefore, during the stage when the second node N2 is disabled (low level) and controls the turn-off of the first output transistor M1 and the second output transistor M2, when the signal of the first node N1 and the second clock signal ck1 are high, the sixth node N6 and the gate drive signal are both high. The high level of the sixth node N6 is used as the regulated signal Vm, and the first control signal Vct can reuse the corresponding signal (such as the first level signal Vgh, the signal of the first node N1, the signal of the fifth node N5, or the gate drive signal Gout, etc.). The embodiment of the present invention exemplarily shows the case where the first control signal Vct reuses the signal of the fifth node N5. This allows the signal of the sixth node N6 to be transmitted to the third node N3 through the output voltage regulator module 150, clamping the third node N3 to a high level. This forms a negative gate-source voltage between the gate (connected to the low level of the second node N2) and the source (connected to the high level of the third node N3) of the second output transistor M42. This can prevent the second output transistor M42 from failing to turn off completely due to the negative drift of the threshold voltage, thereby effectively suppressing leakage current during the stage when the gate drive signal Gout outputs a high level.

[0082] In one exemplary embodiment, taking as an example that all transistors in the shift register are oxide thin-film transistors, Figure 21 This is a driving timing diagram of a shift register provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 17 and Figure 21 Taking the first control signal Vct multiplexing the first level signal Vgh, and the regulated signal Vm multiplexing the signal of the first node N1 as an example, the working process of the shift register G is explained.

[0083] During stage t1, the input signal Vin and the first clock signal ck1 are at high level, and the second clock signal ck2 is at low level. Therefore, the first node control transistor M5 and the second node control transistor M6 are turned on, and the second inter-control transistor M12 is turned off. The high-level input signal Vin is transmitted to the first node N1 through the first node control transistor M5, making the signal of the first node N1 high level. The first level signal Vgh of the first level terminal VGH is transmitted to the second node N2 through the second node control transistor M6, making the second node N2 high level. The second level signal Vgl of the second level terminal VGL is transmitted to the sixth node N6 through the second inter-control transistor M12, making the sixth node N6 low level. The signal of the fourth node N4 remains high, consistent with the signal of the first node N1. The high-level signal of the first node N1 controls the third inter-control transistor M13 to turn on, and the high-level signal of the fourth node N4 controls the first voltage regulator transistor M8 and the third output transistor M4 to turn on. The high level of the first clock signal ck1 is transmitted to the second node N2 through the third inter-control transistor M13, and the second node N2 is stabilized at a high level. The low level of the second clock signal ck2 is transmitted to the fifth node N5 through the first voltage regulator transistor M8, and to the scan output terminal GOUT through the third output transistor M4, so that the signal of the fifth node N5 and the gate drive signal Gout are kept at a low level. The high-level signal at the second node N2 controls the first mutual control transistor M11, the second voltage regulator transistor M9, the third voltage regulator transistor M10, and the first output transistor M1 to conduct. Then, the second-level signal Vgl at the second-level terminal VGL is transmitted sequentially through the second voltage regulator transistor M9 and the third voltage regulator transistor M10 to the fifth node N5. Since the second clock signal ck2 and the second-level signal Vgl received by the fifth node N5 are both low, the fifth node N5 remains stably low. Simultaneously, the output voltage regulator transistor M3 remains in the conducting state under the control of the first-level signal Vgh, and the first electrode of the output voltage regulator transistor M3 is electrically connected to the first node N1, making the signal at the third node N3 consistent with the signal at the first node N1 at a high level. This causes the gate and source of the second output transistor M2 to be at the same potential, turning off the second output transistor M2. The signal at the third node N3 and the second clock signal ck2 are not transmitted to the scan output terminal GOUT, ensuring that the gate drive signal Gout remains consistent with the second clock signal ck2 at a stable low level.

[0084] In stage t2, the input signal Vin and the first clock signal ck1 transition to low level, while the second clock signal ck2 remains low. Therefore, the first node control transistor M5, the second node control transistor M6, and the second inter-control transistor M12 are turned off. No new signal is written to the first node N1, so it remains at the high level of the previous stage. The signals of the third node N3 and the fourth node N4 remain high, consistent with the signal of the first node N1. The high-level signal of the first node N1 controls the third inter-control transistor M13 to turn on. The low level of the first clock signal ck1 is written to the second node N2 through the third inter-control transistor M13, causing the second node N2 to transition to low level. The high level of the fourth node N4 controls the first voltage regulator transistor M8 and the third output transistor M4 to turn on. The low level of the second clock signal ck2 is transmitted to the fifth node N5 through the first voltage regulator transistor M8 and to the scan output terminal GOUT through the third output transistor M4, ensuring that the signal of the fifth node N5 remains low, consistent with the gate drive signal Gout. The low level at the second node N2 controls the first inter-controller transistor M11, the second voltage regulator transistor M9, the third voltage regulator transistor M10, and the first output transistor M1 to turn off; the sixth node N6 remains at the low level of the previous stage as no new signal is written. During this stage, the gate-source voltage Vgs of the second output transistor M2 = V_N2 - V_N3, ensuring that the second output transistor M2 is completely turned off and effectively suppressing the off-state leakage current of the second output transistor M2.

[0085] In stage t3, the input signal Vin and the first clock signal ck1 remain low, while the second clock signal ck2 jumps to high. Therefore, the first node control transistor M5 and the second node control transistor M6 remain off, and the second inter-control transistor M12 is turned on. No new signal is written to the first node N1, thus maintaining the high level of the previous stage. The signal of the third node N3 remains high, consistent with the signal of the first node N1. The high-level signal of the first node N1 is transmitted to the fourth node N4 through the isolation Zener transistor M7, making the fourth node N4 high. The high-level signal at the first node N1 controls the third inter-control transistor M13 to turn on. The low level of the first clock signal ck1 is written to the second node N2 through the third inter-control transistor M13, and the second node N2 remains at a low level. The high level at the fourth node N4 controls the first voltage regulator transistor M8 and the third output transistor M4 to turn on. The high level of the second clock signal ck2 is transmitted to the fifth node N5 through the first voltage regulator transistor M8 and to the scan output terminal GOUT through the third output transistor M4, so that the signal of the fifth node N5 and the gate drive signal Gout are kept at a high level. At this time, due to the bootstrap effect of the first capacitor C1, the potential of the fourth node N4 is further raised. The low level at the second node N2 controls the first inter-control transistor M11, the second voltage regulator transistor M9, the third voltage regulator transistor M10 and the first output transistor M1 to turn off. The high level at the first node N1 is transmitted to the sixth node N6 through the second inter-control transistor M12, and the sixth node N6 jumps to a high level. During this stage, the gate-source voltage Vgs of the second output transistor M2 = V_N2 - V_N3, which ensures that the second output transistor M2 is completely turned off and effectively suppresses the off-state leakage current of the second output transistor M2, thereby ensuring the stability and accuracy of the gate drive signal Gout outputting a high level.

[0086] In stage t4, the input signal Vin and the first clock signal ck1 remain low, while the second clock signal ck2 transitions to low. This turns off the first node control transistor M5, the second node control transistor M6, and the second inter-control transistor M12. Since no new signal is written to the first node N1, it remains at the high level of the previous stage. The signal of the third node N3 remains high, consistent with the signal of the first node N1. The high-level signal of the first node N1 is transmitted to the fourth node N4 through the isolation Zener transistor M7, causing the fourth node N4 to be high. The high-level signal at the first node N1 controls the third inter-control transistor M13 to turn on. The low level of the first clock signal ck1 is written to the second node N2 through the third inter-control transistor M13, and the second node N2 remains at a low level. The high level at the fourth node N4 controls the first voltage regulator transistor M8 and the third output transistor M4 to turn on. The low level of the second clock signal ck2 is transmitted to the fifth node N5 through the first voltage regulator transistor M8 and to the scan output terminal GOUT through the third output transistor M4, causing the signal at the fifth node N5 to switch to a low level in line with the gate drive signal Gout. At this time, the low level at the scan output terminal GOUT causes the potential of the fourth node N4 to fall back to the same level as the first node N1. The low level at the second node N2 controls the first inter-control transistor M11, the second voltage regulator transistor M9, the third voltage regulator transistor M10, and the first output transistor M1 to turn off. The sixth node N6 remains at a high level as in the previous stage because no new signal is written. During this stage, the gate-source voltage Vgs of the second output transistor M2 is V_N2-V_N3, which ensures that the second output transistor M2 is completely turned off and effectively suppresses the off-state leakage current of the second output transistor M2.

[0087] In stage t5, the input signal Vin and the second clock signal ck2 remain low, while the first clock signal ck1 jumps to a high level. This turns on the first node control transistor M5 and the second node control transistor M6, while turning off the second inter-control transistor M12. The low-level input signal Vin is transmitted to the first node N1 through the first node control transistor M5, causing the signal at the first node N1 to jump to a low level. The first-level signal Vgh at the first level terminal VGH is transmitted to the second node N2 through the second node control transistor M6, making the second node N2 high. The signals at the third node N3 and the fourth node N4 follow the same pattern as the signal at the first node N1, jumping to a low level. The low-level signal at the first node N1 turns off the third inter-control transistor M13, and the high-level signal at the fourth node N4 turns off the first voltage regulator transistor M8 and the third output transistor M4. The high level at the second node N2 controls the first inter-control transistor M11, the second voltage regulator transistor M9, the third voltage regulator transistor M10, the first output transistor M1, and the first output transistor M2 to conduct; then the second level signal Vgl of the second level terminal VGL is transmitted to the sixth node N6 through the first inter-control transistor M11, and the sixth node N6 jumps to a low level; the second level signal Vgl of the second level terminal VGL is transmitted to the fifth node N5 through the second voltage regulator transistor M9 and the third voltage regulator transistor M10 in sequence, and the fifth node N5 remains at a low level; at the same time, the second level signal Vgl of the second level terminal VGL is transmitted to the scan output terminal GOUT through the first output transistor M1 and the first output transistor M2 in sequence, so that the gate drive signal Gout is consistent with the signal of the fifth node N5 and remains at a low level.

[0088] After stage t5, since the input signal Vin remains low, the first node N1 remains low. The signals of the third node N3 and the fourth node N4 are consistent with the signal of the first node N1, remaining low. Consequently, the third inter-control transistor M13 remains off, allowing the second node N2 to only receive the first-level signal Vgh, meaning the second node N2 remains high. The other transistors maintain the state of stage t5, keeping the gate drive signal Gout and the signal of the fifth node N5 low until the input signal Vin jumps high again, repeating the above stages.

[0089] The above embodiment exemplifies the specific working process of the shift register G when the first control signal Vct is multiplexed with the first level signal Vgh and the regulated signal Vm is multiplexed with the signal of the first node N1. Figure 21 The potential changes of each node in shift register G have been shown. For other multiplexing details of the first control signal Vct and the regulated signal Vm, please refer to [the documentation / reference]. Figure 21The analysis will be based on the relevant explanations and descriptions in the above embodiments, and will not be repeated here.

[0090] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes the display panel provided in any embodiment of the present invention. Therefore, the display device provided in the embodiments of the present invention includes the technical features of the display panel provided in any embodiment of the present invention, and can achieve the beneficial effects of the display panel provided in any embodiment of the present invention. The similarities can be referred to the above description of the display panel provided in the embodiments of the present invention, and will not be repeated here.

[0091] For example, Figure 22 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 22 As shown, the display device 200 includes the display panel 100 provided in this embodiment of the invention. The display device 200 provided in this embodiment of the invention can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc., and this embodiment of the invention does not make any special limitations on these categories.

[0092] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Drive circuit; The driving circuit includes N cascaded shift registers; the shift registers include: a first node control module, a second node control module, a first output module, a second output module, and an output voltage regulator module; In the same shift register: The first node control module is used to receive input signals and a first clock signal, and to control the signals of the first node; The second node control module is used to receive the first level signal and the first clock signal, and to control the signals of the second node; The first output module is used to receive the signal from the first node and the second clock signal, and to control the gate drive signal; The second output module is used to receive the signal from the second node and the second level signal, and control the gate drive signal; the second output module includes a first output transistor and a second output transistor, the gates of the first output transistor and the second output transistor are electrically connected to the second node, the first terminal of the first output transistor receives the second level signal, the second terminal of the first output transistor is electrically connected to the first terminal of the second output transistor and the third node, and the second terminal of the second output transistor outputs the gate control signal; The output voltage regulator module is electrically connected to the third node, and the output voltage regulator module receives a first control signal and a voltage regulator signal; the output voltage regulator module is used to transmit the voltage regulator signal to the third node under the control of the first control signal; Wherein, the gate drive signal of the shift register of the i-th stage is the input signal of the shift register of the j-th stage; i, j and N are all positive integers, i ≠ j and i and j are both less than or equal to N.

2. The display panel according to claim 1, characterized in that, When the gate drive signal is at the enable level, the first control signal is at the enable level, and the voltage regulation signal has the opposite polarity to the signal of the second node.

3. The display panel according to claim 1, characterized in that, The output voltage regulator module includes an output voltage regulator transistor; The first terminal of the output Zener transistor receives the regulated signal, the gate of the output Zener transistor receives the first control signal, and the second terminal of the output Zener transistor is electrically connected to the third node.

4. The display panel according to claim 1, characterized in that, The first control signal is the first level signal, and the voltage regulation signal reuses the signal of the first node.

5. The display panel according to claim 1, characterized in that, Both the first control signal and the voltage regulation signal reuse the signal from the first node.

6. The display panel according to claim 1, characterized in that, The first control signal reuses the gate drive signal, and the voltage regulation signal reuses the signal of the first node.

7. The display panel according to claim 1, characterized in that, The shift register further includes: an isolation voltage regulator module; The first electrode of the isolation voltage regulator module is electrically connected to the first node, the gate of the isolation voltage regulator module receives the first level signal, and the second electrode of the isolation voltage regulator module is electrically connected to the control terminal of the first output module at the fourth node.

8. The display panel according to claim 7, characterized in that, The first control signal reuses the first level signal, and the voltage regulation signal reuses the signal of the fourth node.

9. The display panel according to claim 7, characterized in that, Both the first control signal and the voltage regulation signal reuse the signal from the fourth node.

10. The display panel according to claim 7, characterized in that, The first control signal reuses the gate drive signal, and the voltage regulation signal reuses the signal of the fourth node.

11. The display panel according to claim 1, characterized in that, The shift register further includes: a first voltage regulation control module and a second voltage regulation control module; The first voltage regulation control module receives the signal from the first node and the second clock signal, and controls the signal from the fifth node; The second voltage regulation control module receives the signal from the second node and the second level signal, and controls the signal of the fifth node; The first control signal reuses the signal from the fifth node.

12. The display panel according to claim 11, characterized in that, The first voltage regulation control module includes: a first voltage regulation control transistor; The first terminal of the first voltage regulator transistor receives the second clock signal, the gate of the first voltage regulator transistor is electrically connected to the first node, and the second terminal of the first voltage regulator transistor is electrically connected to the fifth node.

13. The display panel according to claim 11, characterized in that, The second voltage regulation control module includes: a second voltage regulation control transistor; The first terminal of the second voltage regulator transistor receives the second level signal, the gate of the second voltage regulator transistor is electrically connected to the second node, and the second terminal of the second voltage regulator transistor is electrically connected to the fifth node.

14. The display panel according to claim 11, characterized in that, The second voltage regulation control module includes: a second voltage regulation control transistor and a third voltage regulation control transistor; The first terminal of the second voltage regulator transistor receives the second level signal. The gates of the second voltage regulator transistor and the third voltage regulator transistor are both electrically connected to the second node. The second terminal of the second voltage regulator transistor is electrically connected to the first terminal of the third voltage regulator transistor. The second terminal of the third voltage regulator transistor is electrically connected to the fifth node.

15. The display panel according to claim 11, characterized in that, The shift register also includes: a first node mutual control module; The first node mutual control module receives at least the signal from the second node, the second level signal, and the second clock signal, and controls the signal of the first node.

16. The display panel according to claim 15, characterized in that, The first node inter-control module includes a first inter-control transistor and a second inter-control transistor; The first terminal of the first inter-controlling transistor receives the second level signal, the gate of the first inter-controlling transistor is electrically connected to the second node, and the second terminal of the first inter-controlling transistor is electrically connected to the sixth node; The first terminal of the second inter-control transistor is electrically connected to the sixth node, the gate of the second inter-control transistor receives the second clock signal, and the second terminal of the second inter-control transistor is electrically connected to the first node.

17. The display panel according to any one of claims 11 to 16, characterized in that, The regulated signal reuses the signal from the first node.

18. The display panel according to any one of claims 11 to 16, characterized in that, The regulated signal reuses the signal from the fifth node.

19. The display panel according to claim 16, characterized in that, The regulated signal reuses the signal from the sixth node.

20. The display panel according to claim 1, characterized in that, The shift register also includes: a second node mutual control module; The first terminal of the second node mutual control module receives the first clock signal, the control terminal of the second node mutual control module is electrically connected to the first node, and the second terminal of the second node mutual control module is electrically connected to the second node; The second node mutual control module is used to control the signal transmission path from the first clock signal to the second node based on the signal from the first node.

21. A display device, characterized in that, include: The display panel according to any one of claims 1 to 20.

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