Display device

Abstract

This disclosure provides a display device comprising: a light-emitting element; a driving TFT including a first electrode connected to a first node, a first gate electrode connected to a second node, and a second electrode connected to a third node; a first switching TFT including a gate electrode to which a first scan signal is input, a first electrode connected to the second node, and a second electrode connected to the third node; a second switching TFT including a gate electrode to which a second scan signal is input, a first electrode connected to a data line to which a data voltage signal is applied, and a second electrode connected to the first node; and a capacitor unit connected between a high-potential voltage input line and the second node to store a data voltage compensated by a threshold voltage.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2025-0008196, filed on January 20, 2025, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0002] This disclosure relates to display devices. Background Technology

[0003] Electroluminescent displays (EMDs) have advantages such as fast response time, high luminous efficiency, and wide viewing angle, and are therefore widely used as display devices. Based on the material of the light-emitting layer, EMDs are classified into inorganic EMDs and organic EMDs. Each pixel of an EMD may include a self-emissive element and at least one transistor for driving the light-emitting element.

[0004] Such electroluminescent displays display images based on light generated from light-emitting elements, and therefore have various advantages. However, to improve image quality, it is necessary to improve the accuracy of the pixel driving circuitry that controls the light emission from the light-emitting elements. Summary of the Invention

[0005] Therefore, this disclosure relates to display devices that substantially eliminate one or more problems caused by the limitations and disadvantages of related technologies.

[0006] The embodiments disclosed herein are intended to solve the problems mentioned above and to provide a display device that can improve the operational accuracy of subpixels.

[0007] Additional advantages, objects, and features of this disclosure will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon reviewing the following, or may be learned by practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in its written description and claims, and in the accompanying drawings.

[0008] To achieve these and other advantages, and for the purposes of this disclosure, as embodied and broadly described herein, a display device includes: a light-emitting element; a driving TFT including a first electrode connected to a first node, a first gate electrode connected to a second node, and a second electrode connected to a third node, and the driving TFT being configured to apply a voltage based on a data voltage signal applied to the first node to the second node during a threshold voltage sampling period, generate a driving current based on the voltage applied to the second node using a high potential voltage applied to the first node during an emission period, and apply the driving current to the third node; a first switching TFT including a gate electrode to which a first scan signal is input, a first electrode connected to the second node, and a second electrode connected to the third node; a second switching TFT including a gate electrode to which a second scan signal is input, a first electrode connected to a data line to which a data voltage signal is applied, and a second electrode connected to the first node; and a capacitor unit connected between the high potential voltage input line and the second node to store a data voltage compensated by a threshold voltage, wherein the capacitance of the capacitor unit decreases during the threshold voltage sampling period and increases during the emission period.

[0009] The capacitor unit may include: a first capacitor including a first electrode connected to a second node and a second electrode connected to a fifth node; a second capacitor including a first electrode connected to the fifth node and a second electrode connected to an input line of a high potential voltage; and a first switch configured to interconnect the first and second capacitors during a threshold voltage sampling period and to connect the fifth node to the input line of a high potential voltage during periods other than the threshold voltage sampling period.

[0010] The first switch may include a gate electrode configured to receive a second scan signal, a first electrode connected to an input line with a high potential voltage, and a second electrode connected to a fifth node, and the first switch may be turned on and off in the opposite manner to the on / off operation of the second switch TFT.

[0011] The driving TFT may include a second gate electrode of the bottom gate, and the display device may also include a gate control circuit configured to connect the second gate electrode of the driving TFT to a second node during a threshold voltage sampling period, and to connect the second gate electrode of the driving TFT to a high-potential voltage input line during periods other than the threshold voltage sampling period.

[0012] The gate control circuit may include: a second switch, the second switch including a gate electrode configured to receive a second scan signal, a first electrode connected to a second node, and a second electrode connected to a second gate electrode of a driving TFT; and a third switch, the third switch including a gate electrode configured to receive the second scan signal, a first electrode connected to an input line of a high potential voltage, and a second electrode connected to a second gate electrode of a driving TFT, wherein the second switch can be turned on and off synchronously with the on / off operation of the second switch TFT, and the third switch can be turned on and off opposite to the on / off operation of the second switch TFT.

[0013] The second switch TFT may include a P-type TFT, and the third switch may include an N-type TFT.

[0014] A semiconductor layer, a first metal layer, and a gate metal layer can be stacked sequentially on a light-shielding pattern. A first VDD pattern configured to apply a high potential voltage can be formed in the light-shielding pattern. A first node can be formed in the semiconductor layer. A second VDD pattern configured to apply a high potential voltage and a first metal first scan line pattern configured to transmit a first scan signal can be formed in the first metal layer. A gate metal first scan line pattern can be formed in the gate metal layer at the position where it overlaps with the first metal first scan line pattern. The first VDD pattern can be formed to extend further than the second VDD pattern.

[0015] The first VDD pattern can be formed as an extension from the semiconductor layer to the region where no active semiconductor layer is formed.

[0016] A semiconductor layer, a first gate metal layer, a first metal layer, and a second gate metal layer can be stacked sequentially on a light-shielding pattern. A first VDD pattern configured to apply a high potential voltage can be formed in the light-shielding pattern. A first node can be formed in the semiconductor layer. A second scan line pattern configured to apply a first scan signal can be formed in the first gate metal layer. A second VDD pattern configured to apply a high potential voltage and a first metal first scan line pattern configured to transmit the first scan signal can be formed in the first metal layer. A gate metal first scan line pattern can be formed in the second gate metal layer at a position overlapping with the first metal first scan line pattern. The second scan line pattern, the first metal first scan line pattern, and the gate metal first scan line pattern can be formed to overlap in the same region.

[0017] The first VDD pattern can be formed to extend further than the second VDD pattern.

[0018] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0019] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0020] Figure 1 This is a schematic block diagram of a display device;

[0021] Figure 2 It is a circuit diagram of the sub-pixels included in the display device;

[0022] Figure 3 yes Figure 2 Waveform diagrams of the scanning signal and transmission control signal of the sub-pixel;

[0023] Figures 4 to 6 It is shown Figure 2 A diagram of the driving method in each driving period of the sub-pixel;

[0024] Figures 7 to 9 It is used to describe in Figure 2 A diagram showing the sampling errors occurring in the sub-pixels;

[0025] Figure 10 and Figure 11 This is a circuit diagram used to describe the error reduction structure of a sub-pixel according to a first embodiment of the present disclosure;

[0026] Figures 12 to 14 This is a circuit diagram used to describe the error reduction structure of a sub-pixel according to the second embodiment of the present disclosure;

[0027] Figure 15 and Figure 16 This is a circuit diagram used to describe the sub-pixel error reduction structure according to the third embodiment of this disclosure; and

[0028] Figure 17 and Figure 18 This is a circuit diagram used to describe the sub-pixel error reduction structure according to the fourth embodiment of the present disclosure. Detailed Implementation

[0029] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become clear from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below and can be implemented in various different forms. These embodiments are provided only to complete the disclosure and to enable those skilled in the art to fully understand the scope of the invention.

[0030] The shapes, dimensions, ratios, angles, numbers, etc., disclosed in the accompanying drawings describing embodiments of this disclosure are exemplary, and therefore this disclosure is not limited to the matters shown. Throughout the specification, the same reference numerals denote the same parts. When terms such as "comprising," "having," and "consisting of" are used in this disclosure, additional parts may be added unless "only" is used. When a part is indicated in the singular, this includes cases where the parts are plural, unless there is a particularly explicit description to the contrary.

[0031] When interpreting a component, it is interpreted as including a range of errors, even if there is no separate, explicit description.

[0032] When describing positional relationships, such as when the positional relationship between two parts is described as "on top of", "above", "below", "adjacent to", etc., one or more other parts may be located between the two parts, unless "closely to" or "directly" is used.

[0033] Although the terms "first," "second," etc., can be used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the "first component" mentioned below can be a "second component" within the technical concept of this disclosure.

[0034] Furthermore, each of the pixel circuits and gate drivers in the display device described below may include multiple transistors. The transistors may be implemented as oxide thin-film transistors (TFTs) including oxide semiconductors, LTPS TFTs including low-temperature polycrystalline silicon (LTPS), etc. Each transistor may be implemented as a p-channel TFT or an n-channel TFT.

[0035] A transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. Inside the transistor, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-channel transistor, current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, this disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0036] The gate signal oscillates between the gate on-voltage and the gate off-voltage. The gate on-voltage is set to a voltage higher than the transistor's threshold voltage, and the gate off-voltage is set to a voltage lower than the transistor's threshold voltage. The transistor turns on in response to the gate on-voltage and turns off in response to the gate off-voltage. In an n-channel transistor, the gate on-voltage can be gate high (VGH), and the gate off-voltage can be gate low (VGL). In a p-channel transistor, the gate on-voltage can be VGL, and the gate off-voltage can be VGH.

[0037] Each pixel of an electroluminescent display device includes a light-emitting element and a driving element. The driving element generates a pixel current based on the voltage between the gate and the source to drive the light-emitting element. The light-emitting element includes an anode, a cathode, and an organic compound layer formed between these electrodes. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emitter layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When the pixel current flows in the light-emitting element, holes passing through the HTL and electrons passing through the ETL move to the EML, thereby forming excitons, and thus, the EML can emit visible light.

[0038] Recently, there has been an increasing trend of implementing some transistors, including those in the pixel circuitry of electroluminescent display devices, as oxide transistors. Oxide transistors use an oxide called IGZO instead of polycrystalline silicon as the semiconductor material. IGZO is a combination of In (indium), Ga (gallium), Zn (zinc), and O (oxygen).

[0039] Oxide transistors (OTs) exhibit low turn-off current and therefore offer advantages in high drive stability and reliability during low-speed operation with relatively long turn-off periods. Consequently, OTs can be used in large liquid crystal display devices requiring high resolution and low power operation, or in OLED TVs where the screen size is unsuitable for low-temperature polycrystalline silicon processes.

[0040] The display device according to this embodiment can be implemented as a television, video player, personal computer (PC), home theater, automotive electronics, smartphone, etc., but this disclosure is not limited thereto. The display device according to the embodiments of this disclosure can be implemented as a light-emitting diode (LED) display, a quantum dot (QDD) display device, a liquid crystal display (LCD) device, etc. However, for ease of explanation, a display device based on direct light emission from inorganic or organic light-emitting diodes will be used as an example below.

[0041] Throughout this specification, the same reference numerals refer to substantially the same parts. Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In the following description, detailed descriptions of known functions or configurations related to this disclosure are omitted where such unnecessarily obscure the gist of the disclosure.

[0042] Figure 1 It is a block diagram that schematically illustrates the configuration of the display device.

[0043] Reference Figure 1 The display device may include an image supply unit 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, a power supply 180, etc.

[0044] The image supply unit 110 can output various drive signals as well as image data signals supplied from an external source or stored in an internal memory. The image supply unit 110 can supply data signals and various drive signals to the timing controller 120. The image supply unit 110 can be any of a TV system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, wearable device, or vehicle system.

[0045] In the display panel 150, multiple data lines DL1 to DLn and multiple gate lines GL1 to GLm intersect, and sub-pixels SP are arranged in a matrix at the corresponding intersection areas. Each sub-pixel SP is connected to both the gate line GL and the data line DL. A sub-pixel SP can receive a gate signal from the gate driver 130 via the gate line GL and a data signal from the data driver 140 via the data line DL. Here, the gate line GL can supply a scan signal Scan and an emission control signal EM, and the data line DL can supply a data voltage Vdata. Each sub-pixel SP includes a light-emitting element and a pixel circuit that controls the amount of current applied to the anode of the light-emitting element. The pixel circuit may include a driving transistor that controls the amount of current so that a constant current can flow to the light-emitting element. The light-emitting element emits light during the emission period and does not emit light during other periods. During the periods other than the emission period, initialization, programming, and resetting of the light-emitting element can be performed on the pixel circuit.

[0046] The timing controller 120 can output a gate timing control signal GDC for controlling the operating timing of the gate driver 130, a data timing control signal DDC for controlling the operating timing of the data driver 140, and various synchronization signals (Vsync as a vertical synchronization signal and Hsync as a horizontal synchronization signal). The timing controller 120 can supply the data signal DATA supplied from the image supply unit 110 together with the data timing control signal DDC to the data driver 140. The timing controller 120 can be formed as an IC (integrated circuit) and mounted on a printed circuit board, but this disclosure is not limited thereto.

[0047] The data driver 140 can sample and latch the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, convert the digital data signal into an analog data voltage based on a gamma reference voltage, and output the analog data voltage. The data driver 140 can supply data voltage to the sub-pixels included in the display panel 150 via data lines DL1 to DLn. The data driver 140 can be formed as an IC and mounted on the display panel 150 or a printed circuit board, but this disclosure is not limited thereto.

[0048] The gate driver 130 can output scan and transmit signals in response to a gate timing control signal GDC supplied from the timing controller 120. The gate driver 130 can supply at least one scan and transmit signal to the sub-pixels SP included in the display panel 150 via gate lines GL1 to GLm. The gate driver 130 can be formed as an IC or can be formed directly on the display panel 150 as an in-panel gate.

[0049] The power supply 180 can convert externally supplied power into the power required to drive the display device, and output the power under the control of the timing controller 120. For example, the power supply 180 can convert externally supplied power into a high-potential voltage EVDD, a low-potential voltage EVSS, etc., and output the power. The power supply 180 can also generate and output the voltage required to drive the gate driver 130 or the voltage required to drive the data driver 140.

[0050] Figure 2 It is a circuit diagram of the sub-pixels included in the display device. Figure 3 yes Figure 2 The waveform diagram of the scanning signal and transmission control signal of the sub-pixel. Figures 4 to 6 It is shown Figure 2 A diagram of the driving method for each driving period of a subpixel.

[0051] Reference Figure 2 A sub-pixel SP can be supplied with a high potential voltage EVDD, a low potential voltage EVSS, an initialization voltage Vini, a conduction bias stress (OBS) voltage Vobs, and an anode reset voltage VAR, and can receive the first scan signal Scan1 to the fourth scan signal Scan4, the transmit signal EM, and the data voltage signal Vdata.

[0052] A sub-pixel SP may include an OLED (Organic Light Emitting Diode), a driving TFT DT, a first capacitor C1, and first switching TFTs T1 through seventh switching TFTs T7. Each TFT of the sub-pixel SP may be configured as a p-type MOSFET (PMOS) or an n-type MOSFET (NMOS). In this embodiment, the following example is used for illustration, in which the first switching TFT T1 and the fifth switching TFT T5 are implemented as n-type, and the remaining switching TFTs T2 through T4 and T6 through T7, as well as the driving TFT DT, are implemented as p-type. Therefore, when a high voltage is applied to the gate electrode, the first switching TFT T1 and the fifth switching TFT T5 are turned on, and when a low voltage is applied to the gate electrode, the remaining switching TFTs T2 through T4 and T6 through T7, as well as the driving TFT DT, are turned on.

[0053] According to embodiments of the present disclosure, in a sub-pixel circuit, a first switch TFT T1 can be used as a compensation transistor, a second switch TFT T2 can be used as a data supply transistor, a third switch TFT T3 and a fourth switch TFT T4 can be used as emission control transistors, a fifth switch TFT T5 can be used as an initialization transistor, a sixth switch TFT T6 can be used as an anode reset transistor, and a seventh switch TFT T7 can be used as a conduction bias transistor.

[0054] OLEDs emit light by a driving current supplied from the driving TFT DT. The anode of the OLED can be connected to the fourth node N4, and the cathode of the OLED can be connected to wiring supplied with a low potential voltage EVSS.

[0055] The driving TFT DT can have a gate electrode connected to the second node N2, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The driving TFT DT can generate a driving current supplied to the OLED based on the voltage of the second node N2. The driving TFT DT can be formed as a four-terminal transistor with dual gate electrodes. When the driving TFT DT is a four-terminal transistor, the top gate can be connected to the second node N2, and the bottom gate can be in contact with VDD. The structure of the four-terminal transistor will be described in more detail later.

[0056] The first capacitor C1 has: one electrode connected to a second node N2, which is connected to the gate electrode of the driving TFT DT; and another electrode connected to the input line of the high-potential voltage EVDD. The first capacitor C1 can store data voltage for a certain period of time and provide the data voltage to the OLED. The first capacitor C1 can be used as a storage capacitor.

[0057] The first switch TFT T1 can be turned on in response to the first scan signal Scan1. When the first switch TFT T1 is turned on, the second node N2 and the third node N3 can be interconnected. Therefore, the gate electrode of the driving TFT DT and the second electrode, which is the drain electrode, are interconnected, so that the driving TFT DT can be switched to a diode-connected state. The first switch TFT T1 may include a gate electrode connected to the input line of the first scan signal Scan1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The first switch TFT T1 may be an NMOS and may be implemented as an oxide TFT to have a low turn-off current and minimize leakage current during the turn-off period. Therefore, the first switch TFT T1 is turned on in response to the first scan signal Scan1 at a high level as the turn-on voltage, and the threshold voltage Vth of the driving TFT DT can be sampled by connecting the diodes of the second node N2 and the third node N3. The first switch TFT T1 may be a compensation transistor.

[0058] The second switch TFT T2 can be turned on in response to the second scan signal Scan2. When the second switch TFT T2 is turned on, a data voltage signal Vdata is applied to the first node N1, which serves as the first electrode driving the TFT DT. The second switch TFT T2 may include a gate electrode connected to the input line of the second scan signal Scan2, a first electrode connected to the data line supplied with the data voltage signal Vdata, and a second electrode connected to the first node N1. The second switch TFT T2 can apply the data voltage signal Vdata supplied from the data line to the first node N1 in response to the second scan signal Scan2 at a low level, which is the turn-on voltage, and the first node N1 serves as the first electrode driving the TFT DT. The second switch TFT T2 may be a data supply transistor.

[0059] A control operation is performed to simultaneously turn the third switch TFT T3 and the fourth switch TFT T4 on / off according to the emission signal EM simultaneously input to the corresponding gate electrodes of the third switch TFT T3 and the fourth switch TFT T4. The third switch TFT T3 and the fourth switch TFT T4 can control whether the OLED emits light. The third switch TFT T3 may have a first electrode connected to the input line of the high potential voltage EVDD and a second electrode connected to the first node N1. The third switch TFT T3 can be used to transmit the high potential voltage EVDD to the first electrode of the driving TFT DT in response to the emission signal EM. The fourth switch TFT T4 may have a first electrode connected to the third node N3 and a second electrode connected to the fourth node N4. The fourth switch TFT T4 can be used to transmit a driving current to the anode of the OLED in response to the emission signal EM. The third switch TFT T3 and the fourth switch TFT T4 may be emission control transistors.

[0060] The fifth switch TFT T5 can be turned on in response to the fourth scan signal Scan4. The fifth switch TFT T5 is turned on to apply an initialization voltage Vini to the second node N2, which serves as the gate electrode of the driving TFT DT. The fifth switch TFT T5 may include a gate electrode connected to the input line of the fourth scan signal Scan4, a first electrode connected to the input line of the initialization voltage Vini, and a second electrode connected to the second node N2. The fifth switch TFT T5 can initialize the gate electrode of the driving TFT DT by applying the initialization voltage Vini to the second node N2 in response to the fourth scan signal Scan4 at a high level, which serves as the turn-on voltage. The fifth switch TFT T5 may be an initialization transistor.

[0061] The sixth switch TFT T6 can be turned on in response to the third scan signal Scan3. The sixth switch TFT T6 is turned on to apply the anode reset voltage VAR to the anode of the OLED. The sixth switch TFT T6 may include a gate electrode connected to the input line of the third scan signal Scan3, a first electrode connected to the input line of the anode reset voltage VAR, and a second electrode connected to the fourth node N4. The sixth switch TFT T6 can apply the anode reset voltage VAR to the anode of the OLED in response to the third scan signal Scan3 at a low level, which is the turn-on voltage. The sixth switch TFT T6 can be an anode reset transistor.

[0062] The seventh switch TFT T7 can be turned on in response to the third scan signal Scan3. The seventh switch TFT T7 is turned on to apply the OBS voltage Vobs to the first electrode of the driving TFT DT. The seventh switch TFT T7 may include a gate electrode connected to the input line of the third scan signal Scan3, a first electrode connected to the input line of the OBS voltage Vobs, and a second electrode connected to the first node N1. The seventh switch TFT T7 can apply the OBS voltage Vobs to the first electrode of the driving TFT DT in response to the third scan signal Scan3 at a low level, which is the turn-on voltage. The seventh switch TFT T7 may be a bias transistor.

[0063] Figure 3 It is a description Figure 2 A diagram showing the operation of the scanning signal and emission control signal of the sub-pixel. Figures 4 to 6 It is shown Figure 2 A diagram of the driving method for each driving period of a subpixel.

[0064] Reference Figure 3 The driving period for a subpixel may include an initialization period Ti, a sampling period Ts, an emission period Te, and at least one bias period OBS1 and OBS2. The initialization period Ti and the sampling period Ts may be performed during the non-emission period when the emission signal EM is applied at a shutdown level. During this non-emission period, multiple OBS operations may be performed.

[0065] During the first bias period OBS1, the first scan signal Scan1 and the third scan signal Scan3 are applied at an on level. In response to the first scan signal Scan1 being applied at a high voltage as an on level, the first switch TFT T1 is turned on, allowing the second node N2 and the third node N3 to interconnect to interconnect the gate electrode and drain electrode of the driving TFT DT, the drain electrode being the second electrode. In response to the third scan signal Scan3 being applied at a low voltage as an on level, the seventh switch TFT T7 is turned on, allowing the bias voltage Vobs to be applied to the first electrode of the driving TFT DT. In response to the third scan signal Scan3 being applied at a low voltage as an on level, the sixth switch TFT T6 is turned on, allowing the anode reset voltage VAR to be applied to the anode of the OLED.

[0066] Reference Figure 3 and Figure 4 The pixel driving circuit can be operated by including an initialization period Ti. The initialization period Ti is a period in which the voltage of the second node N2, which is connected to the gate electrode of the driving TFT DT, is initialized.

[0067] During the initialization period Ti, the fourth scan signal Scan4 is applied at an on level. In response to the application of a high voltage, which is the on level, the fifth switch TFT T5 is turned on to apply the initialization voltage Vini to the second node N2, which serves as the gate electrode of the driving TFT DT. Therefore, the gate electrode of the driving TFT DT can be initialized to the initialization voltage Vini.

[0068] Reference Figure 3 and Figure 5The pixel driving circuit can operate by including a sampling period Ts. The sampling period Ts is the period during which the threshold voltage Vth of the driving TFT DT is sampled and the data voltage Vdata is programmed. During the sampling period Ts, the first scan signal Scan1 and the second scan signal Scan2 are applied at an on level. In response to the first scan signal Scan1 being applied at a high voltage as the on level, the first switch TFT T1 is turned on, allowing the driving TFT DT to be diode-connected. In response to the second scan signal Scan2 being applied at a low voltage as the on level, the second switch TFT T2 is turned on, allowing the data voltage signal Vdata to be applied to the first node N1, which serves as the first electrode of the driving TFT DT. Since the data voltage signal Vdata is applied to the first node N1 of the driving TFT DT in the diode-connected state, the second node N2 is charged with a voltage Vdata-|Vth| corresponding to the difference between the data voltage Vdata and the threshold voltage Vth of the driving TFT DT by the current flowing from the source electrode to the drain electrode. Therefore, when the sampling period Ts is completed, the threshold voltage Vth can be sampled at the first capacitor C1.

[0069] During the second bias period OBS2, the third scan signal Scan3 is applied at an on level. In response to the third scan signal Scan3 being applied at a low voltage as the on level, the seventh switch TFT T7 is turned on, allowing the bias voltage Vobs to be applied to the first electrode of the driving TFT DT. In response to the third scan signal Scan3 being applied at a low voltage as the on level, the sixth switch TFT T6 is turned on, allowing the anode reset voltage VAR to be applied to the anode of the OLED.

[0070] Reference Figure 3 and Figure 6 The emission period Te is the period during which the OLED emits light using a driving current, which corresponds to a sampled data voltage offset by a sampling threshold voltage Vth.

[0071] During the transmission period Te, the transmission signal EM is applied at a conduction level. In response to the application of a low voltage as the conduction level to the transmission signal EM, the third switch TFT T3 and the fourth switch TFT T4 are simultaneously turned on. When the third switch TFT T3 and the fourth switch TFT T4 are turned on, the first electrode of the driving TFT DT can be connected to the input line of the high-potential voltage EVDD, and the second electrode can be connected to the anode of the OLED. Therefore, the driving TFT DT can apply a driving current corresponding to the data voltage to the OLED, causing the OLED to emit light.

[0072] As mentioned above, having such Figure 2The configured sub-pixels can sample the threshold voltage Vth during the sampling period Ts and emit light from the OLED using a driving current during the emission period Te, the driving current corresponding to the data voltage Vdata compensated by the threshold voltage Vth. Therefore, to improve the driving accuracy of the sub-pixels, methods to reduce errors occurring during the sampling period can be sought.

[0073] Figure 7 and Figure 8 It is used to describe in Figure 2 The image shows the sampling error that occurs in the sub-pixels. Figure 7 This is a diagram showing the regions in a sub-pixel where sampling errors occur. Figure 8 This is a graph showing the voltage changes at the first node N1 and the second node N2 during the sampling period, and Figure 9 It is shown Figure 2 The diagram shows the structure of a four-terminal TFT.

[0074] As described above, during the sampling period Ts, the first scan signal Scan1 and the second scan signal Scan2 are applied at the on level, causing the first switch TFT T1 and the second switch TFT T2 to be turned on. When the first switch TFT T1 is turned on, the driving TFT DT is connected by a diode, and the second switch TFT T2 is turned on, causing the data voltage signal Vdata to be applied to the first node N1, which serves as the first electrode of the driving TFT DT.

[0075] Reference Figure 8 When the second scan signal Scan2 is applied at the on level (Scan2 is on), the voltage of the first node N1 can rise to the voltage of the data voltage signal Vdata. Since the driving TFT DT is connected by a diode, when the data voltage signal Vdata is applied to the first node N1, the current Ids flows between the source and drain. The second node N2 is charged with a voltage Vdata-|Vth| corresponding to the difference between the data voltage Vdata of the driving TFT DT and the threshold voltage Vth by the current flowing from the source electrode to the drain electrode. Therefore, the voltage difference Vgs between the first node N1 and the second node N2 is maintained at ΔVth, which is the threshold voltage of the driving TFT DT, and when the first scan signal Scan1 and the second scan signal Scan2 are switched to the off state (Scan1 on -> off), the voltage Vdata-|Vth| of the second node N2 (i.e., the data voltage compensated by the threshold voltage) can be maintained by the first capacitor C1.

[0076] However, in reality, the voltage difference Vgs between the first node N1 and the second node N2 in the sub-pixel may be different from the threshold voltage ΔVth driving the TFT DT (Vgs≠ΔVth), or there may be sampling errors, in which errors occur in the data voltage Vdata-|Vth| compensated by the threshold voltage stored and maintained in the first capacitor C1.

[0077] In the first case (Case 1), sampling errors may occur due to the capacitance of the first capacitor C1. The first capacitor C1 needs to be able to maintain the voltage of the second node N2 below Vdata-|Vth| during the emission period Te. Since the retention characteristic is more advantageous when the capacitance is larger, the first capacitor C1 is designed to have a capacitance larger than a specific value. On the other hand, since the sampling error increases with the capacitance, errors may occur when sampling the threshold voltage Vth.

[0078] In the second scenario (Scenario 2), sampling errors may occur due to changes in the driving characteristics of the driving TFT DT. The driving TFT DT formed on the display panel is a four-terminal transistor, with its bottom gate contacting VDD. (See reference...) Figure 9The diagram illustrates the structure of a four-terminal transistor, which may include a bottom gate electrode 12, a top gate electrode 26, a first electrode 18, and a second electrode 20. It may include a bottom gate electrode 12 formed on a substrate 30, a gate insulating film 14 formed on the bottom gate electrode 12, a first electrode 18 formed on the gate insulating film 14, and a second electrode 20 spaced apart from the first electrode 18. A semiconductor layer 16 forming a channel is formed between the first electrode 18 and the second electrode 20, and may include an etch stop 22 formed on the semiconductor layer 16 to protect it, an interlayer insulating film 24 covering the entire surface of the substrate 30 including the first electrode 18, the second electrode 20, and the etch stop 22, and a top gate electrode 26 formed on the interlayer insulating film 24 facing the bottom gate electrode 12. Here, the bottom gate electrode 12 may be formed using a bottom shielding metal (BSM). When the voltage applied to the BSM is the same as the voltage VGS between the top gate and the source, the operating characteristics of the driving TFT DT are unaffected. However, when the voltage applied to the BSM differs from the voltage VGS between the top gate and the source, the formation of the current channel is affected, causing fluctuations in the operating characteristics of the driving TFT DT, such as the threshold voltage Vth. When the bottom gate of the driving TFT DT is in contact with VDD, the bottom gate's Vgs has a smaller value than the top gate's Vgs at sampling time. For example, the bottom gate's Vgs is at a level of -2V to 3V, while the top gate's Vgs is at a level of -8V to -3V, and therefore the operating voltages are different. In this way, errors may occur when sampling the threshold voltage Vth due to the difference in operating voltage Vgs between the bottom and top gates.

[0079] In the third case (Case 3), when the first scan signal Scan1 is turned off after the threshold voltage Vth is sampled, the voltage of the first node N1 fluctuates due to backlash, which may cause errors during the sampling period.

[0080] Figure 10 and Figure 11 This is a circuit diagram describing the sub-pixel error reduction structure according to a first embodiment of the present disclosure. As described in the first case (Case 1), the sub-pixel error reduction structure according to the first embodiment of the present disclosure can reduce the sampling error that occurs due to the large capacitance of the first capacitor C1 when sampling the threshold voltage Vth.

[0081] The sub-pixel circuit according to the first embodiment of this disclosure and Figure 2 The difference in the sub-pixels lies in the fact that the sub-pixel circuit includes a multi-capacitor circuit 200 in the connection line between the first capacitor C1 and the input line of the high-potential voltage EVDD. This is because other configurations perform... Figure 2The subpixels have the same function, so only the different configurations will be described in detail below.

[0082] The multi-capacitor circuit 200 according to the first embodiment may include a second capacitor Cc and an eighth switch TFTT8.

[0083] The second capacitor Cc has: one electrode connected to the input line of the high-potential voltage EVDD; and another electrode connected to the fifth node N5, which is connected to the first capacitor C1. Therefore, the first capacitor C1 and the second capacitor Cc can be connected in series.

[0084] The eighth switch TFT T8 can be turned on in response to the second scan signal Scan2. The eighth switch TFT T8 may include a gate electrode connected to the input line of the second scan signal Scan2, a first electrode connected to the input line of the high potential voltage EVDD, and a second electrode connected to the fifth node N5. Therefore, the eighth switch TFT T8 can be connected in series with the first capacitor C1 and in parallel with the second capacitor Cc.

[0085] The second capacitor Cc and the eighth switch TFT T8 can be connected in parallel between the input line of the high potential voltage EVDD and the fifth node N5, so that when the eighth switch TFT T8 is turned on, the high potential voltage EVDD can be applied to the fifth node N5, and when the eighth switch TFT T8 is turned off, the second capacitor Cc can be connected between the input line of the high potential voltage EVDD and the fifth node N5.

[0086] When the eighth switch TFT T8 is turned on, a high-potential voltage EVDD is applied to the fifth node N5. Therefore, the voltage across the second capacitor Cc is set to be the same as the high-potential voltage EVDD, and thus the capacitance of the second capacitor Cc becomes 0. Therefore, as in Figure 11 In the circuit of the [comparative example], only the first capacitor C1 operates, and therefore the operation can be similar to... Figure 2 Operations on subpixels.

[0087] When the eighth switch TFT T8 is turned off, the second capacitor Cc can be connected between the high-potential voltage EVDD input line and the fifth node N5. Therefore, as in Figure 11 In the circuit of the [first embodiment], the first capacitor C1 and the second capacitor Cc can be connected in series. When the two capacitors are connected in series, as shown in the following <mathematical formula>, the total capacitance Total CST can be calculated as the reciprocal of the sum of the reciprocals of the capacitances CST1 and CST2 of the two capacitors.

[0088] <Mathematical Formulas>

[0089]

[0090] As can be seen from the above mathematical formula, when the first capacitor C1 and the second capacitor Cc are connected in series, the resulting capacitance is less than the capacitance of each individual capacitor.

[0091] When sampling the threshold voltage Vth of the driving TFT DT, it is advantageous to apply the smallest possible capacitance to shorten the sampling time and reduce sampling error. Therefore, the eighth switch TFT T8 can be configured to be off only during the sampling period. For example, the eighth switch TFT T8 can receive the same scan signal (i.e., the second scan signal Scan2) as the second switch TFT T2, which is turned on only during the sampling period to apply the data voltage signal Vdata, and is configured as a TFT of the opposite type to the second switch TFT T2, so as to perform the on / off operation in the opposite manner to the second switch TFT T2. For example, an n-type TFT that is turned off when the second scan signal Scan2 input to the gate electrode is low can be applied to the eighth switch TFT T8.

[0092] According to the first embodiment of the present disclosure, the sub-pixel circuit can add a second capacitor Cc connected in series with the first capacitor C1 to reduce the capacitance when sampling the threshold voltage Vth, thereby reducing the sampling error.

[0093] Figures 12 to 14 This is a circuit diagram illustrating the sub-pixel error reduction structure according to the second embodiment of the present disclosure. The sub-pixel error reduction structure according to the second embodiment of the present disclosure can reduce the sampling error that occurs due to the change in the driving characteristics of the driving TFT DT described in the second case (case 2).

[0094] The sub-pixel circuit according to the second embodiment of this disclosure and Figure 2 The difference in the sub-pixels lies in that the sub-pixel circuitry includes a dual-gate control circuit 300 that controls the bottom gate of the driving TFT DT'. This is because other configurations perform... Figure 2 The subpixels have the same function, so only the different configurations will be described in detail below.

[0095] Reference Figure 12 In the sub-pixel circuit according to the second embodiment, the driving TFT DT' is provided as a four-terminal transistor. The first gate electrode g1, which serves as the top gate of the driving TFT DT', is connected to the second node N2. The second gate electrode g2, which serves as the bottom gate, can be controlled by the dual-gate control circuit 300.

[0096] The dual-gate control circuit 300 interconnects the second gate electrode g2 with the first gate electrode g1, such that when the threshold voltage Vth is sampled, the Vgs of the bottom gate and the Vgs of the top gate remain the same. During periods other than when the threshold voltage Vth is sampled, the dual-gate control circuit 300 prevents changes in the threshold voltage Vth driving the TFT DT' by connecting the second gate electrode g2 (which serves as the bottom gate) to the input line of VDD. Here, VDD and EVDD have the same voltage level supplied from the same power supply.

[0097] The dual-gate control circuit 300 can be controlled by the same scan signal as the scan signal of the second switch TFT T2 (i.e., the second scan signal Scan2), which is turned on only during the sampling period to apply the data voltage signal Vdata. For example, the dual-gate control circuit 300 may include a ninth switch TFT T9 and a tenth switch TFT T10 that receive the second scan signal Scan2 through a common electrode.

[0098] The ninth switch TFT T9 may include a gate electrode connected to the second scan signal Scan2, a first electrode connected to the second node connected to the first gate electrode g1, and a second electrode connected to the second gate electrode g2. The ninth switch TFT T9 may be implemented as the same type as the second switch TFT T2 to which the data voltage signal Vdata is applied, such as a p-type TFT.

[0099] The tenth switch TFT T10 may include a gate electrode connected to the second scan signal Scan2, a first electrode connected to the input line VDD, and a second electrode connected to the second gate electrode g2. The tenth switch TFT T10 may be implemented as a type opposite to the second switch TFT T2 to which the data voltage signal Vdata is applied, such as an n-type TFT.

[0100] Figure 13 This is a diagram illustrating the operation of the dual-gate control circuit 300 when the second scan signal Scan2 is input at a low level, and Figure 14 This is a diagram illustrating the operation of the dual-gate control circuit 300 when the second scan signal Scan2 is input at a high level.

[0101] Reference Figure 13 When the second scan signal Scan2 is input at a low level, the data voltage signal Vdata is applied to the driving TFT DT'. The ninth switch TFT T9 is turned on in response to the second scan signal Scan2 being at a low level. The turned-on ninth switch TFT T9 interconnects the second gate electrode g2 and the first gate electrode g1. When the second scan signal Scan2 is input at a low level, the tenth switch TFT T10 is turned off.

[0102] Reference Figure 14 When the second scan signal Scan2 is input at a high level, the tenth switch TFT T10 is turned on. The turned-on tenth switch TFT T10 connects the second gate electrode g2 to the input line of VDD. When the second scan signal Scan2 is input at a high level, the ninth switch TFT T9 is turned off.

[0103] The sub-pixel circuit according to the second embodiment of the present disclosure includes a dual-gate control circuit 300 that connects a second gate electrode g2 to a first gate electrode g1, such that when the threshold voltage Vth driving the TFT DT' is sampled, the Vgs of the bottom gate and the Vgs of the top gate can remain the same, thereby reducing the error that occurs when sampling the threshold voltage Vth.

[0104] Figure 15 and Figure 16 This is a diagram used to describe the sub-pixel error reduction structure according to the third embodiment of this disclosure. Figure 15 This is a plan view showing a portion of a sub-pixel according to a comparative example and a sub-pixel according to a third embodiment of this disclosure, and Figure 16 It is a schematic representation based on Figure 15 A cross-sectional view showing the positional relationship between the wiring of the sub-pixels in the comparative example and the third embodiment.

[0105] The sub-pixel error reduction structure according to the third embodiment of this disclosure can reduce the following sampling error, which occurs due to the change in voltage of the first node N1 caused by the backlash phenomenon when the first scan signal Scan1 is switched to the off level (i.e., from a high state to a low state) after sampling the threshold voltage Vth, as described in the third case (case 3).

[0106] Reference Figure 15 and Figure 16 In a region of a sub-pixel according to the [Comparative Example], a semiconductor layer ACT is disposed on a light-shielding pattern BSM (bottom shielding metal) to which VDD power is applied, a first metal layer TM1 is disposed on the semiconductor layer ACT, and a gate metal layer OGAT is formed on the first metal layer TM1.

[0107] The light-shielding pattern BSM includes a VDD pattern, and the semiconductor layer ACT includes a first node N1. In the region where the VDD pattern and the first node N1 overlap, a capacitance C may be generated between the first node N1 and VDD. Node1-VDD The first metal layer TM1 includes a VDD line pattern and a first scan line SC1. The gate metal layer OGAT includes the first scan line SC1.

[0108] When the voltage applied to the first scan line SC1 formed on the first metal layer TM1 and the first scan line SC1 formed on the gate metal layer OGAT switches from a high state to a low state, the voltage of the adjacent first node N1 may change.

[0109] Compared to the sub-pixel structure according to the [Comparative Example], in the sub-pixel according to the [Third Embodiment], the VDD pattern formed on the light-shielding pattern BSM has an extended size VDD+. Therefore, the area where the VDD pattern overlaps with the first node N1 increases the extended area VDD+, such that the capacitance between the first node N1 and VDD may increase in the extended area (C). Node1-VDD+ Here, the light-shielding pattern BSM can extend into the area where the semiconductor active layer LTPS has not been formed.

[0110] As the capacitance of the first node N1 increases, the voltage of the first node N1 can be maintained stably even when the voltage of the adjacent first scan line SC1 fluctuates.

[0111] The sub-pixel circuit according to the third embodiment of this disclosure can increase the size of the VDD pattern adjacent to the first node N1, thereby increasing the capacitance between the first node N1 and VDD, and thus reducing the error that occurs when sampling the threshold voltage Vth.

[0112] Figure 17 and Figure 18 This is a diagram used to describe the sub-pixel error reduction structure according to the fourth embodiment of this disclosure. Figure 17 This is a plan view showing a portion of a sub-pixel according to a comparative example and a sub-pixel according to a fourth embodiment of this disclosure, and Figure 18 It is a brief illustration Figure 17 A cross-sectional view showing the positional relationship between the wiring of the sub-pixels in the comparative example and the fourth embodiment.

[0113] The sub-pixel error reduction structure according to the fourth embodiment of this disclosure can reduce the following sampling error, which is caused by the change in voltage of the first node N1 due to the backlash phenomenon when the first scan signal Scan1 is switched to the off level after sampling the threshold voltage Vth, as described in the third case (case 3).

[0114] Reference Figure 17 and Figure 18 In a region of a sub-pixel according to the [Comparative Example], the semiconductor layer ACT, the first gate metal layer GAT, the first metal layer TM1, and the second gate metal layer OGAT can be sequentially positioned on a light-shielding pattern BSM to which VDD power is applied.

[0115] The light-shielding pattern BSM includes a VDD pattern, and the semiconductor layer ACT includes a first node N1. The first gate metal layer GAT includes a second scan line SC2, and the first metal layer TM1 includes a VDD line pattern and a first scan line SC1. The second scan line SC2 and the first scan line SC1 may be formed at locations where they do not overlap. The second gate metal layer OGAT includes a first scan line SC1 formed at a location where it overlaps with the first scan line SC1 of the first metal layer TM1.

[0116] In the sub-pixel according to the [Comparative Example], the second scan line SC2 and the first scan line SC1 are formed at positions that do not overlap. Therefore, a capacitance C is generated between the first node N1 and the first scan line SC1. Node1-SC1 The first scan line SC1 is formed in the first metal layer TM1 and the second gate metal layer OGAT. Therefore, when the voltage applied to the first scan line SC1 formed in the first metal layer TM1 and the second gate metal layer OGAT switches from a high state to a low state, the voltage of the first node N1 may change due to the change in capacitance between the first scan line SC1 and the first node N1.

[0117] According to the [fourth embodiment], a first scan line SC1 and a second scan line SC2 are formed at an overlapping position on the first node N1 by a sub-pixel. Therefore, the second scan line SC2 and the first scan line SC1 can be sequentially positioned on the first node N1. The capacitance generated between the first node N1 and the first scan line SC1 can be removed by the second scan line SC2 located between the first node N1 and the first scan line SC1. Therefore, even when the first scan signal Scan1 applied to the first scan line SC1 switches from a high state to a low state and a recoil occurs, the effect of the recoil can be shielded by the second scan line SC2, so that the voltage of the first node N1 can be stably maintained.

[0118] The sub-pixel circuit according to the fourth embodiment of this disclosure can reduce the error that occurs during the sampling of the threshold voltage Vth by forming the first scan line SC1 to overlap with the second scan line SC2 and thereby eliminating the capacitance generated between the first node N1 and the first scan line SC1.

[0119] The display device according to embodiments of the present disclosure can improve the operational accuracy of sub-pixels by applying various error reduction structures that reduce errors occurring during sampling to sub-pixels of an internal compensation structure, wherein the internal compensation structure samples the threshold voltage of the driving TFT and applies a data voltage compensated by the threshold voltage to the gate electrode of the driving TFT.

[0120] The effects of this disclosure are not limited to those described above, and include a wider variety of other effects.

[0121] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments, and various modifications can be made without departing from the technical spirit of the present disclosure. Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical spirit of the present disclosure, but rather to describe it, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of protection of this disclosure should be interpreted by the claims, and all technical concepts within the scope of the claims should be interpreted as included within the scope of the claims of this disclosure.

Claims

1. A display device, comprising: Light-emitting elements; A driving TFT includes a first electrode connected to a first node, a first gate electrode connected to a second node, and a second electrode connected to a third node, and the driving TFT is configured to: apply a voltage based on a data voltage signal applied to the first node to the second node during a threshold voltage sampling period, generate a driving current based on the voltage applied to the second node using a high potential voltage applied to the first node during an emission period, and apply the driving current to the third node; A first switch TFT, the first switch TFT including a gate electrode to which a first scan signal is input, a first electrode connected to the second node and a second electrode connected to the third node; The second switch TFT includes a gate electrode to which a second scan signal is input, a first electrode connected to a data line to which the data voltage signal is applied, and a second electrode connected to the first node. as well as A capacitor unit connected between the high-potential voltage input line and the second node to store a data voltage compensated by a threshold voltage; The capacitance of the capacitor unit decreases during the threshold voltage sampling period and increases during the transmission period.

2. The display device according to claim 1, wherein, The capacitor unit includes: A first capacitor, the first capacitor including a first electrode connected to the second node and a second electrode connected to the fifth node; A second capacitor, comprising a first electrode connected to the fifth node and a second electrode connected to the input line of the high-potential voltage; and A first switch is configured to interconnect the first capacitor and the second capacitor during the threshold voltage sampling period, and to connect the fifth node to the input line of the high potential voltage during periods other than the threshold voltage sampling period.

3. The display device according to claim 2, wherein, The first switch includes a gate electrode configured to receive the second scan signal, a first electrode connected to the input line of the high potential voltage, and a second electrode connected to the fifth node, and the first switch is turned on and off in the opposite manner to the on / off operation of the second switch TFT.

4. The display device according to claim 3, wherein: The second switching TFT includes a P-type TFT; and The first switch includes an N-type TFT.

5. The display device according to claim 1, wherein: The driving TFT includes a second gate electrode with a bottom gate, and The display device further includes a gate control circuit configured to connect the second gate electrode of the driving TFT to the second node during the threshold voltage sampling period, and to connect the second gate electrode of the driving TFT to the input line of the high potential voltage during periods other than the threshold voltage sampling period.

6. The display device according to claim 5, wherein: The gate control circuit includes: The second switch includes a gate electrode configured to receive the second scan signal, a first electrode connected to the second node, and a second electrode connected to the second gate electrode of the driving TFT; and A third switch, comprising a gate electrode configured to receive the second scan signal, a first electrode connected to the input line of the high potential voltage, and a second electrode connected to the second gate electrode of the driving TFT, and The second switch is turned on and off synchronously with the on / off operation of the second switch TFT, and the third switch is turned on and off in the opposite manner to the on / off operation of the second switch TFT.

7. The display device according to claim 6, wherein: The second switching TFT includes a P-type TFT; The second switch includes a P-type TFT; and The third switch includes an N-type TFT.

8. The display device according to claim 1, wherein: A semiconductor layer, a first metal layer, and a gate metal layer are stacked sequentially on a light-shielding pattern. A first VDD pattern configured to apply the high potential voltage is formed in the light-shielding pattern. The first node is formed in the semiconductor layer. A second VDD pattern configured to apply the high potential voltage and a first metal first scan line pattern configured to transmit the first scan signal are formed in the first metal layer. A first scan line pattern of gate metal is formed in the gate metal layer at a position overlapping with the first scan line pattern of the first metal, and The first VDD pattern is formed to extend further than the second VDD pattern.

9. The display device according to claim 8, wherein, The first VDD pattern is formed to extend from the semiconductor layer to the region where no active semiconductor layer is formed.

10. The display device according to claim 1, wherein: A semiconductor layer, a first gate metal layer, a first metal layer, and a second gate metal layer are sequentially stacked on a light-shielding pattern. A first VDD pattern configured to apply the high potential voltage is formed in the light-shielding pattern. The first node is formed in the semiconductor layer. A second scan line pattern configured to apply the first scan signal is formed in the first gate metal layer. A second VDD pattern configured to apply the high potential voltage and a first metal first scan line pattern configured to transmit the first scan signal are formed in the first metal layer. A first scan line pattern of gate metal is formed in the second gate metal layer at a position overlapping with the first scan line pattern of the first metal layer, and The second scan line pattern, the first metal first scan line pattern, and the gate metal first scan line pattern are formed to overlap in the same region.

11. The display device according to claim 10, wherein, The first VDD pattern is formed to extend further than the second VDD pattern.

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