Display panel and display device

Abstract

This invention discloses a display panel and display device, comprising: an array of pixel circuits; the operation of the pixel circuits includes a non-light-emitting stage and a light-emitting stage; in the non-light-emitting stage, the light-emitting control signal received by the pixel circuits is at an invalid level; the display panel includes a first operating mode, in which the light-emitting control signal includes N effective pulses in the light-emitting stage; among the N effective pulse signals, the pulse width of the first m effective pulses is greater than the pulse width of the last N-m effective pulses; wherein, N≥2, 1≤m<N, and m and N are both integers, which can establish a stable bias state for the pixel circuits using the preceding wide pulses in low-brightness, low-grayscale display scenarios, overcome the negative impact of transistor offset characteristics on the charging process, and then achieve fine dimming with subsequent narrow pulses, thereby effectively suppressing the distortion and oscillation of the light-emitting current waveform, significantly reducing SVM, and effectively improving the subjective visual experience.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In existing display driving technologies, PWM (Pulse Width Modulation) combined with multi-pulse settings is often used to achieve wide-range brightness adjustment. In low-brightness, low-grayscale display scenarios, there is a significant degradation in both subjective and objective visual effects of SVM (Flicker Visibility Index). Summary of the Invention

[0003] The present invention provides a display panel and display device to improve the poor visual effect of SVM.

[0004] According to one aspect of the present invention, a display panel is provided, comprising: an array of pixel circuits; The operation of the pixel circuit includes a non-light-emitting stage and a light-emitting stage; in the non-light-emitting stage, the light-emitting control signal received by the pixel circuit is at an invalid level. The display panel includes a first working mode, in which the light emission control signal includes N effective pulses during the light emission phase; Of the N valid pulse signals, the pulse width of the first m valid pulses is greater than the pulse width of the last Nm valid pulses; Where N≥2, 1≤m<N, and m and N are both integers.

[0005] According to another aspect of the present invention, a display device is provided, comprising: the display panel described above.

[0006] The display panel provided by this invention realizes the display function through an array of pixel circuits. The light emission of the pixel circuits is controlled by a light emission control signal. The light emission control signal outputs an invalid level during the non-light emission stage to control the pixel circuits from emitting light. When the display panel is in the first working mode, by setting the light emission control signal to include N effective pulses during the light emission stage, a wider range of continuous adjustment from extremely low brightness to normal brightness can be achieved. This can avoid the negative impact of offset characteristics on the driving current under low brightness and low grayscale conditions, while significantly improving the deep dimming capability of the display panel. Furthermore, by setting the pulse width of the first m effective pulses in the N effective pulse signals to be greater than the pulse width of the last Nm effective pulses, a stable bias state can be established for the pixel circuits using the preceding wide pulses in low brightness and low grayscale display scenarios. This overcomes the negative impact of transistor offset characteristics on the charging process. Then, fine dimming is achieved with subsequent narrow pulses, thereby effectively suppressing the distortion and oscillation of the light emission current waveform, significantly reducing SVM, and effectively improving the subjective visual experience.

[0007] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 2 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention; Figure 5 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention; Figure 6 and Figure 7 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention; Figure 8 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention; Figure 9 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention; Figure 10 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0010] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0011] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0012] As described in the background section, existing display driving technologies often employ PWM (Pulse Width Modulation) combined with multi-pulse settings to achieve wide-range brightness adjustment. However, in low-brightness, low-grayscale display scenarios, the PWM pulse width is significantly compressed, resulting in an extremely short effective light-emitting time within a single cycle. This leads to discontinuous light-emitting waveforms and reduced energy concentration, causing a significant deterioration in both subjective and objective visual effects of SVM (Flicker Visibility Index). Simultaneously, TFTs (Thin Film Transistors) such as Low Temperature Polycrystalline Silicon (LTPS) or Indium Oxide (IGZO) are susceptible to threshold voltage drift under low-grayscale bias driving, resulting in poor consistency in pixel charging and discharging processes. This further exacerbates brightness fluctuations and visual instability in low-light conditions. The coupling effect of these TFT offset characteristics in the low-brightness range makes the screen more prone to problems such as poor SVM visual effects, increased flicker, and uneven grayscale transitions.

[0013] To address the aforementioned technical problems, embodiments of the present invention provide a display panel, comprising: an array of pixel circuits; the operation of the pixel circuits includes a non-light-emitting stage and a light-emitting stage; in the non-light-emitting stage, the light-emitting control signal received by the pixel circuits is at an invalid level; the display panel includes a first operating mode, in which the light-emitting control signal includes N valid pulses in the light-emitting stage; among the N valid pulse signals, the pulse width of the first m valid pulses is greater than the pulse width of the last Nm valid pulses; wherein, N≥2, 1≤m<N, and m and N are both integers.

[0014] The above technical solution achieves display functionality through an array of pixel circuits. The illumination of the pixel circuits is controlled by an illumination control signal, which outputs an invalid level during the non-illuminating phase to prevent the pixel circuits from emitting light. In the first operating mode, by setting the illumination control signal to include N effective pulses during the illumination phase, a wider range of continuous adjustment from extremely low brightness to normal brightness is achieved. This significantly improves the deep dimming capability of the display panel while avoiding the negative impact of transistor offset characteristics on the driving current under low brightness and low grayscale conditions. Furthermore, by setting the pulse width of the first m effective pulses in the N effective pulse signals to be greater than the pulse width of the subsequent Nm effective pulses, a stable bias state can be established for the pixel circuits using the preceding wide pulses in low brightness and low grayscale display scenarios. This overcomes the negative impact of transistor offset characteristics on the charging process, and subsequent narrow pulses achieve fine dimming, effectively suppressing distortion and oscillation of the luminous current waveform. This significantly reduces SVM and effectively improves the subjective visual experience.

[0015] The above outlines the core ideas of this application. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0016] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 1 and Figure 2 The display panel 100 includes an array of pixel circuits 110. The operation of the pixel circuits 110 includes a non-light-emitting stage T1 and a light-emitting stage T2. In the non-light-emitting stage T1, the light-emitting control signal EM received by the pixel circuits 110 is at an invalid level UL. The display panel 100 includes a first operating mode. In the first operating mode Mode1, the light-emitting control signal EM includes N valid pulses AP in the light-emitting stage T2. Among the N valid pulse signals AP, the pulse width of the first m valid pulses AP is greater than the pulse width of the last Nm valid pulses AP. Wherein, N≥2, 1≤m<N, and m and N are both integers.

[0017] For example, the working process of a typical pixel circuit will be explained. Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, such as... Figure 3As shown, the pixel circuit 110 includes a light-emitting element D0, a driving transistor T1, a first light-emitting control transistor T2, a second light-emitting control transistor T3, a data writing transistor T4, a threshold compensation transistor T5, an initialization transistor T6, a reset transistor T7, and a storage capacitor Cst.

[0018] In this configuration, the first terminal of the first light-emitting control transistor T2 is electrically connected to the positive power supply terminal PVDD to receive the positive power supply signal Pvdd, and the second terminal of the first light-emitting control transistor T2 is electrically connected to the first terminal of the driving transistor T1. The gate of the first light-emitting control transistor T2 receives the light-emitting control signal EM. The first terminal of the second light-emitting control transistor T3 is electrically connected to the second terminal of the driving transistor T1, and the second terminal of the second light-emitting control transistor T3 is electrically connected to the anode of the light-emitting element D0. The cathode of the light-emitting element D0 is electrically connected to the negative power supply terminal PVEE to receive the negative power supply signal Pvee, and the gate of the second light-emitting control transistor T3 receives the light-emitting control signal EM. Therefore, the first light-emitting control transistor T2 and the second light-emitting control transistor T3 can be turned on or off under the control of the light-emitting control signal EM. When on, a current path is formed between the positive power supply terminal PVDD and the negative power supply terminal PVEE, allowing the driving current generated by the driving transistor T0 to control the light-emitting element D0 to emit light.

[0019] The first terminal of the data writing transistor T4 receives the data signal Vdata, and the second terminal of the data writing transistor T4 is electrically connected to the first terminal of the driving transistor T1. The gate of the data writing transistor T4 receives the first scan control signal S1. Therefore, the data writing transistor T4 can be turned on or off under the control of the first scan control signal S1, and when on, it writes the data signal Vdata to the first terminal of the driving transistor to refresh the signal at the first terminal of the driving transistor T1. The first terminal of the threshold compensation transistor T5 is electrically connected to the second terminal of the driving transistor T1, and the second terminal of the threshold compensation transistor T5 is electrically connected to the gate of the driving transistor. The gate of the threshold compensation transistor T5 receives the second scan control signal S2, and therefore, the threshold compensation transistor T5 can be turned on or off under the control of the second scan control signal S2.

[0020] The first terminal of the initialization transistor T6 receives the initialization signal Vini, and the second terminal of the initialization transistor T6 is electrically connected to the gate of the driving transistor T1. The gate of the initialization transistor T6 receives the third scan control signal S3. Therefore, the initialization transistor T6 can be turned on or off under the control of the third scan control signal S3, and when it is on, it writes the initialization signal Vini to the gate of the driving transistor T1 to initialize the gate potential of the driving transistor T1. The first terminal of the reset transistor T7 receives the reset signal Vref, and the second terminal of the reset transistor T7 is electrically connected to the anode of the light-emitting element D0. The gate of the reset transistor T7 receives the fourth scan control signal S4. Therefore, the reset transistor T7 can be turned on or off under the control of the fourth scan control signal S4, and when it is on, it writes the reset signal Vref to the anode of the light-emitting element D0 to reset the anode potential of the light-emitting element D0.

[0021] A storage capacitor Cst has a first plate that receives a fixed signal (e.g., a positive power supply signal PVDD) and a second plate that is electrically connected to the gate of a driving transistor T1 to store the signal at the gate of the driving transistor T1.

[0022] Reference Figure 2 and Figure 3Taking a pixel circuit 110 with PMOS transistors (driving transistor T1, first light-emitting control transistor T2, second light-emitting control transistor T3, data writing transistor T4, and reset transistor T7) and NMOS transistors (threshold compensation transistor T5 and initialization transistor T6), the operation includes a non-light-emitting stage T1 and a light-emitting stage T2. In the non-light-emitting stage T2, the light-emitting control transistor EM remains at an inactive level to control the first light-emitting control transistor T2 and the second light-emitting control transistor T3 to be in a turned-off state, thus breaking the circuit between the positive power supply terminal PVDD and the negative power supply terminal PVEE, and preventing the light-emitting element D0 from emitting light. Simultaneously, in the non-light-emitting stage T2, the pixel circuit 100 includes a reset stage t1, an initialization stage t2, and a data writing and threshold compensation stage t3 performed sequentially. During the reset phase t1, the second scan control signal S2, the third scan control signal S3, and the fourth scan control signal S4 are at low levels, and the first scan control signal S1 is at a high level. Therefore, the fourth scan control signal S4 controls the reset transistor T7 to turn on, while the other transistors are turned off. The reset signal Vref is transmitted through the reset transistor T7 to the anode of the light-emitting element D1, resetting the anode of D1. During the initialization phase t2, the second scan control signal S2 is at a low level, while the first scan control signal S1, the third scan control signal S3, and the fourth scan control signal S4 are at high levels. Therefore, the third scan control signal S3 controls the initialization transistor T6 to turn on, while the other transistors are turned off. The initialization signal Vini is transmitted through the initialization transistor T6 to the gate of the driving transistor T1, initializing the gate potential of the driving transistor T1. During the data writing phase t3, the first scan control signal S1 and the third scan control signal S3 are at a low level, while the second scan control signal S2 and the fourth scan control signal S4 are at a high level. The first scan control signal S1 controls the data writing transistor T2 to turn on, and the second scan control signal S2 controls the threshold compensation transistor T4 to turn on. The data signal Vdata can then be written to the first terminal of the driving transistor T1 through the data writing transistor T1 to refresh the signal at the first terminal of the driving transistor T1. If the driving transistor T1 is in the on state at this time, the data signal Vdata can also be provided to the second terminal of the driving transistor T1 through the driving transistor T1, and to the gate of the driving transistor T1 through the threshold compensation transistor T3, compensating the threshold voltage Vth of the driving transistor T1 to the gate of the driving transistor T1. This refreshes the signals at the gate and the second terminal of the driving transistor T1, making the driving current generated by the driving transistor T1 independent of its threshold voltage Vth.

[0023] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 5 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 4 and Figure 5 The pixel circuit 110 may further include a bias transistor T8. The first terminal of the bias transistor T8 receives a bias voltage signal, and the gate of the bias transistor T8 receives a fourth scan control signal S4. Taking the bias transistor T8 as a PMOS transistor as an example, the operation of the pixel circuit 110 also includes a bias stage t4. The bias stage t4 may be located before the data writing and threshold compensation stage t3 and the light emission stage T2 (but is not limited to this). During the bias stage t4, the second scan control signal S2 is at a high level and the fourth scan control signal S4 is at a low level. The bias transistor T8 and the threshold compensation transistor T5 are turned on, which can adjust the bias of the driving transistor T1.

[0024] It should be noted that, Figure 3 Figure 4 Only two pixel circuit structures are provided as examples, but not all of them. Provided that the core inventive points of the embodiments of the present invention can be achieved, the embodiments of the present invention do not limit the specific structure of the pixel circuit.

[0025] The operating modes of the display panel 100 include a first operating mode, Mode 1. For example, the display brightness of the display panel 100 in the first operating mode, Mode 1, is lower than or equal to a preset brightness, and / or the display grayscale of the display panel 100 in the first operating mode, Mode 1, is lower than or equal to a preset grayscale. That is, the first operating mode, Mode 1, can be a low brightness mode, a low grayscale mode, or a display mode that combines low brightness and low grayscale.

[0026] When the display panel 100 is in the first operating mode (Mode), during the light-emitting phase T2, the light-emitting control signal EM includes N valid pulses AP (during the low-level output phase of phase T2). During the phase where the light-emitting control signal AP outputs valid pulses, a current path is formed between the positive power supply terminal PVDD and the negative power supply terminal PVEE. The driving transistor T1 is turned on according to the data signal written to the gate, so that the light-emitting element D0 can emit light at the corresponding brightness when the light-emitting control signal AP outputs valid pulses AP. When the display panel 100 is operating in a low-brightness or low-grayscale scene (i.e., the first operating mode Mode1), if only a single wide pulse is used (i.e., the traditional analog dimming method), the driving transistor T1 needs to operate under an extremely low gate-source voltage bias. At this time, the threshold voltage drift, subthreshold region nonlinearity, and leakage current of the driving transistor T1 will be significantly amplified, resulting in poor driving current accuracy, deterioration of pixel consistency, and the human eye's sensitivity to light fluctuations is actually enhanced under extremely low brightness, making it easy to perceive low-frequency flicker. Using N effective pulses (AP) discretizes the total emission time into multiple short pulses, effectively transforming deep dimming into multiple short, medium-brightness emission cycles. This allows for a relatively high data voltage within each effective pulse, enabling the driving transistor T1 to operate in the linear or saturation region, thus effectively avoiding nonlinear distortion in the subthreshold region. Simultaneously, by adjusting the total width or number of the N effective pulses, the average brightness can be effectively reduced digitally while maintaining the stability of the driving transistor T1's operating point, overcoming the control accuracy issue of driving current caused by threshold voltage drift. Compared to traditional single-pulse solutions, which are limited by subthreshold precision and cannot stably output a lower brightness limit, this solution, through multi-pulse discretization, significantly widens the minimum achievable brightness range without sacrificing driving precision. This allows for a wider range of continuous adjustment from extremely low brightness to normal brightness, significantly improving the deep dimming capability of the display panel while avoiding the negative impact of offset characteristics on the driving current under low brightness and low grayscale conditions.

[0027] In the first operating mode (Mode1, such as low brightness or low grayscale), the width of each pulse in the traditional equal-width narrow pulse scheme is the same and too narrow. As a result, when the first few pulses are applied, the gate node of the driving transistor T1 has not yet established a stable bias voltage. Affected by threshold voltage drift and hysteresis effect, the channel cannot be fully turned on, the leading edge of the luminous current is slow and the peak value is low. Subsequent pulses exacerbate waveform oscillation due to charge residue and capacitive coupling effect, which ultimately causes light output fluctuation and SVM increase.

[0028] Based on this, and in conjunction with references Figure 2 and Figure 3 or in conjunction with references Figure 4 and Figure 5When the display panel 100 is in the first working mode, the N effective pulses AP contained in the light emission control signal EM during the light emission stage T2 can be configured not to be of equal width. Specifically, the pulse width of the first m effective pulses AP can be set to be greater than the pulse width of the subsequent Nm effective pulses AP. This allows the wider pulse width of the first m pulses to provide sufficient turn-on time and charge build-up time for the driving transistor T1, allowing the data voltage to be fully written into the storage capacitor Cst of the driving transistor, enabling the gate-source voltage to quickly reach the target value and stabilize, overcoming the turn-on delay and insufficient current problems caused by the offset characteristics. Simultaneously, the moderate driving current generated by the first few wide pulses can consume the residual charge accumulated in the pixel node due to the leakage path, causing the anode potential of the light-emitting element D0 to tend towards equilibrium. After the circuit state pre-stabilization is completed by the first m effective pulses, the subsequent Nm narrow pulses only need to be finely dimmed based on the established stable bias. Even with a narrow width, the driving transistor T1 can respond quickly and linearly output a corresponding driving current, thereby significantly suppressing the leading edge jitter, trailing edge trailing, and oscillation distortion of the current waveform.

[0029] The display panel provided in this embodiment of the invention realizes the display function through an array of pixel circuits. The light emission control signal controls the light emission of the pixel circuits, so that the light emission control signal outputs an invalid level during the non-light emission stage to control the pixel circuits not to emit light. When the display panel is in the first working mode, by setting the light emission control signal to include N effective pulses during the light emission stage, a wider range of continuous adjustment from extremely low brightness to normal brightness can be achieved. This can avoid the negative impact of the offset characteristics on the driving current under low brightness and low grayscale conditions, while significantly improving the deep dimming capability of the display panel. Furthermore, by setting the pulse width of the first m effective pulses in the N effective pulse signals to be greater than the pulse width of the last Nm effective pulses, a stable bias state can be established for the pixel circuits using the preceding wide pulses in low brightness and low grayscale display scenarios, overcoming the negative impact of transistor offset characteristics on the charging process. Then, fine dimming is achieved with subsequent narrow pulses, thereby effectively suppressing the distortion and oscillation of the light emission current waveform, significantly reducing SVM, and effectively improving the subjective visual experience.

[0030] In some embodiments, in conjunction with reference Figure 2 and Figure 3 or in conjunction with references Figure 4 and Figure 5The value m can be set to 1. That is, in the light emission stage T2 under the first working mode Mode1, the width of the first effective pulse AP of the light emission control signal EM can be set to be greater than the width of all subsequent effective pulse APs. This can simplify the timing control complexity to the greatest extent while ensuring the improvement of SVM, which is beneficial to reducing the waveform output burden and power consumption of the gate drive circuit (such as GOA). Its working principle is as follows: at the beginning of the light emission stage T2, a first effective pulse AP with a larger width is set. This wide pulse can provide sufficient turn-on time and charge build-up time for the drive transistor T1 in the pixel circuit 110, so that its gate source voltage can quickly reach and stabilize near the target value, overcoming the turn-on delay problem caused by threshold voltage drift and hysteresis effect. This establishes a stable and consistent working bias condition for the subsequent N-1 narrower equal-width (or non-equal-width) pulses, which can achieve a substantial improvement in SVM visual effect under low brightness and low grayscale with minimal timing modification cost. It is especially suitable for display panels 100 that are more sensitive to timing resources and power consumption.

[0031] In some embodiments, Figure 6 and Figure 7 This is another driving timing diagram of a pixel circuit provided in an embodiment of the present invention, in conjunction with reference to... Figure 3 and Figure 6 or in conjunction with references Figure 3 and Figure 7 Alternatively, m ≥ 2 can be set. Figure 6 An example is shown for the case where m=2, and Figure 7 An example is shown with m=3. Compared to the m=1 scheme, setting m≥2 means configuring two or more wide pulses at the beginning of the light-emitting stage T2 in the first operating mode Mode1. The width of these wide pulses is greater than the width of the subsequent Nm effective pulses. In low-brightness, low-grayscale display scenarios, when the transistor offset characteristics are significant (e.g., in low-temperature environments or aging states) or the parasitic capacitance in the pixel circuit 110 is large, a single wide pulse may not be able to completely establish a stable bias state. However, multiple consecutive wide pulses can perform multiple rounds of "pre-charging" and charge replenishment operations on the gate node of the driving transistor, so that the gate-source voltage gradually approaches and stabilizes near the target value, more effectively overcoming the turn-on delay and current fluctuation problems caused by threshold voltage drift and hysteresis effects. At the same time, placing multiple wide pulses at the beginning of the light-emitting stage T2 also allows the invalid level interval between adjacent wide pulses to perform a brief charge balance on the pixel node, further suppressing the response distortion of subsequent narrow pulses caused by residual charge from the preceding light emission.

[0032] For example, continue to refer to the reference Figure 3 and Figure 6 or in conjunction with references Figure 3 and Figure 7When m≥2, the pulse widths of the first m effective pulses AP can be set to be equal. On the one hand, multiple equal and relatively wide pre-charge pulses AP can perform continuous and consistent pre-charge operations on the pixel circuit 110, allowing the gate node of the driving transistor T1 to gradually build up and stabilize to the target voltage over multiple pulse cycles. This avoids differences in charging degree caused by inconsistent pulse widths (such as decreasing or increasing), thereby further improving the waveform smoothness of the luminous current and the consistency between pulses under low brightness and low grayscale conditions. On the other hand, the equal-width design of the pre-charge pulses AP simplifies the timing generation logic of the luminous control signal, reduces the waveform output complexity of the gate driving circuit (such as the GOA circuit), reduces timing deviations or coupling noise that may be introduced due to frequent changes in pulse width, and improves the engineering feasibility and mass production reliability of the driving scheme.

[0033] For example, taking the first operating mode (Mode1) where the light emission control signal EM includes 32 effective pulses (AP) during the light emission stage (T2), a comparison is provided. Tables 1A and 1B are effective pulse width configuration tables provided by embodiments of the present invention. They exemplarily show a comparison of the pulse widths of the 32 effective pulses (AP1, AP2, ..., AP32) in three different schemes (Scheme 1, Scheme 2, and Scheme 3) of the conventional scheme and the present invention when the light emission brightness is 2 nits. Table 2 is a comparison table of SVM test results for different driving schemes at 2 nits, as shown in Table 1 (including Tables 1A and 1B). Table 1A. Effective Pulse Width Configuration Table (showing effective pulses AP1~AP16) Table 1B. Effective Pulse Width Configuration Table (showing effective pulses AP17~AP32) Table 2. Comparison of SVM test results for different driving schemes at 2 nits as shown in Table 1. Based on the experimental data shown in Tables 1A, 1B, and 2, the pulse width settings, duty cycles, and SVM comparisons under different schemes are as follows. Tables 1A and 1B show the width configuration (in clock cycles H) and corresponding duty cycles of the effective pulses during the emission stage for each driving scheme. The traditional scheme uses a uniform pulse width configuration, where each pulse is 9H, resulting in a total duty cycle of 10.11% for the emission control signal EM. Scheme 1 uses a configuration where the first two effective pulses are 73H and subsequent pulses are 5H (wide at the beginning and narrow at the end), resulting in a total duty cycle of 10.39% for the emission control signal EM; Scheme 2 uses a configuration where the first three effective pulses are 73H and subsequent pulses are 5H, resulting in a total duty cycle of 12.78% for the emission control signal EM; and Scheme 3 uses a configuration where the first two effective pulses are 41H and subsequent pulses are 5H, resulting in a total duty cycle of 8.15% for the emission control signal EM. All three schemes of the present invention adopt a pulse distribution that is wider at the beginning and narrower at the end, and the first m effective pulses are of equal width (the first two in Scheme 1 are 73H, the first three in Scheme 2 are 73H, and the first two in Scheme 3 are 41H).

[0034] Table 2 further illustrates the SVM test results of the above schemes in a 2nit low-brightness scenario. The data shows that the average SVM value of the traditional scheme in five tests (#1, #2, #3, #4, #5) was 1.3078, with a maximum value of 1.482, exceeding the human eye's comfortable perception threshold. This indicates that the uniform pulse width distribution cannot effectively overcome the negative impact of TFT offset characteristics on the stability of the luminous current under low brightness. In contrast, Schemes 1, 2, and 3, which employ the front-wide and rear-narrow pulse configuration of this invention, all showed significantly reduced SVM values. Specifically, Scheme 1 had an average SVM value of only 0.1786 and a maximum value of 0.211, a decrease of approximately 86% compared to the traditional scheme, demonstrating the best performance. Scheme 2 had an average SVM value of 0.3188 and a maximum value of 0.402, a decrease of approximately 76% compared to the traditional scheme. Scheme 3 had an average SVM value of 0.6066 and a maximum value of 0.696, a decrease of approximately 54% compared to the traditional scheme.

[0035] As shown in Tables 1A, 1B, and 2, the pulse width distribution has a decisive impact on SVM performance. Traditional solutions using equal-width pulses cannot address the problem caused by TFT offset characteristics at low brightness, resulting in poor SVM performance. The present invention employs a pulse distribution that is wider at the beginning and narrower at the end. A wide initial pulse (e.g., 73H or 41H) establishes a stable bias state for the pixel circuit, followed by a narrow pulse (e.g., 5H) for fine-tuning, thus significantly reducing the SVM value. The equal-width setting of the first m effective pulses (e.g., the first two 73H pulses in Scheme 1, the first three 73H pulses in Scheme 2, and the first two 41H pulses in Scheme 3) further optimizes the consistency and stability of pre-charging. Furthermore, a comparison of Schemes 1 and 3 shows that the wider the initial wide pulse, the more significant the SVM improvement, indicating that the charging capability of the initial wide pulse is crucial for overcoming TFT offset characteristics. The above data fully validates the effectiveness and superiority of the present invention.

[0036] In some embodiments, Figure 8 This is another driving timing diagram of a pixel circuit provided in an embodiment of the present invention, in conjunction with reference to... Figure 3 and Figure 8 When m≥2, the pulse width of the first m valid pulses AP can also be set to decrease sequentially.

[0037] Specifically, Figure 8 An example is shown where, when m=3, the pulse widths of the first three effective pulses AP decrease sequentially. Specifically, in the light-emitting stage T2, the width of the first effective pulse AP is t01, the second is t05, and the third is t06, with t01 < t05 < t06. At the beginning of the light-emitting stage T2, the first wide pulse provides a strong initial charge to the pixel circuit with its maximum width, causing the gate node voltage of the driving transistor T1 to rise rapidly and approach the target value. Subsequent, wider effective pulses AP have progressively smaller pulse widths. This maintains the established bias state of the circuit while avoiding overshoot or oscillation caused by prolonged charging, achieving gradual fine-tuning and stabilization of the gate voltage. The decreasing wide pulse sequence can more precisely match the nonlinear charging characteristics of the driving transistor T1 during the turn-on process. That is, the driving transistor T1 requires more energy in the initial stage to overcome the inertia of offset characteristics and parasitic capacitance, while in subsequent stages only less energy is needed to maintain a stable state, thus achieving a better balance between charging efficiency and waveform smoothness. Furthermore, the sequentially decreasing pulse width helps reduce the overall emission duty cycle, minimizing unnecessary power consumption while ensuring effective bias setup. This is particularly suitable for applications requiring both high-quality low-grayscale images and efficient power consumption, achieving superior overall performance through more refined timing design.

[0038] Optional, see reference Figure 3 and in conjunction with references Figure 2 , Figure 6 and Figure 7 In any of the attached figures, each invalid level UL adjacent to the first m valid pulses AP has a first duration t03, and each invalid level UL adjacent to the pulse width of the next Nm valid pulses AP has a second duration t04; the first duration t03 is less than the second duration t04.

[0039] Specifically, at the beginning of the light-emitting stage T2, since the first m wide pulses are responsible for pre-charging and stabilizing the bias of the pixel circuit 110, the adjacent invalid levels UL (i.e., the turn-off interval between pulses) are set to be short (first duration t03). This reduces the discharge loss of the gate voltage of the driving transistor T1 during the turn-off period, allowing the gate node of the driving transistor T1 to maintain high potential stability between multiple wide pulses, avoiding the need for recharging due to charge loss caused by excessively long turn-off intervals. At the same time, the shorter turn-off interval can also speed up the overall rhythm of the pulse sequence, accommodating more effective pulses AP or leaving more ample dimming time in the limited total light-emitting stage time. At the end of the light-emitting stage T2, the last Nm narrow pulses are mainly used for fine dimming to achieve the target low brightness. At this time, setting the adjacent invalid levels UL to a longer second duration t04 is beneficial for fully releasing the residual charge in the pixel node after each narrow pulse light emission, preventing crosstalk or waveform distortion caused by charge accumulation. At the same time, the longer turn-off interval can also reduce the power consumption caused by frequent switching. Therefore, by differentiating the duration of the invalid level UL to match the width of the valid pulse AP, the performance and power consumption characteristics of SVM can be further optimized while ensuring the bias setup effect and fine dimming accuracy.

[0040] Optional, see reference Figure 2 , Figures 5-8 In any of the attached figures, Nm ≥ 2; the pulse widths of the last Nm effective pulses AP are equal.

[0041] Specifically, after the first m wide effective pulses AP complete the pre-charging and bias establishment of the pixel circuit 110, the subsequent Nm narrower effective pulses AP (referred to as narrow pulses) mainly undertake the function of fine dimming to achieve the target low brightness. Setting these narrow pulses to have equal width, as shown in the figure (t02), ensures that the driving transistor T1 operates under the same and stable bias conditions during the duration of each narrow pulse, thereby outputting a consistent driving current. This makes the luminous brightness corresponding to multiple effective pulses AP uniform and consistent, avoiding brightness fluctuations and visual flicker caused by unequal pulse widths. Furthermore, the equal width design simplifies the subsequent digital dimming control logic. The average brightness can be linearly changed by directly adjusting the number of narrow pulses Nm or the overall pulse frequency, facilitating uniform grayscale division and precise control. This ensures both brightness uniformity and dimming linearity while maintaining the SVM improvement effect.

[0042] For example, the pulse width of the last Nm valid pulses AP is the minimum pulse width that the driver IC can support.

[0043] Specifically, setting the width of the last Nm effective pulses AP to the minimum pulse width supported by the driver IC, i.e., t02 can be the minimum pulse width supported by the driver IC, can contribute the minimum amount of light emission with the shortest light emission time during each narrow pulse period. This allows the lowest possible average brightness to be achieved by adjusting the number or frequency of narrow pulses, thereby significantly widening the dimming range of the display panel towards extremely low brightness. On the other hand, the minimum pulse width usually corresponds to the timing limit of the driver IC. Under this limit condition, the pulse width consistency is good and the accuracy is high, which can avoid additional brightness errors and flicker caused by pulse width fluctuations. In addition, using the minimum pulse width can effectively shorten the duration of the total light emission stage, thereby reserving more time for the non-light emission stage T1 (especially the data writing and threshold compensation stage t3) in high refresh rate display scenarios, so that the pixel circuit 110 can complete more sufficient data writing and threshold voltage compensation, further improving the accuracy and uniformity of the light emission current at low gray levels. Alternatively, using the minimum pulse width can support more pulses within a fixed frame period, enabling finer brightness level adjustment without reducing the refresh rate, thus widening the dimming range. This allows the display panel 100 to maintain a low SVM value and good visual comfort even in demanding scenarios where high refresh rates and low brightness coexist.

[0044] Optional, Figure 9 This is another driving timing diagram of a pixel circuit provided in an embodiment of the present invention, such as... Figure 9 As shown, Nm≥2; among the last Nm effective pulses AP, at least some of the effective pulses AP have unequal pulse widths.

[0045] Specifically, after the first m wide pulses pre-charge and bias the pixel circuit, the subsequent Nm narrow pulses perform fine dimming to achieve the target low brightness. However, in actual display, the state of the pixel circuit 100 may vary slightly at different pulse times. For example, after the first few narrow pulses, the pixel node may have a small amount of residual charge, while the residual charge has been largely released by the time of the subsequent narrow pulses; or, due to the transistor hysteresis effect, multiple consecutive narrow pulses of the same width may cause a slow drift in the response characteristics of the driving transistor T1. To address these issues, the subsequent Nm effective pulses AP are set to be partially equal in width, partially unequal in width, or exhibit a specific pattern of change (such as increasing, decreasing, increasing then decreasing, etc.). The figure exemplifies the case where, when m=1, the width of the second effective pulse AP is t02, the width of the third effective pulse AP is t07, and the width of the last effective pulse AP is t08, with t02 < t08 < t07, but this is not the only possibility. By setting the last Nm effective pulses AP to be partially of equal and partially unequal width, targeted compensation can be made for the differences in circuit state at different pulse stages, thereby achieving more precise control over luminous brightness. For example, the first few narrow pulses can be set to have a slightly wider width to overcome the interference of residual charge, and the standard width can be restored in the later narrow pulses to accurately output the target brightness; or the narrow pulse width can be set to increase sequentially to match the gradually stabilizing response characteristics of the driving transistor T1 during continuous switching. This is particularly suitable for application scenarios with extreme requirements for low grayscale image quality and those requiring fine compensation for pulse accumulation effects.

[0046] Optional, Figure 10 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention, in conjunction with reference to... Figure 2 and Figure 10 The display panel 100 also includes a second working mode, Mode2. In the second working mode, Mode2, the light emission control signal EM remains at an effective level during the light emission phase T2.

[0047] Specifically, in the second operating mode (Mode2), the light emission control signal EM is a single, continuously effective level throughout the entire light emission phase, and no longer contains multiple discrete effective pulses. The second operating mode (Mode2) is typically suitable for display panels 100 in normal or high brightness display scenarios (e.g., strong ambient light, display content mainly in high grayscale, or situations where users have high brightness requirements).

[0048] For example, the display panel 100 in the second operating mode Mode2 has a display brightness greater than a preset brightness, and the display panel 100 in the second operating mode Mode2 has a display grayscale greater than a preset grayscale. The second operating mode Mode2 corresponds to the display panel operating in a relatively high brightness range and a relatively high grayscale range. At this time, the displayed content has a sufficient brightness level, the human eye's sensitivity to flicker is relatively reduced, and the driving transistor T1 operates in a deeper region of the linear region or saturation region, the data voltage is higher, and the offset characteristics of the driving transistor T1 (such as threshold voltage drift and hysteresis effect) have a relatively small impact on the light emission current.

[0049] In such high-brightness, high-grayscale scenarios, there is no need to use the multi-pulse discrete drive in the first working mode (Mode 1) to improve the SVM visual effect. Instead, a traditional analog dimming method can be used—that is, the light emission control signal EM remains a continuously effective single level during the light emission phase (T2), and the brightness is adjusted by changing the data voltage Vdata. On the one hand, this avoids unnecessary switching losses in high-brightness scenarios caused by multi-pulse drive, reducing the dynamic power consumption of the gate drive circuit (GOA). On the other hand, the continuous light emission mode ensures that the light-emitting element D0 achieves the highest luminous efficiency during high-brightness display, avoiding problems such as excessive peak current or decreased luminous efficiency that may be introduced by pulse drive. The specific values ​​of the preset brightness and preset grayscale can be flexibly configured according to the application scenario of the display panel 100, the process characteristics of each transistor in the pixel circuit (such as LTPS or IGZO), and the sensitivity curve of the human eye to SVM. For example, in scenarios with extremely high visual comfort requirements, such as automotive or medical displays, the preset brightness can be set to a lower 5 nits and the preset grayscale to 30 levels (taking a maximum grayscale of 225 or 1023 levels as an example) to expand the coverage of the first working mode, Mode 1. For conventional scenarios such as consumer electronics, the preset brightness can be set to 10 nits and the preset grayscale to 60 levels to optimize power consumption while ensuring image quality. Through the above dual-condition limitation of brightness and grayscale, this invention ensures that the display panel 100 can automatically switch to the second working mode, Mode 2, in high-brightness, high-grayscale scenarios, realizing an intelligent driving strategy under different display conditions, and taking into account both the low SVM requirement of low-brightness scenarios and the low power consumption requirement of high-brightness scenarios.

[0050] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes the display panel provided in the embodiments of the present invention. Therefore, this display device possesses the technical features of the display panel and its driving method provided in the embodiments of the present invention, and can achieve the beneficial effects of the display panel provided in the embodiments of the present invention. Similarities can be found in the above description of the display panel provided in the embodiments of the present invention, and will not be repeated here.

[0051] For example, Figure 11This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 11 As shown, the display device 200 includes the display panel 100 provided in this embodiment of the invention. The display device 200 provided in this embodiment of the invention can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc., and this embodiment of the invention does not make any special limitations on these categories.

[0052] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Pixel circuitry arranged in an array; The operation of the pixel circuit includes a non-light-emitting stage and a light-emitting stage; During the non-light-emitting phase, the light-emitting control signal received by the pixel circuit is at an invalid level; The display panel includes a first working mode, in which the light emission control signal includes N effective pulses during the light emission phase; Of the N valid pulse signals, the pulse width of the first m valid pulses is greater than the pulse width of the last Nm valid pulses; Where N≥2, 1≤m<N, and m and N are both integers.

2. The display panel according to claim 1, characterized in that, m=1。 3. The display panel according to claim 1, characterized in that, m≥2; the pulse widths of the first m effective pulses are equal.

4. The display panel according to claim 1, characterized in that, m≥2; the pulse widths of the first m effective pulses decrease sequentially.

5. The display panel according to claim 1, characterized in that, Each invalid level adjacent to the first m valid pulses has a first duration, and each invalid level adjacent to the pulse width of the next Nm valid pulses has a second duration. The first duration is less than the second duration.

6. The display panel according to claim 1, characterized in that, Nm≥2; the pulse widths of the last Nm effective pulses are equal.

7. The display panel according to claim 6, characterized in that, The pulse width of the last Nm effective pulses is the minimum pulse width that the driver IC can support.

8. The display panel according to claim 1, characterized in that, Nm≥2; among the last Nm effective pulses, at least some of the effective pulses have unequal pulse widths.

9. The display panel according to claim 1, characterized in that, The display panel's display brightness in the first working mode is lower than or equal to a preset brightness, and / or the display panel's grayscale in the first working mode is lower than or equal to a preset grayscale.

10. The display panel according to claim 1, characterized in that, The display panel also includes a second operating mode, in which the light emission control signal remains at an effective level during the light emission phase.

11. The display panel according to claim 10, characterized in that, The display panel has a brightness greater than a preset brightness in the second working mode, and the display grayscale of the display panel in the second working mode is greater than the preset grayscale.

12. A display device, characterized in that, include: The display panel according to any one of claims 1 to 11.

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