Display device and electronic device having the same

Abstract

A display device and an electronic device are disclosed. The display device includes: a plurality of sub-pixel circuits arranged in a matrix having a plurality of rows and a plurality of columns; a plurality of light-emitting devices, each of which is connected to a corresponding sub-pixel circuit in the plurality of sub-pixel circuits; a data driver configured to output data signals to the plurality of sub-pixel circuits via a plurality of output lines; and a scan driver configured to output scan signals to the plurality of sub-pixel circuits via a plurality of first scan lines, a plurality of second scan lines, and a plurality of third scan lines, wherein each of the plurality of output lines is commonly connected to three sub-pixel circuits included in a pixel in the plurality of sub-pixel circuits.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0012679, filed on January 31, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Various embodiments of this disclosure relate to a display device and an electronic device having the display device. Background Technology

[0003] With the development of information technology, the importance of display devices as a connection medium between users and information has been emphasized. Due to the importance of display devices, the use of various types of display devices, such as liquid crystal displays, organic light-emitting diode displays, and plasma displays, has increased.

[0004] Typically, a display device includes a display unit for displaying images and a display driver for driving the display unit. The display unit includes a scan driver and multiple sub-pixels. The display driver includes a data driver that outputs data signals to data lines and a timing controller. The timing controller controls the scan driver and the data driver.

[0005] The display device described above can display an image by outputting a scan signal to a scan line connected to the pixel to be displayed and providing a data voltage corresponding to the image to be displayed to a data line connected to the pixel. Summary of the Invention

[0006] Aspects and features of embodiments of this disclosure are to provide a display device and an electronic device having the display device, which are capable of reducing the power consumption and heat generation required for the operation of the data driver and reducing the number of transistors included in the display driver.

[0007] A display device according to one or more embodiments of the present disclosure includes a plurality of sub-pixel circuits, a plurality of light-emitting devices, a data driver, and a scan driver. The plurality of sub-pixel circuits are arranged in a matrix having a plurality of rows and columns. Each of the plurality of light-emitting devices is connected to a corresponding sub-pixel circuit within the plurality of sub-pixel circuits. The data driver is configured to output data signals to the plurality of sub-pixel circuits via a plurality of output lines. The scan driver is configured to output scan signals to the plurality of sub-pixel circuits via a plurality of first scan lines, a plurality of second scan lines, and a plurality of third scan lines. Each of the plurality of output lines is commonly connected to three sub-pixel circuits included in a pixel within the plurality of sub-pixel circuits. Each of the plurality of first scan lines is connected to a first color sub-pixel circuit in a corresponding row within the plurality of sub-pixel circuits. Each of the plurality of second scan lines is connected to a second color sub-pixel circuit in a corresponding row within the plurality of sub-pixel circuits. Each of the plurality of third scan lines is connected to a third color sub-pixel circuit in a corresponding row within the plurality of sub-pixel circuits.

[0008] According to one or more embodiments, multiple sub-pixel circuits can be arranged in a matrix with m rows and n columns. The number of first scan lines can be m, the number of second scan lines can be m, and the number of output lines can be n / 3. During a horizontal time period corresponding to a selected row among the multiple rows, the scan driver can activate the voltage of the first scan line corresponding to the selected row among the multiple first scan lines during a first time period of the horizontal time period, activate the voltage of the second scan line corresponding to the selected row among the multiple second scan lines during a second time period of the horizontal time period different from the first time period, and activate the voltage of the third scan line corresponding to the selected row among the multiple third scan lines during a third time period of the horizontal time period different from the first and second time periods. Here, m and n are both integers of 2 or greater.

[0009] According to one or more embodiments, during a first time period, data output to multiple output lines can be applied to a first color sub-pixel circuit in the sub-pixel circuit corresponding to the selected row; during a second time period, data output to multiple output lines can be applied to a second color sub-pixel circuit in the sub-pixel circuit corresponding to the selected row; and during a third time period, data output to multiple output lines can be applied to a third color sub-pixel circuit in the sub-pixel circuit corresponding to the selected row.

[0010] According to one or more embodiments, multiple light-emitting devices may be located above or below multiple sub-pixel circuits.

[0011] According to one or more embodiments, three sub-pixel circuits can be arranged along the row direction in a single pixel.

[0012] According to one or more embodiments, the shared region may be located between sub-pixels in the first row and sub-pixels in the second row, and at least one common line connecting the sub-pixels in the first row and the sub-pixels in the second row may be in the shared region.

[0013] According to one or more embodiments, the circuit layout of each of the sub-pixels in the first row and the circuit layout of each of the sub-pixels in the second row may have a linearly symmetrical shape relative to the shared region.

[0014] According to one or more embodiments, the common line may include a repair line for repairing defective pixels.

[0015] According to one or more embodiments, three sub-pixel circuits can be arranged along the column direction in a pixel. A shared region can be located between the sub-pixels in the first to third rows and the sub-pixels in the fourth to sixth rows, and at least one common line connecting the sub-pixels in the first to third rows and the sub-pixels in the fourth to sixth rows can be in the shared region.

[0016] According to one or more embodiments, the third color sub-pixel circuit can be located in the third and fourth rows of a pixel closest to the shared region, the second color sub-pixel circuit can be located in the second and fifth rows adjacent to the third color sub-pixel circuit, and the first color sub-pixel circuit can be located in the first and sixth rows of a pixel furthest from the shared region.

[0017] According to one or more embodiments, the circuit layout of each of the sub-pixels in the first row and the circuit layout of each of the sub-pixels in the sixth row may have a linearly symmetrical shape relative to the shared region, the circuit layout of each of the sub-pixels in the second row and the circuit layout of each of the sub-pixels in the fifth row may have a linearly symmetrical shape relative to the shared region, and the circuit layout of each of the sub-pixels in the third row and the circuit layout of each of the sub-pixels in the fourth row may have a linearly symmetrical shape relative to the shared region.

[0018] According to one or more embodiments, the data driver can be configured to output data to k output lines, and the scan driver can be configured to output scan signals to m first scan lines, m second scan lines, and m third scan lines. Multiple sub-pixel circuits can be arranged in a matrix with m rows and 3k columns. The h-th output line among the output lines can be connected to the sub-pixel circuits located in columns 3h-2, 3h-1, and 3h among the multiple sub-pixel circuits. The i-th first scan line among the first scan lines can be connected to the 3j-2 sub-pixel circuit located in the i-th row. The i-th second scan line among the second scan lines can be connected to the 3j-1 sub-pixel circuit located in the i-th row. The i-th third scan line among the third scan lines can be connected to the 3j sub-pixel circuit located in the i-th row. Here, m and n are both integers of 2 or greater, k is an integer of 1 or greater, h is an integer greater than 0 and less than or equal to k, i is an integer greater than 0 and less than or equal to m, and j is an integer greater than 0 and less than or equal to k.

[0019] According to one or more embodiments, during a horizontal time period corresponding to the i-th row, the scan driver can activate the voltage of the i-th first scan line during a first time period of the horizontal time period, activate the voltage of the i-th second scan line during a second time period of the horizontal time period that is different from the first time period, and activate the voltage of the i-th third scan line during a third time period of the horizontal time period that is different from the first and second time periods.

[0020] According to one or more embodiments, the shared region may be located between the sub-pixels in row 2i-1 and row 2i, and at least one common line connecting the sub-pixels in row 2i-1 and row 2i may be arranged in the shared region.

[0021] A display device according to one or more embodiments of the present disclosure includes a data driver, a scan driver, and a pixel unit. The data driver may be configured to output data to k output lines. The scan driver may be configured to output scan signals to m first scan lines, m second scan lines, and m third scan lines. The pixel unit is connected to the output lines, the first scan lines, the second scan lines, and the third scan lines. The pixel unit includes a plurality of sub-pixel circuits arranged in a matrix having 3m rows and k columns, and a plurality of light-emitting devices, each of the plurality of light-emitting devices being connected to a corresponding sub-pixel circuit among the plurality of sub-pixel circuits. The h-th output line among the output lines is commonly connected to the sub-pixel circuit located in the h-th column among the plurality of sub-pixel circuits. The i-th first scan line among the first scan lines is connected to the sub-pixel circuit in the 3i-2 row. The i-th second scan line among the second scan lines is connected to the sub-pixel circuit in the 3i-1 row. The i-th third scan line among the third scan lines is connected to the sub-pixel circuit in the 3i row. Here, m and n are both integers of 2 or greater, k is an integer of 1 or greater, h is an integer greater than 0 and less than or equal to k, and i is an integer greater than 0 and less than or equal to m.

[0022] According to one or more embodiments, the sub-pixel circuit in row 3i-2 may be a first color sub-pixel circuit, the sub-pixel circuit in row 3i-1 may be a second color sub-pixel circuit, and the sub-pixel circuit in row 3i may be a third color sub-pixel circuit.

[0023] According to one or more embodiments, the shared region may be located between the sub-pixels in row 3i and row 3i+1. At least one common line commonly connected to the sub-pixel circuits in rows 3i-2, 3i-1, 3i, 3i+1, 3i+2, and 3i+3 may be located within the shared region.

[0024] According to one or more embodiments, the sub-pixel circuit in row 3i+1 can be a third color sub-pixel circuit, the sub-pixel circuit in row 3i+2 can be a second color sub-pixel circuit, and the sub-pixel circuit in row 3i+3 can be a first color sub-pixel circuit.

[0025] According to one or more embodiments, the circuit layout of each of the sub-pixel circuits in row 3i+1 and the circuit layout of each of the sub-pixel circuits in row 3i can have a linearly symmetrical shape relative to the shared region, the circuit layout of each of the sub-pixel circuits in row 3i+2 and the circuit layout of each of the sub-pixel circuits in row 3i-1 can have a linearly symmetrical shape relative to the shared region, and the circuit layout of each of the sub-pixel circuits in row 3i+3 and the circuit layout of each of the sub-pixel circuits in row 3i-2 can have a linearly symmetrical shape relative to the shared region.

[0026] An electronic device according to one or more embodiments of the present disclosure includes a processor and a display device. The processor may be configured to provide input image data. The display device may be configured to display an image based on the input image data. The display device includes a plurality of sub-pixel circuits, a plurality of light-emitting devices, a data driver, and a scan driver. The plurality of sub-pixel circuits are arranged in a matrix having a plurality of rows and columns. Each of the plurality of light-emitting devices is connected to a corresponding sub-pixel circuit among the plurality of sub-pixel circuits. The data driver may be configured to output data signals to the plurality of sub-pixel circuits via a plurality of output lines. The scan driver may be configured to output scan signals to the plurality of sub-pixel circuits via a plurality of first scan lines, a plurality of second scan lines, and a plurality of third scan lines. Each of the plurality of output lines is commonly connected to three sub-pixel circuits included in a pixel among the plurality of sub-pixel circuits. Each of the plurality of first scan lines is connected to a first color sub-pixel circuit in a corresponding row among the plurality of sub-pixel circuits. Each of the plurality of second scan lines is connected to a second color sub-pixel circuit in a corresponding row among the plurality of sub-pixel circuits. Each of the plurality of third scan lines is connected to a third color sub-pixel circuit in a corresponding row among the plurality of sub-pixel circuits. Attached Figure Description

[0027] Figure 1 This is a diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0028] Figure 2 It is shown Figure 1 The image of subpixels.

[0029] Figure 3 yes Figure 1 A schematic diagram of the equivalent circuit of a sub-pixel.

[0030] Figure 4 It is shown Figure 1 A diagram of an embodiment of the pixel portion shown.

[0031] Figure 5 Is showing the connection to Figure 4 The diagram shows the data lines and scan lines of the sub-pixel circuit.

[0032] Figure 6 This is a timing diagram illustrating the operation of a display device according to one or more embodiments of the present disclosure.

[0033] Figure 7 This is a diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0034] Figure 8 It is shown Figure 7 A diagram of an embodiment of the pixel portion shown.

[0035] Figure 9 It shows the basis Figure 8 A timing diagram of the operation of the display device in an embodiment.

[0036] Figure 10 It is shown Figure 7 A diagram of another embodiment of the pixel portion shown.

[0037] Figure 11 It is shown Figure 7 A diagram of another embodiment of the pixel portion shown.

[0038] Figure 12A and Figure 12B This is a diagram illustrating an embodiment of pixels sharing a common line arranged in a shared area.

[0039] Figure 13 It is a block diagram of an electronic device according to one or more embodiments.

[0040] Figure 14 Schematic diagrams of electronic devices according to various embodiments are shown. Detailed Implementation

[0041] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the present disclosure. The present disclosure may be implemented in various forms and is not limited to the embodiments described herein.

[0042] In the accompanying drawings, parts unrelated to this disclosure will be omitted for clarity. Reference should be made to the drawings, in which similar reference numerals are used in different drawings to denote similar components. Therefore, the aforementioned reference numerals may be used in other drawings.

[0043] For reference and for the sake of explanation, the dimensions and thickness of each component are arbitrarily represented, and this disclosure is not limited to what is shown in the accompanying drawings. In the drawings, the thickness of each component may be exaggerated to clearly depict multiple layers and regions.

[0044] Furthermore, the expression "identical" can mean "substantially identical." In other words, the expression "identical" can include the range that is tolerable to those skilled in the art. Other expressions may also be those in which "substantially" has been omitted.

[0045] In this specification, it will be understood that when an element (or region, layer, portion, etc.) is referred to as being "on" another element, "connected to" or "integrated into" another element, the element may be directly disposed on, directly connected to or directly integrated into the other element, or other elements may be disposed between them.

[0046] In this application, the phrase "directly disposed on..." can indicate that no layer, membrane, region, plate, etc., is added between one part and another. For example, the phrase "directly disposed on..." can indicate that two layers or two components are disposed without the use of additional components such as adhesive components between them.

[0047] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed elements.

[0048] It will be understood that while the terms “first,” “second,” etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, a first element discussed below may be referred to as a second element without departing from the spirit or scope of this disclosure. Similarly, a second element may be referred to as a first element. In this specification, unless the context clearly indicates otherwise, the singular expressions “a,” “an,” and “the” are intended to include the plural forms as well.

[0049] Additionally, the terms "below," "under," "on the lower side," "above," "over (throughout)," and / or "on the upper side," etc., may be used to describe the relationships between the elements shown in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0050] It will also be understood that when the terms “comprising,” “including,” “having,” and / or variations thereof are used in this specification, it indicates the presence of the stated features, quantities, steps, operations, elements, components, or combinations thereof, but does not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements, components, and / or combinations thereof.

[0051] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense.

[0052] In this specification, the expression "A and / or B" means A, B, or A and B. Additionally, expressions such as "at least one of A and B (species / man)" may include A, B, or A and B.

[0053] In this specification, the x-axis, y-axis, and z-axis directions are not limited to the directions of the three axes of a Cartesian coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis directions can be orthogonal to each other, but can also refer to different directions that are not orthogonal to each other.

[0054] In this specification, the term "plane" refers to the view of the target portion from above (e.g., when viewed in a direction perpendicular to the upper surface of the substrate), and the term "section" refers to a vertical cut section of the target portion when viewed from the side.

[0055] In this specification, when the first element is stacked with the second element, this may mean that the first element is arranged above or below the second element and is at least partially stacked with the second element in a plane.

[0056] In this specification, a particular process sequence may be performed differently from the described sequence when an embodiment can be implemented differently. As an example, two processes described consecutively may be performed substantially concurrently (e.g., simultaneously) or in the reverse order of the described sequence.

[0057] For ease of description, the dimensions of the elements in the accompanying drawings may be exaggerated. For example, because the dimensions and thicknesses of the elements in the drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0058] In view of the full contents of this disclosure, those skilled in the art will understand that each suitable feature of the various embodiments of this disclosure may be combined in part or in whole or in combination with one another, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently or in combination with one another in any suitable manner.

[0059] In the following description, embodiments of the present disclosure are illustrated with reference to the accompanying drawings.

[0060] Figure 1This is a figure illustrating a display device 1000 according to one or more embodiments of the present disclosure.

[0061] Reference Figure 1 A display device 1000 according to one or more embodiments of the present disclosure includes a processor 100, a display driver 200, and a display unit 300. The display driver 200 may include a timing controller 210, a data driver 230, and a demultiplexer 250. Additionally, the display unit 300 may include a scan driver 310 and a pixel unit 330.

[0062] The timing controller 210 can receive grayscale and timing signals for each frame period from the processor 100. The processor 100 can be at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP). The timing signals can include vertical synchronization signals, horizontal synchronization signals, and / or data enable signals, etc.

[0063] Each cycle of the vertical sync signal can correspond to each frame period. Each cycle of the horizontal sync signal can correspond to each horizontal time period. In response to a pulse at the enable level of the data enable signal, grayscale can be supplied on a horizontal line basis in each horizontal time period. A horizontal line can refer to pixels connected to the same scan line and the same emission line (e.g., a pixel row).

[0064] The timing controller 210 can render grayscale to correspond to the specifications of the display device 1000. For example, the processor 100 can provide red, green, and blue gradients for each unit point. For example, when the pixel unit 330 has an RGB stripe structure, pixels can be mapped to corresponding grayscale values ​​one-to-one. In this case, gradient rendering may be unnecessary. However, for example, when the pixel unit 330 has a pentiline... ® In structuring, because pixels are shared between adjacent unit points, pixels may not be able to correspond to corresponding gray levels in a one-to-one manner. This is the PENTILE. ® The arrangement structure can be referred to as an RGBG matrix structure (e.g., Pentium). ® Matrix structure or RGBG structure (e.g., Pentium) ® Structure). PENTILE ® This is a registered trademark of Samsung Display Co., Ltd. of South Korea. In this case, gradient rendering may be necessary. Rendered or unrendered grayscale can be provided to data driver 230. In addition, timing controller 210 can provide data control signals to data driver 230. In addition, timing controller 210 can provide scan control signals to scan driver 310.

[0065] The data driver 230 can use grayscale and data control signals received from the timing controller 210 to generate data voltages (i.e., data signals) to be output to output lines YL1, YL2, ..., YLk. Here, k can be an integer greater than zero. The data signals output to output lines YL1, YL2, ..., YLk can be multiplexed data signals. For example, the data signal output from the first output line YL1 can be selectively provided to the first data line DL1, the second data line DL2, or the third data line DL3. Additionally, the data signal output from the second output line YL2 can be selectively provided to the fourth data line DL4, the fifth data line DL5, or the sixth data line DL6. In the same manner, the data signal output from the k-th output line YLk can be selectively provided to the (n-2)-th data line DL(n-2), the (n-1)-th data line DL(n-1), or the n-th data line DLn.

[0066] Demultiplexer 250 can demultiplex the data voltages output from output lines YL1, YL2, ..., and YLk, and selectively provide the demultiplexed data voltages to data lines DL1, DL2, DL3, DL4, ..., and DLn. In one or more embodiments, demultiplexer 250 can be a 1:3 demultiplexer. In this case, n, which represents the number of data lines DL1, DL2, DL3, DL4, ..., and DLn, can be three times k, which represents the number of output lines YL1, YL2, ..., and YLk. In other words, a relationship of "n=3k" can be established.

[0067] Scan driver 310 can use scan control signals (e.g., clock signals and / or scan start signals, etc.) received from timing controller 210 to generate scan signals to be provided to scan lines SL1, SL2, SL3, ..., SLm. Scan driver 310 can sequentially supply scan signals with on-level pulses to scan lines SL1 to SLm. Scan driver 310 may include scan stages constructed in the form of shift registers. Scan driver 310 can generate scan signals under the control of a clock signal in a manner that sequentially transmits scan start signals in the form of on-level pulses to the next scan stage. Here, m can be an integer greater than zero.

[0068] In one or more embodiments, the scan driver 310 may be connected to lines in the row direction other than scan lines SL1, SL2, SL3, ... and SLm.

[0069] The pixel unit 330 includes a plurality of sub-pixels SPXij. Each of the plurality of sub-pixels SPXij may be composed of a sub-pixel circuit and a light-emitting device. Specifically, the pixel unit 330 may include sub-pixel circuits arranged in a matrix having m rows and n columns, and each of the sub-pixel circuits may be connected to the anode of the corresponding light-emitting device. m and n may both be integers greater than or equal to 2.

[0070] Each sub-pixel SPXij can be connected to the corresponding data line and the corresponding scan line. Sub-pixel SPXij can be connected to the i-th scan line SLi (see...). Figure 2 ) and the j-th data line DLj (see Figure 2 The subpixel SPXij can include subpixels that emit light of a first color, subpixels that emit light of a second color, and subpixels that emit light of a third color. The first color, the second color, and the third color can be different colors. For example, the first color can be one of red, green, and blue; the second color can be one of red, green, and blue that is not the first color; and the third color can be another color of red, green, and blue that is not the first color or the second color. Alternatively, magenta, cyan, and yellow can be used instead of red, green, and blue as the first to third colors.

[0071] Figure 2 It is shown Figure 1 The image of subpixels SPXij.

[0072] Reference Figure 2 Subpixel SPXij includes subpixel circuit SPCij and light-emitting device LDij.

[0073] The sub-pixel circuit SPCij may include multiple transistors. In one or more embodiments, the sub-pixel circuit SPCij may include a driving transistor. The current applied to the light-emitting device LDij can be controlled according to the gate voltage of the driving transistor.

[0074] In one or more embodiments, the sub-pixel circuit SPCij may include one or more capacitors. Because the sub-pixel circuit SPCij can be implemented in various ways, a detailed description of examples of implementations of the sub-pixel circuit SPCij will be omitted herein.

[0075] The scan line SLi and data line DLj can be connected to the sub-pixel circuit SPCij. Additionally, the sub-pixel circuit SPCij can be connected to the first power line ELVDD, the initialization voltage line Vint, and the second power line ELVSS.

[0076] The light-emitting device LDij may have an anode connected to the sub-pixel circuit SPCij and a cathode connected to the second electric field line ELVSS. The light-emitting device LDij may be a light-emitting diode. The light-emitting device LDij may be composed of an organic light-emitting diode (OLED), an inorganic light-emitting diode, and / or a quantum dot / well light-emitting diode, etc. The light-emitting device LDij may emit light of one of a first color, a second color, and a third color. In this embodiment, only one light-emitting device LDij is disposed in each pixel, but in other embodiments, multiple light-emitting devices may be disposed in each pixel. Multiple light-emitting devices may be connected in series, parallel, and / or series-parallel connections, etc.

[0077] A first power voltage can be applied to a first power line ELVDD, a second power voltage can be applied to a second power line ELVSS, and an initialization voltage can be applied to an initialization voltage line Vint. For example, the first power voltage can be greater than the second power voltage. For example, the initialization voltage can be greater than or equal to the second power voltage. For example, the initialization voltage can correspond to the minimum value of the available data voltages. In another example, the value of the initialization voltage can be less than the value of the available data voltages.

[0078] Figure 3 yes Figure 1 A schematic diagram of the equivalent circuit of the sub-pixel SPXij. Figure 3 The diagrams are illustrative and this disclosure is not limited thereto. Figure 1 The sub-pixel SPXij in the middle can be composed of having the same as Figure 3 The equivalent circuits of various structures shown are constructed using the different structures illustrated.

[0079] Reference Figure 3 Subpixel SPXij may include a first transistor T1 to a sixth transistor T6, a storage capacitor Cst, a holding capacitor Chold, and a light-emitting device LDij.

[0080] The first transistor T1 (i.e., the driving transistor) includes a first control electrode connected to a first node N1, a first electrode connected to a fourth node N4, a second electrode connected to a second node N2, and a second control electrode connected to a holding capacitor Chold. The second transistor T2 includes a control electrode for receiving a first gate signal GW, a first electrode for receiving a data voltage Vdata, and a second electrode connected to the first node N1. The third transistor T3 includes a control electrode for receiving a second gate signal GR, a first electrode connected to a reference voltage line VREF, and a second electrode connected to the first node N1. The fourth transistor T4 includes a control electrode for receiving a third gate signal GB, a first electrode connected to the third node N3, and a second electrode for receiving an initialization voltage. The fifth transistor T5 includes a control electrode for receiving a first transmit control signal EM, a first electrode connected to a first power line ELVDD, and a second electrode connected to the fourth node N4. The sixth transistor T6 includes a control electrode for receiving a second transmit control signal EMB, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The first electrode of the storage capacitor Cst can be connected to the first node N1, and the second electrode of the storage capacitor Cst can be connected to the second node N2. The first electrode of the holding capacitor Chold can be connected to the reference voltage line VREF, and the second electrode of the holding capacitor Chold can be connected to the second control electrode of the first transistor T1.

[0081] Reference Figure 3 The data voltage Vdata is provided via data line DLj, and the first gate signal GW can be provided via the first scan line SL1i. The second gate signal GR can be provided via the second scan line SL2i, and the third gate signal GB can be provided via the third scan line SL3i. The first transmit control signal EM can be provided via the first transmit control line EL1i, and the second transmit control signal EMB can be provided via the second transmit control line EL2i. The first scan line SL1i, the second scan line SL2i, and the third scan line SL3i can be connected to... Figure 1 The scan driver 310. In one or more embodiments, the first transmit control line EL1i and the second transmit control line EL2i can be connected to Figure 1 The scan driver 310. In one or more embodiments, the first transmit control line EL1i and the second transmit control line EL2i may be connected to a transmit controller that is separate from the scan driver 310.

[0082] In one or more embodiments, the first transistor T1 to the sixth transistor T6 of the sub-pixel SPXij may be N-type transistors. However, this is an example, and the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the sixth transistor T6 may be a P-type transistor.

[0083] Figure 4 It is shown Figure 1 A diagram of an embodiment of the pixel portion 330 shown.

[0084] Reference Figure 4 It shows 30 sub-pixel circuits and 30 light-emitting devices connected to the 30 sub-pixel circuits, as well as... Figure 4 The sub-pixel circuits, not shown, connect to three light-emitting devices. Specifically, the sub-pixel circuits and their corresponding light-emitting devices are shown in a matrix of 3 rows and 10 columns.

[0085] For example, ten sub-pixel circuits SPC11, SPC12, SPC13, ..., and SPC20, respectively connected to ten light-emitting devices LD11, LD12, LD13, ..., and LD20, are arranged in the first row. Furthermore, ten sub-pixel circuits SPC21, ..., respectively connected to ten light-emitting devices LD21, ..., are arranged in the second row. Ten sub-pixel circuits are arranged in the third row, and each of the ten light-emitting devices is connected to one of the ten sub-pixel circuits. For ease of description, the reference numerals for the sub-pixel circuits after SPC21 in the second row and the light-emitting devices after LD21 in the second row are omitted and not described.

[0086] according to Figure 4 The pixel shown has light-emitting devices constituting a sub-pixel arranged in an RGB stripe structure. However, this is illustrative, and the present disclosure is not limited thereto. For example, the light-emitting devices constituting a sub-pixel can be pentiline. ® Structures or other structural arrangements of various types.

[0087] exist Figure 4 In this embodiment, the light-emitting device can be arranged above the sub-pixel circuit, and the anode electrode of the light-emitting device can be connected to the corresponding sub-pixel circuit via a contact. However, embodiments of this disclosure are not limited thereto; the light-emitting device can also be arranged below the sub-pixel circuit.

[0088] exist Figure 4 In this specification, light-emitting devices emitting red light are shaded, those emitting green light are shown in white, and those emitting blue light are shaded. In this specification, a subpixel including a red-light-emitting device and its connected subpixel circuit is referred to as a red subpixel. Similarly, in this specification, a subpixel including a green-light-emitting device and its connected subpixel circuit is referred to as a green subpixel. Finally, in this specification, a subpixel including a blue-light-emitting device and its connected subpixel circuit is referred to as a blue subpixel.

[0089] In this specification, the sub-pixel circuit connected to the light-emitting device that emits red light is called the red sub-pixel circuit, the sub-pixel circuit connected to the light-emitting device that emits green light is called the green sub-pixel circuit, and the sub-pixel circuit connected to the light-emitting device that emits blue light is called the blue sub-pixel circuit.

[0090] For example, among the light-emitting devices LD11, LD12, LD13, ... and LD20 connected to the sub-pixel circuits SPC11, SPC12, SPC13, ... and SPC20 located in the first row, light-emitting devices LD11, LD14, LD17 and LD20 emit red light, light-emitting devices LD12, LD15 and LD18 emit green light, and light-emitting devices LD13, LD16 and LD19 emit blue light. The sub-pixel circuits SPC11, SPC14, SPC17, and SPC20, which are connected to the red-emitting light-emitting devices LD11, LD14, LD17, and LD20 respectively, are marked with "R". The sub-pixel circuits SPC12, SPC15, and SPC18, which are connected to the green-emitting light-emitting devices LD12, LD15, and LD18 respectively, are marked with "G". And the sub-pixel circuits SPC13, SPC16, and SPC19, which are connected to the blue-emitting light-emitting devices LD13, LD16, and LD19, are marked with "B". The same applies to the sub-pixel circuits shown in the second and third rows.

[0091] Reference Figure 4 The sub-pixel circuits in each row are arranged in order to connect to the light-emitting devices that display the color "RGBRGBRGBR".

[0092] Reference Figure 5 Description of connection Figure 4 The data lines and scan lines of the sub-pixel circuit shown are illustrated.

[0093] Figure 5 Is showing the connection to Figure 4 The diagram shows the data lines and scan lines of the sub-pixel circuit.

[0094] Reference Figure 5 , showed Figure 4 The diagram shows a circuit with 30 sub-pixels. For ease of discussion, from... Figure 5 The illustration of the light-emitting device is omitted. Figure 5 In the image, the sub-pixel circuit connected to the light-emitting device emitting red light is shaded, the sub-pixel circuit connected to the light-emitting device emitting green light is shown in white, and the sub-pixel circuit connected to the light-emitting device emitting blue light is shaded. As described above, each component of the sub-pixel circuit is included in the sub-pixel of the pixel section 330.

[0095] The first data line DL1 is connected to the sub-pixel circuit located in the first column, and the second data line DL2 is connected to the sub-pixel circuit located in the second column. The third data line DL3 is connected to the sub-pixel circuit located in the third column, and the fourth data line DL4 is connected to the sub-pixel circuit located in the fourth column. In this manner, each of the data lines DL1 to DL10 can be connected to the sub-pixel circuit located in the corresponding column.

[0096] Scan line SL1, corresponding to the first row, is connected to the sub-pixel circuit located in the first row; scan line SL2, corresponding to the second row, is connected to the sub-pixel circuit located in the second row; and scan line SL3, corresponding to the third row, is connected to the sub-pixel circuit located in the third row. In this manner, each of scan lines SL1 to SL3 can be connected to the sub-pixel circuit located in the corresponding row.

[0097] The demultiplexer 250 can be connected to the pixel unit 330 via data lines DL1 to DL10. The demultiplexer 250 can selectively output data signals from output lines YL1 to YL3 to data lines DL1 to DL10 based on control signals from control signal lines CLA, CLB, and CLC.

[0098] For example, during the first time period, the first control signal line CLA can be activated, and the second control signal line CLB and the third control signal line CLC can be deactivated. The transistor connected to the first control signal line CLA is turned on, and the transistors connected to the second control signal line CLB and the third control signal line CLC are turned off. Therefore, the demultiplexer 250 can output the data signals from the output lines YL1 to YL3 to the data lines DL1, DL4, DL7, and DL10 connected to the red sub-pixel circuit.

[0099] During the second time period following the first time period, the first control signal line CLA and the third control signal line CLC can be deactivated, and the second control signal line CLB can be activated. The transistors connected to the first control signal line CLA and the third control signal line CLC are turned off, and the transistor connected to the second control signal line CLB is turned on. Therefore, the demultiplexer 250 can output the data signals from the output lines YL1 to YL3 to the data lines DL2, DL5, and DL8 connected to the green sub-pixel circuit.

[0100] Furthermore, during the third time period following the second time period, the first control signal line CLA and the second control signal line CLB can be deactivated, and the third control signal line CLC can be activated. The transistors connected to the first control signal line CLA and the second control signal line CLB are turned off, and the transistor connected to the third control signal line CLC is turned on. Therefore, the demultiplexer 250 can output the data signals from the output lines YL1 to YL3 to the data lines DL3, DL6, and DL9 connected to the blue sub-pixel circuit.

[0101] Figure 6 This is a timing diagram illustrating the operation of a display device 1000 according to one or more embodiments of the present disclosure.

[0102] Reference Figure 6 The diagram shows the timing of the operation of the sub-pixel circuits located in rows i-1, i, and i+1 during the first time period p1 to the twelfth time period p12.

[0103] Specifically, Figure 6 The first gate signal GW(i-1), the first gate signal GWi, and the first gate signal GW(i+1) supplied to the sub-pixel circuit in the (i-1)th row are shown. Figure 6 The diagram also shows the signals connected to the first control signal line CLA, the second control signal line CLB, and the third control signal line CLC of the demultiplexer 250. Finally, Figure 6 The data signal output from the output line YL is shown. Figure 6 The output line YL in the middle can be Figure 5 One of the output lines YL1 to YL3 shown. Figure 6 In the diagram, the data signal applied to the red sub-pixel circuit is shaded, the data signal applied to the green sub-pixel circuit is represented in white, and the data signal applied to the blue sub-pixel circuit is shaded.

[0104] Reference Figure 6 During the first time period p1, the first gate signal GW(i-1) supplied to the sub-pixel circuit in the (i-1)th row is activated at a high level, and the signal of the first control signal line CLA is activated at a low level. The signals of the second control signal line CLB and the third control signal line CLC are deactivated (e.g., at a high level). Therefore, during the first time period p1, the data voltage Vdata is supplied to the red sub-pixel circuit in the (i-1)th row.

[0105] During the second time period p2, the first gate signal GW(i-1) supplied to the sub-pixel circuit in row i-1 remains active, and the signal of the second control signal line CLB is activated to a low level. The signals of the first control signal line CLA and the third control signal line CLC are deactivated (e.g., at a high level). Therefore, during the second time period p2, the data voltage Vdata is supplied to the green sub-pixel circuit in row i-1.

[0106] During the third time period p3, the first gate signal GW(i-1) supplied to the sub-pixel circuit in row i-1 remains active, and the signal of the third control signal line CLC is activated to a low level. The signals of the first control signal line CLA and the second control signal line CLB are deactivated (e.g., at a high level). Therefore, during the third time period p3, the data voltage Vdata is supplied to the blue sub-pixel circuit in row i-1.

[0107] The first time period p1, the second time period p2, and the third time period p3 can constitute a horizontal time period 1H, and the data voltage Vdata is supplied to the sub-pixel circuit in the (i-1)th row during the first time period p1, the second time period p2, and the third time period p3.

[0108] During the fourth time period p4, the first gate signal GW(i-1) supplied to the sub-pixel circuit in row i-1 can be changed to a deactivated state (e.g., at a low level). During the fourth time period p4, the signals of the first control signal line CLA, the second control signal line CLB, and the third control signal line CLC can be deactivated (e.g., at a high level).

[0109] Then, using a similar process, the data voltage Vdata is supplied to the sub-pixel circuit of the i-th row during the fifth time period p5, the sixth time period p6, and the seventh time period p7, and the data voltage Vdata can be supplied to the sub-pixel circuit of the (i+1)-th row during the ninth time period p9, the tenth time period p10, and the eleventh time period p11. The signals of the first control signal line CLA, the second control signal line CLB, and the third control signal line CLC can be deactivated (e.g., at a high level) during the eighth time period p8 and the twelfth time period p12.

[0110] according to Figures 4 to 6 In the embodiment shown, the number of output lines YL1 to YLk for outputting data from the data driver 230 is one-third the number of data lines DL1 to DLn connected to the pixel unit 330. That is, the number of lines directly connected to the data driver 230 can be reduced to one-third of the number of sub-pixel columns. However, according to... Figures 4 to 6The embodiment shown requires transmitting the voltage corresponding to the data signal to the gate of the driving transistor in each of the sub-pixel circuits during a time period (H / 3) corresponding to 1 / 3 of a horizontal time period 1H, which may not be desirable for high-speed driving. Furthermore, a demultiplexer 250 exists between the data driver 230 and the pixel section 330, and the number of transistors included in the demultiplexer 250 is the same as the number of data lines DL1 to DLn. That is, because the demultiplexer 250, which requires a large number of transistors, is included in the display driver 200, the area occupied by the display driver 200 and the power consumed by the display driver 200 increase.

[0111] According to one or more embodiments of the present disclosure, in a display device 1000, the sub-pixel circuits corresponding to three columns share each of the output lines YL connected to the data driver 230 without the demultiplexer 250. Therefore, since the transistors included in the demultiplexer 250 can be removed, the area used to manufacture the display driver 200 can be reduced.

[0112] In addition, because the sub-pixel circuit is directly connected to k (1 / 3 of n) output lines YL1 to YLk, instead of being connected to n data lines DL1 to DLn, the number of lines arranged in the vertical direction can be reduced.

[0113] Figure 7 This is a figure illustrating a display device 1001 according to one or more embodiments of the present disclosure.

[0114] Reference Figure 7 A display device 1001 according to one or more embodiments of the present disclosure includes a processor 101, a display driver 201, and a display unit 301. The display driver 201 may include a timing controller 211 and a data driver 231. Additionally, the display unit 301 may include a scan driver 311 and a pixel unit 331. (The remaining text is omitted.) Figure 7 The shown with Figure 1 The components shown are substantially the same or partially repeated.

[0115] Figure 7 The processor 101 and timing controller 211 can be with Figure 1 The processor 100 and timing controller 210 are essentially the same.

[0116] The data driver 231 can use grayscale and data control signals received from the timing controller 211 to generate data voltages (i.e., data signals) output to output lines YL1, YL2, ..., and YLk. The data signals output to output lines YL1, YL2, ..., and YLk can be multiplexed data signals. The data driver 231 can output a data signal via at least one of the output lines YL1, YL2, ..., and YLk using the grayscale and data control signals received from the timing controller 211.

[0117] The data driver 231 can be directly connected to the pixel section 331 of the display section 301 via output lines YL1, YL2, ... and YLk. In the sub-pixel SPXij of the pixel section 331, three sub-pixels can be connected to share a single output line.

[0118] Scan driver 311 can generate scan signals to be provided to first scan lines SL1a, SL2a, ... and SLma, second scan lines SL1b, SL2b, ... and SLmb, and third scan lines SL1c, SL2c, ... and SLmc by using scan control signals (e.g., clock signals and / or scan start signals, etc.) received from timing controller 211. Scan driver 311 can supply scan signals with on-level pulses to first scan lines SL1a, SL2a, ... and SLma, second scan lines SL1b, SL2b, ... and SLmb, and third scan lines SL1c, SL2c, ... and SLmc.

[0119] In one or more embodiments, each of the first scan lines SL1a, SL2a, ..., and SLma is connected to the red sub-pixel circuit in the corresponding row's sub-pixel circuit; the second scan lines SL1b, SL2b, ..., and SLmb are connected to the green sub-pixel circuit in the corresponding row's sub-pixel circuit; and the third scan lines SL1c, SL2c, ..., and SLmc are connected to the blue sub-pixel circuit in the corresponding row's sub-pixel circuit. That is, a sub-pixel included in a row can be connected to one of the first, second, and third scan lines corresponding to that row. Figure 1 In the embodiment shown, the number of scan lines in the row direction is m, while Figure 7 In the embodiment shown, the number of scan lines in the row direction is 3m.

[0120] Figure 8 It is shown Figure 7 A diagram of an embodiment of the pixel portion 331 shown.

[0121] Reference Figure 8 This illustrates a 36-subpixel circuit. For ease of discussion, from... Figure 8The illustration of the light-emitting device is omitted. The sub-pixel circuits in each row are arranged in order to connect to the light-emitting devices that display the color "RGBRGBRGBRGB". As described above, each component in the sub-pixel circuit includes a sub-pixel SPXij in the pixel section 331.

[0122] according to Figure 8 In the embodiment shown, each of the sub-pixel circuits is not connected to a data line, but directly to output lines YL1 to YL4. Output lines YL1 to YL4 can also be connected to data driver 231. Specifically, each of output lines YL1 to YL4 can be collectively connected to the sub-pixel corresponding to the three columns.

[0123] Specifically, the first output line YL1 is connected to the sub-pixel circuits located in the first, second, and third columns; the second output line YL2 is connected to the sub-pixel circuits located in the fourth, fifth, and sixth columns; the third output line YL3 is connected to the sub-pixel circuits located in the seventh, eighth, and ninth columns; and the fourth output line YL4 is connected to the sub-pixel circuits located in the tenth, eleventh, and twelfth columns. In this manner, each of the output lines YL1 to YL4 can be jointly connected to the sub-pixel circuits located in the corresponding three columns.

[0124] A first scan line SL1a corresponding to the first row is connected to the red sub-pixel circuit in the sub-pixel circuit located in the first row, and a second scan line SL1b corresponding to the first row is connected to the green sub-pixel circuit in the sub-pixel circuit located in the first row. A first scan line SL2a corresponding to the second row is connected to the red sub-pixel circuit in the sub-pixel circuit located in the second row, and a second scan line SL2b corresponding to the second row is connected to the green sub-pixel circuit in the sub-pixel circuit located in the second row. A first scan line SL3a corresponding to the third row is connected to the red sub-pixel circuit in the sub-pixel circuit located in the third row, and a second scan line SL3b corresponding to the third row is connected to the green sub-pixel circuit in the sub-pixel circuit located in the third row. In this manner, the first scan lines SL1a to SL3a and the second scan lines SL1b to SL3b can be selectively connected to either the odd-numbered or even-numbered sub-pixel circuits in the corresponding rows. Furthermore, the third scan line SL1c corresponding to the first row is connected to the blue sub-pixel circuit in the sub-pixel circuit located in the first row, the third scan line SL2c corresponding to the second row is connected to the blue sub-pixel circuit in the sub-pixel circuit located in the second row, and the third scan line SL3c corresponding to the third row is connected to the blue sub-pixel circuit in the sub-pixel circuit located in the third row. In this manner, the third scan lines SL1c to SL3c can be selectively connected to either the odd-numbered or even-numbered sub-pixel circuits in the corresponding rows.

[0125] Figure 9 It shows the basis Figure 8 A timing diagram of the operation of the display device 1001 in an embodiment.

[0126] Reference Figure 9 The diagram shows the timing of the operation of the sub-pixel circuits located in rows i-1, i, and i+1 during the first time period p1 to the twelfth time period p12.

[0127] Specifically, Figure 9 The diagram shows the first gate signal GW(i-1)a, the second gate signal GW(i-1)b, and the third gate signal GW(i-1)c supplied to the sub-pixel circuit in row i-1; the first gate signal GWia, the second gate signal GWib, and the third gate signal GWic supplied to the sub-pixel circuit in row i; and the first gate signal GW(i+1)a, the second gate signal GW(i+1)b, ​​and the third gate signal GW(i+1)c supplied to the sub-pixel circuit in row i+1. Figure 9 The diagram also shows the data signal output from the output line YL. Figure 9 The output line YL in the middle can be Figure 8One of the output lines YL1 to YL4 shown. Figure 9 In the diagram, the data signal applied to the red sub-pixel circuit is shaded, the data signal applied to the green sub-pixel circuit is represented in white, and the data signal applied to the blue sub-pixel circuit is shaded.

[0128] Reference Figure 9 During the first time period p1, the first gate signal GW(i-1)a, one of the first gate signals GW(i-1)a, the second gate signal GW(i-1)b, and the third gate signal GW(i-1)c supplied to the sub-pixel circuit of the (i-1)th row, is activated at a high level, while the second gate signals GW(i-1)b and the third gate signal GW(i-1)c remain deactivated (e.g., at a low level). Additionally, during the first time period p1, the first gate signals GWia, the second gate signal GWib, and the third gate signal GWic supplied to the sub-pixel circuit of the i-th row, as well as the first gate signals GW(i+1)a, the second gate signal GW(i+1)b, ​​and the third gate signal GW(i+1)c supplied to the sub-pixel circuit of the (i+1)th row, are also deactivated (e.g., at a low level). Therefore, during the first time period p1, the data voltage Vdata is supplied to the red sub-pixel circuit of the (i-1)th row.

[0129] During the second time period p2, the second gate signal GW(i-1)b, one of the first gate signals GW(i-1)a, the second gate signal GW(i-1)b, and the third gate signal GW(i-1)c supplied to the sub-pixel circuit in the (i-1)th row, is activated at a high level, while the first gate signal GW(i-1)a and the third gate signal GW(i-1)c remain deactivated (e.g., at a low level). Additionally, during the second time period p2, the first gate signals GWia, the second gate signal GWib, and the third gate signal GWic supplied to the sub-pixel circuit in the ith row, as well as the first gate signals GW(i+1)a, the second gate signal GW(i+1)b, ​​and the third gate signal GW(i+1)c supplied to the sub-pixel circuit in the (i+1)th row, also remain deactivated (e.g., at a low level). Therefore, during the second time period p2, the data voltage Vdata is supplied to the green sub-pixel circuit in the (i-1)th row.

[0130] During the third time period p3, the third gate signal GW(i-1)c is activated at a high level among the first gate signal GW(i-1)a, second gate signal GW(i-1)b, and third gate signal GW(i-1)c supplied to the sub-pixel circuit in row i-1, while the first gate signal GW(i-1)a and second gate signal GW(i-1)b remain deactivated (e.g., at a low level). Additionally, during the third time period p3, the first gate signals GWia, second gate signal GWib, and third gate signal GWic supplied to the sub-pixel circuit in row i, and the first gate signals GW(i+1)a, second gate signal GW(i+1)b, ​​and third gate signal GW(i+1)c supplied to the sub-pixel circuit in row i+1, also remain deactivated (e.g., at a low level). Therefore, during the third time period p3, the data voltage Vdata is supplied to the blue sub-pixel circuit in row i-1.

[0131] The first time period p1, the second time period p2, and the third time period p3 can constitute a horizontal time period 1H, and the data voltage Vdata is supplied to the sub-pixel circuit in the (i-1)th row during the first time period p1, the second time period p2, and the third time period p3.

[0132] During the fourth time period p4, the first gate signal GW(i-1)a, the second gate signal GW(i-1)b, and the third gate signal GW(i-1)c supplied to the sub-pixel circuits in row (i-1) can remain in a deactivated state (e.g., at a low level). Additionally, during the fourth time period p4, the first gate signal GWia, the second gate signal GWib, and the third gate signal GWic supplied to the sub-pixel circuits in row i, and the first gate signal GW(i+1)a, the second gate signal GW(i+1)b, ​​and the third gate signal GW(i+1)c supplied to the sub-pixel circuits in row i+1 can remain in a deactivated state (e.g., at a low level).

[0133] Then, through a similar process, the data voltage Vdata is supplied to the sub-pixel circuit of the i-th row during the fifth time period p5, the sixth time period p6, and the seventh time period p7, and the data voltage Vdata can be supplied to the sub-pixel circuit of the (i+1)-th row during the ninth time period p9, the tenth time period p10, and the eleventh time period p11. The first gate signal GW(i-1)a, the second gate signal GW(i-1)b, and the third gate signal GW(i-1)c supplied to the sub-pixel circuit of the (i-1)-th row, the first gate signal GWia, the second gate signal GWib, and the third gate signal GWic supplied to the sub-pixel circuit of the i-th row, and the first gate signal GW(i+1)a, the second gate signal GW(i+1)b, ​​and the third gate signal GW(i+1)c supplied to the sub-pixel circuit of the (i+1)-th row can be in a deactivated state during the eighth time period p8 and the twelfth time period p12.

[0134] according to Figures 7 to 9 The embodiment shown corresponds to three columns of sub-pixel circuits sharing each of the output lines YL connected to the data driver 231 without the demultiplexer 250. Therefore, because the transistors included in the demultiplexer 250 can be removed, the area used to manufacture the display driver 201 can be reduced.

[0135] In addition, because the sub-pixel circuit is directly connected to k (1 / 3 of n) output lines YL1 to YLk, instead of being connected to n data lines DL1 to DLn, the number of lines arranged in the vertical direction can be reduced.

[0136] Figure 10 It is shown Figure 7 A diagram of another embodiment of the pixel portion 331 shown.

[0137] Reference Figure 10 This illustrates a circuit with 18 sub-pixels. For ease of discussion, from... Figure 10 The output lines are omitted from the diagram. As described above, each component in the sub-pixel circuit includes a sub-pixel SPXij in the pixel section 331.

[0138] exist Figure 10 In this context, it includes three sub-pixels within a single pixel arranged in the row direction. Specifically, in... Figure 10 In this design, sub-pixel circuits SPC11, SPC12, and SPC13 constitute a pixel. The sub-pixel circuits SPC11, SPC12, and SPC13 are arranged in the row direction, which is the direction along which the scan line extends.

[0139] A shared region CA can be arranged between pixels in the first row and pixels in the second row. Common lines CLs can be arranged within the shared region CA. The common lines CLs can be connected together to the sub-pixel circuits included in each of the pixels in the first row and the sub-pixel circuits included in each of the pixels in the second row.

[0140] As an example, common lines (CLs) can include Figure 3 The reference voltage line VREF, the second scan line SL2i, the third scan line SL3i, the first emission control line EL1i, and the second emission control line EL2i shown are included. In one or more embodiments, the common lines CLs may include repair lines for repairing defective pixels.

[0141] Similarly, the shared region CA can be placed between the pixels in the third row and the pixels in the fourth row.

[0142] According to one or more embodiments of this disclosure, sub-pixel circuits formed on opposite sides of the shared region CA in the column direction can have a symmetrical layout. For example, the layout of the circuit forming the red sub-pixel circuit SPC11 in the first row of the first column and the layout of the circuit forming the red sub-pixel circuit SPC21 in the second row of the first column can have a linearly symmetrical shape with respect to the shared region CA. Similarly, the layout of the circuit forming the green sub-pixel circuit SPC12 in the first row of the second column and the layout of the circuit forming the green sub-pixel circuit SPC22 in the second row of the second column can have a linearly symmetrical shape with respect to the shared region CA. Sub-pixel circuits SPC13, SPC14, SPC15, SPC16, SPC17, SPC18 and SPC19 in the first row and sub-pixel circuits SPC23, SPC24, SPC25, SPC26, SPC27, SPC28 and SPC29 in the second row have similar structures. Therefore, sub-pixel circuits located on opposite sides of the shared region CA in the column direction can have the same electrical characteristics.

[0143] Figure 11 It is shown Figure 7 A diagram of another embodiment of the pixel portion 331 shown.

[0144] Reference Figure 11 This illustrates a circuit with 18 sub-pixels. For ease of discussion, from... Figure 11 The output lines are omitted from the diagram. As described above, each component in the sub-pixel circuit includes a sub-pixel SPXij in the pixel section 331.

[0145] and Figure 10 The arrangements shown are different, in Figure 11In this context, three subpixels belonging to a single pixel are arranged in a column direction. Specifically, in... Figure 11 In this design, sub-pixel circuits SPC11, SPC12, and SPC13 constitute a pixel. Sub-pixel circuits SPC11, SPC12, and SPC13 are arranged in the column direction, which is the direction along which the output line YL extends.

[0146] and Figure 10 Similarly, in Figure 11 In this configuration, a shared region CA can be arranged between pixels in the first row and pixels in the second row. Common lines CLs can be arranged within the shared region CA. The common lines CLs can be jointly connected to the sub-pixel circuits included in each of the pixels in the first row and the sub-pixel circuits included in each of the pixels in the second row.

[0147] Similarly, in one or more embodiments, the shared region CA may be arranged between the pixels in the third row and the pixels in the fourth row.

[0148] According to one or more embodiments of this disclosure, sub-pixel circuits formed on opposite sides of the shared region CA in the column direction can have a symmetrical layout. For example, blue sub-pixel circuits SPC13, SPC16, SPC19, SPC23, SPC26, and SPC29 can be positioned closest to the shared region CA, green sub-pixel circuits SPC12, SPC15, SPC18, SPC22, SPC25, and SPC28 can be positioned further away from the shared region CA than blue sub-pixel circuits SPC13, SPC16, SPC19, SPC23, SPC26, and SPC29, and red sub-pixel circuits SPC11, SPC14, SPC17, SPC21, SPC24, and SPC27 can be positioned furthest from the shared region CA.

[0149] Furthermore, the circuit layouts for forming the red sub-pixel circuit SPC11 and SPC21 can have a linearly symmetrical shape with respect to the shared region CA. Similarly, the circuit layouts for forming the green sub-pixel circuit SPC12 and SPC22 can have a linearly symmetrical shape with respect to the shared region CA. Therefore, sub-pixel circuits located on opposite sides of the shared region CA in the column direction can have the same electrical characteristics.

[0150] Figure 12A and Figure 12B This is a diagram illustrating an embodiment of pixels shared by common lines CLs arranged in a shared area CA.

[0151] Reference Figure 12A This shows six pixels: PC1, PC2, PC3, PC4, PC5, and PC6. (See reference...) Figure 10 and Figure 11 As described, a pixel may include multiple sub-pixels. For example, pixel PC1 may include sub-pixel circuits SPC11, SPC12, and SPC13; pixel PC2 may include sub-pixel circuits SPC14, SPC15, and SPC16; and pixel PC3 may include sub-pixel circuits SPC17, SPC18, and SPC19. Pixel PC4 may include sub-pixel circuits SPC21, SPC22, and SPC23; pixel PC5 may include sub-pixel circuits SPC24, SPC25, and SPC26; and pixel PC6 may include sub-pixel circuits SPC27, SPC28, and SPC29.

[0152] Figure 12A An embodiment is shown in which pixels PC1, PC2, PC3, PC4, PC5, and PC6 corresponding to two rows share a shared region CA. However, this disclosure is not limited thereto.

[0153] Reference Figure 12B An embodiment is shown in which pixels PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, and PC12 corresponding to the four rows share a shared region CA. When the number of pixel rows sharing the shared region CA increases, the area occupied by the shared region CA in the entire pixel segment decreases. Therefore, the resolution of the pixel segment can be increased.

[0154] Figure 13 This is a block diagram of an electronic device 10 according to one or more embodiments. (Refer to...) Figure 13 The electronic device 10 according to one or more embodiments may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0155] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0156] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0157] The power module 14 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0158] At least one of the aforementioned components of the electronic device 10 may be included in the display device according to the above embodiments. Additionally, one or more separate modules that are functionally included in a single module may be included in the display device, and separate modules other than the one or more separate modules may be disposed separately from the display device. For example, the display device includes a display module 11, and the processor 12, memory 13, and power module 14 may be disposed in the electronic device 10 as other devices besides the display device.

[0159] Figure 14 Schematic diagrams of electronic devices according to various embodiments are shown.

[0160] Reference Figure 14 Various electronic devices that apply a display device according to one or more embodiments may include electronic devices for displaying images (such as smartphones 10_1a, tablet PCs 10_1b, laptops 10_1c, televisions 10_1d, or desktop monitors 10_1e), wearable electronic devices including display modules (such as smart glasses 10_2a, head-mounted displays 10_2b, or smartwatches 10_2c), and automotive electronic devices 10_3 including display modules (such as car dashboards, central dashboards, central information displays (CIDs) placed on dashboards, and / or interior mirror displays).

[0161] The foregoing accompanying drawings and the detailed description of this disclosure are merely examples and are intended to illustrate the disclosure, not to limit the meaning or scope of the disclosure claimed in the appended claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments can be made based on the foregoing accompanying drawings and detailed description. Consequently, the true scope of technical protection of this disclosure should be determined by the technical spirit of the appended claims and their equivalents.

[0162] According to one or more embodiments of the present disclosure, the power consumption and heat generation required for the operation of the data driver can be reduced, and the number of transistors included in the display driver can be reduced.

Claims

1. A display device, the display device comprising: Multiple sub-pixel circuits are arranged in a matrix form with multiple rows and multiple columns; A plurality of light-emitting devices, each of the plurality of light-emitting devices being connected to a corresponding sub-pixel circuit in the plurality of sub-pixel circuits; The data driver is configured to output data signals to the plurality of sub-pixel circuits via multiple output lines; as well as The scan driver is configured to output scan signals to the plurality of sub-pixel circuits via multiple first scan lines, multiple second scan lines, and multiple third scan lines. Each of the plurality of output lines is connected to three sub-pixel circuits within a single pixel, which are part of the plurality of sub-pixel circuits. Each of the plurality of first scan lines is connected to the first color sub-pixel circuit in the corresponding row of the plurality of sub-pixel circuits. Each of the plurality of second scan lines is connected to the second color sub-pixel circuit in the corresponding row of the plurality of sub-pixel circuits, and Each of the plurality of third scan lines is connected to the third color sub-pixel circuit in the corresponding row of the plurality of sub-pixel circuits.

2. The display device according to claim 1, wherein The multiple sub-pixel circuits are arranged in a matrix with m rows and n columns. Wherein, the number of the first scan lines is m, the number of the second scan lines is m, and the number of the output lines is n / 3. Specifically, during a horizontal time period corresponding to a selected row among the plurality of rows, the scan driver: during a first time period of the horizontal time period, activates the voltage of the first scan line among the plurality of first scan lines corresponding to the selected row; during a second time period of the horizontal time period, different from the first time period, activates the voltage of the second scan line among the plurality of second scan lines corresponding to the selected row; and during a third time period of the horizontal time period, different from the first and second time periods, activates the voltage of the third scan line among the plurality of third scan lines corresponding to the selected row. Where m and n are both integers of 2 or greater.

3. The display device according to claim 2, wherein During the first time period, the data output to the plurality of output lines is applied to the first color sub-pixel circuit in the sub-pixel circuit corresponding to the selected row. During the second time period, the data output to the plurality of output lines is applied to the second color sub-pixel circuit in the sub-pixel circuit corresponding to the selected row, and During the third time period, the data output to the plurality of output lines is applied to the third color sub-pixel circuit in the sub-pixel circuit corresponding to the selected row.

4. The display device according to claim 1, wherein The plurality of light-emitting devices are located above or below the plurality of sub-pixel circuits.

5. The display device according to claim 1, wherein, The three sub-pixel circuits are arranged in the row direction within the pixel.

6. The display device according to claim 5, wherein, The shared region is located between the sub-pixels in the first row and the sub-pixels in the second row, and In this shared area, at least one common line connecting the sub-pixels in the first row and the sub-pixels in the second row is present.

7. The display device according to claim 6, wherein, The circuit layout of each of the sub-pixels in the first row and the circuit layout of each of the sub-pixels in the second row have a linearly symmetrical shape with respect to the shared region.

8. The display device according to claim 6, wherein, The common lines include repair lines for fixing defective pixels.

9. The display device according to claim 1, wherein, The three sub-pixel circuits are arranged along the column direction in the pixel. The shared region is located between the sub-pixels in the first, second, and third rows and the sub-pixels in the fourth, fifth, and sixth rows, and... In the shared area, at least one common line connecting the sub-pixels in the first to the third rows and the sub-pixels in the fourth to the sixth rows is present.

10. The display device according to claim 9, wherein, The third color sub-pixel circuit is located in the third and fourth rows of the pixel closest to the shared region. Wherein, the second color sub-pixel circuit is located in the second row and the fifth row adjacent to the third color sub-pixel circuit, and The first color sub-pixel circuit is located in the first row and the sixth row of the pixel that are furthest from the shared region.

11. The display device according to claim 10, wherein, The circuit layout of each of the sub-pixels in the first row and the circuit layout of each of the sub-pixels in the sixth row have a linearly symmetrical shape with respect to the shared region. Wherein, the circuit layout of each of the sub-pixels in the second row and the circuit layout of each of the sub-pixels in the fifth row have a linearly symmetrical shape with respect to the shared region, and The circuit layout of each of the sub-pixels in the third row and the circuit layout of each of the sub-pixels in the fourth row have a linearly symmetrical shape with respect to the shared region.

12. The display device according to claim 1, wherein, The data driver is configured to output data to k output lines. The scan driver is configured to output scan signals to m first scan lines, m second scan lines, and m third scan lines. The plurality of sub-pixel circuits are arranged in a matrix with m rows and 3k columns. Among them, the h-th output line is connected to the sub-pixel circuits located in columns 3h-2, 3h-1, and 3h in the plurality of sub-pixel circuits. Specifically, the i-th scan line in the first scan line is connected to the 3j-2 sub-pixel circuit located in the i-th row of the sub-pixel circuit. Wherein, the i-th second scan line in the second scan line is connected to the 3j-1 sub-pixel circuit located in the sub-pixel circuit in the i-th row. Wherein, the i-th third scan line of the third scan line is connected to the 3j-th sub-pixel circuit located in the i-th row of the sub-pixel circuit, and Where m and n are both integers of 2 or greater, k is an integer of 1 or greater, h is an integer greater than 0 and less than or equal to k, i is an integer greater than 0 and less than or equal to m, and j is an integer greater than 0 and less than or equal to k.

13. The display device according to claim 12, wherein, During the horizontal time period corresponding to the i-th row, the scan driver: During the first time period of the horizontal time period, the voltage of the i-th first scan line is activated; During a second time period, which is different from the first time period, the voltage of the i-th second scan line is activated; and During a third time period, which is different from the first and second time periods, the voltage of the i-th third scan line is activated.

14. The display device according to claim 13, wherein, The shared region lies between the sub-pixels in row 2i-1 and row 2i, and In this shared area, at least one common line connecting the sub-pixels in the 2i-1 row and the sub-pixels in the 2i row is arranged.

15. A display device, the display device comprising: The data driver is configured to output data to k output lines; The scan driver is configured to output scan signals to m first scan lines, m second scan lines, and m third scan lines; as well as The pixel unit is connected to the output line, the first scan line, the second scan line, and the third scan line. The pixel portion includes: Multiple sub-pixel circuits are arranged in a matrix with 3m rows and k columns; and multiple light-emitting devices, each of which is connected to a corresponding sub-pixel circuit within the multiple sub-pixel circuits. Among the output lines, the h-th output line is connected to the sub-pixel circuit located in the h-th column of the plurality of sub-pixel circuits. In this case, the i-th scan line in the first scan line is connected to the sub-pixel circuit in the (3i-2)-th row. In this case, the i-th second scan line in the second scan line is connected to the sub-pixel circuit in the (3i-1)-th row. Among them, the i-th third scan line in the third scan line is connected to the sub-pixel circuit in the 3i-th row, and Where m and n are both integers of 2 or greater, k is an integer of 1 or greater, h is an integer greater than 0 and less than or equal to k, and i is an integer greater than 0 and less than or equal to m.

16. The display device according to claim 15, wherein, The sub-pixel circuit in row 3i-2 is a first color sub-pixel circuit, the sub-pixel circuit in row 3i-1 is a second color sub-pixel circuit, and the sub-pixel circuit in row 3i is a third color sub-pixel circuit.

17. The display device according to claim 16, wherein, The shared region is located between the sub-pixels in the 3i-th row and the sub-pixels in the 3i+1-th row, and Among them, at least one common line that is connected to the sub-pixel circuit in the 3i-2 row, the sub-pixel circuit in the 3i-1 row, the sub-pixel circuit in the 3i row, the sub-pixel circuit in the 3i+1 row, the sub-pixel circuit in the 3i+2 row, and the sub-pixel circuit in the 3i+3 row is located in the shared area.

18. The display device according to claim 17, wherein, The sub-pixel circuit in the 3i+1 row is the third color sub-pixel circuit, the sub-pixel circuit in the 3i+2 row is the second color sub-pixel circuit, and the sub-pixel circuit in the 3i+3 row is the first color sub-pixel circuit.

19. The display device according to claim 18, wherein, The circuit layout of each of the sub-pixel circuits in the 3i+1th row and the circuit layout of each of the sub-pixel circuits in the 3ith row have a linearly symmetrical shape with respect to the shared region. Wherein, the circuit layout of each of the sub-pixel circuits in the 3i+2 row and the circuit layout of each of the sub-pixel circuits in the 3i-1 row have a linearly symmetrical shape with respect to the shared region, and The circuit layout of each of the sub-pixel circuits in the 3i+3 row and the circuit layout of each of the sub-pixel circuits in the 3i-2 row have a linearly symmetrical shape with respect to the shared region.

20. An electronic device, the electronic device comprising: The processor is configured to provide input image data; as well as A display device configured to display an image based on the input image, wherein the display device includes: a plurality of sub-pixel circuits arranged in a matrix having a plurality of rows and columns; a plurality of light-emitting devices, each of the plurality of light-emitting devices being connected to a corresponding sub-pixel circuit among the plurality of sub-pixel circuits; a data driver configured to output data signals to the plurality of sub-pixel circuits via a plurality of output lines; and a scan driver configured to output scan signals to the plurality of sub-pixel circuits via a plurality of first scan lines, a plurality of second scan lines, and a plurality of third scan lines. Each of the plurality of output lines is connected to three sub-pixel circuits within a single pixel, which are part of the plurality of sub-pixel circuits. Each of the plurality of first scan lines is connected to the first color sub-pixel circuit in the corresponding row of the plurality of sub-pixel circuits. Each of the plurality of second scan lines is connected to the second color sub-pixel circuit in the corresponding row of the plurality of sub-pixel circuits, and Each of the plurality of third scan lines is connected to the third color sub-pixel circuit in the corresponding row of the plurality of sub-pixel circuits.

Images