Display device and electronic device including the display device

Abstract

A display device and an electronic device including the display device are provided. The display device includes: pixel circuits arranged in a first direction and a second direction; first gate lines and second gate lines extending in the first direction; and data lines extending in the second direction. In the pixel circuits, pixel circuits arranged in odd-numbered columns and pixel circuits arranged in even-numbered columns that are adjacent to each other are electrically connected to a data line, and pixel circuits in odd-numbered columns of odd-numbered rows and pixel circuits in even-numbered columns of even-numbered rows are each electrically connected to a corresponding first gate line in the first gate line, and pixel circuits in even-numbered columns of odd-numbered rows and pixel circuits in odd-numbered columns of even-numbered rows are each electrically connected to a corresponding second gate line in the second gate line.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0012635, filed with the Korean Intellectual Property Office on January 31, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a display device and an electronic device including the display device. Background Technology

[0003] Generally, a display device includes multiple gate lines, multiple data lines, and multiple pixels. Each of the multiple pixels is electrically connected to a corresponding gate line and a corresponding data line. As high-resolution and large-size display devices have developed, the number of data lines has increased, thereby increasing manufacturing costs. Summary of the Invention

[0004] One or more embodiments include a display device with a reduced number of data lines and an electronic device including the display device. One or more embodiments include a display device and an electronic device including the display device that further prevents or reduces the increase in power consumption. However, this technical purpose is illustrative, and one or more embodiments are not limited thereto.

[0005] Additional aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0006] According to one or more embodiments, a display device includes: pixel circuits arranged in a first direction and a second direction intersecting the first direction; first gate lines and second gate lines extending in the first direction; and data lines extending in the second direction. Pixel circuits arranged in odd-numbered columns and even-numbered columns that are adjacent to each other in the first direction are electrically connected to a data line. Pixel circuits arranged in odd-numbered columns of odd-numbered rows and even-numbered columns of even-numbered rows are each electrically connected to a corresponding first gate line of the first gate lines. Pixel circuits arranged in even-numbered columns of odd-numbered rows and odd-numbered columns of even-numbered rows are each electrically connected to a corresponding second gate line of the second gate lines.

[0007] In an embodiment, each of the pixel circuits may include: a first transistor electrically connected between a driving voltage line and a light-emitting diode; and a second transistor electrically connected between a corresponding data line and the first transistor. The second transistor of one pixel circuit arranged in an odd-numbered column and another pixel circuit arranged in an even-numbered column, which are adjacent to each other in a first direction, may be connected to a corresponding first gate line in the first gate line, and the second transistor of the other pixel circuit may be connected to a corresponding second gate line in the second gate line.

[0008] In an embodiment, the first transistor may be an oxide semiconductor transistor.

[0009] In an embodiment, the second transistor may include a second gate electrode, and in a plan view, the second gate electrode may have an island shape.

[0010] In one embodiment, the display device may further include: light-emitting diodes (LEDs) electrically connected to the pixel circuit. LEDs electrically connected to the same data line can emit light of the same color.

[0011] In an embodiment, the light-emitting diode (LED) may include a first LED emitting light of a first color, a second LED emitting light of a second color, and a third LED emitting light of a third color. In each odd-numbered LED column, the first and second LEDs may alternate with each other in a second direction, and in each even-numbered LED column, the third LED may be arranged in the second direction.

[0012] In an embodiment, the light-emitting diode (LED) may include a first LED emitting light of a first color, a second LED emitting light of a second color, and a third LED emitting light of a third color. A first LED column arranging the first LEDs in a second direction, a second LED column arranging the second LEDs in a second direction, and a third LED column arranging the third LEDs in a second direction may be sequentially repeated in the first direction.

[0013] In an embodiment, the display device may further include: light-emitting diodes (LEDs) electrically connected to the pixel circuitry. The LEDs may include a first LED emitting light of a first color, a second LED emitting light of a second color, and a third LED emitting light of a third color. Odd-numbered data lines in the data lines may be electrically connected to the first and third LEDs, and even-numbered data lines in the data lines may be electrically connected to the second LED.

[0014] In an embodiment, a first LED column in which the first LED and the third LED alternate in a second direction, a second LED column in which the second LED is arranged in a second direction, a third LED column in which the third LED and the first LED alternate in a second direction, and a fourth LED column in which the second LED is arranged in a second direction can be repeated sequentially in a first direction.

[0015] According to one or more embodiments, a display device includes: a first pixel circuit and a second pixel circuit, adjacent to each other in a row of first pixel circuits; a third pixel circuit and a fourth pixel circuit, adjacent to each other in a row of second pixel circuits; a data driver configured to output a data signal to a data line; a first gate driver configured to sequentially output a first gate signal to a first gate line; and a second gate driver configured to sequentially output a second gate signal to a second gate line. Each of the first pixel circuit and the fourth pixel circuit is electrically connected to a corresponding first gate line in the first gate line, and each of the second pixel circuit and the third pixel circuit is electrically connected to a corresponding second gate line in the second gate line.

[0016] In an embodiment, the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit can be electrically connected to the first data line in the data line.

[0017] In an embodiment, the first data line may be arranged between the first pixel circuit and the second pixel circuit, and between the third pixel circuit and the fourth pixel circuit.

[0018] In an embodiment, the data signal corresponding to the first data line may include a first data voltage corresponding to the first pixel circuit, a second data voltage corresponding to the second pixel circuit, a fourth data voltage corresponding to the fourth pixel circuit, and a third data voltage corresponding to the third pixel circuit. The first data voltage, second data voltage, fourth data voltage, and third data voltage may be output sequentially.

[0019] In an embodiment, the display device may further include: a first light-emitting diode electrically connected to a first pixel circuit; a second light-emitting diode electrically connected to a second pixel circuit; a third light-emitting diode electrically connected to a third pixel circuit; and a fourth light-emitting diode electrically connected to a fourth pixel circuit. The first, second, third, and fourth light-emitting diodes can emit light of the same color.

[0020] In an embodiment, the distance between the first pixel circuit and the first light-emitting diode may be different from the distance between the second pixel circuit and the second light-emitting diode.

[0021] In an embodiment, the display device may further include: a fifth pixel circuit and a sixth pixel circuit, adjacent to each other in a first pixel circuit row; a seventh pixel circuit and an eighth pixel circuit, adjacent to each other in a second pixel circuit row; a fifth light-emitting diode electrically connected to the fifth pixel circuit; a sixth light-emitting diode electrically connected to the sixth pixel circuit; a seventh light-emitting diode electrically connected to the seventh pixel circuit; and an eighth light-emitting diode electrically connected to the eighth pixel circuit. The fifth pixel circuit, the sixth pixel circuit, the seventh pixel circuit, and the eighth pixel circuit may be electrically connected to a second data line in the data lines.

[0022] In an embodiment, each of the first, second, third, and fourth light-emitting diodes can emit green light, each of the fifth and sixth light-emitting diodes can emit blue light, and each of the seventh and eighth light-emitting diodes can emit red light.

[0023] In an embodiment, the second gate driver can be configured to output a second gate signal that is delayed by a specific period of time compared to the first gate signal output from the first gate driver.

[0024] In an embodiment, each of the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit may include: a first transistor electrically connected between a driving voltage line and a light-emitting diode; and a second transistor electrically connected between a corresponding data line and the first transistor. The second transistor of each pixel circuit in the first and fourth pixel circuits may be electrically connected to a corresponding first gate line in the first gate line, and the second transistor of each pixel circuit in the second and third pixel circuits may be electrically connected to a corresponding second gate line in the second gate line.

[0025] In an embodiment, the first transistor may be an oxide semiconductor transistor.

[0026] According to one or more embodiments, an electronic device includes: a display device; a memory for storing image data signals or input control signals; and one or more processors configured to transmit the image data signals or input control signals stored in the memory to the display device. The display device includes: a first pixel circuit and a second pixel circuit adjacent to each other in a row of first pixel circuits; a third pixel circuit and a fourth pixel circuit adjacent to each other in a row of second pixel circuits; a first gate line and a second gate line extending in a first direction; and a data line extending in a second direction intersecting the first direction. The first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are electrically connected to a first data line in the data line. Each of the first pixel circuit and the fourth pixel circuit is electrically connected to a corresponding first gate line in the first gate line, and each of the second pixel circuit and the third pixel circuit is electrically connected to a corresponding second gate line in the second gate line.

[0027] In an embodiment, each of the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit may include: a first transistor electrically connected between a driving voltage line and a light-emitting diode; and a second transistor electrically connected between a first data line and the first transistor. The second transistor of each pixel circuit in the first and fourth pixel circuits may be connected to a corresponding first gate line among the first gate lines, and the second transistor of each pixel circuit in the second and third pixel circuits may be connected to a corresponding second gate line among the second gate lines.

[0028] In an embodiment, the display device may further include: a first light-emitting diode electrically connected to a first pixel circuit; a second light-emitting diode electrically connected to a second pixel circuit; a third light-emitting diode electrically connected to a third pixel circuit; and a fourth light-emitting diode electrically connected to a fourth pixel circuit. The first, second, third, and fourth light-emitting diodes can emit light of the same color.

[0029] In this embodiment, the electronic device may be an electronic device for image display, a wearable electronic device, or a vehicle electronic device. Attached Figure Description

[0030] The above and other aspects, features and advantages of specific embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0031] Figure 1A and Figure 1B Each is a schematic plan view of a display device according to an embodiment.

[0032] Figure 2 This is a schematic diagram of an electronic device according to an embodiment.

[0033] Figure 3 This is a schematic cross-sectional view of a display device according to an embodiment.

[0034] Figure 4 This is a schematic diagram illustrating the equivalent circuit diagram of a pixel according to an embodiment.

[0035] Figure 5 This is a schematic plan view of the pixel circuit according to an embodiment.

[0036] Figure 6 This is a diagram used to schematically illustrate the connection between the pixel circuit and the data lines and gate lines according to an embodiment.

[0037] Figure 7A and Figure 7B Each diagram is used to schematically illustrate the connection between the pixel circuit and the light-emitting diode according to an embodiment.

[0038] Figure 8 It is used to describe what is applied to Figure 6 The diagram shows the gate voltage and data voltage of the pixel circuit.

[0039] Figure 9 This is a schematic plan view of a part of a display device according to an embodiment.

[0040] Figure 10 It is used for illustrative description Figure 9 A diagram illustrating the operation of the pixel circuit and light-emitting diodes in a display device.

[0041] Figure 11 It is applied to Figure 9 A schematic diagram of the data voltage of the first data line of the display device.

[0042] Figure 12 This is a diagram used to schematically illustrate the connection between the pixel circuit and the data lines and gate lines according to an embodiment.

[0043] Figure 13 It is used for illustrative description Figure 12 The diagram shows the connection between the pixel circuit and the light-emitting diode.

[0044] Figure 14 It is used to describe what is applied to Figure 12 The diagram shows the gate voltage and data voltage of the pixel circuit.

[0045] Figure 15 This is a diagram used to schematically illustrate the connection between the pixel circuit and the data lines and gate lines according to an embodiment.

[0046] Figure 16 It is used to describe what is applied to Figure 15The diagram shows the gate voltage and data voltage of the pixel circuit.

[0047] Figure 17 This is a block diagram of an electronic device according to an embodiment.

[0048] Figure 18 An electronic device according to various embodiments is illustrated schematically. Detailed Implementation

[0049] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this respect, the present embodiments may take different forms and should not be construed as limited to the description set forth herein. Accordingly, the embodiments are described below with reference to the accompanying drawings only to explain aspects of this description. As used herein, the term “and / or” includes any and all combinations of one or more of the listed associated items. Throughout this disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0050] While terms such as “first” and “second” can be used to describe various elements, such elements are not necessarily limited to these terms. These terms are used only to distinguish one element from another. As used herein, the terms “even” and “odd” are not used in a restrictive sense, but rather to distinguish elements arranged in sequence.

[0051] As used herein, the singular forms “a” and “the (said)” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0052] It will be understood that, as used herein, the terms “comprising,” “including,” and “having” indicate the presence of the described feature or element, but do not preclude the addition of one or more other features or elements.

[0053] It will be further understood that when a layer, area, or element is referred to as being "on" another layer, area, or element, it can be directly or indirectly on that other layer, area, or element. That is, for example, there can be an intermediate layer, area, or element.

[0054] It will be further understood that when layers, zones, or elements are referred to as being “connected” to each other, they may be directly connected to each other, or they may be indirectly connected to each other with an intervening layer, zone, or element located between them. For example, when layers, zones, or elements are referred to as being “electrically connected” to each other, they may be directly electrically connected to each other, or they may be indirectly electrically connected to each other with an intervening layer, zone, or element located between them.

[0055] In this description, the x, y, and z directions are not limited to directions along the three axes of a Cartesian coordinate system, and can be interpreted in a broader sense. For example, the x, y, and z directions can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0056] As used herein, the phrase “in a plan view” refers to a portion of the target object viewed from above (e.g., in a direction perpendicular to the upper surface of the substrate), and the phrase “in a cross-sectional view” refers to a portion of the target object cut vertically and viewed from the side.

[0057] In this description, when the first element is referred to as "overlapping" with the second element, the first element may be above or below the second element, and may at least partially overlap with the second element in a plan view.

[0058] As used herein, the term "ON" in association with the state of a device can indicate the active state of the device, and the term "OFF" can indicate the inactive state of the device. The term "ON" in association with a signal received by the device can indicate a signal that activates the device, and the term "OFF" can indicate a signal that deactivates the device. A device can be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low-level voltage, and an N-channel transistor (N-type transistor) is activated by a high-level voltage. Therefore, it should be understood that the "ON" voltage for P-type transistors and N-type transistors are opposite voltage levels (low level versus high level).

[0059] When embodiments can be implemented differently, a particular order of processing may be executed differently from the order described. For example, two consecutively described processes may be executed substantially simultaneously, or in the reverse order of their description.

[0060] For ease of explanation, the dimensions of the elements in the accompanying drawings may be enlarged or reduced. For example, since the dimensions and thicknesses of the elements in the accompanying drawings are arbitrarily illustrated for ease of description, the following embodiments are not limited thereto.

[0061] Figure 1A and Figure 1B Each is a schematic plan view of the display device 10 according to an embodiment. Figure 2 This is a schematic diagram of an electronic device 1 including a display device 10 according to an embodiment.

[0062] refer to Figure 1A and Figure 1B The display device 10 may include a display area DA for displaying an image and a peripheral area PA outside the display area DA. The display area DA may be completely surrounded by the peripheral area PA.

[0063] In a plan view, the display area DA can be rectangular. In embodiments, the display area DA can have other polygonal shapes such as triangles, pentagons, or hexagons, or circular, elliptical, or atypical shapes. The corners of the edges of the display area DA can be curved. In embodiments, such as... Figure 1A As shown, the display device 10 may have a display area DA in which the length in a first direction (x-direction or row direction) is greater than the length in a second direction (y-direction or column direction). In an embodiment, as... Figure 1B As shown, the display device 10 may have a display area DA in which the length in the second direction (y direction) is greater than the length in the first direction (x direction).

[0064] refer to Figure 2 The electronic device 1 according to the embodiment may include a display device 10, a controller 20, and a power supply circuit 30. The display device 10 may include a pixel unit 11, a first gate driver 12, a second gate driver 13, and a data driver 15.

[0065] Pixel unit 11 may be provided in display area DA. Various conductive lines configured to transmit electrical signals to be applied to display area DA, external circuitry electrically connected to the pixel, and pads on which a printed circuit board or driver integrated circuit (IC) chip is attached may be located in peripheral area PA. For example, first gate driver 12 and second gate driver 13 may be provided in peripheral area PA.

[0066] like Figure 2 As shown, pixel circuits PC connected to the first gate lines GWLa_1, GWLa_2, ..., GWLa_m, the second gate lines GWLb_1, GWLb_2, ..., GWLb_m, and data lines DL1, DL2, ..., DLn can be arranged in pixel unit 11. The pixel circuits PC can be arranged in an m×n matrix in the first direction (x-direction) and the second direction (y-direction). In this respect, m and n can each be a natural number greater than 1.

[0067] Each pixel in the PC can be electrically connected to a corresponding display element (e.g., a light-emitting diode). The display elements can be arranged in a pattern such as stripes or pentiles. ®Various arrangements, including diamond and mosaic arrangements, can be used to display images. The display elements can be organic light-emitting diodes (OLEDs). Each display element can emit, for example, red, green, blue, or white light. The pixel circuit PC can include multiple transistors and at least one capacitor. Each pixel circuit PC can be electrically connected to a corresponding gate line among the first gate lines GWLa_1, GWLa_2, ..., GWLa_m and the second gate lines GWLb_1, GWLb_2, ..., GWLb_m, and can be electrically connected to the corresponding data lines DL1, DL2, ..., DLn. A pixel can include a pixel circuit PC and an organic light-emitting diode electrically connected to the pixel circuit PC.

[0068] First gate lines GWLa_1, GWLa_2, ..., GWLa_m and second gate lines GWLb_1, GWLb_2, ..., GWLb_m can each extend in a first direction (x-direction or row direction) and can be connected to pixel circuits PC located in the same row. Two pixel circuits PCs that are adjacent to each other in the first direction (x-direction) can be defined as a pixel circuit pair PP. In this respect, when two pixel circuits PCs are said to be adjacent to each other in the first direction (x-direction), these two pixel circuits PCs can be adjacent to each other in the first direction (x-direction), and there are no other pixel circuits arranged between these two pixel circuits PCs. A pixel circuit pair PP can be arranged in the same row and can include odd-numbered pixel circuits and even-numbered pixel circuits that are adjacent to each other.

[0069] Each pixel circuit pair PP may include a pixel circuit connected to a corresponding first gate line among the first gate lines GWLa_1, GWLa_2, ..., GWLa_m, and a pixel circuit connected to a corresponding second gate line among the second gate lines GWLb_1, GWLb_2, ..., GWLb_m. For example, in the pixel circuits PC arranged in the first pixel circuit row, the pixel circuits PC arranged in odd-numbered columns may be electrically connected to the first gate line GWLa_1, and the pixel circuits PC arranged in even-numbered columns may be electrically connected to the first second gate line GWLb_1. In the pixel circuits PC arranged in the second pixel circuit row, the pixel circuits PC arranged in odd-numbered columns may be electrically connected to the second second gate line GWLb_2, and the pixel circuits PC arranged in even-numbered columns may be electrically connected to the second first gate line GWLa_2.

[0070] In other words, the pixel circuits PC arranged in odd-numbered columns of odd-numbered rows and the pixel circuits PC arranged in even-numbered columns of even-numbered rows can each be electrically connected to the corresponding first gate lines among the first gate lines GWLa_1, GWLa_2, ..., GWLa_m. Similarly, the pixel circuits PC arranged in even-numbered columns of odd-numbered rows and the pixel circuits PC arranged in odd-numbered columns of even-numbered rows can each be electrically connected to the corresponding second gate lines among the second gate lines GWLb_1, GWLb_2, ..., GWLb_m.

[0071] Data lines DL1, DL2, ..., DLn can extend in the second direction (y-direction). Data lines DL1, DL2, ..., DLn can each be arranged between pixel circuits PC arranged in odd-numbered columns and pixel circuits PC arranged in even-numbered columns, and can be electrically connected to pixel circuits PC arranged in odd-numbered columns and pixel circuits PC arranged in even-numbered columns. That is, pixel circuits PC belonging to the same pixel circuit pair PP can be electrically connected to the same data line.

[0072] The first gate driver 12 can be electrically connected to the first gate lines GWLa_1, GWLa_2, ..., GWLa_m, and can be configured to generate a first gate signal in response to a first gate drive control signal GCS1 transmitted from the controller 20, and sequentially supply the first gate signal to the first gate lines GWLa_1, GWLa_2, ..., GWLa_m. When the first gate signal is sequentially supplied to the first gate lines GWLa_1, GWLa_2, ..., GWLa_m, the pixel circuits PC connected to the first gate lines GWLa_1, GWLa_2, ..., GWLa_m can be selected row by row. Data lines DL1, DL2, ..., DLn can be configured to deliver data voltage to the pixel circuit PC connected to the first gate line in each selected row.

[0073] The second gate driver 13 can be electrically connected to the second gate lines GWLb_1, GWLb_2, ..., GWLb_m, and can be configured to generate a second gate signal in response to the second gate drive control signal GCS2 transmitted from the controller 20, and sequentially supply the second gate signal to the second gate lines GWLb_1, GWLb_2, ..., GWLb_m. When the second gate signal is sequentially supplied to the second gate lines GWLb_1, GWLb_2, ..., GWLb_m, the pixel circuits PC connected to the second gate lines GWLb_1, GWLb_2, ..., GWLb_m can be selected row by row. Data lines DL1, DL2, ..., DLn can be configured to transmit data signals to the pixel circuits PC connected to the second gate lines in each selected row.

[0074] In this respect, the first gate lines GWLa_1, GWLa_2, ..., GWLa_m and the second gate lines GWLb_1, GWLb_2, ..., GWLb_m can be connected to the gates of the data write transistors included in the pixel. The first gate signal and the second gate signal can each be a gate control signal used to control the on and off states of the data write transistors. The first gate signal and the second gate signal can each be a square wave signal, in which the on-state voltage that enables the data write transistors to conduct and the off-state voltage that enables the data write transistors to turn off are repeated.

[0075] Data driver 15 can be electrically connected to data lines DL1, DL2, ..., DLn. Data driver 15 can be configured to convert the image data signal IMG into a voltage-form data signal (i.e., data voltage) according to the data drive control signal DCS input from controller 20, and output the data signal. Relative to each row, data lines DL1, DL2, ..., DLn can each be electrically connected to a pixel circuit pair PP, and data driver 15 can be configured to output a data signal in which the data voltage corresponding to the pixel circuit PC connected to the first gate line and the data voltage corresponding to the pixel circuit PC connected to the second gate line alternate with each other.

[0076] The power supply circuit 30 can be configured to supply a first driving voltage ELVDD and a second driving voltage ELVSS to the pixels of the pixel unit 11. The first driving voltage ELVDD can be a high-level voltage provided to the display element that is electrically connected to a first electrode (pixel electrode or anode) of each pixel circuit PC. The second driving voltage ELVSS can be a low-level voltage provided to the display element that is electrically connected to a second electrode (counter electrode or cathode) of each pixel circuit PC. The first driving voltage ELVDD and the second driving voltage ELVSS can be driving voltages that enable multiple pixels to emit light. The power supply circuit 30 can be configured to generate initialization voltages, reference voltages, etc., and supply them to the pixels of the pixel unit 11.

[0077] Controller 20 can be configured to generate a first gate drive control signal GCS1, a second gate drive control signal GCS2, and a data drive control signal DCS in response to an image data signal IMG and a control signal CONT supplied from an application processor. Controller 20 can be configured to output the first gate drive control signal GCS1 to a first gate driver 12, the second gate drive control signal GCS2 to a second gate driver 13, and the data drive control signal DCS to a data driver 15. Controller 20 can be configured to remap image data according to the operating sequence of the pixel circuitry PC. For example, controller 20 can receive the image data signal IMG from the application processor, decode the received image data signal IMG to convert it into image data, and store the image data in graphics memory. Controller 20 can read the image data stored in graphics memory according to the operating sequence of the pixel circuitry PC and pass it to data driver 15.

[0078] The first gate driver 12 and the second gate driver 13 can be directly formed on the substrate. The data driver 15, the controller 20, and / or the power supply circuit 30 can be arranged on a printed circuit board electrically connected to pads arranged on one side of the substrate. The printed circuit board can be a flexible printed circuit board (FPCB), a robust and non-bending rigid printed circuit board (rigid PCB), or a hybrid printed circuit board including both rigid PCB and FPCB. In an embodiment, the data driver 15, the controller 20, and / or the power supply circuit 30 can be directly arranged on the substrate in a chip-on-glass (COG) or chip-on-plastic (COP) manner. In an embodiment, the data driver 15 and the controller 20 can be integrated into a single integrated circuit. For example, the data driver 15 and the controller 20 can be provided as a timing controller embedded driver integrated circuit (T-con embedded driver IC).

[0079] Although the organic light-emitting display device, which includes an organic light-emitting diode as a display element, is described below as an example of the display device 10 according to an embodiment, the display device 10 described herein is not limited thereto. In embodiments, the display device 10 described herein may be a display device such as an inorganic light-emitting display (or an inorganic electroluminescent (EL) display) or a quantum dot light-emitting display.

[0080] Figure 3 This is a schematic cross-sectional view of the display device 10 according to an embodiment.

[0081] refer to Figure 3 The display device 10 may include pixels arranged in the display area DA. A pixel may include pixel circuitry and an organic light-emitting diode (OLED) electrically connected to the pixel circuitry. The pixel circuitry may include a plurality of thin-film transistors and at least one capacitor. Figure 3 The first transistor T1 shown can be a driving transistor arranged between the driving voltage line and the organic light-emitting diode (OLED), and the sixth transistor T6 can be an emission control transistor arranged between the first transistor T1 and the OLED.

[0082] The display device 10 may include a substrate 100. The substrate 100 may include a region corresponding to the display area DA and a peripheral area PA (see reference). Figure 1A The corresponding area. In this description, when the substrate 100 is referred to as including the display area DA and the peripheral area PA, the substrate 100 may include the area corresponding to the display area DA and the area corresponding to the peripheral area PA.

[0083] The substrate 100 may include glass, ceramic, metallic, or flexible or bendable materials. When the substrate 100 is flexible or bendable, it may include polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0084] The substrate 100 may have a single-layer structure or a multi-layer structure. In an embodiment, the substrate 100 may have a multi-layer structure in which inorganic layers are disposed between a base layer comprising a polymer resin.

[0085] The first electrode CEs1 of the storage capacitor Cst and the first electrode CEh1 of the holding capacitor Chd can be disposed on the substrate 100. In an embodiment, the first electrode CEs1 of the storage capacitor Cst and the first electrode CEh1 of the holding capacitor Chd can be integrally formed with each other. The first electrode CEs1 of the storage capacitor Cst and the first electrode CEh1 of the holding capacitor Chd can include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can have a single-layer or multi-layer structure.

[0086] The buffer layer 111 may be disposed above the first electrode CEs1 of the storage capacitor Cst and the first electrode CEh1 of the holding capacitor Chd. The buffer layer 111 may include inorganic materials (such as oxides or nitrides), organic materials, or organic-inorganic compounds, and may have a single-layer or multi-layer structure including inorganic and / or organic materials.

[0087] The first semiconductor layer A1 of the first transistor T1, the sixth semiconductor layer A6 of the sixth transistor T6, and the second electrode CEh2 of the holding capacitor Chd can be disposed on the buffer layer 111. In an embodiment, the first semiconductor layer A1 of the first transistor T1, the sixth semiconductor layer A6 of the sixth transistor T6, and the second electrode CEh2 of the holding capacitor Chd can comprise an oxide semiconductor material. For example, the oxide semiconductor material can comprise an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). The oxide semiconductor material can be IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O).

[0088] Each of the first semiconductor layer A1 and the sixth semiconductor layer A6 may include a channel region and source and drain regions disposed on both sides of the channel region. The source region S1 and drain region D1 of the first semiconductor layer A1, the source region S6 and drain region D6 of the sixth semiconductor layer A6, and the second electrode CEh2 of the holding capacitor Chd may be doped with impurities.

[0089] Gate insulating layer 113 may be disposed on first semiconductor layer A1 and sixth semiconductor layer A6. Gate insulating layer 113 may include an inorganic insulating layer such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. In embodiments, gate insulating layer 113 may be patterned to have a shape corresponding to the shape of the conductive layer located on gate insulating layer 113.

[0090] The first gate electrode GE1 of the first transistor T1 and the sixth gate electrode GE6 of the sixth transistor T6 can be disposed on the gate insulating layer 113. Each of the first gate electrode GE1 of the first transistor T1 and the sixth gate electrode GE6 of the sixth transistor T6 may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a single-layer or multi-layer structure.

[0091] In the plan view, the first gate electrode GE1 of the first transistor T1 may overlap with the channel region of the first semiconductor layer A1. The first gate electrode GE1 of the first transistor T1 may be integrally formed with the second electrode CEs2 of the storage capacitor Cst. In the plan view, the sixth gate electrode GE6 of the sixth transistor T6 may overlap with the channel region of the sixth semiconductor layer A6.

[0092] The first insulating layer 115 may be disposed on the first gate electrode GE1 of the first transistor T1, the sixth gate electrode GE6 of the sixth transistor T6, and the second electrode CEh2 of the holding capacitor Chd. The first insulating layer 115 may include inorganic materials (such as oxides or nitrides), organic materials, or organic-inorganic compounds, and may have a single-layer or multi-layer structure including inorganic and / or organic materials.

[0093] The first connecting electrode 134 and the second connecting electrode 136 can be disposed on the first insulating layer 115. The first connecting electrode 134 can electrically connect the source region S1 of the first transistor T1 and the drain region D6 of the sixth transistor T6 to each other by penetrating the contact hole of the first insulating layer 115. The first connecting electrode 134 can be electrically connected to the first electrode CEs1 of the storage capacitor Cst and the first electrode CEh1 of the holding capacitor Chd by penetrating the contact hole of the buffer layer 111 and the first insulating layer 115. The second connecting electrode 136 can be electrically connected to the source region S6 of the sixth transistor T6 by penetrating the contact hole of the first insulating layer 115.

[0094] The first connecting electrode 134 can be integrally formed with the third electrode CEs3 of the storage capacitor Cst and the third electrode CEh3 of the holding capacitor Chd. The first electrode CEs1, the second electrode CEs2, and the third electrode CEs3 of the storage capacitor Cst can overlap each other in a planar view. The first electrode CEh1, the second electrode CEh2, and the third electrode CEh3 of the holding capacitor Chd can overlap each other in a planar view.

[0095] The first connecting electrode 134 and the second connecting electrode 136 may include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may have a multilayer or single-layer structure including the materials described above. For example, the first connecting electrode 134 and the second connecting electrode 136 may have a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti).

[0096] The second insulating layer 117 may be disposed above the first connecting electrode 134 and the second connecting electrode 136. In embodiments, the second insulating layer 117 may comprise organic insulating materials such as polymethyl methacrylate (PMMA), polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0097] The third connecting electrode 138 may be disposed on the second insulating layer 117. The third connecting electrode 138 may be electrically connected to the second connecting electrode 136 through contact holes penetrating the second insulating layer 117. The third connecting electrode 138 may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a multilayer or single-layer structure comprising the materials described above. For example, the third connecting electrode 138 may have a multilayer structure of titanium (Ti) / aluminum (Al) / titanium (Ti).

[0098] The third insulating layer 118 may be disposed on the third connecting electrode 138. The third insulating layer 118 may include organic materials. For example, the third insulating layer 118 may include organic insulating materials such as polymethyl methacrylate (PMMA), polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0099] The organic light-emitting diode (OLED) can be disposed on the third insulating layer 118. The OLED may include a pixel electrode 210, an intermediate layer 220, and a counter electrode 230.

[0100] Pixel electrode 210 can be disposed on the third insulating layer 118. Pixel electrode 210 can be electrically connected to the third connection electrode 138 through contact holes penetrating the third insulating layer 118. Pixel electrode 210 can be electrically connected to the source region S6 of the sixth transistor T6 through the second connection electrode 136 and the third connection electrode 138.

[0101] Pixel electrode 210 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. In embodiments, pixel electrode 210 may further include a conductive oxide layer on and / or under the reflective layer described above. The conductive oxide layer may include indium tin oxide, indium zinc oxide, zinc oxide, indium oxide, indium gallium oxide, and / or aluminum zinc oxide. In embodiments, pixel electrode 210 may have a three-layer structure of ITO / Ag / ITO.

[0102] A dam layer 119 can be disposed on the pixel electrode 210. An opening 119OP can be defined in the dam layer 119 to expose at least a portion of the pixel electrode 210. The central portion of the pixel electrode 210 can be exposed through the opening 119OP defined in the dam layer 119. The dam layer 119 can prevent phenomena such as electric arcing at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the counter electrode 230. The opening 119OP in the dam layer 119 can define the emission region of a pixel including an organic light-emitting diode (OLED).

[0103] The dam layer 119 may comprise organic insulating materials such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and phenolic resin. The dam layer 119 may be formed by methods such as spin coating.

[0104] In an embodiment, the dam layer 119 may include a light-blocking material and may be black. The light-blocking material may include carbon black, carbon nanotubes, a resin or slurry containing a black dye, metal particles (e.g., nickel (Ni), aluminum (Al), molybdenum (Mo), and alloys thereof), metal oxide (e.g., chromium oxide) particles, or metal nitride (e.g., chromium nitride) particles. When the dam layer 119 includes a light-blocking material, reflections from metal components disposed beneath the dam layer 119 can be reduced.

[0105] The intermediate layer 220 may include an emission layer. The emission layer may include an organic material comprising a fluorescent or phosphorescent material that emits red, green, blue, or white light. The emission layer may include a low molecular weight organic material or a polymeric organic material, and functional layers such as a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer may optionally be further arranged on and / or under the emission layer.

[0106] The emitter layer can have a patterned shape corresponding to the pixel electrode 210. Functional layers such as the hole transport layer can be a single layer spanning multiple pixel electrodes 210.

[0107] Counter electrode 230 may be disposed on intermediate layer 220. Counter electrode 230 may include a conductive material having a low work function. For example, counter electrode 230 may include a transparent or (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. In embodiments, counter electrode 230 may further include a layer such as ITO, IZO, ZnO, or In2O3 on the transparent or (semi-)transparent layer comprising the materials described above. In embodiments, counter electrode 230 may be a single layer spanning multiple pixel electrodes 210 that can completely cover the display area DA.

[0108] although Figure 3 The illustration shows a sixth semiconductor layer A6 of a sixth transistor T6 disposed on a layer on which a first semiconductor layer A1 of a first transistor T1 is disposed, but one or more embodiments are not limited thereto. In an embodiment, the sixth semiconductor layer A6 of the sixth transistor T6 may be disposed on a different layer than the layer on which the first semiconductor layer A1 of the first transistor T1 is disposed. For example, the sixth transistor T6 may be disposed between the substrate 100 and the first semiconductor layer A1 of the first transistor T1. The sixth semiconductor layer A6 of the sixth transistor T6 may comprise a silicon semiconductor material. In this regard, the first transistor T1 may be a drive transistor that outputs a drive current corresponding to a data signal, and the sixth transistor T6 may be a switching transistor that is turned on or off according to a gate signal.

[0109] Figure 4 This is a schematic diagram illustrating the equivalent circuit diagram of a pixel according to an embodiment.

[0110] refer to Figure 4 A pixel circuit pair PP can be arranged in the same row and can include a first pixel circuit PCa and a second pixel circuit PCb that are adjacent to each other. The first pixel circuit PCa can be electrically connected to a first light-emitting diode EDa to form a first pixel PXa. The second pixel circuit PCb can be electrically connected to a second light-emitting diode EDb to form a second pixel PXb.

[0111] Each of the first pixel circuit PCa and the second pixel circuit PCb may include first to sixth transistors T1, T2, T3, T4, T5 and T6, a storage capacitor Cst and a holding capacitor Chd. The first transistor T1 may be a driving transistor that outputs a driving current corresponding to the data signal Vdata, and the second to sixth transistors T2 to T6 may be switching transistors that are turned on or off according to the gate-source voltage or the gate voltage.

[0112] The first to sixth transistors T1 to T6 can be implemented as thin-film transistors. The first terminal and the second terminal of each of the first to sixth transistors T1 to T6 can be either the source or the drain. For example, when the first terminal is the source, the second terminal can be the drain.

[0113] The first pixel circuit PCa can be connected to a first gate line GWLa configured to transmit a first gate signal GWa, a third gate line GBL configured to transmit a third gate signal GB, a fourth gate line GRL configured to transmit a fourth gate signal GR, a fifth gate line EML configured to transmit a fifth gate signal EM, a sixth gate line EMBL configured to transmit a sixth gate signal EMB, and a data line DL configured to transmit a data signal Vdata.

[0114] The second pixel circuit PCb can be connected to the second gate line GWLb configured to transmit the second gate signal GWb, the third gate line GBL configured to transmit the third gate signal GB, the fourth gate line GRL configured to transmit the fourth gate signal GR, the fifth gate line EML configured to transmit the fifth gate signal EM, the sixth gate line EMBL configured to transmit the sixth gate signal EMB, and the data line DL configured to transmit the data signal Vdata.

[0115] In addition, the first pixel circuit PCa and the second pixel circuit PCb can each be connected to the driving voltage line VDDL configured to transmit the first driving voltage ELVDD, the reference voltage line VRL configured to transmit the reference voltage VREF, and the initialization voltage line VAIL configured to transmit the initialization voltage Vaint.

[0116] In this embodiment, the first to sixth transistors T1 to T6 can be provided as N-channel MOSFETs (NMOS). In this embodiment, some of the first to sixth transistors T1 to T6 can be provided as N-channel MOSFETs (NMOS), and the others can be provided as P-channel MOSFETs (PMOS). For example, the first transistor T1 can be provided as an N-channel MOSFET (NMOS), and the second to sixth transistors T2 to T6 can be provided as either N-channel MOSFETs (NMOS) or P-channel MOSFETs (PMOS), but at least one transistor can be provided as a P-channel MOSFET (PMOS). In this embodiment, the first to fourth transistors T1 to T4 can be provided as N-channel MOSFETs (NMOS), and the fifth transistor T5 and the sixth transistor T6 can be provided as P-channel MOSFETs (PMOS). In this embodiment, the first to sixth transistors T1 to T6 can be provided as P-channel MOSFETs (PMOS).

[0117] In the embodiments, the first to sixth transistors T1 to T6 may be oxide semiconductor transistors comprising an oxide semiconductor material. For example, the oxide semiconductor material may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). The oxide semiconductor material may be IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O).

[0118] Because oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not significant even with long drive times. Consequently, oxide semiconductor transistors can be driven at low frequencies. Furthermore, when using oxide semiconductor transistors, the crystallization process performed by excimer laser annealing (ELA) is not required to form low-temperature polycrystalline silicon (LTPS) semiconductor transistors, and therefore, the manufacturing cost of display devices can be reduced.

[0119] In this embodiment, some of the first to sixth transistors T1 to T6 may be oxide semiconductor transistors, and the other transistors may be silicon semiconductor transistors comprising silicon-based semiconductor materials. For example, the first transistor T1 may be an oxide semiconductor transistor, and the second to sixth transistors T2 to T6 may be oxide semiconductor transistors or silicon semiconductor transistors, but at least one transistor may be a silicon semiconductor transistor. In this embodiment, the first to fourth transistors T1 to T4 may be oxide semiconductor transistors, and the fifth transistor T5 and the sixth transistor T6 may be silicon semiconductor transistors. In this embodiment, the first to sixth transistors T1 to T6 may be silicon semiconductor transistors. The silicon-based semiconductor material may be polycrystalline silicon or amorphous silicon.

[0120] Regarding the first pixel PXa, the first transistor T1 (driving transistor) may include a first terminal connected to the driving voltage line VDDL via the fifth transistor T5, a second terminal connected to the second node N2, and a gate connected to the first node N1. The first transistor T1 of the first pixel circuit PCa can receive the data signal Vdata corresponding to the first pixel PXa according to the switching operation of the second transistor T2, and supply driving current to the first light-emitting diode EDa.

[0121] The second transistor T2 (data write transistor) may include a gate connected to the first gate line GWLa, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second transistor T2 may be turned on according to a first gate signal GWa received through the first gate line GWLa to perform a switching operation for transmitting the data signal Vdata transmitted through the data line DL to the first node N1.

[0122] The third transistor T3 (the first initialization transistor) may include a gate connected to the fourth gate line GRL, a first terminal connected to the reference voltage line VRL, and a second terminal connected to the first node N1. The third transistor T3 may be turned on according to the fourth gate signal GR received through the fourth gate line GRL to transfer the reference voltage VREF transmitted through the reference voltage line VRL to the first node N1 and initialize the first node N1.

[0123] The fourth transistor T4 (the second initialization transistor) may include a gate connected to the third gate line GBL, a first terminal connected to the initialization voltage line VAIL, and a second terminal connected to the third node N3. The fourth transistor T4 may be turned on according to the third gate signal GB received through the third gate line GBL to transfer the initialization voltage Vaint transmitted through the initialization voltage line VAIL to the third node N3 and initialize the pixel electrode of the first light-emitting diode EDa.

[0124] The fifth transistor T5 (first emitter control transistor) may include a gate connected to the fifth gate line EML, a first terminal connected to the drive voltage line VDDL, and a second terminal connected to the first terminal of the first transistor T1. The sixth transistor T6 (second emitter control transistor) may include a gate connected to the sixth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The fifth transistor T5 can be turned on according to the fifth gate signal EM received through the fifth gate line EML, and the sixth transistor T6 can be turned on according to the sixth gate signal EMB received through the sixth gate line EMBL, and therefore, drive current can flow through the first light-emitting diode EDa.

[0125] In this embodiment, the gate of the fifth transistor T5 and the gate of the sixth transistor T6 can be connected to the same gate line (emit control signal line). In this case, the fifth transistor T5 and the sixth transistor T6 can be simultaneously turned on by the same gate signal (emit control signal).

[0126] The storage capacitor Cst may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. The storage capacitor Cst is a storage capacitor and can store a voltage corresponding to the threshold voltage of the first transistor T1 and the data signal Vdata.

[0127] The holding capacitor Chd may include a first electrode connected to the drive voltage line VDDL and a second electrode connected to the second node N2. In some embodiments, the first electrode of the holding capacitor Chd may be electrically connected to a voltage line such as the initialization voltage line VAIL, the reference voltage line VRL, etc. In an embodiment, the display device 10 may further include an auxiliary drive voltage line configured to deliver a second drive voltage ELVSS, and the first electrode of the holding capacitor Chd may be electrically connected to the auxiliary drive voltage line. In an embodiment, the capacitance of the storage capacitor Cst may be greater than the capacitance of the holding capacitor Chd.

[0128] The first light-emitting diode EDa may include a pixel electrode connected to the third node N3 and a counter electrode (e.g., a cathode) facing the pixel electrode, and the counter electrode may receive a second driving voltage ELVSS. The counter electrode may be a common electrode shared by multiple light-emitting diodes.

[0129] Regarding the second pixel circuit PCb, the first transistor T1 (driving transistor) may include a first terminal connected to the driving voltage line VDDL via the fifth transistor T5, a second terminal connected to the second node N2, and a gate connected to the first node N1. The first transistor T1 of the second pixel circuit PCb can receive the data signal Vdata corresponding to the second pixel PXb according to the switching operation of the second transistor T2, and supply driving current to the second light-emitting diode EDb.

[0130] The second transistor T2 (data write transistor) may include a gate connected to the second gate line GWLb, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second transistor T2 may be turned on according to the second gate signal GWb received through the second gate line GWLb to perform a switching operation for transmitting the data signal Vdata transmitted through the data line DL to the first node N1.

[0131] The third transistor T3 (the first initialization transistor) may include a gate connected to the fourth gate line GRL, a first terminal connected to the reference voltage line VRL, and a second terminal connected to the first node N1. The third transistor T3 may be turned on according to the fourth gate signal GR received through the fourth gate line GRL to transfer the reference voltage VREF transmitted through the reference voltage line VRL to the first node N1 and initialize the first node N1.

[0132] The fourth transistor T4 (the second initialization transistor) may include a gate connected to the third gate line GBL, a first terminal connected to the initialization voltage line VAIL, and a second terminal connected to the third node N3. The fourth transistor T4 may be turned on according to the third gate signal GB received through the third gate line GBL to transfer the initialization voltage Vaint transmitted through the initialization voltage line VAIL to the third node N3 and initialize the pixel electrode of the second light-emitting diode EDb.

[0133] The fifth transistor T5 (first emitter control transistor) may include a gate connected to the fifth gate line EML, a first terminal connected to the drive voltage line VDDL, and a second terminal connected to the first terminal of the first transistor T1. The sixth transistor T6 (second emitter control transistor) may include a gate connected to the sixth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The fifth transistor T5 can be turned on according to the fifth gate signal EM received through the fifth gate line EML, and the sixth transistor T6 can be turned on according to the sixth gate signal EMB received through the sixth gate line EMBL, and therefore, drive current can flow through the second light-emitting diode EDb.

[0134] The storage capacitor Cst may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. The storage capacitor Cst is a storage capacitor and can store a voltage corresponding to the threshold voltage of the first transistor T1 and the data signal Vdata.

[0135] The holding capacitor Chd may include a first electrode connected to the drive voltage line VDDL and a second electrode connected to the second node N2. In an embodiment, the capacitance of the storage capacitor Cst may be greater than the capacitance of the holding capacitor Chd.

[0136] The second light-emitting diode EDb may include a pixel electrode connected to the third node N3 and a counter electrode (e.g., a cathode) facing the pixel electrode, and the counter electrode may receive a second driving voltage ELVSS. The counter electrode may be a common electrode shared by multiple light-emitting diodes.

[0137] The second gate signal GWb can be an output that is phase-delayed (offset) from the first gate signal GWa by a specific time period. For example, the second gate signal GWb can be an output that is delayed by 0.5 horizontal time periods (0.5H) from the first gate signal GWa. Accordingly, the second transistor T2 of the first pixel circuit PCa can be turned on first, and the second transistor T2 of the second pixel circuit PCb can be turned on subsequently, and the second transistor T2 of the first pixel circuit PCa can be turned off first, and the second transistor T2 of the second pixel circuit PCb can be turned off subsequently. Accordingly, the data signal Vdata supplied through a data line DL can be supplied to the first pixel circuit PCa and the second pixel circuit PCb in a time-division manner. Since the two pixel circuits constituting the pixel circuit pair PP share a single data line DL, the number of data lines DL can be reduced, and therefore, the manufacturing cost of the display device 10 can be reduced.

[0138] Figure 5 This is a schematic plan view of the pixel circuit according to an embodiment.

[0139] refer to Figure 5 A pixel circuit pair PP may include a first pixel circuit PCa and a second pixel circuit PCb electrically connected to the same data line DL. The first pixel circuit PCa may be a pixel circuit electrically connected to a first gate line GWLa, and the second pixel circuit PCb may be a pixel circuit electrically connected to a second gate line GWLb. The first pixel circuit PCa and the second pixel circuit PCb may be adjacent to each other in a first direction (x direction), and the data line DL may be arranged between the first pixel circuit PCa and the second pixel circuit PCb and may extend in a second direction (y direction).

[0140] although Figure 5 The diagram shows a first pixel circuit PCa located to the left of the data line DL (e.g., in the -x direction) and a second pixel circuit PCb located to the right of the data line DL (e.g., in the +x direction), but one or more embodiments are not limited thereto. Figure 5 When the pixel circuit pair PP shown is located in the m-th pixel circuit row, the first pixel circuit PCa of the pixel circuit pair located in the (m+1)-th pixel circuit row can be located to the right of the data line DL (e.g., in the +x direction), and the second pixel circuit PCb can be located to the left of the data line DL (e.g., in the -x direction). In this respect, m can be a natural number greater than 1.

[0141] Each of the first pixel circuit PCa and the second pixel circuit PCb may include first to sixth transistors T1, T2, T3, T4, T5, and T6, a storage capacitor Cst, and a holding capacitor Chd. The first pixel circuit PCa may be connected to the first gate line GWLa, the third gate line GBL, the fourth gate line GRL, the fifth gate line EML, the sixth gate line EMBL, and the data line DL. The second pixel circuit PCb may be connected to the second gate line GWLb, the third gate line GBL, the fourth gate line GRL, the fifth gate line EML, the sixth gate line EMBL, and the data line DL. The second gate line GWLb, the third gate line GBL, the fourth gate line GRL, the fifth gate line EML, and the sixth gate line EMBL may extend in a first direction (x-direction). Furthermore, the first pixel circuit PCa and the second pixel circuit PCb may each be electrically connected to a reference voltage line VRL, a horizontal drive voltage line VDDLh, and an initialization voltage line VAIL. The first transistor T1 and the fourth to sixth transistors T4 to T6 of the first pixel circuit PCa and the second pixel circuit PCb may be substantially symmetrical with respect to the data line DL. Unless otherwise stated, each element is described below based on the first pixel circuit PCa.

[0142] The first transistor T1 may include a first semiconductor layer A1 and a first gate electrode GE1 that overlaps with the first semiconductor layer A1 in a plan view. The first semiconductor layer A1 may include a channel region and a source region S1 and a drain region D1 disposed on both sides of the channel region.

[0143] The first gate electrode GE1 of the first transistor T1 can be integrally formed with the second electrode CEs2 of the storage capacitor Cst. In a planar view, the second electrode CEs2 of the storage capacitor Cst can overlap with the first electrode CEs1 and the third electrode CEs3 of the storage capacitor Cst.

[0144] The second transistor T2 may include a second semiconductor layer A2 and a second gate electrode GE2 that overlaps with the second semiconductor layer A2 in a plan view. The second semiconductor layer A2 may include a channel region and a source region S2 and a drain region D2 disposed on both sides of the channel region. The source region S2 of the second transistor T2 can be electrically connected to the first gate electrode GE1 of the first transistor T1 and the drain region D3 of the third transistor T3 via connection electrodes. The drain region D2 of the second transistor T2 can be electrically connected to the data line DL.

[0145] The second gate electrode GE2 of the second transistor T2 can have an isolated shape (i.e., island-shaped) in the planar view. In the first pixel circuit PCa, the second gate electrode GE2 of the second transistor T2 can be electrically connected to the first gate line GWLa via the fourth connection electrode CTEa. The fourth connection electrode CTEa can overlap with the first gate line GWLa and the second gate line GWLb, but can be connected by penetrating the insulating layer (e.g., the first insulating layer 115 (reference)). Figure 3 The fourth connecting electrode CTEa and the second gate line GWLb are electrically isolated by at least one insulating layer.

[0146] In the second pixel circuit PCb, the second gate electrode GE2 of the second transistor T2 can be electrically connected to the second gate line GWLb via the fifth connection electrode CTEb. The fifth connection electrode CTEb can overlap with the first gate line GWLa and the second gate line GWLb, but can be connected to the second gate line GWLb via a contact hole CTb that penetrates the insulating layer (e.g., the first insulating layer 115). The fifth connection electrode CTEb and the first gate line GWLa can be electrically isolated by at least one insulating layer.

[0147] The third transistor T3 may include a third semiconductor layer A3 and a third gate electrode GE3 that overlaps with the third semiconductor layer A3 in a plan view. The third semiconductor layer A3 of the third transistor T3 and the second semiconductor layer A2 of the second transistor T2 may be integrally formed with each other.

[0148] The third semiconductor layer A3 may include a channel region and a source region S3 and a drain region D3 disposed on both sides of the channel region. The drain region D3 of the third transistor T3 may be electrically connected to the first gate electrode GE1 of the first transistor T1 and the source region S2 of the second transistor T2 via connection electrodes. The source region S3 of the third transistor T3 may be electrically connected to the reference voltage line VRL.

[0149] The third gate electrode GE3 of the third transistor T3 can have an isolated shape in the planar view. The third gate electrode GE3 of the third transistor T3 can be electrically connected to the fourth gate line GRL by connecting electrodes.

[0150] The fourth transistor T4 may include a fourth semiconductor layer A4 and a fourth gate electrode GE4 overlapping the fourth semiconductor layer A4 in a plan view. The fourth semiconductor layer A4 may include a channel region and a source region S4 and a drain region D4 disposed on both sides of the channel region. The source region S4 of the fourth transistor T4 may be electrically connected to the initialization voltage line VAIL.

[0151] In an embodiment, the initialization voltage line VAIL may include a first initialization voltage line VAIL1 and a second initialization voltage line VAIL2. Depending on the color of the light emitted by the organic light-emitting diode (OLED) connected to the pixel circuit, the pixel circuit can be selectively connected to either the first initialization voltage line VAIL1 or the second initialization voltage line VAIL2. For example, when the OLED connected to the pixel circuit emits light of a first color, the pixel circuit can be electrically connected to the first initialization voltage line VAIL1 and can receive the first initialization voltage. When the OLED connected to the pixel circuit emits light of a second color, the pixel circuit can be electrically connected to the second initialization voltage line VAIL2 and can receive a second initialization voltage different from the first initialization voltage. In an embodiment, the first color may be blue or green, and the second color may be red. In this respect, Figure 5 The first pixel circuit PCa and the second pixel circuit PCb are shown to be electrically connected to the second initialization voltage line VAIL2.

[0152] The drain region D4 of the fourth transistor T4 can be electrically connected to the source region S6 of the sixth transistor T6 and the pixel electrode of the organic light-emitting diode. The fourth gate electrode GE4 of the fourth transistor T4 can be part of the third gate line GBL. In other words, the fourth gate electrode GE4 of the fourth transistor T4 can be integrally formed with the third gate line GBL.

[0153] The fifth transistor T5 may include a fifth semiconductor layer A5 and a fifth gate electrode GE5 overlapping the fifth semiconductor layer A5 in a plan view. In an embodiment, the first semiconductor layer A1 and the fifth semiconductor layer A5 may be integrally formed with each other. The fifth semiconductor layer A5 may include a channel region and a source region S5 and a drain region D5 disposed on both sides of the channel region. The source region S5 of the fifth transistor T5 may be connected to the drain region D1 of the first transistor T1. The drain region D5 of the fifth transistor T5 may be electrically connected to a horizontal drive voltage line VDDLh. In an embodiment, the drive voltage line VDDLh (see reference) Figure 4 A portion of the horizontal drive voltage line VDDLh can be electrically connected to the vertical drive voltage line via connection electrodes and can be configured to transmit the first drive voltage ELVDD (see reference). Figure 4 ).

[0154] The fifth gate electrode GE5 of the fifth transistor T5 can be part of the fifth gate line EML. For example, the fifth gate electrode GE5 of the fifth transistor T5 can be integrally formed with the fifth gate line EML.

[0155] The sixth transistor T6 may include a sixth semiconductor layer A6 and a sixth gate electrode GE6 that overlaps with the sixth semiconductor layer A6 in a plan view. The sixth semiconductor layer A6 of the sixth transistor T6 and the fourth semiconductor layer A4 of the fourth transistor T4 may be integrally formed with each other.

[0156] The sixth semiconductor layer A6 may include a channel region and a source region S6 and a drain region D6 disposed on both sides of the channel region. The source region S6 of the sixth transistor T6 may be electrically connected to the drain region D4 of the fourth transistor T4 and the pixel electrode of the organic light-emitting diode. The drain region D6 of the sixth transistor T6 may be electrically connected to the source region S1 of the first transistor T1, the storage capacitor Cst, and the holding capacitor Chd via the third electrode CEs3 of the storage capacitor Cst. The sixth gate electrode GE6 of the sixth transistor T6 may be part of the sixth gate line EMBL. In other words, the sixth gate electrode GE6 of the sixth transistor T6 may be integrally formed with the sixth gate line EMBL.

[0157] The holding capacitor Chd may include a first electrode CEh1, a second electrode CEh2, and a third electrode CEh3 that overlap each other in a planar view. The first electrode CEh1 of the holding capacitor Chd may be integrally formed with the first electrode CEs1 of the storage capacitor Cst, and the third electrode CEh3 of the holding capacitor Chd may be integrally formed with the third electrode CEs3 of the storage capacitor Cst. The second electrode CEh2 of the holding capacitor Chd may be separate from the second electrode CEs2 of the storage capacitor Cst in a planar view.

[0158] Figure 6This is a diagram used to schematically illustrate the connection between the pixel circuit and the data lines and gate lines according to an embodiment. Figure 7A and Figure 7B It is used for illustrative description Figure 6 The diagram shows the connection between the pixel circuit and the light-emitting diode. Figure 8 It is used to describe what is applied to Figure 6 The diagram shows the gate voltage and data voltage of the pixel circuit.

[0159] refer to Figure 6 Pixel circuits PCmn can be arranged in a matrix along a first direction (x-direction) and a second direction (y-direction) intersecting the first direction (x-direction). In this respect, m represents the row of pixel circuits, and n represents the column of pixel circuits. In this respect, each of m and n is a natural number greater than 1. Although... Figure 6 A segment of twelve pixel circuits PC11, PC12, ..., PC26 arranged in a 2×6 matrix is ​​shown, but one or more embodiments are not limited thereto. The display device 10 may include more pixel circuits PCmn and signal lines.

[0160] The first gate line may include a first gate line GWLa1 and a second gate line GWLa2 extending in a first direction (x-direction). The second gate line may include a first second gate line GWLb1 and a second second gate line GWLb2 extending in the first direction (x-direction). The data lines may include a first data line DL1, a second data line DL2, and a third data line DL3 each extending in a second direction (y-direction). Each of the pixel circuits PCmn may be electrically connected to a corresponding data line and a corresponding gate line among the first and second gate lines.

[0161] A pair of pixel circuit columns adjacent to each other in the first direction (x-direction) can be electrically connected to a corresponding data line. For example, pixel circuits PC11 and PC21 arranged in the first pixel circuit column n1 and pixel circuits PC12 and PC22 arranged in the second pixel circuit column n2 can be electrically connected to the first data line DL1. Pixel circuits PC13 and PC23 arranged in the third pixel circuit column n3 and pixel circuits PC14 and PC24 arranged in the fourth pixel circuit column n4 can be electrically connected to the second data line DL2. Pixel circuits PC15 and PC25 arranged in the fifth pixel circuit column n5 and pixel circuits PC16 and PC26 arranged in the sixth pixel circuit column n6 can be electrically connected to the third data line DL3.

[0162] A pixel circuit arranged in an odd-numbered pixel circuit column and a pixel circuit arranged in an even-numbered pixel circuit column, which are electrically connected to a data line and are adjacent to each other in a first direction (x direction), can be defined as a pixel circuit pair PP. One of the two pixel circuits constituting the pixel circuit pair PP can be electrically connected to the corresponding first gate line, and the other can be electrically connected to the corresponding second gate line.

[0163] Pixel circuits PC11, PC13, and PC15, located in odd-numbered pixel circuit columns (also referred to as odd columns) of odd-numbered pixel circuit rows m1 (also referred to as odd rows), can be electrically connected to the first first gate line GWLa1. Pixel circuits PC22, PC24, and PC26, located in even-numbered pixel circuit columns (also referred to as even columns) of even-numbered pixel circuit rows m2 (also referred to as even rows), can be electrically connected to the second first gate line GWLa2. Pixel circuits PC12, PC14, and PC16, located in even-numbered pixel circuit columns of odd-numbered pixel circuit rows m1, can be electrically connected to the first second gate line GWLb1. Pixel circuits PC21, PC23, and PC25, located in odd-numbered pixel circuit columns of even-numbered pixel circuit rows m2, can be electrically connected to the second second gate line GWLb2.

[0164] refer to Figure 7A and Figure 7B Each pixel in the PCmn pixel circuit can be electrically connected to the corresponding light-emitting diode. Figure 7A and Figure 7B The boundaries of the light-emitting diodes EDr1, EDg1, EDb1, ..., EDr4, EDg4, EDb4 shown schematically illustrate the boundaries of the emission regions of each light-emitting diode.

[0165] refer to Figure 7A The light-emitting diodes EDr1, EDg1, EDb1, ..., EDr4, EDg4, and EDb4 can be arranged in the first direction (x-direction) and the second direction (y-direction). Red light-emitting diodes EDr1, EDr2, EDr3, and EDr4 emitting red light, and green light-emitting diodes EDg1, EDg2, EDg3, and EDg4 emitting green light, can alternate in odd-numbered rows of diodes, and blue light-emitting diodes EDb1, EDb2, EDb3, and EDb4 emitting blue light can be arranged in even-numbered rows of diodes. The light-emitting diodes EDr1, EDg1, EDb1, ..., EDr4, EDg4, and EDb4 can be arranged in a striped pattern.

[0166] refer to Figure 7BThe light-emitting diodes EDr1, EDg1, EDb1, ..., EDr4, EDg4, and EDb4 can be arranged in a first direction (x-direction) and a second direction (y-direction). Columns of red light-emitting diodes EDr1, EDr2, EDr3, and EDr4 arranged in the second direction (y-direction), columns of green light-emitting diodes EDg1, EDg2, EDg3, and EDg4 arranged in the second direction (y-direction), and columns of blue light-emitting diodes EDb1, EDb2, EDb3, and EDb4 arranged in the second direction (y-direction) can be repeated sequentially in the first direction (x-direction). Within a repeating unit, the arrangement order of the columns of red light-emitting diodes, the columns of green light-emitting diodes, and the columns of blue light-emitting diodes can be varied.

[0167] Light-emitting diodes (LEDs) EDr1, EDg1, EDb1, ..., EDr4, EDg4, and EDb4 can be electrically connected to their respective data lines via corresponding pixel circuits. LEDs electrically connected to the same data line can emit light of the same color. For example, the first red LED EDr1 can be electrically connected to pixel circuit PC11 ([1,1]), the second red LED EDr2 can be electrically connected to pixel circuit PC12 ([1,2]), the third red LED EDr3 can be electrically connected to pixel circuit PC21 ([2,1]), and the fourth red LED EDr4 can be electrically connected to pixel circuit PC22 ([2,2]). Pixel circuit PC11 ([1,1]), pixel circuit PC12 ([1,2]), pixel circuit PC21 ([2,1]), and pixel circuit PC22 ([2,2]) can be electrically connected to the first data line DL1. The first to fourth red LEDs EDr1, EDr2, EDr3, and EDr4 can emit red light.

[0168] Similarly, the first blue LED EDb1 can be electrically connected to the [1,3] pixel circuit PC13, the second blue LED EDb2 can be electrically connected to the [1,4] pixel circuit PC14, the third blue LED EDb3 can be electrically connected to the [2,3] pixel circuit PC23, and the fourth blue LED EDb4 can be electrically connected to the [2,4] pixel circuit PC24. The first to fourth blue LEDs EDb1, EDb2, EDb3 and EDb4 can each be electrically connected to the second data line DL2 and can emit blue light.

[0169] The second green LED EDg2 can be electrically connected to the [1,5] pixel circuit PC15, and the fourth green LED EDg4 can be electrically connected to the [2,5] pixel circuit PC25. Each of the first green LED EDg1 and the third green LED EDg3 can be electrically connected to the pixel circuit arranged on the left (in the -x direction). Each of the [1,6] pixel circuit PC16 and the [2,6] pixel circuit PC26 can be electrically connected to the green LED arranged on the right. The second green LED EDg2 and the fourth green LED EDg4 can each be electrically connected to the third data line DL3 and can emit green light.

[0170] Accordingly, the data signal transmitted by each of the data lines DL1, DL2 and DL3 may include only the data voltage used to drive the pixels that emit light of the same color, and thus the display device 10 can reduce power consumption due to changes in data voltage.

[0171] The distance between the [1,1]th pixel circuit PC11 and the first red LED EDr1 can be different from the distance between the [1,2]th pixel circuit PC12 and the second red LED EDr2. For example, the first red LED EDr1 can overlap with the [1,1]th pixel circuit PC11 in a planar view, and the second red LED EDr2 can be separated from the [1,2]th pixel circuit PC12 in a planar view.

[0172] refer to Figure 8 The first gate signal GWa[1] can be transmitted to the first gate line GWLa1, the second gate signal GWa[2] can be transmitted to the second gate line GWLa2, the first gate signal GWb[1] can be transmitted to the first gate line GWLb1, and the second gate signal GWb[2] can be transmitted to the second gate line GWLb2. The gate signals GWa[1], GWa[2], GWb[1] and GWb[2] can be supplied as square wave signals. In the square wave signal, the connected second transistor T2 (reference) can be made to... Figure 4 The turn-on voltage and the voltage that enables the connected second transistor T2 (reference) to conduct. Figure 4 The cutoff voltage is repeatedly output. In an embodiment, the turn-on voltage of the second transistor T2 can be a high-level voltage, and the cutoff voltage of the second transistor T2 can be a low-level voltage.

[0173] First gate driver 12 (reference) Figure 2The first gate signal GWa[1] and GWa[2] can be configured to sequentially supply first gate lines GWLa1 and GWLa2. The second first gate signal GWa[2] can be an output of the first first gate signal GWa[1] with a phase delay of 1 horizontal time period (1H).

[0174] Second gate driver 13 (reference) Figure 2 The first gate signal GWb[1] and GWb[2] can be configured to sequentially supply second gate lines GWLb1 and GWLb2. The first gate signal GWb[1] can be an output whose phase is delayed by a specific time period from the first gate signal GWa[1]. For example, the first gate signal GWb[1] can be an output whose phase is delayed by 0.5 horizontal time periods (0.5H) from the first gate signal GWa[1]. The second gate signal GWb[2] can be an output whose phase is delayed by 1 horizontal time period (1H) from the first gate signal GWb[1].

[0175] Data drive 15 (reference) Figure 2 The circuit can be configured to supply a first data signal D[1] to a first data line DL1, a second data signal D[2] to a second data line DL2, and a third data signal D[3] to a third data line DL3. The first data signal D[1] may include sequentially output red data voltage R11 corresponding to the [1,1] pixel circuit PC11, red data voltage R12 corresponding to the [1,2] pixel circuit PC12, red data voltage R22 corresponding to the [2,2] pixel circuit PC22, and red data voltage R21 corresponding to the [2,1] pixel circuit PC21. The second data signal D[2] may include sequentially output blue data voltage B13 corresponding to the [1,3] pixel circuit PC13, blue data voltage B14 corresponding to the [1,4] pixel circuit PC14, blue data voltage B24 corresponding to the [2,4] pixel circuit PC24, and blue data voltage B23 corresponding to the [2,3] pixel circuit PC23. The third data signal D[3] may include the green data voltage G15 corresponding to the [1,5] pixel circuit PC15, the green data voltage G16 corresponding to the [1,6] pixel circuit PC16, the green data voltage G26 corresponding to the [2,6] pixel circuit PC26, and the green data voltage G25 corresponding to the [2,5] pixel circuit PC25, which are output sequentially.

[0176] In other words, each of the data signals D[1], D[2] and D[3] can sequentially output the data voltage corresponding to the pixel circuits PC11, PC13 and PC15 connected to the first first gate line GWLa1, the data voltage corresponding to the pixel circuits PC12, PC14 and PC16 connected to the first second gate line GWLb1, the data voltage corresponding to the pixel circuits PC22, PC24 and PC26 connected to the second first gate line GWLa2, and the data voltage corresponding to the pixel circuits PC21, PC23 and PC25 connected to the second second gate line GWLb2.

[0177] Accordingly, the data signals D[1], D[2] and D[3] transmitted by data lines DL1, DL2 and DL3 respectively can include only the data voltage used to drive the pixels that emit light of the same color, and thus the power consumption for data voltage switching can be reduced.

[0178] Figure 9 This is a schematic plan view of a part of a display device according to an embodiment. Figure 10 It is used for illustrative description Figure 9 A diagram illustrating the operation of the pixel circuit and light-emitting diodes in a display device. Figure 11 It is applied to Figure 9 A schematic diagram of the data voltage of the first data line of the display device.

[0179] Figure 9 The display device 10 is shown (reference). Figure 1A The image pattern PTN extending in the second direction (y direction) is displayed in the display area DA. Pixel unit 11 (reference) Figure 2 It can be provided in the display area DA, and the image pattern PTN can be achieved through the brightness difference between multiple pixels.

[0180] Figure 10 yes Figure 9 An enlarged view of area I. Figure 10 A segment of pixel circuits PC11, PC12, PC21, and PC22, electrically connected to the first data line DL1 and red light-emitting diodes EDr11, EDr13, EDr21, and EDr23, is shown as an example. Region I may include the boundary of an image pattern PTN extending in a second direction (y-direction).

[0181] refer to Figure 10The first red LED EDr11 can be electrically connected to the [1,1] pixel circuit PC11, the third red LED EDr13 can be electrically connected to the [1,2] pixel circuit PC12, the second red LED EDr21 can be electrically connected to the [2,1] pixel circuit PC21, and the fourth red LED EDr23 can be electrically connected to the [2,2] pixel circuit PC22. At the boundary of the image pattern PTN extending in the second direction (y direction), the brightness of LEDs arranged in the same LED column can be the same, and the brightness of LEDs arranged in different LED columns can be different. For example, the brightness of LEDs arranged in the first LED column (refer to...) Figure 6 The first red LED EDr11 and the second red LED EDr21 in the array can emit light at a first brightness and are arranged in the third LED column (see reference). Figure 6 The third red LED EDr13 and the fourth red LED EDr23 in the first red LED can emit light at a second brightness, which is different from the first brightness.

[0182] refer to Figure 11 The first data signal D[1] supplied to the first data line DL1 may include the red data voltage R11 corresponding to the [1,1]th pixel circuit PC11, the red data voltage R12 corresponding to the [1,2]th pixel circuit PC12, the red data voltage R22 corresponding to the [2,2]th pixel circuit PC22, and the red data voltage R21 corresponding to the [2,1]th pixel circuit PC21, which are output sequentially. Figure 9 and Figure 10 As shown, at the boundary of the image pattern PTN extending in the second direction (y direction), the data voltage R11 corresponding to the [1,1]th pixel circuit PC11 and the data voltage R21 corresponding to the [2,1]th pixel circuit PC21 can have an amplitude corresponding to the first brightness, and the data voltage R12 corresponding to the [1,2]th pixel circuit PC12 and the data voltage R22 corresponding to the [2,2]th pixel circuit PC22 can have an amplitude corresponding to the second brightness.

[0183] In the display device 10 according to one or more embodiments, since the pixel circuit PC11 arranged in the odd-numbered pixel circuit column of the odd-numbered pixel circuit row and the pixel circuit PC22 arranged in the even-numbered pixel circuit column of the even-numbered pixel circuit row are electrically connected to the corresponding first gate lines GWLa1 and GWLa2, and the pixel circuit PC12 arranged in the even-numbered pixel circuit column of the odd-numbered pixel circuit row and the pixel circuit PC21 arranged in the odd-numbered pixel circuit column of the even-numbered pixel circuit row are electrically connected to the corresponding second gate lines GWLb1 and GWLb2, data voltages with the same amplitude can be continuously output. Accordingly, the display device 10 according to one or more embodiments can reduce the number of times the data voltage is changed. That is, the red data voltage R12 corresponding to the [1,2]th pixel circuit PC12 and the red data voltage R22 corresponding to the [2,2]th pixel circuit PC22 have the same amplitude, which eliminates the need to change the data voltage. Similarly, the red data voltage R21 corresponding to the [2,1] pixel circuit PC21 and the red data voltage R31 corresponding to the [3,1] pixel circuit have the same amplitude, which does not require changing the data voltage.

[0184] In an embodiment, in the display device according to the comparative example, in all pixel circuit rows, pixel circuits arranged in odd-numbered pixel circuit columns can each be electrically connected to a corresponding first gate line, and pixel circuits arranged in even-numbered pixel circuit columns can each be electrically connected to a corresponding second gate line. In this case, the data voltage may vary for each pixel circuit, and power consumption may increase due to the variation in data voltage.

[0185] Figure 12 This is a diagram used to schematically illustrate the connection between the pixel circuit and the data lines and gate lines according to an embodiment. Figure 13 It is used for illustrative description Figure 12 The diagram shows the connection between the pixel circuit and the light-emitting diode. Figure 14 It is used to describe what is applied to Figure 12 The diagram shows the gate voltage and data voltage of the pixel circuit.

[0186] refer to Figure 12 Pixel circuits PCmn can be arranged in a matrix along a first direction (x-direction) and a second direction (y-direction). In this respect, m represents the row of the pixel circuit, and n represents the column of the pixel circuit. In this respect, each of m and n is a natural number greater than 1. Although... Figure 12 A segment of sixteen pixel circuits PC11, PC12, ..., PC28 arranged in a 2×8 matrix is ​​shown, but one or more embodiments are not limited thereto. The display device 10 may include more pixel circuits PCmn and signal lines.

[0187] The first gate line may include a first gate line GWLa1 and a second gate line GWLa2 extending in a first direction (x-direction). The second gate line may include a first second gate line GWLb1 and a second second gate line GWLb2 extending in the first direction (x-direction). The data lines may include a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL4, each extending in a second direction (y-direction). Each of the pixel circuits PCmn may be electrically connected to a corresponding data line and a corresponding gate line among the first and second gate lines.

[0188] A pair of pixel circuit columns adjacent to each other in the first direction (x-direction) can be electrically connected to a corresponding data line. For example, pixel circuits PC11 and PC21 arranged in the first pixel circuit column n1 and pixel circuits PC12 and PC22 arranged in the second pixel circuit column n2 can be electrically connected to the first data line DL1. Pixel circuits PC13 and PC23 arranged in the third pixel circuit column n3 and pixel circuits PC14 and PC24 arranged in the fourth pixel circuit column n4 can be electrically connected to the second data line DL2. Pixel circuits PC15 and PC25 arranged in the fifth pixel circuit column n5 and pixel circuits PC16 and PC26 arranged in the sixth pixel circuit column n6 can be electrically connected to the third data line DL3. Pixel circuits PC17 and PC27 arranged in the seventh pixel circuit column n7 and pixel circuits PC18 and PC28 arranged in the eighth pixel circuit column n8 can be electrically connected to the fourth data line DL4.

[0189] One of the two pixel circuits constituting pixel circuit pair PP can be electrically connected to the corresponding first gate line, and the other can be electrically connected to the corresponding second gate line. Pixel circuits PC11, PC13, PC15, and PC17 arranged in the odd-numbered pixel circuit column of odd-numbered pixel circuit row m1 in pixel circuit PCmn can be electrically connected to the first first gate line GWLa1, and pixel circuits PC22, PC24, PC26, and PC28 arranged in the even-numbered pixel circuit column of even-numbered pixel circuit row m2 can be electrically connected to the second first gate line GWLa2. Pixel circuits PC12, PC14, PC16, and PC18 arranged in the even-numbered pixel circuit column of odd-numbered pixel circuit row m1 in pixel circuit PCmn can be electrically connected to the first second gate line GWLb1, and pixel circuits PC21, PC23, PC25, and PC27 arranged in the odd-numbered pixel circuit column of even-numbered pixel circuit row m2 can be electrically connected to the second second gate line GWLb2.

[0190] refer to Figure 13 Each pixel in the PCmn circuit can be electrically connected to a light-emitting diode. Figure 13The boundaries of the light-emitting diodes EDr1, EDg1a, EDb1, EDg1b, ..., EDb4, EDg4a, EDr4, and EDg4b shown schematically illustrate the boundaries of the emission region of each light-emitting diode. The light-emitting diodes EDr1, EDg1a, EDb1, EDg1b, ..., EDb4, EDg4a, EDr4, and EDg4b can be arranged in a first direction (x-direction) and a second direction (y-direction). Red light-emitting diodes EDr1, EDr2, EDr3, and EDr4, and blue light-emitting diodes EDb1, EDb2, EDb3, and EDb4 can alternate in odd-numbered rows of light-emitting diodes, and green light-emitting diodes EDg1a, EDg1b, EDg2a, EDg2b, EDg3a, EDg3b, EDg4a, and EDg4b can be arranged in even-numbered rows of light-emitting diodes. In this embodiment, green LEDs can be positioned at each of the four corners of the virtual quadrilateral, and blue or red LEDs can be positioned at the center of the virtual quadrilateral. LEDs EDr1, EDg1a, EDb1, EDg1b, ..., EDb4, EDg4a, EDr4, and EDg4b can be arranged in PenTile form. ® Arrange the items in a diamond pattern.

[0191] LEDs EDr1, EDg1a, EDb1, EDg1b, ..., EDb4, EDg4a, EDr4, and EDg4b can be electrically connected to their respective data lines via corresponding pixel circuits. Odd-numbered data lines DL1 and DL3 can be electrically connected to the red and blue LEDs, respectively, while even-numbered data lines DL2 and DL4 can be electrically connected to the green LED.

[0192] The first red LED EDr1 can be electrically connected to the [1,1] pixel circuit PC11, the second red LED EDr2 can be electrically connected to the [1,2] pixel circuit PC12, the third blue LED EDb3 can be electrically connected to the [2,1] pixel circuit PC21, and the fourth blue LED EDb4 can be electrically connected to the [2,2] pixel circuit PC22. The [1,1] pixel circuit PC11, the [1,2] pixel circuit PC12, the [2,1] pixel circuit PC21, and the [2,2] pixel circuit PC22 can each be electrically connected to the first data line DL1. The first red LED EDr1 and the second red LED EDr2 can emit red light. The third blue LED EDb3 and the fourth blue LED EDb4 can emit blue light.

[0193] The first blue LED EDb1 can be electrically connected to the [1,5]th pixel circuit PC15, the second blue LED EDb2 can be electrically connected to the [1,6]th pixel circuit PC16, the third red LED EDr3 can be electrically connected to the [2,5]th pixel circuit PC25, and the fourth red LED EDr4 can be electrically connected to the [2,6]th pixel circuit PC26. The [1,5]th pixel circuit PC15, the [1,6]th pixel circuit PC16, the [2,5]th pixel circuit PC25, and the [2,6]th pixel circuit PC26 can each be electrically connected to the third data line DL3. The first blue LED EDb1 and the second blue LED EDb2 can emit blue light. The third red LED EDr3 and the fourth red LED EDr4 can emit red light.

[0194] In other words, for the first data line DL1, a pair of pixel circuits PC11 and PC12 connected to red LEDs EDr1 and EDr2 that emit red light, and a pair of pixel circuits PC21 and PC22 connected to blue LEDs EDb3 and EDb4 that emit blue light, can be arranged alternately in the second direction (y direction). For the third data line DL3, a pair of pixel circuits PC15 and PC16 connected to blue LEDs EDb1 and EDb2 that emit blue light, and a pair of pixel circuits PC25 and PC26 connected to red LEDs EDr3 and EDr4 that emit red light, can be arranged alternately in the second direction (y direction).

[0195] The first green LED EDg1a can be electrically connected to the [1,3]th pixel circuit PC13, the second green LED EDg2a can be electrically connected to the [1,4]th pixel circuit PC14, the third green LED EDg3a can be electrically connected to the [2,3]th pixel circuit PC23, and the fourth green LED EDg4a can be electrically connected to the [2,4]th pixel circuit PC24. The [1,3]th pixel circuit PC13, the [1,4]th pixel circuit PC14, the [2,3]th pixel circuit PC23, and the [2,4]th pixel circuit PC24 can each be electrically connected to the second data line DL2. The first green LED EDg1a, the second green LED EDg2a, the third green LED EDg3a, and the fourth green LED EDg4a can emit green light.

[0196] The first and second green LEDs, EDg1b, can be electrically connected to the [1,7] pixel circuit PC17; the second and second green LEDs, EDg2b, can be electrically connected to the [1,8] pixel circuit PC18; the third and second green LEDs, EDg3b, can be electrically connected to the [2,7] pixel circuit PC27; and the fourth and second green LEDs, EDg4b, can be electrically connected to the [2,8] pixel circuit PC28. The [1,7] pixel circuit PC17, the [1,8] pixel circuit PC18, the [2,7] pixel circuit PC27, and the [2,8] pixel circuit PC28 can each be electrically connected to the fourth data line DL4. The first and second green LEDs, EDg1b, EDg2b, EDg3b, and EDg4b can emit green light.

[0197] Each of the second data line DL2 and the fourth data line DL4 can be electrically connected to a green light-emitting diode (LED). The data signal transmitted by each of the second data line DL2 and the fourth data line DL4 can consist only of the data voltage used to drive the pixel emitting green light.

[0198] The first LED column in which red LEDs EDr1 and blue LEDs EDb3 alternate in the second direction (y direction), the second LED column in which green LEDs EDg1a and EDg3a are arranged to emit green light, the third LED column in which blue LEDs EDb1 and red LEDs EDr3 alternate in the second direction (y direction), and the fourth LED column in which green LEDs EDg1b and EDg3b are arranged can be repeated sequentially in the first direction (x direction).

[0199] refer to Figure 14 The first gate signal GWa[1] can be transmitted to the first gate line GWLa1, the second gate signal GWa[2] can be transmitted to the second gate line GWLa2, the first gate signal GWb[1] can be transmitted to the first gate line GWLb1, and the second gate signal GWb[2] can be transmitted to the second gate line GWLb2. The gate signals GWa[1], GWa[2], GWb[1] and GWb[2] can be supplied as square wave signals. In the square wave signal, the connected second transistor T2 (reference) can be made to... Figure 4 The conduction voltage that enables the connected second transistor T2 (reference) to conduct. Figure 4 The cutoff voltage is repeatedly output.

[0200] First gate driver 12 (reference) Figure 2The first gate signal GWa[1] and GWa[2] can be configured to sequentially supply first gate lines GWLa1 and GWLa2. The second first gate signal GWa[2] can be an output of the first first gate signal GWa[1] with a phase delay of 1 horizontal time period (1H).

[0201] Second gate driver 13 (reference) Figure 2 The first gate signal GWb[1] and GWb[2] can be configured to sequentially supply second gate lines GWLb1 and GWLb2. The first gate signal GWb[1] can be an output whose phase is delayed by a specific time period from the first gate signal GWa[1]. For example, the first gate signal GWb[1] can be an output whose phase is delayed by 0.5 horizontal time periods (0.5H) from the first gate signal GWa[1]. The second gate signal GWb[2] can be an output whose phase is delayed by 1 horizontal time period (1H) from the first gate signal GWb[1].

[0202] Data drive 15 (reference) Figure 2 It can be configured to supply a first data signal D[1] to a first data line DL1, a second data signal D[2] to a second data line DL2, a third data signal D[3] to a third data line DL3, and a fourth data signal D[4] to a fourth data line DL4.

[0203] The first data signal D[1] may include the red data voltage R11 corresponding to the [1,1] pixel circuit PC11, the red data voltage R12 corresponding to the [1,2] pixel circuit PC12, the blue data voltage B22 corresponding to the [2,2] pixel circuit PC22, and the blue data voltage B21 corresponding to the [2,1] pixel circuit PC21, which are output sequentially. The second data signal D[2] may include the green data voltage G13 corresponding to the [1,3] pixel circuit PC13, the green data voltage G14 corresponding to the [1,4] pixel circuit PC14, the green data voltage G24 corresponding to the [2,4] pixel circuit PC24, and the green data voltage G23 corresponding to the [2,3] pixel circuit PC23, which are output sequentially. The third data signal D[3] may include the blue data voltage B15 corresponding to the [1,5] pixel circuit PC15, the blue data voltage B16 corresponding to the [1,6] pixel circuit PC16, the red data voltage R26 corresponding to the [2,6] pixel circuit PC26, and the red data voltage R25 corresponding to the [2,5] pixel circuit PC25, which are output sequentially. The fourth data signal D[4] may include the green data voltage G17 corresponding to the [1,7] pixel circuit PC17, the green data voltage G18 corresponding to the [1,8] pixel circuit PC18, the green data voltage G28 corresponding to the [2,8] pixel circuit PC28, and the green data voltage G27 corresponding to the [2,7] pixel circuit PC27, which are output sequentially.

[0204] In other words, each of the data signals D[1], D[2], D[3] and D[4] can sequentially output the data voltage corresponding to the pixel circuits PC11, PC13, PC15 and PC17 connected to the first first gate line GWLa1, the data voltage corresponding to the pixel circuits PC12, PC14, PC16 and PC18 connected to the first second gate line GWLb1, the data voltage corresponding to the pixel circuits PC22, PC24, PC26 and PC28 connected to the second first gate line GWLa2, and the data voltage corresponding to the pixel circuits PC21, PC23, PC25 and PC27 connected to the second second gate line GWLb2.

[0205] The second data signal D[2] transmitted by the second data line DL2 and the fourth data signal D[4] transmitted by the fourth data line DL4 can include only the data voltage for driving the pixels emitting green light, and therefore, the power consumption for data voltage switching can be reduced. Furthermore, when displaying image patterns including boundaries extending in the second direction (y direction) (such as...) Figure 9 When the image pattern PTN shown is used, the number of data voltage changes can be reduced.

[0206] Figure 15 This is a diagram used to schematically illustrate the connection between the pixel circuit and the data lines and gate lines according to an embodiment. Figure 16 It is used to describe what is applied to Figure 15 The diagram shows the gate voltage and data voltage of the pixel circuit.

[0207] refer to Figure 15 Pixel circuits PCmn can be arranged in a matrix along a first direction (x-direction) and a second direction (y-direction). In this respect, m represents the row of the pixel circuit, and n represents the column of the pixel circuit. In this respect, each of m and n is a natural number greater than 1. Although... Figure 15 A segment of sixteen pixel circuits PC11, PC12, ..., PC28 arranged in a 2×8 matrix is ​​shown, but one or more embodiments are not limited thereto. The display device 10 may include more pixel circuits PCmn and signal lines.

[0208] The first gate line may include a first gate line GWLa1 and a second gate line GWLa2 extending in a first direction (x-direction). The second gate line may include a first second gate line GWLb1 and a second second gate line GWLb2 extending in the first direction (x-direction). The data lines may include a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL4, each extending in a second direction (y-direction). Each of the pixel circuits PCmn may be electrically connected to a corresponding data line and a corresponding gate line among the first and second gate lines.

[0209] A pair of pixel circuit columns adjacent to each other in the first direction (x-direction) can be electrically connected to a corresponding data line. For example, pixel circuits PC11 and PC21 arranged in the first pixel circuit column n1 and pixel circuits PC12 and PC22 arranged in the second pixel circuit column n2 can be electrically connected to the first data line DL1. Pixel circuits PC13 and PC23 arranged in the third pixel circuit column n3 and pixel circuits PC14 and PC24 arranged in the fourth pixel circuit column n4 can be electrically connected to the second data line DL2. Pixel circuits PC15 and PC25 arranged in the fifth pixel circuit column n5 and pixel circuits PC16 and PC26 arranged in the sixth pixel circuit column n6 can be electrically connected to the third data line DL3. Pixel circuits PC17 and PC27 arranged in the seventh pixel circuit column n7 and pixel circuits PC18 and PC28 arranged in the eighth pixel circuit column n8 can be electrically connected to the fourth data line DL4.

[0210] One of the two pixel circuits constituting pixel circuit pair PP can be electrically connected to the corresponding first gate line, and the other can be electrically connected to the corresponding second gate line. Pixel circuits PC11, PC13, PC15, and PC17 arranged in the odd-numbered pixel circuit column of odd-numbered pixel circuit row m1 can be electrically connected to the first first gate line GWLa1, and pixel circuits PC12, PC14, PC16, and PC18 arranged in the even-numbered pixel circuit column of odd-numbered pixel circuit row m1 in pixel circuit PCmn can be electrically connected to the first second gate line GWLb1. In the pixel circuits arranged in the even-numbered pixel circuit row m2, pixel circuits PC21 and PC25 connected to odd-numbered data lines DL1 and DL3 and arranged in odd-numbered columns, and pixel circuits PC24 and PC28 connected to even-numbered data lines DL2 and DL4 and arranged in even-numbered columns, can be electrically connected to the second first gate line GWLa2. In the pixel circuits arranged in the even-numbered pixel circuit row m2, pixel circuits PC22 and PC26, which are connected to the odd-numbered data lines DL1 and DL3 and are arranged in the even-numbered columns, and pixel circuits PC23 and PC27, which are connected to the even-numbered data lines DL2 and DL4 and are arranged in the odd-numbered columns, can be electrically connected to the second gate line GWLb2.

[0211] Each pixel in the PCmn circuit can be electrically connected to a light-emitting diode. Figure 15 The pixel circuit PCmn shown can be used with reference Figure 13 The pixel circuit PCmn described is connected to the corresponding light-emitting diodes EDr1, EDg1a, EDb1, EDg1b, ..., EDb4, EDg4a, EDr4, and EDg4b in the same way as the corresponding light-emitting diodes.

[0212] refer to Figure 16 The first gate signal GWa[1] can be transmitted to the first gate line GWLa1, the second gate signal GWa[2] can be transmitted to the second gate line GWLa2, the first gate signal GWb[1] can be transmitted to the first gate line GWLb1, and the second gate signal GWb[2] can be transmitted to the second gate line GWLb2. The gate signals GWa[1], GWa[2], GWb[1] and GWb[2] can be supplied as square wave signals. In the square wave signal, the connected second transistor T2 (reference) can be made to... Figure 4 The turn-on voltage and the voltage that enables the connected second transistor T2 (reference) to conduct. Figure 4 The cutoff voltage is repeatedly output.

[0213] First gate driver 12 (reference) Figure 2The first gate signal GWa[1] and GWa[2] can be configured to sequentially supply first gate lines GWLa1 and GWLa2. The second first gate signal GWa[2] can be an output of the first first gate signal GWa[1] with a phase delay of 1 horizontal time period (1H).

[0214] Second gate driver 13 (reference) Figure 2 The first gate signal GWb[1] and GWb[2] can be configured to sequentially supply second gate lines GWLb1 and GWLb2. The first gate signal GWb[1] can be an output whose phase is delayed by a specific time period from the first gate signal GWa[1]. For example, the first gate signal GWb[1] can be an output whose phase is delayed by 0.5 horizontal time periods (0.5H) from the first gate signal GWa[1]. The second gate signal GWb[2] can be an output whose phase is delayed by 1 horizontal time period (1H) from the first gate signal GWb[1].

[0215] Data drive 15 (reference) Figure 2 It can be configured to supply a first data signal D[1] to a first data line DL1, a second data signal D[2] to a second data line DL2, a third data signal D[3] to a third data line DL3, and a fourth data signal D[4] to a fourth data line DL4.

[0216] The first data signal D[1] may include the red data voltage R11 corresponding to the [1,1] pixel circuit PC11, the red data voltage R12 corresponding to the [1,2] pixel circuit PC12, the blue data voltage B21 corresponding to the [2,1] pixel circuit PC21, and the blue data voltage B22 corresponding to the [2,2] pixel circuit PC22, which are output sequentially. The second data signal D[2] may include the green data voltage G13 corresponding to the [1,3] pixel circuit PC13, the green data voltage G14 corresponding to the [1,4] pixel circuit PC14, the green data voltage G24 corresponding to the [2,4] pixel circuit PC24, and the green data voltage G23 corresponding to the [2,3] pixel circuit PC23, which are output sequentially. The third data signal D[3] may include the blue data voltage B15 corresponding to the [1,5] pixel circuit PC15, the blue data voltage B16 corresponding to the [1,6] pixel circuit PC16, the red data voltage R25 corresponding to the [2,5] pixel circuit PC25, and the red data voltage R26 corresponding to the [2,6] pixel circuit PC26, which are output sequentially. The fourth data signal D[4] may include the green data voltage G17 corresponding to the [1,7] pixel circuit PC17, the green data voltage G18 corresponding to the [1,8] pixel circuit PC18, the green data voltage G28 corresponding to the [2,8] pixel circuit PC28, and the green data voltage G27 corresponding to the [2,7] pixel circuit PC27, which are output sequentially.

[0217] In other words, each of the data signals D[1], D[2], D[3] and D[4] can sequentially output data voltages corresponding to pixel circuits PC11, PC13, PC15 and PC17 connected to the first first gate line GWLa1, data voltages corresponding to pixel circuits PC12, PC14, PC16 and PC18 connected to the first second gate line GWLb1, data voltages corresponding to pixel circuits PC21, PC24, PC25 and PC28 connected to the second first gate line GWLa2, and data voltages corresponding to pixel circuits PC22, PC23, PC26 and PC27 connected to the second second gate line GWLb2.

[0218] Each of the second data signal D[2] transmitted by the second data line DL2 and the fourth data signal D[4] transmitted by the fourth data line DL4 can include only the data voltage for driving the pixel emitting green light, and thus, the power consumption for data voltage switching can be reduced. Furthermore, when displaying an image pattern including a boundary extending in the second direction (y direction) (such as...) Figure 9When the image pattern PTN shown is displayed, data voltages of pixels with the same brightness can be continuously output to reduce the number of times the data voltage changes.

[0219] The display device 10 according to the embodiment can be applied to various electronic devices. The electronic device according to the embodiment may include the above-described display device 10, and may further include modules or devices with other additional functions in addition to the display device 10.

[0220] Figure 17 This is a block diagram of an electronic device 1 according to an embodiment.

[0221] refer to Figure 17 The electronic device 1 according to the embodiment may include a display module 1200, a processor 1100, a memory 1300, and a power module 1400.

[0222] Processor 1100 may include a CPU, application processor (AP), graphics processing unit (GPU), communication processor (CP), image signal processor (ISP), and controller 20 (reference). Figure 2 At least one of the following. In embodiments, processor 1100 may be divided into two or more from a functional or structural perspective. For example, processor 1100 may include one or more processors, and may include a main processor in the form of a first driver chip containing a CPU, and a component configured to receive image signals from the main processor (e.g., Figure 2 The auxiliary processor in the form of a second driver chip of the controller 20, which processes the image data signal (IMG) shown in the figure to meet the interface specifications of the display module 1200.

[0223] Memory 1300 may include at least one of non-volatile memory and volatile memory. Data information required for the operation of processor 1100 or display module 1200 may be stored in memory 1300. When processor 1100 executes an application stored in memory 1300, image data signals (e.g., Figure 2 The image data signal (IMG) shown in the figure and / or input control signal (e.g., Figure 2 The control signal CONT shown can be transmitted to the display module 1200, and the display module 1200 can process the received signal and output image information through the display screen.

[0224] The power module 1400 may include a power supply module such as a power adapter or battery device, and a power conversion module configured to convert the power supplied by the power supply module to generate the power required for the operation of the electronic device 1. The power conversion performed by the power conversion module may include, but is not limited to, DC-DC conversion, AC-DC conversion, and DC-AC conversion.

[0225] At least one of the aforementioned elements of electronic device 1 may be included in the display device according to the above embodiments. In some embodiments, some modules of independent modules that are functionally included in a single module may be included in the display device, and other modules may be provided separately from the display device. For example, the display device may include a display module 1200 and an auxiliary processor of processor 1100, and the main processor of processor 1100, memory 1300, and power module 1400 may be provided in electronic device 1 in the form of other devices besides the display device. As another example, power module 1400 may be provided in the display device and may supply power to processor 1100 and memory 1300 provided in electronic device 1 other than the display device, and one or more embodiments are not limited thereto.

[0226] Figure 18 An electronic device according to various embodiments is illustrated schematically.

[0227] refer to Figure 18 Various electronic devices employing the display device according to the embodiments may include not only electronic devices for image display (such as smartphones 1_1a, tablet PCs 1_1b, laptops 1_1c, TVs 1_1d, and desktop monitors 1_1e), but also wearable electronic devices (such as smart glasses 1_2a, head-mounted displays 1_2b, and smartwatches 1_2c) and vehicle electronic devices 1_3 (such as car dashboards, central information displays (CIDs) arranged on the center console or dashboard of a car, and interior mirror displays) that include display modules.

[0228] Figure 18 Electronic devices may include Figure 17 The components shown. For example, smartphone 1_1a may include... Figure 17 The diagram shows a display module 1200, a processor 1100, a memory 1300, and a power module 1400. The smartphone 1_1a may further include a communication module and a battery device. Power supplied from the battery device can be converted by the power module 1400 and supplied to the processor 1100, memory 1300, and display module 1200. In an embodiment, the display device applied to the smartphone 1_1a may include the display module 1200 and may further include the power module 1400. The processor 1100 and memory 1300 may be provided as chips mounted on a motherboard of an external device, but are not limited thereto.

[0229] According to one or more of the above embodiments, a display device with improved power consumption and an electronic device including the display device can be realized. However, one or more embodiments are not limited to this effect.

[0230] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. Descriptions of features or aspects within the various embodiments should generally be considered as other similar features or aspects that may be used in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made thereto without departing from the spirit and scope defined by the claims.

Claims

1. A display device, comprising: The pixel circuitry is arranged in a first direction and a second direction intersecting the first direction. The first gate line and the second gate line extend in the first direction; as well as The data cable extends in the second direction. Among them, the pixel circuits arranged in odd-numbered columns and the pixel circuits arranged in even-numbered columns that are adjacent to each other in the first direction are electrically connected to a data line, and The pixel circuits arranged in odd-numbered columns of odd-numbered rows and the pixel circuits arranged in even-numbered columns of even-numbered rows are each electrically connected to the corresponding first gate line in the first gate line, and The pixel circuits arranged in the even columns of the odd rows and the pixel circuits arranged in the odd columns of the even rows are each electrically connected to the corresponding second gate line in the second gate line.

2. The display device according to claim 1, wherein Each of the pixel circuits includes: The first transistor is electrically connected between the driving voltage line and the light-emitting diode; and The second transistor is electrically connected between the corresponding data line in the data line and the first transistor. In this configuration, the second transistor of one of the pixel circuits arranged in the odd-numbered columns and the pixel circuits arranged in the even-numbered columns, which are adjacent to each other in the first direction, is connected to the corresponding first gate line in the first gate line, and the second transistor of the other pixel circuit is connected to the corresponding second gate line in the second gate line.

3. The display device of claim 2, wherein, The first transistor is an oxide semiconductor transistor.

4. The display device according to claim 2, wherein The second transistor includes a second gate electrode, and In the plan view, the second gate electrode has an island shape.

5. The display device according to claim 1, further comprising: The light-emitting diode is electrically connected to the pixel circuit. Among them, the light-emitting diodes that are electrically connected to the same data line emit light of the same color.

6. The display device of claim 5, wherein, The light-emitting diode includes a first light-emitting diode that emits light of a first color, a second light-emitting diode that emits light of a second color, and a third light-emitting diode that emits light of a third color. In each odd-numbered LED column, the first LED and the second LED alternate in the second direction, and in each even-numbered LED column, the third LED is arranged in the second direction.

7. The display device according to claim 5, wherein The light-emitting diode includes a first light-emitting diode that emits light of a first color, a second light-emitting diode that emits light of a second color, and a third light-emitting diode that emits light of a third color. The first LED column in which the first LED is arranged in the second direction, the second LED column in which the second LED is arranged in the second direction, and the third LED column in which the third LED is arranged in the second direction are repeated sequentially in the first direction.

8. The display device according to claim 1, further comprising: The light-emitting diode is electrically connected to the pixel circuit. The light-emitting diode includes a first light-emitting diode that emits light of a first color, a second light-emitting diode that emits light of a second color, and a third light-emitting diode that emits light of a third color. The odd-numbered data lines are electrically connected to the first LED and the third LED, and the even-numbered data lines are electrically connected to the second LED.

9. The display device of claim 8, wherein, The first light-emitting diode column in which the first light-emitting diode and the third light-emitting diode alternate with each other in the second direction, the second light-emitting diode column in which the second light-emitting diode is arranged in the second direction, the third light-emitting diode column in which the third light-emitting diode and the first light-emitting diode alternate with each other in the second direction, and the fourth light-emitting diode column in which the second light-emitting diode is arranged in the second direction are repeated sequentially in the first direction.

10. A display device, comprising: The first pixel circuit and the second pixel circuit are adjacent to each other in the first pixel circuit row; The third pixel circuit and the fourth pixel circuit are adjacent to each other in the second pixel circuit row; The data driver is configured to output data signals to the data line; The first gate driver is configured to sequentially output the first gate signal to the first gate line; as well as The second gate driver is configured to sequentially output the second gate signal to the second gate line. Each of the first pixel circuit and the fourth pixel circuit is electrically connected to a corresponding first gate line in the first gate line, and each of the second pixel circuit and the third pixel circuit is electrically connected to a corresponding second gate line in the second gate line.

11. The display device of claim 10, wherein, The first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are electrically connected to the first data line in the data line.

12. The display device of claim 11, wherein, The first data line is arranged between the first pixel circuit and the second pixel circuit, and between the third pixel circuit and the fourth pixel circuit.

13. The display device of claim 11, wherein, The data signals corresponding to the first data line include a first data voltage corresponding to the first pixel circuit, a second data voltage corresponding to the second pixel circuit, a fourth data voltage corresponding to the fourth pixel circuit, and a third data voltage corresponding to the third pixel circuit. The first data voltage, the second data voltage, the fourth data voltage, and the third data voltage are output sequentially.

14. The display device according to claim 11, further comprising: The first light-emitting diode is electrically connected to the first pixel circuit; The second light-emitting diode is electrically connected to the second pixel circuit; The third light-emitting diode is electrically connected to the third pixel circuit; as well as The fourth light-emitting diode is electrically connected to the fourth pixel circuit. The first light-emitting diode, the second light-emitting diode, the third light-emitting diode, and the fourth light-emitting diode emit light of the same color.

15. The display device of claim 14, wherein, The distance between the first pixel circuit and the first light-emitting diode is different from the distance between the second pixel circuit and the second light-emitting diode.

16. The display device according to claim 10, wherein, Each of the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit includes: The first transistor is electrically connected between the driving voltage line and the light-emitting diode; and The second transistor is electrically connected between the corresponding data line in the data line and the first transistor. In this configuration, the second transistor of each pixel circuit in the first pixel circuit and the fourth pixel circuit is electrically connected to the corresponding first gate line in the first gate line, and the second transistor of each pixel circuit in the second pixel circuit and the third pixel circuit is electrically connected to the corresponding second gate line in the second gate line.

17. An electronic device comprising: Display device; Memory, used to store image data signals or input control signals; as well as One or more processors are configured to transmit the image data signal or the input control signal stored in the memory to the display device. The display device includes: The first pixel circuit and the second pixel circuit are adjacent to each other in the first pixel circuit row; The third pixel circuit and the fourth pixel circuit are adjacent to each other in the second pixel circuit row; The first and second gate lines extend in a first direction; and The data cable extends in a second direction that intersects the first direction. The first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit are electrically connected to the first data line in the data line. Each of the first pixel circuit and the fourth pixel circuit is electrically connected to a corresponding first gate line in the first gate line, and each of the second pixel circuit and the third pixel circuit is electrically connected to a corresponding second gate line in the second gate line.

18. The electronic device according to claim 17, wherein, Each of the first pixel circuit, the second pixel circuit, the third pixel circuit, and the fourth pixel circuit includes: The first transistor is electrically connected between the driving voltage line and the light-emitting diode; and The second transistor is electrically connected between the first data line and the first transistor. In this configuration, the second transistor of each pixel circuit in the first pixel circuit and the fourth pixel circuit is electrically connected to the corresponding first gate line in the first gate line, and the second transistor of each pixel circuit in the second pixel circuit and the third pixel circuit is electrically connected to the corresponding second gate line in the second gate line.

19. The electronic device according to claim 17, wherein, The display device further includes: The first light-emitting diode is electrically connected to the first pixel circuit; The second light-emitting diode is electrically connected to the second pixel circuit; A third light-emitting diode is electrically connected to the third pixel circuit; and The fourth light-emitting diode is electrically connected to the fourth pixel circuit. The first light-emitting diode, the second light-emitting diode, the third light-emitting diode, and the fourth light-emitting diode emit light of the same color.

20. The electronic device according to any one of claims 17 to 19, wherein, The electronic device is an electronic device for image display, a wearable electronic device, or a vehicle electronic device.

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