Display panel and display device

Abstract

This invention provides a display panel and a display device. The display panel includes a substrate, a driving layer and an electrode layer located on one side of the substrate; the driving layer includes a shift register, which includes a plurality of cascaded shift register units; the electrode layer includes a plurality of electrode groups, each electrode group including a first electrode and a second electrode; wherein, along a direction perpendicular to the plane of the substrate, the shift register units at least partially overlap with at least one electrode group. This invention, when applied to transparent displays, can achieve a borderless display effect with high edge transparency.

Description

[0001] This application is a divisional application of Chinese Patent No. 202411127800.X, filed on August 16, 2024, entitled “Display Panel and Display Device”. Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0003] LEDs (light-emitting diodes) efficiently convert electrical energy into light energy, featuring small size, long lifespan, high efficiency, energy saving, and rich colors. With continuous technological advancements, LEDs have been widely applied in fields such as photography, flat panel displays, and medical devices. In the display field, LEDs can be used as sub-pixels in transparent displays or large-screen splicing displays. A key research challenge is how to achieve borderless displays while ensuring sufficient transmittance at the edges. Summary of the Invention

[0004] This invention provides a display panel and a display device to solve the technical problem of achieving borderless display with transmittance in the edge area.

[0005] In a first aspect, embodiments of the present invention provide a display panel, the display panel including a substrate, a driving layer located on one side of the substrate, and an electrode layer; the driving layer includes a shift register, the shift register including a plurality of cascaded shift register units; the electrode layer includes a plurality of electrode groups, the electrode groups including a first electrode and a second electrode; wherein, Along a direction perpendicular to the plane of the substrate, the shift register cell at least partially overlaps with at least one electrode group.

[0006] Secondly, based on the same inventive concept, embodiments of the present invention provide a display device, including a display panel provided in any embodiment of the present invention.

[0007] The display panel and display device provided in this embodiment of the invention have the following beneficial effects: A shift register unit is disposed in the display panel, at least partially overlapping with at least one electrode group, such that at least a portion of the shift register unit is located within the display area, thereby reducing the bezel and achieving a borderless display. Furthermore, a certain area of ​​transmittance is left between adjacent electrode groups in the column direction, resulting in a certain transmittance at the edge of the display panel. When applied to transparent displays, the display panel provided in this embodiment of the invention can achieve a borderless display effect with high edge transmittance. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 3 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 4 for Figure 3 Schematic diagram of the cross section at the position of the tangent line A-A'; Figure 5 This is a schematic diagram of a first shift register unit provided in an embodiment of the present invention; Figure 6 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 8 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of a second shift register unit provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of a second shift register unit provided in an embodiment of the present invention; Figure 11 A schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 12 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 13 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 14 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 15 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 16 for Figure 15 A schematic circuit diagram of an electrostatic discharge circuit; Figure 17 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 18This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 19 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 20 for Figure 18 A schematic diagram of a membrane structure at the position of the tangent line BB′; Figure 21 A partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 22 A partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 23 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 24 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0012] It should be understood that although the terms "first" and "second" may be used to describe XX in the embodiments of the present invention, these XX should not be limited to these terms. These terms are only used to distinguish XX from each other. For example, without departing from the scope of the embodiments of the present invention, the first XX may also be referred to as the second XX, and similarly, the second XX may also be referred to as the first XX.

[0013] This invention provides a display panel including a shift register located on one side of a substrate, multiple electrode groups, and multiple light-emitting devices. Each electrode group includes a first electrode and a second electrode, and the two electrodes of each light-emitting device are connected to the first and second electrodes, respectively. The shift register is used to drive multiple pixel rows across the entire panel line by line. This invention arranges the shift register unit to overlap with at least one electrode group, thereby reducing the bezel to achieve a borderless display and leaving a certain area of ​​high transmittance at the edge of the display panel. Furthermore, in some embodiments of the present invention, the lengths of the shift register units in the row and column directions are designed, or the number of pixel rows driven by the shift register units is designed, or the structure of the transistors in the shift register units is designed, or the driving signal lines connected to the shift register units are designed; in some embodiments of the present invention, the position of the electrostatic discharge circuit, the lengths of the electrostatic discharge circuit in the row and column directions, and the structure of the transistors in the electrostatic discharge circuit are also designed; in other embodiments of the present invention, the connection lines connecting the pixel circuits to the electrode groups near the edges are also designed; in other embodiments, the pixel circuit setting area is further set as a high-density arrangement area and a low-density arrangement area, and the lengths of the pixel circuits in the rows and columns in the two arrangement areas are further differentiated. The designs of the above embodiments can be applied to increase the area of ​​the transparent region in transparent displays, achieving a high-transparency display effect in the edge area. The above are the main technical ideas of the embodiments of the present invention. The technical solutions of the present invention will be illustrated below with specific embodiments.

[0014] The display panel provided in this embodiment of the invention includes a substrate, a driving layer, an electrode layer, and a light-emitting device located on one side of the substrate. The driving layer includes a shift register, pixel circuitry, and signal lines. The electrode layer is located on the side of the driving layer away from the substrate and includes multiple electrode groups, each including a first electrode and a second electrode. The light-emitting device is connected to a corresponding electrode group. Optionally, the light-emitting device includes a positive electrode and a negative electrode, with the positive electrode connected to the second electrode and the negative electrode connected to the first electrode. In this embodiment of the invention, the light-emitting device is a Micro-LED or a Mini-LED.

[0015] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 1As shown, the shift register 1 includes a plurality of cascaded shift register units 11; the plurality of shift register units 11 in the shift register 1 are arranged in a first direction y, and the display panel includes a first edge Y1 extending along the first direction y, with the pixel circuit 3 located on the side of the shift register 1 away from the first edge Y1. The electrode layer 2 includes a plurality of electrode groups 20, each electrode group 20 including a first electrode 21 and a second electrode 22. One electrode of the light-emitting device 4 is connected to the first electrode 21, and the other electrode is connected to the second electrode 22. One electrode group 20 can be used to connect at least one light-emitting device 4. Figure 1 The diagram illustrates an electrode group 20 connected to two light-emitting devices 4. The second electrode 22 is block-shaped, and multiple first electrodes 21 arranged in the second direction x are interconnected to form a common electrode 21c. The first electrodes 21 and second electrodes 22 in the electrode group 20 overlap in the first direction y. In other words, the portion of the common electrode 21c that overlaps with the second electrode 22 in the first direction y is the first electrode 21. The first direction y and the second direction x intersect each other. Optionally, the first direction y is the column direction, and the second direction x is the row direction. Figure 1 The diagram also shows the connecting line 5, which connects the second electrode 22 in the electrode group 20 located near the first edge Y1 of the display panel to the pixel circuit 3.

[0016] Figure 1 This is a partial top view of the display panel. Figure 1 The substrate is not shown in the image; it can be understood that the direction perpendicular to the plane containing the substrate is parallel to the top view direction. Figure 1 As can be seen, along the plane perpendicular to the substrate, the shift register unit 11 at least partially overlaps with at least one electrode group 20. Optionally, along the plane perpendicular to the substrate, the shift register unit 11 overlaps with the second electrode 22 of at least one electrode group 20, or the shift register unit 11 overlaps with the first electrode 21 and the second electrode 22 of at least one electrode group 20. Furthermore, since the electrode group 20 is connected to at least one light-emitting device 4, it can also be said that along the plane perpendicular to the substrate, the shift register unit 11 at least partially overlaps with at least one light-emitting device 4. That is, at least a portion of the shift register unit 11 is located in the display area.

[0017] In the display panel, the shift register unit 11 moves through the scan lines ( Figure 1 (Not shown) is connected to pixel circuit 3. A scan line is connected to a pixel circuit row extending in the first direction x. Multiple pixel circuit rows are driven line by line through shift register 1 to achieve the display of multiple pixel rows line by line. In related technologies, shift register unit 11 is usually located on the side of pixel circuit 3 near the edge of the display panel and is located in the bezel area.

[0018] The display panel provided in this embodiment of the invention has a shift register unit 11 that at least partially overlaps with at least one electrode group 20, such that at least a portion of the shift register unit 11 is located within the display area, thereby reducing the bezel and achieving a borderless display. Furthermore, a certain area of ​​transparent region (i.e., an area where the shift register unit 11 and other lines are not located) is left between adjacent electrode groups 20 in the column direction, resulting in a certain transmittance at the edge of the display panel. The display panel provided in this embodiment of the invention can be applied to transparent displays to achieve a borderless display effect with high edge transmittance.

[0019] In some implementations... Figure 2 This is another schematic diagram of a display panel provided in an embodiment of the present invention. To clearly illustrate the positional relationship between the shift register and the electrode group, Figure 2 The light-emitting device and pixel circuitry are not shown. For example... Figure 2 As shown, shift register 1 includes a first shift register 1-1, which includes a plurality of cascaded first shift register units 11-1. The plurality of first shift register units 11-1 are arranged along a first direction y. The length of the first shift register unit 11-1 in the first direction y is greater than its length in the second direction x.

[0020] Figure 2 The first shift register unit 11-1 is only simplified in the illustration. In reality, the first shift register unit 11-1 includes multiple transistors. When measuring the length of the first shift register unit 11-1 along the first direction y, the boundary is the edge of the outermost transistor in its overall structure. The same principle applies when measuring the length of the first shift register unit 11-1 along the second direction x. Alternatively, a rectangle is drawn at the location of the first shift register unit 11-1, with its long side extending along the first direction y and its short side extending along the second direction x. All transistors and capacitors of the first shift register unit 11-1 are located within this rectangle. The long side of this rectangle represents the length of the first shift register unit 11-1 along the first direction y, and the short side represents the length of the first shift register unit 11-1 along the second direction x. The above description can be used as a reference when referring to the second shift register unit and the length of the electrostatic discharge circuit along the first direction y / second direction x in the following embodiments.

[0021] Combination Figure 1 To understand this, if the shift register unit 11 overlaps with at least one electrode group 20, meaning the shift register unit 11 is at least partially located in the display area, then the pixel circuit 3 needs to be retracted (i.e., shifted away from the edge of the display panel) to make room for the shift register unit 11. This will also cause misalignment between the retracted pixel circuit 3 and the electrode group 20 connected to it. Figure 1It can be seen that the electrode group 20 and the pixel circuit 3 near the edge of the display panel are misaligned in the second direction x. Therefore, the second electrode 22 in the electrode group 20 needs to be connected to the pixel circuit 3 through the connecting line 5. The greater the distance that the pixel circuit 3 is offset from the edge in the second direction x, the more electrode groups 20 are misaligned with the pixel circuit 3, and the more connecting lines 5 need to be set, which will increase the area occupied by the connecting lines 5.

[0022] In this embodiment of the invention, the length of the first shift register unit 11-1 in the first direction y is greater than its length in the second direction x, thus the width occupied by the first shift register unit 11-1 in the second direction x is smaller. This reduces the number of pixel circuits 3 that are recessed in the second direction x, which helps to reduce the number of connecting lines 5, thereby saving wiring space. When applied to transparent displays, it can increase the area of ​​the transparent region and improve the transparent display effect.

[0023] Figure 2 The diagram also illustrates a first set of drive signal lines 71 connected to the first shift register 1-1. The first set of drive signal lines 71 includes at least a first start signal line, a clock signal line, and a power signal line. Figure 2 The position of the first group of drive signal lines 71 is shown only schematically.

[0024] In some embodiments, the display panel provided in this invention is a transparent display panel. For example... Figure 2 As shown, three electrode groups 20 arranged in the second direction x form a pixel area P. The display panel includes multiple transmittance areas TG, which are areas through which light can pass or whose light transmittance is greater than that of other areas. No metal lines are placed in the transmittance areas TG to ensure the transmittance of the area. At least a portion of the transmittance areas TG are located between adjacent pixel areas P in the first direction y, thus achieving transparent display. Applying the design of this embodiment of the invention to the transparent display, the shift register unit 11 is arranged to at least partially overlap with at least one electrode group 20, which can achieve a borderless display effect with high edge transmittance.

[0025] Optionally, the transmission zone may include transmission zones of different sizes or transmission zones of different shapes.

[0026] In some implementations... Figure 3 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 4 for Figure 3 A schematic diagram of the cross section at the position of the tangent line A-A'. Figure 3 The diagram illustrates the structure of a first shift register unit 11-1. For example... Figure 3As shown, the first shift register unit 11-1 includes a first output module 61 and a first switch module 62. The first output module 61 includes a first output transistor M1 and a second output transistor M2. The channel width direction of the transistors in the first output module 61 is parallel to the first direction y, and the channel length direction of the transistors in the first output module 61 is parallel to the second direction x. (Combined with...) Figure 4 The first output transistor M1 includes multiple first sub-transistors T0 connected in parallel. Each first sub-transistor T0 includes an active layer w, a gate g, a source s, and a drain d. Two parallel and adjacent first sub-transistors T0 share a common electrode, which is the drain of one first sub-transistor T0 and is reused as the source of the other. In one first sub-transistor T0, the region in the active layer w that overlaps with the gate g along the direction e perpendicular to the plane of the substrate O0 is the communication channel of the transistor. The direction from the source s to the drain d is the length direction of the channel, and the direction perpendicular to the length direction of the channel is the width direction of the channel.

[0027] In this embodiment of the invention, the channel width direction of the transistor in the first output module 61 is parallel to the first direction y, and the channel length direction of the transistor is parallel to the second direction x. This allows the transistor in the first output module 61 to have a large width-to-length ratio while occupying less space in the second direction x, so as to meet the output performance of the first output module 61.

[0028] like Figure 4 As shown, the display panel includes a driving layer 000 located on a substrate 00. The driving layer 000 includes at least a semiconductor layer 01, a first metal layer 02, and a second metal layer 03. The active layer w of the transistor is located on the semiconductor layer 01, the gate g is located on the first metal layer 02, and the source s and drain d are located on the second metal layer 03.

[0029] In some implementations, such as Figure 3 As shown, in the first shift register unit 11-1, along the first direction y, the first switch module 62 is located between the first output transistor M1 and the second output transistor M2. This arrangement allows the length of the first shift register unit 11-1 in the first direction y to be greater than its length in the second direction x, while maintaining the output performance of the first output module 61, resulting in a smaller length of the first shift register unit 11-1 in the second direction x. This implementation reduces the number of pixel circuits 3 recessed in the second direction x, which helps reduce the number of connecting lines 5, thereby saving wiring space. When applied to transparent displays, it can increase the area of ​​the transparent region, improving the transparent display effect.

[0030] Figure 5 This is a schematic diagram of a first shift register unit provided in an embodiment of the present invention, combined with... Figure 4 and Figure 5 The first shift register unit 11-1 includes a first switch module 62 comprising a first switch transistor M3, a second switch transistor M4, a third switch transistor M5, a fourth switch transistor M6, a fifth switch transistor M7, a sixth switch transistor M8, a seventh switch transistor M9, an eighth switch transistor M10, a ninth switch transistor M11, a tenth switch transistor M12, an eleventh switch transistor M13, a twelfth switch transistor M14, a thirteenth switch transistor M15, and a fourteenth switch transistor M16. The first shift register unit 11-1 also includes a first capacitor C1, a second capacitor C2, and a third capacitor C3. The input terminal IN of the first shift register unit 11-1 is connected to the output terminal OUT of its predecessor first shift register unit 11-1, and the input terminal IN of the first-stage first shift register unit 11-1 is connected to a first start signal. Driving the first shift register unit 11-1 also requires a first clock signal CK1, a second clock signal XCK1, a first power signal VGH, a second power signal VGL, and a first reset signal RST.

[0031] In this embodiment of the invention, the display panel further includes a plurality of sub-pixels located on one side of the substrate. For example... Figure 1 and Figure 2 As shown, the sub-pixel sp includes an electrode group 20, wherein multiple sub-pixels sp are arranged in a pixel row spH in the second direction x. Figure 1 The diagram also illustrates the light-emitting device 4 within the sub-pixel sp. The driving layer of the display panel includes multiple first scan lines, each connecting multiple sub-pixels sp within a pixel row spH. In other words, one first scan line connects multiple pixel circuits 3 corresponding to a pixel row spH.

[0032] Figure 6 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 6 The diagram illustrates the settings of shift register 1 at the edge of the display panel, as well as some wiring. Figure 6 The electrode assembly 20 and the light-emitting device 4 are not shown in the diagram. The display panel includes multiple first scan lines 73, one of which is connected to multiple pixel circuits 3 arranged in the second direction x. Figure 6 The pixel circuit 3 is shown in a simplified diagram only. Optional structures for the pixel circuit 3 will be described in the following related embodiments. For example... Figure 6 The diagram shows the position Q1 in the middle region. The line led out from the output terminal OUT of the first shift register unit 11-1 is pulled to the right and upward to connect to the two first scan lines 73. That is, one first shift register unit 11-1 drives two pixel rows spH. The first shift register unit 11-1 drives two pixels in a one-to-two manner.

[0033] Combination Figure 6 and Figure 2In other words, only one first shift register unit 11-1 is needed for two pixel rows spH. This reduces the space occupied by the first shift register 1-1. In this embodiment, the length of the first shift register unit 11-1 in the first direction y is greater than its length in the second direction x, thereby reducing the area occupied by the first shift register unit 11-1 in the second direction x, thus reducing the inward distance of the pixel circuit 3 and the number of connecting lines. Furthermore, the output terminal OUT of one first shift register unit 11-1 is connected to two first scan lines 73, which reduces the number of first shift register units 11-1 given a fixed number of pixel rows spH. Although the length of the first shift register unit 11-1 in the first direction y is relatively large, reducing the number of first shift register units 11-1 arranged in the first direction y also allows for a larger transmission area between adjacent first shift register units 11-1. When applied to transparent displays, this not only achieves borderless display but also a high-transparency display effect in the edge area.

[0034] Optionally, the lines leading out from the output terminal OUT of the first shift register unit 11-1 are pulled to the right and upward, that is, the lines leading out from the output terminal OUT of the first shift register unit 11-1 are led out along the second direction X and along the first direction Y. The lines leading out along the second direction X are arranged on the same layer as the first scan line 73, and the lines leading out along the first direction Y are arranged on the same layer as the signal lines in the first direction Y, such as the first clock signal CK1, the second clock signal XCK1, the first power signal VGH, the second power signal VGL, etc.

[0035] In some implementations, such as Figure 2 As shown, the length of the first shift register unit 11-1 in the second direction x is less than the length of the three consecutively arranged electrode groups 20 in the second direction x. This arrangement results in a smaller length occupied by the first shift register unit 11-1 in the second direction x. Correspondingly, the distance that the pixel circuit 3 needs to be recessed due to the overlap between the first shift register unit 11-1 and the electrode group 20 is also smaller. This avoids an excessive number of connecting lines 5, which helps to save wiring space in the edge area of ​​the display panel and allows the edge area to have a larger transparent area.

[0036] In some implementations, such as Figure 2As shown, the length of the first shift register unit 11-1 in the first direction y is L1, and L1 < L2 + L3; L2 is the length of the electrode group 20 in the first direction y, and L3 is the spacing distance between two adjacent electrode groups 20 in the first direction y. When setting the length of the first shift register unit 11-1 in the first direction y to be greater than its length in the second direction x, and the first shift register unit 11-1 overlapping with at least one electrode group 20, further setting L1 < L2 + L3 can save the wiring space at the edge position of the display panel, so that a relatively large area of the through area can still be left at the edge position of the display panel to achieve the display effect of high transparency at the edge of the transparent display.

[0037] In some embodiments, as Figure 2 shown, along the first direction y, the spacing between two adjacent first shift register units 11-1 is greater than the spacing between two adjacent electrode groups 20. In other words, along the first direction y, the spacing between two adjacent first shift register units 11-1 is greater than the spacing between two adjacent pixel rows sph. Here, the spacing between two adjacent first shift register units 11-1 refers to the interval distance between the edges of the two first shift register units 11-1, and the spacing between two adjacent pixel rows sph refers to the interval distance between the edges of the two pixel rows sph. In the embodiments of the present invention, the length of the first shift register unit 11-1 in the first direction y is set to be greater than its length in the second direction x, and two adjacent first shift register units 11-1 respectively overlap with at least one electrode group 20, and the spacing between two adjacent first shift register units 11-1 along the first direction y is limited, so that a through area TG can be left between two adjacent first shift register units 11-1 in the first direction y to achieve the display effect of high transparency at the edge of the transparent display.

[0038] In some embodiments, the first group of driving signal lines is connected to the first shift register 1-1. From Figure 2 the top view, it can be seen that each signal line in the first group of driving signal lines 71 extends along the first direction y; in the direction perpendicular to the plane of the substrate, at least one line in the first group of driving signal lines 71 overlaps with at least part of the electrode group 20. Such a setting can further reduce the border and achieve borderless display.

[0039] Figure 2 shows that the first electrode 21 and the second electrode 22 in an electrode group 20 are arranged along the first direction y, and at least one line in the first group of driving signal lines 71 overlaps with both the first electrode 21 and the second electrode 22 in the electrode group 20.

[0040] In other embodiments, Figure 7 is another schematic diagram of a display panel provided by an embodiment of the present invention, as Figure 7As shown, in an electrode group 20, the first electrode 21 and the second electrode 22 are arranged along a second direction x, that is, the first electrode 21 and the second electrode 22 in the electrode group 20 overlap in the second direction x. Along a direction perpendicular to the plane where the substrate is located, at least one line in the first group of driving signal lines 71 at least partially overlaps with the electrode group 20. Optionally, at least one line in the first group of driving signal lines 71 overlaps with the first electrode 21, or at least one line in the first group of driving signal lines 71 overlaps with the second electrode 22.

[0041] Figure 1 The diagram illustrates an electrode group 20 in which the first electrode 21 and the second electrode 22 are arranged along the first direction y. The electrode group 20 includes positions for binding two light-emitting devices 4, which is equivalent to setting redundant positions within the sub-pixel. For example, initially, a light-emitting device 4 is bound to an electrode group 20. If the light-emitting device 4 is defective and cannot emit light normally, another light-emitting device 4 is bound to the redundant position so that the sub-pixel can emit light normally. Thus, ultimately, two light-emitting devices 4 are bound to the electrode group 20, and the two light-emitting devices 4 are arranged along the second direction x.

[0042] Optionally, in an electrode group 20, the first electrode 21 and the second electrode 22 are arranged along the first direction y. The electrode group 20 includes positions for binding two light-emitting devices 4, which is equivalent to setting redundant positions in the sub-pixel. For example, firstly, a light-emitting device 4 is bound to an electrode group 20. If the light-emitting device 4 is defective and cannot emit light normally, then another light-emitting device 4 is bound to the redundant position so that the sub-pixel can emit light normally. At the same time, the original light-emitting device is removed. In this way, finally, only one light-emitting device 4 is bound to the electrode group 20.

[0043] Optionally, in an electrode group 20, the first electrode 21 and the second electrode 22 are arranged along the first direction y. An electrode group 20 includes positions for binding two light-emitting devices 4, which is equivalent to setting redundant positions in the sub-pixel. For example, a light-emitting device 4 is bound to the first electrode group 20. This light-emitting device is defect-free and can emit light normally. In this way, only one light-emitting device 4 is bound to the electrode group 20.

[0044] Figure 7 Another configuration for electrode assembly 20 is provided. This is understandable. Figure 7 In the embodiment, when redundant positions are provided on the electrode group 20, an electrode group 20 may also include a position where two light-emitting devices 4 are bound, and the two light-emitting devices 4 on the electrode group 20 are arranged along the first direction y.

[0045] Optionally, an electrode group 20 may also include a bonding position for a light-emitting device. For example, a light-emitting device 4 may be bonded to an electrode group 20. When the light-emitting device 4 is defective and cannot emit light normally, the light-emitting device 4 at that position is removed, and then a new light-emitting device 4 is bonded to the original position. In this way, there is finally only one light-emitting device 4 bonded to the electrode group 20.

[0046] In some implementations... Figure 8 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention, such as... Figure 8 As shown, multiple first electrodes 21 arranged in the second direction x are interconnected to form a common electrode 21c; among multiple electrode groups 20 arranged along the second direction x, the second electrode 22 is located on one side of the common electrode 21c in the first direction y; along the plane perpendicular to the substrate, the first shift register unit 11-1 overlaps with the second electrode 22 and the common electrode 21c; the edge of the first shift register unit 11-1 is flush with the edge of the common electrode 21c on the side away from the second electrode 22. This arrangement maximizes the overlap area of ​​the first shift register unit 11-1 and the overlapping electrode group 20, and minimizes the length occupied by the first shift register unit 11-1 and the overlapping electrode group 20 in the first direction y. This allows for a larger transparent area TG to be left in the edge region of the display panel, achieving a high-transparency edge display effect.

[0047] In some implementations, such as Figure 2 As shown, shift register 1 includes a second shift register 1-2, which includes a plurality of cascaded second shift register units 11-2 arranged along a first direction y. The length of the second shift register unit 11-2 in the first direction y is less than its length in the second direction x. Figure 2 The second shift register unit 11-2 is only simplified in the illustration. In reality, the second shift register unit 11-2 includes multiple transistors. When measuring the length of the second shift register unit 11-2 along the first direction y, the edge of the outermost transistor in its overall structure is used as the boundary. The same principle applies when measuring the length of the second shift register unit 11-2 along the second direction x. This embodiment allows the second shift register unit 11-2 to overlap with at least two electrode groups 20 arranged in the second direction x, and also allows the total length occupied by the second shift register unit 11-2 and the overlapping electrode groups 20 in the first direction y to be relatively small. When the second shift register unit 11-2 overlaps with its electrode groups 20 in a transparent display, it minimizes the encroachment on the width of the transparent area in the first direction y, thereby ensuring the area of ​​the transparent area and improving the transparent display effect.

[0048] Figure 2The diagram also illustrates a second set of drive signal lines 72 connected to the second shift register 1-2. The second set of drive signal lines 72 includes at least a second start signal line, a clock signal line, and a power signal line. Figure 2 The position of the second group of drive signal lines 72 is shown only schematically. Figure 2 In order to distinguish the first group of drive signal lines 71 and the second group of drive signal lines 72, different patterns are used for filling. In fact, the two can be made of the same layer and the same material.

[0049] In some implementations... Figure 9 This is a schematic diagram of a second shift register unit provided in an embodiment of the present invention, as shown below. Figure 9 As shown, the second shift register unit 11-2 includes a second output module 63 and a second switch module 64. The second output module 63 includes a third output transistor M17 and a fourth output transistor M18. (Combined with...) Figure 3 and Figure 4 The description of the transistors in the first output module 61, as well as the channel width and channel length directions of the transistors, in the embodiment helps to understand that the third output transistor M17 and the fourth output transistor M18 in the second output module 63 are multiple sub-transistors connected in parallel. The channel length direction of the transistors in the second output module 63 is parallel to the first direction y, and the channel width direction of the transistors in the second output module 63 is parallel to the second direction x. This arrangement allows the second shift register unit 11-2 to occupy less space in the first direction y while ensuring that the transistors in the second output module 63 have a large width-to-length ratio to meet the output performance requirements of the second output module 63.

[0050] In some implementations, such as Figure 9 As shown, the second switch module 64 and the second output module 63 in the second shift register unit 11-2 are arranged along the second direction x. This arrangement ensures that the length of the second shift register unit 11-2 in the first direction y is less than its length in the second direction x. When the second shift register unit 11-2 overlaps with at least one electrode group 20, the total length occupied by the overlapping second shift register unit 11-2 and the electrode group 20 in the first direction y is minimized. When applied to transparent displays, this increases the transmittance of the edge area, achieving a high-transmittance display effect in the edge area.

[0051] Figure 10 This is a schematic diagram of a second shift register unit provided in an embodiment of the present invention, combined with... Figure 9 and Figure 10The second shift register unit 11-2 includes a second output module 63 comprising a third output transistor M17 and a fourth output transistor M18, and a second switching module 64 comprising a fifteenth transistor M19, a sixteenth transistor M20, a seventeenth transistor M21, an eighteenth transistor M22, a nineteenth transistor M23, and a twentieth transistor M24. The second shift register unit 11-2 also includes a fourth capacitor C4 and a fifth capacitor C5. The input terminal IN of the second shift register unit 11-2 is connected to the output terminal OUT of its predecessor second shift register unit 11-2, and the input terminal IN of the first-stage second shift register unit 11-2 is connected to a second start signal. Driving the second shift register unit 11-2 also requires a third clock signal CK2, a fourth clock signal XCK2, a first power supply signal VGH, and a second power supply signal VGL. In this circuit, both the first power signal VGH and the second power signal VGL are constant voltage signals. The voltage value of the first power signal VGH is greater than the voltage value of the second power signal VGL. The first power signal VGH is a high-level signal and the second power signal VGL is a low-level signal.

[0052] In some embodiments, one terminal of the third output transistor M17 is connected to the second power supply signal VGL. When the third output transistor M17 is turned on, it provides a low-level signal from the second power supply signal VGL to the output terminal OUT of the second shift register unit 11-2 as an enable signal for driving the pixel circuit. Figure 7 As shown, the channel width-to-length ratio of the third output transistor M17 is set to be greater than that of the fourth output transistor M18. This setting ensures that the output performance of the second shift register unit 11-2 meets the driving requirements.

[0053] In some implementations, such as Figure 6 As shown, the display panel includes a first set of drive signal lines 71 and a second set of drive signal lines 72. A first shift register 1-1 is connected to the first set of drive signal lines 71, and a second shift register 1-2 is connected to the second set of drive signal lines 72. The first set of drive signal lines 71 includes a first set of clock signal lines 711, which includes a first clock signal line CK1 and a second clock signal line XCK1. The first set of drive signal lines 71 also includes a first start signal line STV1, a first power signal line VGH, a second power signal line VGL, and a first reset signal line RST. The signal lines and the signals they provide are marked with the same symbol; for example, the first clock signal line CK1 and the first clock signal CK1 are marked with the same symbol. The second set of drive signal lines 72 includes a second set of clock signal lines 722, which includes a third clock signal CK2 and a fourth clock signal XCK2. The second set of drive signal lines 72 also includes a second start signal line STV2, a first power signal line VGH, and a second power signal line VGL.

[0054] In this design, the line width of the second group of clock signal lines 722 is greater than that of the first group of clock signal lines 711. When the first shift register 1-1 provides the light emission control signal and the second shift register 1-2 provides the scan control signal, the output signal of the second shift register 1-2 has a high requirement for signal delay. Increasing the line width of the second group of clock signal lines 722 can reduce the voltage drop across the second group of clock signal lines 722, thus meeting the signal delay requirements of the output signal of the second shift register 1-2. Making the line width of the first group of clock signal lines 711 relatively narrow helps to save space in the second direction x, thereby reducing the inward distance of the pixel circuit and reducing the number of connecting lines.

[0055] In some implementations, the second set of clock signal lines 722 is configured with double-layer routing, that is, the third clock signal CK2 and the fourth clock signal XCK2 are each made with two metal layers. This can further reduce the voltage drop of the second set of clock signal lines 722 and further reduce the delay of the output signal of the second shift register 1-2.

[0056] In some implementations, such as Figure 6 As shown, the line widths of the first power signal line VGH and the second power signal line VGL in the second group of drive signal lines 72 are greater than the line widths of the first power signal line VGH and the second power signal line VGL in the first group of drive signal lines 71. This setting ensures that the output signal of the second shift register 1-2 meets the signal delay requirements.

[0057] In some implementations, by Figure 8 As shown in the schematic top view, along the plane perpendicular to the substrate, the second shift register unit 11-2 overlaps with the second electrode 22 and the common electrode 21c; the edge of the second shift register unit 11-2 is flush with the edge of the common electrode 21c on the side away from the second electrode 22. This arrangement maximizes the overlap area of ​​the second shift register unit 11-2 and the overlapping electrode group 20, while minimizing the length occupied by the second shift register unit 11-2 and the overlapping electrode group 20 in the first direction y. This allows for a larger transparent area TG between two adjacent pixel regions P, achieving a high-transparency edge display effect.

[0058] In some embodiments, the display panel further includes multiple second scan lines, combined with Figure 1 As you can see, the second scan line connects multiple sub-pixels sp in a pixel row spH. In other words, one second scan line connects multiple pixel circuits 3 corresponding to a pixel row spH. Figure 6 The second scan line 74 is shown in the diagram. Figure 6As can be seen, the output terminal OUT of the second shift register unit 11-2 is connected to a second scan line 74 that drives one pixel row by pulling a line to the right. That is to say, one second shift register unit 11-2 drives one pixel row. The second shift register unit 11-2 is driven in a one-to-one manner.

[0059] Figure 11 A pixel circuit schematic diagram provided for an embodiment of the present invention, such as... Figure 11 As shown, the pixel circuit includes a driving transistor Tm, a data writing transistor T1, a gate reset transistor T3, a threshold compensation transistor T4, an electrode reset transistor T2, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a storage capacitor Cst. The operation of the pixel circuit includes at least a reset stage, a writing stage, and a light-emitting stage. In the reset stage, the gate reset transistor T3 is turned on under the control of the first scan signal S1, writing the reset signal Ref to the gate of the driving transistor Tm; the electrode reset transistor T7 is turned on under the control of the first scan signal S1, writing the reset signal Ref to the electrode of the light-emitting device 4. In the writing stage, the data writing transistor T1 and the threshold compensation transistor T4 are turned on under the control of the second scan signal S2, writing the data voltage Data to the gate of the driving transistor Tm and performing self-testing and compensation on the threshold voltage of the driving transistor Tm. In the light-emitting stage, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on under the control of the light-emitting control signal Emit; the driving transistor Tm generates a driving current under the control of its gate voltage and provides the driving current to the light-emitting device 4. To drive the pixel circuit, a positive power supply voltage VDD and a negative power supply voltage VEE are also required.

[0060] Figure 11 The pixel circuit is shown for illustrative purposes only and is not intended to limit the invention. The pixel circuit in the display panel provided by the present invention can be any of the prior art.

[0061] Figure 12 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 12 The image illustrates the location of a pixel circuit. Combined with... Figure 11 To understand Figure 12 The connection relationships between the transistors in the circuit. Figure 12 The diagram also illustrates the first scan line 73, the second scan line 74, the third scan line 75, the reset signal line 76, and the data line 77. Specifically, the first scan line 73 provides the emission control signal Emit, the second scan line 74 provides the first scan signal S1, the third scan line 75 provides the second scan signal S2, the reset signal line 76 provides the reset signal Ref, and the data line 77 provides the data signal Data.

[0062] Combination Figure 6 The output terminal OUT of the first shift register 11-1 is connected to two first scan lines 73. The output terminal OUT of the second shift register 11-2 is connected to a second scan line 74 and a third scan line 75. The second scan line 74 and the third scan line 75 connected to the output terminal OUT of the second shift register 11-2 drive different pixel rows. That is, the second scan line 74 and the third scan line 75 driving the same pixel row are respectively provided with signals by two adjacent second shift register units 11-2. In this embodiment, the first shift register 1-1 provides the light emission control signal, and the second shift register 1-2 provides the scan control signal. The second shift register 1-2 has a greater impact on the operation of the pixel circuit than the first shift register 1-1. Therefore, the first shift register 1-1 can be driven in a one-to-two manner, and the second shift register 1-2 can be driven in a one-to-one manner. That is, one first shift register unit 11-1 drives two pixel rows, and one second shift register unit 11-2 drives one pixel row.

[0063] Figure 6 The diagram also illustrates the reset bus REF, with reset signal line 76 connected to the reset bus REF. Additionally... Figure 6 The diagram also illustrates the constant voltage line (BSM). A bottom light-shielding layer is also present in the display panel, connected to the BSM. This bottom light-shielding layer is located between the substrate and the active layers of each transistor. The bottom light-shielding layer blocks light incident from the substrate side onto the transistor channels, preventing light from affecting transistor performance.

[0064] In some implementations, such as Figure 2 , Figure 7 or Figure 8As shown, shift register 1 includes a first shift register 1-1 and a second shift register 1-2. The first shift register 1-1 includes multiple cascaded first shift register units 11-1, and the second shift register 1-2 includes multiple cascaded second shift register units 11-2. Optionally, the first shift register 1-1 provides the light emission control signal, and the second shift register 1-2 provides the scan control signal. The first shift register 1-1 can be configured to drive two pixels in a one-to-two manner, in which case only one first shift register unit 11-1 needs to be set for each two pixel rows. Space can then be left between two adjacent first shift register units 11-1 as a transmission zone to ensure the transmittance at the setting position of the first shift register 1-1. Furthermore, based on the one-to-two driving method, the length of the first shift register unit 11-1 in the first direction y can be set to be greater than its length in the second direction x, and the length of the first shift register unit 11-1 in the second direction x can be set to be less than the length of the second shift register unit 11-2 in the second direction x, and / or, the length of the first shift register unit 11-1 in the first direction y can be greater than the length of the second shift register unit 11-2 in the first direction y. This allows for an appropriate increase in the length of the first shift register unit 11-1 in the first direction y to reduce the length occupied by the first shift register unit 11-1 in the second direction x, thereby reducing the number of pixel circuits 3 recessed in the second direction x, which is beneficial for reducing the number of connecting lines.

[0065] In some implementations, such as Figure 6 As shown, the first shift register 1-1 is located on the side of the second shift register 1-2 furthest from the pixel circuit 3. That is, the first shift register 1-1 is closer to the edge of the display panel than the second shift register 1-2. When the first shift register 1-1 provides the light emission control signal and the second shift register 1-2 provides the scan control signal, the second shift register 1-2 is positioned closer to the pixel circuit 3, which helps reduce the delay of the output signal of the second shift register 1-2 and improves the uniformity of the display within the display panel.

[0066] In other implementations, Figure 13 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention, such as... Figure 13 As shown, shift register 1 includes a first shift register 1-1 and a second shift register 1-2. The first shift register 1-1 is located on the side of the second shift register 1-2 closer to the pixel circuit 3.

[0067] In some implementations... Figure 14 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention, such as... Figure 14 As shown, the display panel also includes an electrostatic discharge circuit 80. Figure 14As can be seen from the top view, the electrostatic discharge circuit 80 overlaps with at least one electrode group 20 along a direction perpendicular to the plane of the substrate. The electrode group 20 includes a first electrode 21 and a second electrode 22, wherein the electrostatic discharge circuit 80 overlaps with the first electrode 21 and / or the second electrode 22 of at least one electrode group 20. Since the electrode group 20 is used to bond the light-emitting device 4, that is, the electrostatic discharge circuit 80 overlaps with at least one light-emitting device 4. In conventional designs, the electrostatic discharge circuit is located in the bezel area of ​​the display panel. However, in this embodiment of the invention, the electrostatic discharge circuit 80 overlaps with at least one electrode group 20, meaning that at least a portion of the electrostatic discharge circuit 80 is located in the display area, and the electrostatic discharge circuit 80 overlaps with at least one electrode group. This further reduces the bezel of the display panel, and when applied to transparent displays, it does not encroach on the area of ​​the transmissive zone, achieving a high-transmittance display effect in the edge area. Figure 14 As shown, the length of the electrostatic discharge circuit 80 in the first direction y is less than its length in the second direction x. Because the electrostatic discharge circuit 80 has a shorter length in the first direction y, when it overlaps with at least one electrode group 20, the overall length occupied by the overlapping electrostatic discharge circuit 80 and electrode group 20 in the first direction y is smaller. This allows for a larger transparent area between adjacent pixel rows spH, meeting the requirements for transparent displays. Conversely, by having a longer length in the second direction x, the electrostatic discharge circuit 80 can overlap with two or more electrode groups 20 arranged in the second direction x, thus satisfying the performance and structural requirements of the electrostatic discharge circuit 80.

[0068] In some implementations... Figure 15 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 15 The location of the electrostatic discharge circuit is shown. Figure 16 for Figure 15 A schematic circuit diagram of an electrostatic discharge circuit. (Combined with...) Figure 15 and Figure 16 The electrostatic discharge circuit includes a first transistor T11 and a second transistor T12. The first terminal of the first transistor T11 is connected to the second power supply signal VGL, and the gate and second terminal of the first transistor T11 are connected to the first node N1. The gate and first terminal of the second transistor T12 are connected to the first power supply signal VGH, and the second terminal of the second transistor T12 is connected to the first node N1. Furthermore, the input terminal IN and the output terminal OUT of the electrostatic discharge circuit 80 are respectively connected to the first node N1.

[0069] like Figure 15 As shown, in the electrostatic discharge circuit 80, the first transistor T11 and the second transistor T12 are arranged in the second direction x. Combined with... Figure 3The description of the channel length and channel width directions of the transistors in the first output module 61 in the embodiment indicates that the first transistor T11 and the second transistor T12 each include multiple sub-transistors connected in parallel. As shown in Figure 15, the channel width direction of the first transistor T11 and the second transistor T12 is parallel to the second direction x, and the channel length direction of the first transistor T11 and the second transistor T12 is parallel to the first direction y. This configuration ensures that, while satisfying the condition that the length of the electrostatic discharge circuit 80 in the first direction y is less than its length in the second direction x, both the first transistor T11 and the second transistor T12 have relatively large aspect ratios, thus meeting the performance requirements of the electrostatic discharge circuit 80.

[0070] like Figure 14 As shown, a plurality of first electrodes 21 arranged in the second direction x are interconnected to form a common electrode 21c. In a plurality of electrode groups 20 arranged in the second direction x, a second electrode 22 is located on one side of the common electrode 21c in the first direction y. Along the plane perpendicular to the substrate, the electrostatic discharge circuit 80 overlaps with the second electrode 22 and the common electrode 21c.

[0071] In some embodiments, the edge of the electrostatic discharge circuit 80 is flush with the edge of the common electrode 21c on the side furthest from the second electrode 22. This arrangement maximizes the overlap area between the electrostatic discharge circuit 80 and the overlapping electrode group 20, while minimizing the length occupied by the electrostatic discharge circuit 80 and the overlapping electrode group 20 in the first direction y. This allows for a larger transparent area to be left in the peripheral region of the electrostatic discharge circuit 80, improving the transmittance of the transparent display.

[0072] In some implementations, such as Figure 14 As shown, the display panel includes sub-pixels sp, each sub-pixel sp includes an electrode group 20, and multiple sub-pixels sp are arranged in a pixel row spH in the second direction x. Figure 14 As can be seen from the top view, along the direction perpendicular to the plane where the substrate is located, the electrostatic discharge circuit 80 overlaps with the electrode group 20 in the first pixel row spH-1; the first pixel row spH-1 is the pixel row closest to the edge of the display panel. Figure 14 The schematic display panel includes a first edge Y1 extending along a first direction y and a second edge Y2 extending along a second direction x, and the first pixel row spH-1 is the pixel row closest to the second edge Y2.

[0073] Depend on Figure 14As can be seen, the cascaded shift register units in shift register 1 are arranged along the first direction y, and the shift register units in shift register 1 overlap with at least one electrode group 20. In this embodiment of the invention, shift register 1 and electrostatic discharge circuit 80 are placed in the display area, and the electrostatic discharge circuit 80 overlaps with the electrode group 20 in the first pixel row spH-1. This avoids affecting the cascaded arrangement of multiple shift register units in shift register 1, which makes wiring easier and saves wiring space.

[0074] In some embodiments, the electrostatic discharge circuit 80 includes a first electrostatic discharge circuit. For example... Figure 14 As shown, the first electrostatic discharge circuit 81 overlaps with at least one electrode group 20, and the first electrostatic discharge circuit 81 overlaps with the electrode group 20 in the first pixel row spH-1.

[0075] Optional, such as Figure 14 As shown, along the first direction Y, the electrostatic discharge circuit 80 overlaps with at least one electrode group 20 in the first row. The electrode group 20 includes a first electrode 21 and a second electrode 22, wherein the electrostatic discharge circuit 80 overlaps with the first electrode 21 and / or the second electrode 22 in the at least one electrode group 20 in the first row. Since the electrode group 20 is used to bond the light-emitting device 4, that is, the electrostatic discharge circuit 80 overlaps with at least one light-emitting device 4 in the first row.

[0076] Figure 17 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 17 The diagram illustrates the connection between shift register 1 and the scan line, the connection between shift register 1 and the electrostatic discharge circuit 80, and the signal lines driving shift register 1. Figure 17 Electrode group 20 is not shown in the diagram. The overlap relationship between shift register 1 and electrode group 20, and the overlap relationship between electrostatic discharge circuit 80 and electrode group 20 can be found by referring to... Figure 14 To understand. For example Figure 17 As shown, the electrostatic discharge circuit 80 includes a first electrostatic discharge circuit 81, and the structure of the first electrostatic discharge circuit 81 can be adopted as follows: Figure 15 The embodiment design includes a first shift register 1-1 connected to a first set of drive signal lines 71, which includes a first start signal line STV1. A first electrostatic discharge circuit 81 is connected to the first start signal line STV1. Specifically, the input terminal IN of the first electrostatic discharge circuit 81 is connected to the first start signal line STV1, and the output terminal OUT of the first electrostatic discharge circuit 81 is connected to the input terminal IN of the first-stage first shift register unit 11-1. The first electrostatic discharge circuit 81 protects the first start signal line STV1, preventing the accumulation of electrostatic charge from affecting the operating performance of the first shift register 1-1.

[0077] Depend on Figure 17 It can be seen that the length of the first electrostatic discharge circuit 81 in the first direction y is less than the length of the first shift register unit 11-1 in the first direction y, and / or the length of the first electrostatic discharge circuit 81 in the second direction x is greater than the length of the first shift register unit 11-1 in the second direction x.

[0078] By combining the design where the length of the first electrostatic discharge circuit 81 in the first direction y is less than its length in the second direction x, and the length of the first shift register unit 11-1 in the first direction y is greater than its length in the second direction x, the length occupied by the first electrostatic discharge circuit 81 and the overlapping electrode group 20 in the first direction y is less than the length occupied by the first shift register unit 11-1 and the overlapping electrode group 20 in the first direction y. This leaves a larger transparent area around the first electrostatic discharge circuit 81, which is beneficial for improving the transmittance of the edge area of ​​the transparent display. Since the first electrostatic discharge circuit 81 does not need to have multiple signal lines on the left and right sides like the first shift register unit 11-1, setting the length of the first electrostatic discharge circuit 81 in the second direction x to be greater than the length of the first shift register unit 11-1 in the second direction x not only reduces the length of the first electrostatic discharge circuit 81 in the first direction y, but also does not increase the pixel circuit indentation distance.

[0079] like Figure 17 As shown, the first set of drive signal lines 71 includes a first power supply line VGH and a second power supply line VGL; in the second direction x, the first power supply line VGH and the second power supply line VGL are located on both sides of the first shift register 1-1. This arrangement facilitates the connection between the first electrostatic discharge circuit 81 and the first power supply line VGH and the second power supply line VGL, reduces the winding of the power supply lines, and helps to increase the transmittance of the area surrounding the first electrostatic discharge circuit 81, thereby improving the display effect of the transparent display.

[0080] like Figure 17 As shown, along the first direction y, the first electrostatic discharge circuit 81 overlaps with the first shift register unit 11-1. When the first electrostatic discharge circuit 81 is used to protect the first start signal line STV1 that drives the first shift register 1-1, it facilitates the connection between the first start signal line STV1 and the first electrostatic discharge circuit 81, and also facilitates the connection between the output terminal of the first electrostatic discharge circuit 81 and the first-stage first shift register unit 11-1, thereby reducing circuit winding and saving wiring space.

[0081] In some implementations, the first shift register 1-1 includes N first shift register units 11-1. The nth-level first shift register unit 11-1 is connected to the 2n-th pixel row spH and the (2n-1)th pixel row spH respectively via two first scan lines 73, where N and n are both positive integers, and n ≤ N / 2. Figure 14 As shown, if the first electrostatic discharge circuit 81 overlaps with the electrode group 20 in the first pixel row spH, then the first shift register unit 11-1 of the first stage overlaps with the electrode group 20 in the second pixel row spH. Figure 17 The positions of the five pixel rows spH are shown, as well as a portion of the pixel circuits 3 within each pixel row spH. The first scan line 73 is connected to the pixel circuits 3 within the pixel row spH. The two-stage first shift register unit 11-1 is also illustrated. Combined with... Figure 17 As can be seen, the first-stage first shift register unit 11-1 is connected to the second pixel row spH and the first pixel row spH via two first scan lines 73, respectively. The second-stage first shift register unit 11-1 is connected to the fourth pixel row spH and the third pixel row spH via two first scan lines 73, respectively. That is, one first shift register unit 11-1 is connected to two first scan lines 73, and the first shift register 1-1 is driven in a one-to-one manner.

[0082] In some embodiments of the present invention, along a direction perpendicular to the plane of the substrate, the nth-level first shift register unit 11-1 overlaps with at least one electrode group 20 in the 2nth pixel row. Figure 14 and Figure 17 As can be seen, the first-level first shift register unit 11-1 overlaps with at least one electrode group 20 in the second pixel row spH, the second-level first shift register unit 11-1 overlaps with the electrode group 20 in the fourth pixel row spH, while the electrode group 20 in the third pixel row spH does not overlap with the first shift register unit 11-1. Based on setting the length of the first shift register unit 11-1 in the first direction y to be greater than its length in the second direction x to reduce the indentation distance of the pixel circuit 3, the design of this embodiment can also leave a larger transparent area between two adjacent first shift register units 11-1, achieving a high-transparency display effect at the transparent display edge.

[0083] In some implementations, the display panel is further provided with a dummy first shift register unit, which is connected to the last stage first shift register unit. The dummy first shift register unit can be located at the bottom edge of the display panel.

[0084] In some embodiments, the electrostatic discharge circuit 80 further includes a second electrostatic discharge circuit. Figure 14 and Figure 17The structure of the second electrostatic discharge circuit 82 shown in the diagram can be adopted Figure 15 Design of the embodiment. For example... Figure 14 As shown, the second electrostatic discharge circuit 82 overlaps with at least one electrode group 20, and the second electrostatic discharge circuit 82 overlaps with the electrode group 20 in the first pixel row spH-1. Figure 17 As shown, the second shift register 1-2 is connected to the second set of drive signal lines 72, which includes the second start signal line STV2. The second electrostatic discharge circuit 82 is connected to the second start signal line STV2. The input terminal IN of the second electrostatic discharge circuit 82 is connected to the second start signal line STV2, and the output terminal OUT of the second electrostatic discharge circuit 82 is connected to the input terminal IN of the first-stage second shift register unit 11-2. The second electrostatic discharge circuit 82 protects the second start signal line STV2, preventing the accumulation of electrostatic charge from affecting the operating performance of the second shift register 1-2.

[0085] like Figure 17 As shown, along the first direction y, the second electrostatic discharge circuit 82 overlaps with the second shift register unit 11-2. When the second electrostatic discharge circuit 82 is used to protect the second start signal line STV2 that drives the second shift register unit 11-2, it facilitates the connection between the second start signal line STV2 and the second electrostatic discharge circuit 82, and also facilitates the connection between the output terminal of the second electrostatic discharge circuit 82 and the input terminal of the first-stage second shift register unit 11-2, thereby reducing circuit winding and saving wiring space.

[0086] Combination Figure 14 The second electrostatic discharge circuit 82 overlaps with the electrode group 20 in the first pixel row spH-1, and the pixel rows spH are arranged along the first direction y. The first-stage second shift register unit 11-2 overlaps with the second pixel row spH. In the configuration of the second electrostatic discharge circuit 82, the second shift register 1-2 is driven in a one-to-one manner. With the second shift register unit 11-2 overlapping with at least one electrode group 20, the penultimate second-stage second shift register unit 11-2 overlaps with the electrode group 20 in the last pixel row spH. Therefore, the last-stage second shift register unit 11-2 can be located at the bottom edge of the display panel.

[0087] In some embodiments, the display panel also includes a dummy second shift register unit 11-2, which is connected to the last-stage second shift register unit 11-2. The dummy second shift register unit 11-2 can be located at the bottom edge of the display panel.

[0088] like Figure 17As shown, the second shift register 1-2 is connected to the second set of drive signal lines 72; the second set of drive signal lines 72 includes a third power line and a fourth power line. The third power line VGH and the first power line VGH in the first set of drive signal lines 71 provide the same signal, so they are represented by the same label. Similarly, the fourth power line VGL and the second power line VGL in the first set of drive signal lines 71 provide the same signal. In other words, the first set of drive signal lines 71 and the second set of drive signal lines 72 respectively include the first power line VGH and the second power line VGL. In the second direction x, the third power line VGH and the fourth power line VGL are located on opposite sides of the second shift register 1-2. This arrangement facilitates the connection between the second electrostatic discharge circuit 82 and the third power line VGH and the fourth power line VGL, reduces the winding of the power lines, and increases the transmittance of the area surrounding the second electrostatic discharge circuit 82, thus improving the display effect of the transparent display.

[0089] In some embodiments, the first shift register 1-1 includes N first shift register units 11-1, and the second shift register 1-2 includes 2 There are N second shift register units 11-2, where N is a positive integer. Along the second direction x, the m-th level first shift register unit 11-1 overlaps with the 2m-1-th level second shift register unit 11-2, where m is a positive integer and m≤N. Figure 17 The diagram illustrates two first shift register units 11-1 and four second shift register units 11-2. For example... Figure 17 Looking at the second direction x, the first-stage first shift register 11-1 overlaps with the first-stage second shift register 11-2, the second-stage first shift register 11-1 overlaps with the third-stage second shift register 11-2, and the second-stage second shift register 11-2 does not overlap with the first shift register 11-1. In this embodiment, the first shift register 1-1 is driven by a one-to-two approach, and the second shift register 1-2 is driven by a one-to-one approach. The first shift register 1-1 can provide a light emission control signal, and the second shift register 1-2 provides a scan control signal.

[0090] In some implementations... Figure 18 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 18 As shown, the display panel includes multiple pixel circuits 3, which are connected to an electrode assembly 20. Specifically, the pixel circuits 3 are connected to the second electrode 22 in the electrode assembly 20. The electrode assembly 20 is used to bond the light-emitting device 4. Figure 18The diagram illustrates an electrode group 20 including the bonding positions of two light-emitting devices 4. Pixel circuit 3 includes a first pixel circuit 3-1, and electrode group 20 includes a first electrode group 20-1. The first pixel circuit 3-1 is connected to the first electrode group 20-1 via a connecting line 5, and the first electrode group 20-1 and the first pixel circuit 3-1 connected to it are offset in the first direction y. Figure 18 The diagram illustrates a first edge Y1 extending along the first direction y. The first pixel circuit 3-1 is a pixel circuit 3 set inward relative to the first edge Y1. The first electrode group 20-1 and the first pixel circuit 3-1 connected to it are set off in the first direction y. A certain space is left in the display area where the light-emitting device 4 is located near the first edge Y1. This allows the shift register 1 to overlap with at least one electrode group 20, that is, at least a part of the shift register 1 is set in the display area to achieve borderless display.

[0091] In some implementations, the connecting line 5 and the first electrode 21 and the second electrode 22 are located on the same layer, so that the three are manufactured in the same process, which can simplify the process of the display panel and reduce the manufacturing cost.

[0092] like Figure 18 As shown, the connecting line 5 includes a line segment extending along the first direction y and a line segment extending along the second direction x. The two lines extending in opposite directions are connected to form a step, and the connecting line 5 is a stepped wiring pattern. This arrangement can reduce the overall area occupied by multiple connecting lines 5 when multiple connecting lines 5 are arranged, thereby saving wiring space.

[0093] like Figure 18 As shown, the display panel includes a first region Z1 and a second region Z2. The density of pixel circuits 3 in the first region Z1 is greater than that in the second region Z2. The first pixel circuit 3-1 is located in the first region Z1, and the shift register 1 is located on the side of the first pixel circuit 3-1 away from the second region Z2. The first pixel circuit 3-1 is recessed relative to the edge of the display panel, which allows space for the shift register 1 within the display area of ​​the display panel. Setting the density of pixel circuits 3 in the first region Z1 to be greater than that in the second region Z2 reduces the number of misaligned first pixel circuits 3-1, thereby reducing the number of connecting lines 5 and saving wiring space. When applied to transparent displays, this can improve the transmittance at the edge of the display panel.

[0094] like Figure 18As shown, the pixel circuit 3 also includes a second pixel circuit 3-2, which is located in the second region Z2. The length of the first pixel circuit 3-1 in the first direction y is greater than the length of the second pixel circuit 3-2 in the first direction y, and / or the length of the first pixel circuit 3-1 in the second direction x is less than the length of the second pixel circuit 3-2 in the second direction x. The first direction y is the column direction of the pixel circuits 3, and the second direction x is the row direction of the pixel circuits 3. This embodiment, by setting the length of the first pixel circuit 3-1 to be relatively larger in the first direction y and / or relatively smaller in the second direction x compared to the second pixel circuit 3-2, can reduce the number of misaligned first pixel circuits 3-1, thereby reducing the number of connecting lines 5 and saving wiring space. When applied to transparent displays, it can improve the transmittance at the edges of the display panel.

[0095] In some implementations... Figure 19 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 19 The image illustrates the location of a pixel circuit. Combined with... Figure 11 To understand Figure 19 The connection relationships between the transistors in the circuit. Figure 19 The diagram also illustrates the first scan line 73, the second scan line 74, the third scan line 75, the reset signal line 76, and the data line 77. Specifically, the first scan line 73 provides the emission control signal Emit, the second scan line 74 provides the first scan signal S1, the third scan line 75 provides the second scan signal S2, the reset signal line 76 provides the reset signal Ref, and the data line 77 provides the data signal Data.

[0096] Figure 19 This diagram illustrates an optional structure of the first pixel circuit 3-1, employing... Figure 19 The design of this embodiment enables the length of the first pixel circuit 3-1 in the first direction y to be greater than its length in the second direction x. In this embodiment, the second pixel circuit 3-2 can be... Figure 12 The pixel circuit structure provided in the embodiments is the same.

[0097] In some embodiments of the present invention, the pixel circuit 3 includes a first functional transistor, and the aspect ratio of the first functional transistor in the first pixel circuit 3-1 is equal to the aspect ratio of the first functional transistor in the second pixel circuit 3-2. The aspect ratio refers to the ratio of the channel width to the channel length of the transistor. The first functional transistor is a transistor with the same function in both the first pixel circuit 3-1 and the second pixel circuit 3-2, such as a driving transistor Tm. Setting the aspect ratio of the transistors with the same function in both pixel circuits ensures that the driving performance of the two pixel circuits is identical, improving the uniformity of the display within the display panel.

[0098] In some implementations... Figure 20 for Figure 18 A schematic diagram of a membrane structure at the location of the tangent line BB′. (See diagram below.) Figure 20 As shown, the display panel includes a substrate 00 and a driving layer 000 located on the substrate 00. The driving layer 000 includes a semiconductor layer 01, a first metal layer 02, a second metal layer 03, a third metal layer 04, and a fourth metal layer 06. The active layer of the transistors and some circuit traces are located on the semiconductor layer 01. The gate of the transistors and some signal lines, such as the first scan line 73, the second scan line 74, and the third scan line 75, are located on the first metal layer 02. The source and drain terminals of the transistors in the second metal layer 03 and some signal lines, such as the data line 77, are located on the second metal layer 03. One plate of the storage capacitor Cst and the reset signal line 76 are located on the third metal layer 04. The display panel also includes a first constant voltage signal line, which is used to provide the positive power supply voltage VDD required by the pixel circuit 3, and the first constant voltage signal line is located on the fourth metal layer 06. A bottom light-shielding layer 05 is also disposed between the semiconductor layer 01 and the substrate 00. Along the direction e perpendicular to the plane of the substrate 00, the bottom light-shielding layer 05 overlaps with the active layer of the transistor. The bottom light-shielding layer 05 is connected to... Figure 6 The constant voltage line BSM is illustrated in the diagram. Electrode layer 2 is located on the side of the driving layer 000 away from the substrate 00, and includes a first electrode 21 and a second electrode 22. One end of the light-emitting device 4 is connected to the first electrode 21, and the other end is connected to the second electrode 22. Additionally, insulating layers are disposed between the semiconductor layer and the metal layer, and between the two metal layers. Figure 20 The insulating layer is not shown.

[0099] The display panel includes a transparent region (TG) and a non-transparent region (FTG). The pixel circuit 3 and the light-emitting device 4 are located in the non-transparent region (FTG). A cutout is made on at least a portion of the insulating layer above the substrate 00, and the cutout area is the transparent region (TG).

[0100] The presence of perforations in the insulating layer creates a step difference between the transmissive zone (TG) and the non-transmissive zone (FTG), forming a recess in the display panel. The location of this recess is the transmissive zone (TG). The boundary of the transmissive zone (TG) can be defined at the location of this step difference in the display panel. Figure 20 As illustrated in the diagram, the boundary is defined by the bottom edge of the groove on the display panel, as shown in the TG area.

[0101] In some implementations... Figure 21 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 21As shown, the display panel includes a first edge Y1 extending along a first direction y, and connecting lines 5 include a first connecting line 51. The display panel includes multiple pixel areas P, each pixel area P including three electrode groups 20 arranged in a second direction x. The electrode group 20 in pixel area P that is furthest from the first edge Y1 is connected to the first connecting line 51. The first connecting line 51 includes a first line segment 511, which is located between two adjacent pixel areas P and is connected to the edge of the second electrode 22 extending along the first direction y. This arrangement saves the area occupied by multiple connecting lines 5 and the multiple electrode groups 20 they connect to in the first direction y, thereby reducing the area of ​​the non-transparent area and correspondingly increasing the area of ​​the transparent area, thus improving the transmittance of the transparent display.

[0102] Figure 21 The diagram illustrates a first light-emitting device 41, a second light-emitting device 42, and a third light-emitting device 43, each with a different color. A first sub-pixel sp1 includes the first light-emitting device 41, a second sub-pixel sp2 includes the second light-emitting device 42, and a third sub-pixel sp3 includes the third light-emitting device 43. Pixel region P includes the first sub-pixel sp1, the second sub-pixel sp2, and the third sub-pixel sp3 arranged in the second direction x. Optionally, if the first light-emitting device 41 is a red LED, the second light-emitting device 42 is a green LED, and the third light-emitting device 43 is a blue LED, then the second electrode 22 corresponding to the blue LED is connected to the first connecting line 51. Figure 21 The diagram illustrates a portion of the display area on the left side of the display panel. It can be understood that when a pixel circuit is also set in the display area on the right side of the display panel, the second electrode 22 corresponding to the red LED in pixel area P is connected to the first connecting line 51.

[0103] like Figure 21 As shown, the first connecting line 51 includes at least one first sub-segment 51a and at least one second sub-segment 51b. The first sub-segment 51a extends along a first direction y, and the second sub-segment 51b extends along a second direction x. The first sub-segment 51a and the second sub-segment 51b are connected to form a stepped shape; wherein, the second sub-segment 51b includes a first segment 511. This arrangement allows for a more compact arrangement of multiple connecting lines 5, reducing the overall area occupied by the multiple connecting lines 5, thereby saving wiring space.

[0104] like Figure 21As shown, electrode group 20 includes a first sub-electrode group 20a, a second sub-electrode group 20b, and a third sub-electrode group 20c. Specifically, first sub-pixel sp1 includes the first sub-electrode group 20a, second sub-pixel sp2 includes the second sub-electrode group 20b, and third sub-pixel sp3 includes the third sub-electrode group 20c. Within pixel region P, the first sub-electrode group 20a and the second sub-electrode group 20b are located on the side of the third sub-electrode group 20c closest to the first edge Y1; the third sub-electrode group 20c is connected to the first connecting line 51. The connecting line 51 also includes a second connecting line 52; the edge of the second electrode 22 in the second sub-electrode group 20b extending along the second direction x is connected to the second connecting line 52, and the edge of the second electrode 22 in the first sub-electrode group 20a extending along the second direction x is connected to the second connecting line 52. This embodiment rationally designs the connection position between the electrode group 20a and the connecting line 5 based on the position of the electrode group 20a within the pixel area P, and makes reasonable use of the space around the pixel area P, so that the space occupied by the multiple connecting lines 5 and the three electrode groups 20 within the pixel area P is small. This increases the area of ​​the transparent zone in the display panel, and improves the transparent display effect when applied to transparent displays.

[0105] like Figure 21 As shown, pixel region P includes a first pixel region P1 and a second pixel region P2, which are adjacent in the second direction x. The connection method between the three electrode groups 20 in the first pixel region P1 and the connecting line 5 is the same as that in the second pixel region P21. A pixel region P includes a first sub-electrode group 20a, a second sub-electrode group 20b, and a third sub-electrode group 20c arranged in the second direction x. The first sub-electrode group 20a is connected to the first light-emitting device 41, the second sub-electrode group 20b is connected to the second light-emitting device 42, and the third sub-electrode group 20c is connected to the third light-emitting device 43. In both the first pixel region P1 and the second pixel region P2, the first sub-electrode group 20a and the second sub-electrode group 20b are connected to the second connecting line 52, and the third sub-electrode group 20c is connected to the first connecting line 51. This arrangement makes the arrangement of multiple connecting lines 5 in the display panel more regular and saves wiring space.

[0106] In some implementations... Figure 22 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 22 As shown, the first connecting line 51 includes a first line segment 511, which is located between two adjacent pixel areas P. The first line segment 511 is flush with the edge of the second electrode 22 extending along the second direction x. This arrangement not only saves the area occupied by multiple connecting lines 5 and the multiple electrode groups 20 connected to them in the first direction y, but also reduces the etching precision of the connecting lines 5, lowers the manufacturing difficulty of the etching process, and reduces the manufacturing cost of the display panel.

[0107] In some implementations... Figure 23 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 23 The diagram only shows a portion of the structure in the semiconductor layer 01 and the fourth metal layer 06 near the first edge Y1 of the display panel, and indicates the locations of the shift register unit 1 and the electrostatic discharge circuit 80. Figure 23 As shown, the display panel also includes a light-shielding electrode 95, and the film layer containing the light-shielding electrode 95 is located between the shift register unit 1 and the electrode layer 2 (participating in...). Figure 20 (as shown in the diagram). The light-shielding electrode 95 includes a first light-shielding electrode 951 and a second light-shielding electrode 952. Figure 23 This is a top view of the display panel, and in Figure 23 The location of shift register 1 and electrostatic discharge circuit 80 is indicated by the label. Figure 23 As can be seen, along the plane perpendicular to the substrate, the first light-shielding electrode 951 overlaps with the shift register unit 1, and the second light-shielding electrode 952 overlaps with the electrostatic discharge circuit 80. The display panel also includes a first constant voltage signal line 90, and the pixel circuit 3 is connected to the first constant voltage signal line 90; the first constant voltage signal line 90 can provide the positive power supply voltage VDD required by the pixel circuit 3. The light-shielding electrode 95 is connected to the first constant voltage signal line 90, and the light-shielding electrode 95 and the first constant voltage signal line 90 are located in the fourth metal layer 06. This can be combined with... Figure 20 Let's understand the position of the fourth metal layer 06 in the display panel film structure. In this embodiment, a light-shielding electrode 95 is provided. This electrode blocks light incident on the transistor channel from the side of the transistor away from the substrate 00, thereby reducing transistor leakage current caused by light exposure and preventing impact on circuit performance. Furthermore, placing the light-shielding electrode 95 and the first constant voltage signal line 90 on the same layer simplifies the display panel manufacturing process and avoids large-area metal floating of the light-shielding electrode 95.

[0108] The fourth metal layer 06, where the light-shielding electrode 95 and the first constant voltage signal line 90 are located, may include at least one of aluminum, titanium, and molybdenum. For example, it may be a titanium / aluminum / titanium structure or a molybdenum / aluminum / molybdenum structure.

[0109] in addition, Figure 23 The diagram also illustrates the first auxiliary line 91 and the second auxiliary line 92 located in the fourth metal layer 06. Combined with... Figure 6In this embodiment, the first auxiliary line 91 can be overlapped and electrically connected to the third clock signal CK2, and the second auxiliary line 92 can be overlapped and electrically connected to the fourth clock signal XCK2. The first auxiliary line 91 and the third clock signal CK2 form a double-layer trace, and the second auxiliary line 92 and the fourth clock signal XCK2 form a double-layer trace. This can reduce the voltage drop on the second set of clock signal lines and reduce the delay of the output signal of the second shift register 1-2.

[0110] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 24 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 24 As shown, the display device includes the display panel 100 provided in any embodiment of the present invention. The display device provided in the embodiments of the present invention can be, for example, an electronic device with display function such as a mobile phone, tablet, computer, television, or smart wearable product. The display device provided in the embodiments of the present invention can also be a transparent display device, such as a transparent display window or a transparent splicing display device; it can also be a splicing display device, such as a large screen in a conference room or an exhibition hall.

[0111] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized by, include: Substrate; A driving layer is located on one side of the substrate, and the driving layer includes a shift register, which includes a plurality of cascaded shift register units; An electrode layer is located on one side of the substrate, and the electrode layer includes an electrode group, which includes a first electrode and a second electrode. The display panel includes a display area, and at least a portion of the shift register unit is located in the display area; The shift register includes a first shift register and a second shift register. The first shift register includes a plurality of cascaded first shift register units, which are arranged along a first direction. The second shift register includes a plurality of cascaded second shift register units, which are arranged along the first direction. The length of the first shift register unit in the first direction is greater than the length of the first shift register unit in the second direction; The length of the second shift register unit in the first direction is less than the length of the second shift register unit in the second direction; The first direction intersects with the second direction.

2. The display panel according to claim 1, characterized in that, The display panel includes sub-pixels, the sub-pixels are located on one side of the substrate, the sub-pixels include the electrode group, and a plurality of the sub-pixels are arranged in a pixel row in the second direction; The first shift register unit drives two of the pixel rows, and the second shift register unit drives one of the pixel rows.

3. The display panel according to claim 2, characterized in that, The driving layer includes a first scan line and a second scan line, wherein the first scan line connects a plurality of sub-pixels in a pixel row, and the second scan line connects a plurality of sub-pixels in a pixel row; The output of the first shift register unit is connected to the two first scan lines; The output of the second shift register unit is connected to one of the second scan lines.

4. The display panel according to claim 1, characterized in that, The first shift register comprises N first shift register units, and the second shift register comprises 2 N second shift register units, and N is a positive integer. Along the second direction, the first shift register unit of the m-th stage overlaps with the second shift register unit of the (2m-1)-th stage, where m is a positive integer and m≤N.

5. The display panel according to claim 1, characterized in that, The display panel includes sub-pixels, the sub-pixels are located on one side of the substrate, the sub-pixels include the electrode group, and a plurality of the sub-pixels are arranged in a pixel row in the second direction; The driving layer includes multiple first scan lines, which connect multiple sub-pixels in a pixel row; The output of the first shift register unit is connected to the two first scan lines.

6. The display panel according to claim 5, characterized in that, The plurality of the pixel rows are arranged along the first direction; The first shift register includes N first shift register units. The nth level first shift register unit is connected to the 2nth pixel row and the (2n-1)th pixel row through two first scan lines, respectively. N and n are both positive integers, and n ≤ N / 2.

7. The display panel according to claim 6, characterized in that, Along a direction perpendicular to the plane of the substrate, the first shift register unit of the nth stage overlaps with at least one of the electrode groups in the 2nth pixel row.

8. The display panel according to claim 1, characterized in that, The display panel must satisfy at least one of the following: The length of the first shift register unit in the second direction is less than the length of the second shift register unit in the second direction; or, The length of the first shift register unit in the first direction is greater than the length of the second shift register unit in the first direction.

9. The display panel according to claim 1, characterized in that, The display panel includes a first set of driving signal lines and a second set of driving signal lines. The first shift register is connected to the first set of driving signal lines, and the second shift register is connected to the second set of driving signal lines. The first group of drive signal lines includes a first group of clock signal lines, and the second group of drive signal lines includes a second group of clock signal lines; The line width of the second group of clock signal lines is greater than that of the first group of clock signal lines.

10. The display panel according to claim 1, characterized in that, The driving layer includes multiple pixel circuits, and the pixel circuits are connected to the electrode group; The first shift register is located on the side of the second shift register that is furthest from the pixel circuit.

11. The display panel according to claim 1, characterized in that, The first shift register unit includes a first output module; The channel width direction of the transistor in the first output module is parallel to the first direction; The channel length direction of the transistor in the first output module is parallel to the second direction.

12. The display panel according to claim 1, characterized in that, The first shift register unit includes a first switch module and a first output module, and the first output module includes a first output transistor and a second output transistor; Along the first direction, the first switching module is located between the first output transistor and the second output transistor.

13. The display panel according to claim 1, characterized in that, The length of the first shift register unit in the second direction is less than the length of the three consecutively arranged electrode groups in the second direction.

14. The display panel according to claim 1, characterized in that, The length of the first shift register unit in the first direction is L1; The length of the electrode assembly in the first direction is L2; The spacing between two adjacent electrode groups in the first direction is L3; L1 < L2 + L3.

15. The display panel according to claim 1, characterized in that, The driving layer includes a first set of driving signal lines, and the first shift register is connected to the first set of driving signal lines. The first set of driving signal lines includes a first power line and a second power line. In the second direction, the first power line and the second power line are located on both sides of the first shift register.

16. The display panel according to claim 1, characterized in that, The driving layer includes a first set of driving signal lines, and the first shift register is connected to the first set of driving signal lines. Along a direction perpendicular to the plane where the substrate is located, at least one of the first group of driving signal lines at least partially overlaps with the electrode group.

17. The display panel according to claim 1, characterized in that, A plurality of first electrodes arranged in the second direction are interconnected to form a common electrode, and in a plurality of electrode groups arranged along the second direction, the second electrode is located on one side of the common electrode in the first direction; Along the plane perpendicular to the substrate, the first shift register unit overlaps with the second electrode and the common electrode, and the edge of the first shift register unit is flush with the edge of the common electrode on the side away from the second electrode.

18. The display panel according to claim 1, characterized in that, Along the first direction, the spacing between two adjacent first shift register units is greater than the spacing between two adjacent electrode groups.

19. The display panel according to claim 1, characterized in that, The second shift register unit includes a second output module; The channel length direction of the transistor in the second output module is parallel to the first direction; The channel width direction of the transistor in the second output module is parallel to the second direction.

20. The display panel according to claim 1, characterized in that, The second shift register unit includes a second switch module and a second output module, which are arranged along the second direction.

21. The display panel according to claim 1, characterized in that, The display panel includes a second set of drive signal lines, the second shift register is connected to the second set of drive signal lines, and the second set of drive signal lines includes a third power line and a fourth power line. In the second direction, the third power line and the fourth power line are located on both sides of the second shift register.

22. The display panel according to claim 1, characterized in that, The plurality of first electrodes arranged in the second direction are interconnected to form a common electrode; in the plurality of electrode groups arranged along the second direction, the second electrode is located on one side of the common electrode in the first direction; Along the plane perpendicular to the substrate, the second shift register unit overlaps with the second electrode and the common electrode, and the edge of the second shift register unit is flush with the edge of the common electrode on the side away from the second electrode.

23. The display panel according to claim 1, characterized in that, The driving layer includes multiple pixel circuits, and the pixel circuits are connected to the electrode group; The pixel circuit includes a first pixel circuit, and the electrode group includes a first electrode group. The first electrode group and the first pixel circuit are staggered, and the first pixel circuit is connected to the first electrode group through a connecting line.

24. The display panel according to claim 23, characterized in that, The display panel includes a first region and a second region, wherein the density of the pixel circuits in the first region is greater than the density of the pixel circuits in the second region; The first pixel circuit is located in the first region, and the shift register is located on the side of the first pixel circuit away from the second region.

25. The display panel according to claim 24, characterized in that, The pixel circuit further includes a second pixel circuit, which is located in the second region; The display panel must satisfy at least one of the following: The length of the first pixel circuit in the first direction is greater than the length of the second pixel circuit in the first direction; or, The length of the first pixel circuit in the second direction is less than the length of the second pixel circuit in the second direction.

26. The display panel according to claim 25, characterized in that, The pixel circuit includes a first functional transistor; The aspect ratio of the first functional transistor in the first pixel circuit is the same as that of the first functional transistor in the second pixel circuit.

27. The display panel according to claim 23, characterized in that, The connecting line is located on the same layer as the first electrode and the second electrode.

28. The display panel according to claim 27, characterized in that, The display panel includes a first edge extending along a first direction, and the pixel circuit is located on the side of the shift register away from the first edge; The connecting line includes a first connecting line; The display panel includes multiple pixel areas, each pixel area including three electrode groups arranged in a second direction. The electrode group in the pixel area that is farthest from the first edge is connected to the first connecting line. The first direction and the second direction intersect. The first connecting line includes a first line segment located between two adjacent pixel areas, and the first line segment is connected to the edge of the second electrode extending along the first direction.

29. The display panel according to claim 28, characterized in that, The electrode group includes a first sub-electrode group, a second sub-electrode group, and a third sub-electrode group; Within the pixel area, the first sub-electrode group and the second sub-electrode group are located on the side of the third sub-electrode group closer to the first edge; the third sub-electrode group is connected to the first connecting line; The connecting line also includes a second connecting line; In the second sub-electrode group, the side of the second electrode extending along the second direction is connected to the second connecting line, and in the first sub-electrode group, the side of the second electrode extending along the second direction is connected to the second connecting line.

30. The display panel according to claim 27, characterized in that, The first connecting line includes at least one first sub-segment and at least one second sub-segment, the first sub-segment extends along the first direction, the second sub-segment extends along the second direction, and the first sub-segment and the second sub-segment are connected to form a stepped shape; The second sub-segment includes the first segment.

31. The display panel according to claim 27, characterized in that, The first line segment and the edge of the second electrode extending along the second direction are aligned.

32. The display panel according to claim 23, characterized in that, The pixel region includes a first pixel region and a second pixel region, and the first pixel region and the second pixel region are adjacent in the second direction; The connection method between the three electrode groups in the first pixel area and the connecting line is the same as the connection method between the three electrode groups in the second pixel area and the connecting line.

33. The display panel according to claim 1, characterized in that, The driving layer further includes a light-shielding electrode, which is located between the shift register unit and the electrode layer; the light-shielding electrode overlaps with the shift register unit along a direction perpendicular to the plane of the substrate. The display panel further includes a pixel circuit and a first constant voltage signal line, wherein the pixel circuit is connected to the first constant voltage signal line; The light-shielding electrode is connected to the first constant voltage signal line and is located on the same layer as the first constant voltage signal line.

34. The display panel according to claim 1, characterized in that, The multiple shift register units are arranged along a first direction, and the three electrode groups arranged in a second direction form a pixel region, wherein the first direction and the second direction intersect. The display panel includes a plurality of transparent areas, at least a portion of which are located between adjacent pixel areas in the first direction.

35. The display panel according to claim 1, characterized in that, Along a direction perpendicular to the plane of the substrate, the shift register unit at least partially overlaps with at least one of the electrode groups.

36. The display panel according to claim 1, characterized in that, The display panel includes a light-emitting device, which is connected to the electrode group; The light-emitting device includes a positive electrode and a negative electrode; The positive electrode of the light-emitting device is connected to the second electrode, and the negative electrode of the light-emitting element is connected to the first electrode.

37. The display panel according to claim 36, characterized in that, The light-emitting device is either Micro-LED or Mini-LED.

38. A display device comprising: Includes the display panel as described in any one of claims 1-37.

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