Self-repairing interconnection system for small-pitch light emitting diode display matrix

Abstract

This invention belongs to the field of small-pitch LED technology, specifically a self-healing interconnection system for small-pitch LED display matrices. The system includes an interconnection status acquisition interface, a topology fingerprint processor, a fault inference processor, and a remapping controller. By acquiring and receiving control nodes, pixel partition logical addresses, frame data fragmentation order, refresh latch phase, and verification feedback data, a reversible topology fingerprint is generated. Anomaly verification feedback is mapped to the reversible topology fingerprint to determine the fault impact cone and the minimum fault set. Then, based on the minimum fault set, a temporary logical bypass path is generated, simultaneously rewriting the address interpretation relationship and refresh phase compensation relationship of the pixel partitions. This system can distinguish between upstream transmission anomalies, address interpretation mismatches, and refresh phase drift, enabling interconnection fault location and logical bypass recovery to form a consistent control closed loop, reducing black blocks, misalignments, frame skipping, and repair switching interruptions in the small-pitch LED display matrix.

Description

Technical Field

[0001] This invention belongs to the field of small-pitch light-emitting diode technology, specifically a self-healing interconnection system for a small-pitch light-emitting diode display matrix. Background Technology

[0002] Small-pitch LED display matrices typically consist of multiple pixel partitions stitched together to form a complete display area. Each pixel partition corresponds to a certain number of LED pixels, and the receiving control node loads the display data according to row and column addresses, grayscale data, refresh timing, and latch phase. Current display control methods generally involve the transmitting control end splitting a frame of image data into multiple frame data fragments, which are then sent to each receiving control node according to a pre-configured link order. Each receiving control node, based on its stored address mapping, writes the received frame data fragments into the corresponding pixel partition buffer and completes grayscale loading and row and column scanning within a predetermined refresh cycle. Due to the small pixel pitch, large number of pixels, and high refresh rate of small-pitch LED display matrices, the frame data fragments must maintain strict order, address, and phase relationships during transmission. To ensure continuous video transmission, existing systems typically include data verification, frame sequence number checking, retransmission requests, receive buffers, and partition address tables in the communication link. They determine whether data transmission is abnormal by checking for failures, frame sequence errors, or receive timeouts, and handle such abnormalities by retransmission, partial black screens, holding the previous frame, or link switching.

[0003] In the most conventional technical solutions, the interconnection of the display matrix is ​​generally statically determined through configuration files or control card parameters. A fixed binding relationship is formed between pixel partitions and receiving control nodes, and frame data fragments are transmitted according to a fixed link order. When a receiving control node fails to receive complete frame data, or when downstream partitions experience consecutive verification failures, the control end determines the fault area based on the anomaly feedback location and attempts to retransmit the abnormal data. If retransmission still fails to restore the data, the control end marks the corresponding partition as an abnormal partition, maintaining the previous frame or outputting a black screen. Some solutions reserve backup transmission paths, switching to the backup path after a communication interruption is detected. However, the switching is mostly based on whether the link is connected or whether the node returns a response, lacking synchronous processing of the relationship between frame data fragment boundaries, partition logical addresses, and refresh latch phases. Because the address mapping within the display matrix is ​​coupled with the data transmission direction, an upstream link anomaly often manifests as multiple downstream partition anomalies, while an address interpretation error may manifest as local misalignment or miscolumn misalignment. Processing solely based on the anomaly feedback location makes it difficult to distinguish the true fault source from the affected area.

[0004] Existing self-diagnostic methods typically use the number of verification failures, reception timeouts, frame sequence differences, or partition display status as criteria for judgment, and then identify abnormal nodes through preset rules. While this approach can detect interconnect anomalies, its judgment process is insufficiently integrated with the topological relationship of the display matrix. The receive control nodes, pixel partition logical addresses, frame data fragmentation order, and refresh latch phase in an LED display matrix are not independent; any deviation in any of these components can lead to similar black blocks, misalignments, or flickering phenomena in the display area. If the system only judges the fault based on the location of the current abnormal partition, it may easily mistake downstream display anomalies for downstream node failures, or refresh phase drift for link interruptions. If link switching or address reconfiguration is performed directly without simultaneously processing the frame fragment number, entry address, and refresh phase compensation relationship, the repaired display data may be written to the wrong partition, or different partitions may refresh at different frame boundaries, causing continued screen tearing and flickering during the repair process. Therefore, existing solutions lack a reversible mapping relationship between anomaly identification, fault location, and recovery control, making it difficult to support stable interconnect self-repair.

[0005] The main technical problem with existing technologies is that when interconnection anomalies occur in small-pitch LED display matrices, the system lacks a reversible topological basis that can simultaneously characterize transmission order, pixel partition addresses, and refresh phases. This leads to a failure to form a consistent control loop between fault source localization and logical reconnection recovery. Since anomaly feedback often only reflects the display or communication results of a specific partition, the control end cannot determine from the anomaly results whether the fault lies in the upstream transmission edge, the receiving control node, the downstream address interpretation relationship, or the refresh latch phase relationship. Consequently, in cases where interconnection faults are propagating and cascading, conventional solutions tend to treat the affected downstream areas as fault sources or perform link switching without confirming the minimum fault set. Incorrect switching disrupts the original correspondence between frame data fragments and pixel partition logical addresses and lacks a unified version constraint for refresh phase compensation, ultimately causing local black block enlargement, display content misalignment, row and column refresh asynchrony, and repeated switching during the repair process. Summary of the Invention

[0006] The purpose of this invention is to provide a self-healing interconnection system for small-pitch LED display matrices, which can solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A self-healing interconnection system for a small-pitch LED display matrix, comprising an interconnection status acquisition interface, a topology fingerprint processor, a fault inference processor, and a remapping controller; The interconnection status acquisition interface acquires the receiving control node, pixel partition logical address, frame data fragmentation order, refresh latch phase and verification feedback data from the display matrix; The topology fingerprint processor generates a reversible topology fingerprint based on the receiving control node, the pixel partition logical address, the frame data fragmentation order, and the refresh latch phase. The fault reasoning processor maps the anomaly verification feedback data to the reversible topological fingerprint to determine the fault impact cone and the minimum fault set. The remapping controller generates a temporary logical bypass path based on the minimum fault set, and simultaneously rewrites the address interpretation relationship and refreshes the phase compensation relationship of the corresponding pixel partition.

[0008] Preferably, the topology fingerprint processor includes a link sequence encoding subprocessor and a display partition association subprocessor; The link sequence encoding subprocessor encodes the transmission sequence of frame data between each receiving control node into a directed edge sequence, and binds each directed edge sequence to a corresponding fragmentation boundary, check flag, and arrival time flag. The display partition association subprocessor establishes a bidirectional index between the pixel partition logical address and the row and column refresh phase, and writes the bidirectional index into the reversible topological fingerprint, so that any abnormal fragment can be reverse-located to its upstream transmission edge and downstream display partition.

[0009] Preferably, the reversible topological fingerprint further includes an address continuity constraint table and a phase adjacency constraint table; The address continuity constraint table records adjacent address segments, cross-node address boundaries, and fragment loading boundaries according to the logical row and column relationship of pixel partitions in the display matrix; The phase adjacency constraint table records the latching phase, grayscale loading order, and common frame boundary of adjacent pixel partitions; When generating the reversible topological fingerprint, the topological fingerprint processor binds the address continuity constraint table and the phase adjacency constraint table to the same frame sequence identifier.

[0010] Preferably, the fault reasoning processor includes a candidate failure enumeration subprocessor and an influence cone ratio pair subprocessor; The candidate failure enumeration subprocessor receives a set of candidate failures based on the reversible topological fingerprint enumeration, including control node failure, upstream link failure, downstream address interpretation mismatch, and refresh phase drift. The influence cone ratio pair subprocessor generates a corresponding downstream anomaly distribution for each candidate failure set, and performs topological matching between the downstream anomaly distribution and the actual anomaly verification feedback data, the display partition anomaly position, and the frame sequence anomaly position to filter the minimum fault set.

[0011] Preferably, the remapping controller includes a bypass path generation subprocessor and a consistency rewriting subprocessor; The bypass path generation subprocessor generates a temporary logical bypass path to bypass the faulty transmission edge based on the minimum fault set, the segmentation bearing relationship of the unaffected transmission path, and the address boundary of the target pixel partition. The consistency rewrite subprocessor writes the frame fragment number, receive control node entry address, pixel partition interpretation address, and refresh phase compensation value corresponding to the temporary logical bypass path into the same mapping version record.

[0012] Preferably, the topological fingerprint processor is further configured with a fingerprint differential update subprocessor; The fingerprint differential update subprocessor extracts transmission side sequence change items, pixel partition address change items, and refresh phase change items between consecutive frames, keeps the unchanged topological fingerprint segments as stable segments, and forms the change items into differential segments. When anomaly verification feedback data arrives, the fault reasoning processor prioritizes establishing a candidate fault search range in the differential segment and stable segments that have address continuity constraints or phase adjacency constraints with the differential segment.

[0013] Preferably, the influence cone ratio pair subprocessor includes a diffusion boundary truncation subprocessor; The diffusion boundary truncation subprocessor divides the downstream abnormal distribution generated by the candidate failure set into transmission diffusion segment, address mismatch segment and phase drift segment based on the cross-node address boundary, common frame boundary and check flag breakpoint in the reversible topological fingerprint. The fault reasoning processor establishes exclusive constraints between the transmission diffusion segment, the address mismatch segment, and the phase drift segment, and deletes candidate failure sets that are inconsistent with the actual abnormal boundaries based on the exclusive constraints.

[0014] Preferably, the consistency rewrite subprocessor is further configured with a dual-version mapping table; The dual-version mapping table includes a currently active mapping table and a mapping table to be submitted. The mapping table to be submitted stores the frame fragment number, the receiving control node entry address, the pixel partition interpretation address, and the refresh phase compensation value corresponding to the temporary logical bypass path. When the common frame boundary arrives, the remapping controller writes the mapping version records in the mapping table to be submitted into the currently effective mapping table in the topological order from the upstream receiving control node to the downstream pixel partition.

[0015] Preferably, the diffusion boundary truncation subprocessor further includes a reverse verification subprocessor; The reverse verification subprocessor starts from the end boundary of the actual abnormal display partition, traverses the directed edge sequence in the reversible topological fingerprint in reverse, reads the adjacent verification identifier breakpoints, cross-node address boundaries and common frame boundaries in sequence, and matches the boundary sequence obtained by the reverse traversal with the transmission diffusion segment, the address mismatch segment and the phase drift segment for overlap matching. The fault reasoning processor retains only the minimum set of faults that satisfy the overlap matching.

[0016] Preferably, the remapping controller is further configured with a bypass cancellation subprocessor; After the faulty transmission side is restored, the bypass cancellation subprocessor writes the probe frame fragment number, the receiving control node entry address and the refresh phase compensation value of the restored link into a new pending submission mapping table, and forms a parallel mapping record with the temporary logical bypass path in the currently effective mapping table. After the consistency rewriting subprocessor achieves frame order consistency for the parallel mapping record in the continuous common frame boundary kernel, it cancels the temporary logical bypass path in the topological reverse order from the downstream pixel partition to the upstream receiving control node.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The receiving control node, pixel partition logical address, frame data fragmentation order, refresh latch phase, and verification feedback data are acquired through the interconnection status acquisition interface. A reversible topological fingerprint is generated by the topological fingerprint processor, ensuring that the data transmission relationship, address interpretation relationship, and refresh phase relationship in the small-pitch LED display matrix are incorporated into the same topological description. After mapping the anomaly verification feedback data to the reversible topological fingerprint, the fault reasoning processor can determine the minimum fault set based on the fault influence cone, avoiding the need to determine the fault source solely based on the anomaly display area. The remapping controller then generates a temporary logical bypass path based on the minimum fault set and simultaneously rewrites the address interpretation relationship and refresh phase compensation relationship of the corresponding pixel partition, ensuring that the fault location result and the recovery control action maintain the same topological basis. This processing method allows anomaly feedback to be traced back along the reversible topological fingerprint to the corresponding transmission edge, receiving control node, or address interpretation relationship, and limits bypass recovery to the interconnection range directly related to the minimum fault set. Because the frame data fragment number, the receive control node entry address, the pixel partition interpretation address, and the refresh phase compensation value are written into the same mapping version record, the temporary logical bypass path can maintain the consistency of the data entry, display address, and refresh phase after generation, reducing display misalignment caused by erroneous switching. Compared to methods that only perform retransmission, black screen preservation, or simple link switching, this invention can separate the fault source from the affected area when interconnection anomalies have downstream diffusion characteristics, preventing local link anomalies from directly evolving into large-scale address chaos or refresh mismatch, thus forming a closed-loop processing solution for the main technical problems in the background art.

[0018] 2. The reversible topological fingerprint further introduces directed edge sequences, fragmentation boundaries, check flags, arrival time flags, address continuity constraint tables, and phase adjacency constraint tables, enabling the differentiation and processing of transmission changes, address changes, and phase changes between consecutive frames through differential fragments and stable fragments. During fault reasoning, the candidate failure enumeration subprocessor can form a candidate failure set around receiver control node failure, upstream link failure, downstream address interpretation mismatch, and refresh phase drift. The influence cone ratio pair subprocessor then performs topological matching between the downstream anomaly distribution and the actual anomaly check feedback data, the display partition anomaly location, and the frame sequence anomaly location, reducing confusion between different anomaly types. The diffusion boundary truncation subprocessor, based on cross-node address boundaries, common frame boundaries, and check flag breakpoints, divides the downstream anomaly distribution into transmission diffusion segments, address mismatch segments, and phase drift segments, and deletes candidate failure sets inconsistent with the actual anomaly boundaries through exclusive constraints. The reverse verification subprocessor traverses backward along the directed edge sequence from the end boundary of the anomaly display partition and matches the boundary sequence with different anomaly segments, ensuring that the determination of the minimum fault set has traceable data support. The dual-version mapping table separates the currently effective mapping table and the mapping table to be submitted. Mapping version records are submitted in topological order at common frame boundaries, and reverse-order revocation is completed through parallel mapping record and frame order consistency verification during reconnection cancellation. As a result, the interconnection self-healing process can maintain the continuity of mapping versions in the three stages of diagnosis, submission, and revocation, reducing frame skipping, tearing, repeated switching, and residual misalignment after recovery during the repair process. Attached Figure Description

[0019] Figure 1 A flowchart illustrating the overall control process of a self-healing interconnection system for a small-pitch LED display matrix; Figure 2 Here is a flowchart of the reversible topological fingerprint construction and differential update process; Figure 3 Flowchart for fault impact cone reasoning and determination of minimum fault set; Figure 4 This is a flowchart for temporary logic bypass submission and recovery / cancellation. Detailed Implementation

[0020] In one embodiment, refer to Appendix Figure 1The self-healing interconnection system of the small-pitch LED display matrix includes an interconnection status acquisition interface, a topology fingerprint processor, a fault inference processor, and a remapping controller. The interconnection status acquisition interface is connected to the status output terminal of the display control data stream and is used to acquire the receiving control node, pixel partition logical address, frame data fragmentation order, refresh latch phase, and verification feedback data in each frame or a preset continuous frame window. The receiving control node represents the logical control object in the display matrix that is responsible for receiving frame data and loading pixel partitions. The pixel partition logical address represents the correspondence between each display partition in the small-pitch LED display matrix in terms of row and column coordinates, partition number, and data loading range. The frame data fragmentation order represents the order in which the complete frame image is transmitted between multiple receiving control nodes after being split. The refresh latch phase represents the time position when the corresponding pixel partition completes grayscale data loading and enters the scan refresh. The verification feedback data includes frame sequence verification results, fragmentation verification results, arrival time anomaly identifiers, and address interpretation status returned by the receiving control node. The topology fingerprint processor generates a reversible topology fingerprint based on the above data, so that the transmission order, address interpretation relationship, and phase relationship are uniformly expressed in the same data structure. The fault reasoning processor maps the anomaly verification feedback data to the reversible topology fingerprint, and determines the fault impact cone and minimum fault set by matching the anomaly propagation direction with the display partition position. The remapping controller generates a temporary logical bypass path based on the minimum fault set, and synchronously rewrites the address interpretation relationship and refresh phase compensation relationship of the corresponding pixel partition, so that the recovery action after the interconnection anomaly occurs and the fault location result maintain the same topology basis. This embodiment can distinguish and process downstream display anomalies and upstream interconnection faults, reducing display misalignment and refresh mismatch caused by blind switching.

[0021] In this embodiment, the reversible topological fingerprint is implemented using a graph data structure. The nodes in the graph include a receive control node, pixel partition nodes, and frame fragment nodes. The directed edges in the graph include frame fragment transmission edges, address interpretation edges, and phase synchronization edges. The frame fragment transmission edges record the direction of frame data fragment transmission from the transmit control terminal to the receive control node and between receive control nodes. The address interpretation edges record the row and column address ranges used when frame fragments are written into the pixel partition buffer. The phase synchronization edges record the constraint relationships between adjacent pixel partitions on the common frame boundary and latched phase. The topological fingerprint processor binds the directed edges according to the frame order identifier within each sampling window, forming a reversible traceability mechanism. In this data structure, when a pixel partition reports a frame sequence abnormality or displays an abnormal partition location, the fault inference processor can reverse along the address interpretation edge from the abnormal partition node to find the corresponding frame fragment node, then reverse along the frame fragment transmission edge to find the upstream receiving control node, and determine whether the abnormality crosses the common frame boundary along the phase synchronization edge. The reversible topology fingerprint does not store the abnormality log separately, but records the location of the abnormality together with its upstream transmission source, downstream display range, and adjacent refresh phase under the same frame sequence identifier. This embodiment thus provides a traceable data foundation for the construction of the fault impact cone, avoiding the direct equation of a single partition's display abnormality with a single receiving control node failure.

[0022] In this embodiment, the fault influence cone is used to describe the abnormal propagation area that a candidate fault object may cause in the display matrix. The fault inference processor takes the abnormal verification feedback data as input and, based on the directed edge direction and boundary constraints in the reversible topological fingerprint, calculates the influence range of each candidate fault object on downstream pixel partitioning, downstream frame fragmentation, and adjacent refresh phases. The candidate fault objects include upstream transmission edge anomalies, receive control node anomalies, downstream address interpretation anomalies, and refresh latch phase anomalies. The fault inference processor does not directly adopt fixed fault rules, but compares the simulated abnormal area generated by the candidate fault object with the actual abnormal feedback area. If a candidate object can cover the actual abnormal area and does not cover a large number of non-abnormal areas, it is included in the candidate set. If there is an inclusion relationship between multiple candidate objects, the object that can interpret the abnormal feedback data and has a smaller coverage range is selected to form the minimum fault set. The construction of the fault influence cone can be expressed by the following formula: ; in, Indicates candidate fault objects The corresponding fault-affected cone, Represents the set of nodes in a reversible topological fingerprint. Represents the set of directed edges in an invertible topological fingerprint. This indicates the nodes affected by the candidate failure object. Indicates from candidate fault objects To the node There are reachable transmission edges, address interpretation edges, or phase synchronization edges. Indicates the frame epoch or phase position of the candidate fault object. Represents a node The epoch or phase position of the frame, the operator This indicates the reachability along directed edges. In the example, if the candidate fault object is the upstream transmission edge of the second receiving control node, and the second to fifth pixel partitions are reachable along the directed edges, and the phase positions of these partitions are all no earlier than the candidate fault object, then... The candidate fault object is retained if the actual abnormal feedback only covers the 2nd to 5th pixel partitions. If another candidate fault object covers the 2nd to 8th pixel partitions and the feedback of the 6th to 8th pixel partitions is normal, the other candidate fault object is excluded.

[0023] Preferably, after obtaining the minimum set of faults, the remapping controller does not change the physical connection relationship of the display matrix. Instead, it establishes a temporary logical bypass path in the control data layer. This temporary logical bypass path consists of a bypass entry point, a bypass transmission sequence, a target pixel partition address boundary, a frame fragment number rewriting relationship, and a refresh phase compensation relationship. The bypass entry point represents the entry point of the receiving control node on the unaffected transmission path that can receive data from the downstream partition of the fault. The bypass transmission sequence represents the logical order in which frame fragments are delivered to the target partition via the unaffected path. The target pixel partition address boundary represents the row and column range corresponding to the bypassed data when it is written into the display matrix. The frame fragment number rewriting relationship uses... The frame fragment number that originally pointed to the fault path is converted into a number that the wrapping path can recognize. The phase compensation relationship is refreshed to enable the target pixel partition to be latched within the common frame boundary. When the remapping controller writes the temporary logical wrapping path, it writes the frame fragment number, the entry address of the receiving control node, the pixel partition interpretation address and the refreshed phase compensation value into the same mapping version record. The mapping version record does not affect the current display output before it is submitted. It takes effect when the common frame boundary is reached and the fault inference result is consistent. This embodiment makes the logical wrapping, address interpretation and phase compensation change synchronously to avoid the situation where the frame data has been wrapped but the pixel address still uses the old interpretation relationship.

[0024] In one embodiment, refer to Appendix Figure 2The topology fingerprint processor includes a link sequence encoding subprocessor and a display partition association subprocessor. The link sequence encoding subprocessor reads the transmission sequence of each frame data fragment between the receiving control nodes, encodes the transmission relationship between the sending control terminal and the first receiving control node, the first receiving control node and the second receiving control node, and subsequent nodes into a directed edge sequence, and binds a fragment boundary, a check flag, and an arrival time flag to each directed edge sequence. The fragment boundary records the start and end positions of the frame data carried by the current directed edge, the check flag records the check result of the corresponding fragment on the current edge, and the arrival time flag records the check result of the corresponding fragment on the current edge. The interval identifier records the intra-frame timing position of the corresponding fragment arriving at the downstream node. The display partition association subprocessor establishes a bidirectional index between the pixel partition logical address and the row and column refresh phase. The bidirectional index includes a forward index from the pixel partition logical address to the refresh phase and a reverse index from the refresh phase abnormality to the pixel partition logical address. After the bidirectional index is written into the reversible topology fingerprint, any abnormal fragment can be reversed to its upstream transmission edge and downstream display partition. In this embodiment, by jointly encoding the link sequence and the display partition association relationship, the transmission source, display landing point and refresh timing of the abnormal fragment have a unified reference basis.

[0025] Specifically, the link sequence coding subprocessor uses frame order identifiers, transmission side identifiers, and fragmentation boundaries to form side codes, which can be represented as follows: ,in Indicates frame sequence identifier, Indicates the transmission edge identifier. Indicates the starting position of the fragment. Indicates the end position of the fragment. Indicates the verification identifier. Indicates the arrival time identifier, showing the partition-associated subprocessor used. This indicates the relationship between the pixel partition logical address and the refresh phase, where Indicates the partition row address. Indicates the partition column address. Indicates the data loading range within the partition. This indicates the latch phase identifier. A mapping is established between the edge code and the associated code through the fragment boundary and the data loading interval. When the fragment boundary... Coverage loading area At that time, the transmission edge corresponding to the fragment is associated with the pixel partition. If a check flag indicates an anomaly in the third transmission edge, the system can find the corresponding frame order and fragment boundary along the edge encoding, and then obtain the logical address of the affected pixel partition through loading interval mapping. If a pixel partition has a misaligned row, the system can... By reversely searching the edge code that carries its data, this embodiment enables link anomalies and display anomalies to be mutually verified in the same index system, improving the interpretability and verifiability of the fault location process.

[0026] In a preferred embodiment, the reversible topological fingerprint further includes an address continuity constraint table and a phase adjacency constraint table. The address continuity constraint table records adjacent address segments, cross-node address boundaries, and fragment loading boundaries according to the logical row and column relationships of pixel partitions in the display matrix. Adjacent address segments represent the continuous address relationship between adjacent pixel partitions in the same row or column. Cross-node address boundaries represent the boundary positions when adjacent pixel partitions are interpreted by different receiving control nodes. Fragment loading boundaries represent the boundary positions when fragments of the same frame are loaded into different pixel partitions. The phase adjacency constraint table records the latching phase, grayscale loading order, and... When generating a reversible topological fingerprint, the topological fingerprint processor binds the address continuity constraint table and the phase adjacency constraint table to the same frame sequence identifier, enabling address boundaries and phase boundaries within the same frame to participate in fault inference synchronously. If an actual abnormal region crosses the address continuity boundary but not the phase adjacency boundary, the fault inference processor preferentially classifies it into the address interpretation mismatch related candidate set. If an actual abnormal region is related to the common frame boundary and is accompanied by frame sequence abnormality, the fault inference processor classifies it into the phase drift related candidate set. This embodiment enables address continuity and phase adjacency to jointly define the abnormality type, reducing confusion between different fault manifestations.

[0027] In this embodiment, the address continuity constraint table and the phase adjacency constraint table can be organized as shown in the table below. Each record in the table is bound to the same frame sequence identifier and is written into a reversible topological fingerprint by the topological fingerprint processor. The fields in Table 1 below are not hardware structure limitations, but are used to describe the logical constraint relationships between data processing objects: Table 1. Constraint Table: Field Definitions and Logical Constraint Descriptions

[0028] In a preferred embodiment, refer to the appendix. Figure 3The fault reasoning processor includes a candidate failure enumeration subprocessor and an influence cone ratio subprocessor. The candidate failure enumeration subprocessor enumerates a set of candidate failures based on reversible topological fingerprints, including control node failures, upstream link failures, downstream address interpretation mismatches, and refresh phase drift. The enumeration of the candidate failure set is not a random traversal of all objects, but rather uses the frame sequence identifier, fragment boundary, and display partition position corresponding to the anomaly verification feedback data as entry points, limiting it to relevant directed edge sequences, relevant address contiguous segments, and relevant phase adjacency segments. The influence cone ratio subprocessor generates a corresponding downstream anomaly distribution for each candidate failure set. The downstream anomaly distribution includes the set of affected pixel partitions, the set of affected frame fragments, and the set of adjacent partitions that may experience phase drift. Then, the downstream anomaly distribution is topologically matched with the actual anomaly verification feedback data, the display partition anomaly location, and the frame order anomaly location. If the downstream anomaly distribution generated by a certain candidate failure set meets the matching conditions with the actual anomaly feedback in terms of partition location, transmission direction, and frame order relationship, then the candidate failure set is retained. If the candidate failure set requires the introduction of additional partitions unrelated to the actual anomaly to explain the fault, then it is deleted. This embodiment enables the minimum fault set to converge from multiple candidate failure objects.

[0029] In this embodiment, the candidate failure set of the subprocessor affecting the cone ratio can be sorted using a matching cost function. The matching cost function considers three types of factors simultaneously: missed interpretation anomalies, over-coverage of normal areas, and frame order inconsistencies. Specifically, it can be expressed as follows: ; in, Represents the candidate failure set The matching cost, Represents the actual set of abnormal nodes. Represents the candidate failure set The resulting fault affects the set of cone nodes. Indicates the actual abnormal node Frame sequence position, The node representing the predicted candidate failure set Frame sequence position, , , These represent the weights for missed anomalies, over-coverage of normal regions, and frame order inconsistencies, respectively. In the example, the actual set of anomalous nodes consists of 4 partitions. A certain candidate failure set covers 4 of these partitions but does not cover any normal partitions, and the sum of the frame order differences is 0. , , hour Another candidate failure set covers 4 anomalous partitions and additionally covers 2 normal partitions, with a frame order difference sum of 1. The fault reasoning processor selects the candidate fault set with the lowest matching cost and no more elements that can be deleted to form the minimum fault set.

[0030] Further, see attached document. Figure 4 The remapping controller includes a bypass path generation subprocessor and a consistency rewriting subprocessor. The bypass path generation subprocessor generates a temporary logical bypass path that bypasses the faulty transmission edge based on the minimum fault set, the fragmentation bearer relationship of the unaffected transmission path, and the address boundary of the target pixel partition. The unaffected transmission path is determined by the verification identifier, arrival time identifier, and common frame boundary in the reversible topology fingerprint. The fragmentation bearer relationship indicates the range of frame data fragments that the path can receive and forward. The address boundary of the target pixel partition is given by the adjacent address segment, cross-node address boundary, and fragment loading boundary in the address continuity constraint table. The consistency rewriting subprocessor writes the frame fragment number, receive control node entry address, pixel partition interpretation address, and refresh phase compensation value corresponding to the temporary logical bypass path into the same mapping version record. The mapping version record carries a version identifier and frame sequence identifier when written and is isolated from the currently effective mapping record. It is then committed when the common frame boundary arrives. In this embodiment, the bypass path generation and mapping relationship rewriting are executed together, so that data bypass and display interpretation relationship are effective together.

[0031] In this embodiment, the selection of temporary logic bypass paths can be based on path availability, segmented bearer matching degree, and phase compensation cost. The smaller the path cost, the more suitable the corresponding bypass path is as a temporary logic bypass path. Specifically, it can be expressed as follows: ; in, Indicates candidate bypass paths Path cost, This represents the cumulative value of the anomaly check flag or arrival time anomaly flag in the candidate bypass path. This indicates the amount of mismatch between the segment boundary carried by the candidate wrapping path and the target pixel partition address boundary. This represents the set of target pixel partitions corresponding to the candidate wrapping paths. Represents pixel partitions The latch phase in the original mapping, Represents pixel partitions Phase latching after compensation in candidate bypass paths , , These represent the weights of path availability, boundary matching degree, and phase compensation, respectively. In the example, candidate path A... , The phase difference accumulates to 1, in , , hour Candidate path B , When the phase difference accumulates to 1 The remapping controller selects candidate path A and writes its corresponding entry address, interpretation address and phase compensation value into the same mapping version record.

[0032] In one embodiment, the topology fingerprint processor is further configured with a fingerprint differential update subprocessor. The fingerprint differential update subprocessor extracts transmission edge sequence change items, pixel partition address change items, and refresh phase change items between consecutive frames, keeps the unchanged topology fingerprint segments as stable segments, and forms differential segments from the change items. The transmission edge sequence change items include changes in directed edge order, fragment boundary changes, and check flag state changes. The pixel partition address change items include changes in address interpretation boundaries and fragment loading boundaries. The refresh phase change items include changes in latch phase and common frame boundaries. When abnormal check feedback data enters, the fault inference processor prioritizes establishing a candidate fault search range in the differential segments and stable segments that have address continuity constraints or phase adjacency constraints with the differential segments. When the differential segment is not adjacent to the abnormal feedback location and there is no transmission reachability relationship, the fault inference processor expands the search range to the upstream directed edge sequence of the actual abnormal partition. This embodiment reduces redundant graph construction through differential updates and prioritizes newly changed transmission edges, address boundaries, and phase boundaries into the fault inference range.

[0033] Specifically, the fingerprint differential update subprocessor performs a field-level comparison between the topological fingerprint of the previous frame and the topological fingerprint of the current frame. If the transmission edge identifier, fragmentation boundary, address interpretation boundary, and latch phase of a certain directed edge in the two frame sequences are the same, the corresponding fingerprint fragment is marked as a stable fragment. If any field changes, the corresponding fingerprint fragment is marked as a differential fragment. The differential fragment saves the fields before the change, the fields after the change, and the associated boundaries. The stable fragment saves the original reference relationship and updates the frame sequence identifier. When the fault inference processor searches the candidate fault set, it starts from the differential fragment and extends along the address continuity constraint table to the adjacent address segment, along the phase adjacency constraint table to the adjacent latch phase, and along the transmission directed edge to the downstream partition. The extended fragments together form the candidate fault search range. If the abnormal feedback data falls within the search range, a fault influence cone is constructed within that range. If the abnormal feedback data falls outside the search range, the partition where the abnormal feedback is located is traced back to the upstream transmission edge before a new search range is established. This embodiment enables topological inference to take into account both continuous frame changes and the actual location of the abnormality, avoiding misjudgments caused by focusing only on static topology and ignoring inter-frame changes.

[0034] In a preferred embodiment, the influencing cone ratio subprocessor includes a diffusion boundary truncation subprocessor. Based on the cross-node address boundaries, common frame boundaries, and check flag breakpoints in the reversible topological fingerprint, the diffusion boundary truncation subprocessor divides the downstream anomaly distribution generated by the candidate failure set into a transmission diffusion segment, an address mismatch segment, and a phase drift segment. The transmission diffusion segment represents the region continuously affected by the anomaly along the frame fragmentation transmission direction; the address mismatch segment represents the region where the anomaly shifts at the cross-node address boundary or fragmentation loading boundary; and the phase drift segment represents the region where the anomaly is related to the common frame boundary or latched phase shift. The fault reasoning processor establishes exclusive constraints among the transmission diffusion segment, the address mismatch segment, and the phase drift segment. These exclusive constraints include that the transmission diffusion segment must not cross a check flag breakpoint where no check anomaly has occurred; the address mismatch segment must not cross a cross-node address boundary where no address interpretation change has occurred; and the phase drift segment must be associated with a common frame boundary or phase adjacency constraint. If the anomaly distribution of the candidate failure set violates the exclusive constraints, it is deleted from the candidate set. This embodiment partitions different anomaly sources through diffusion boundary truncation, making the determination process of the minimum fault set more stable.

[0035] In this embodiment, the diffusion boundary truncation can be performed according to the data logic in Table 2 below. Each truncation basis in Table 2 is derived from the existing constraint fields in the reversible topological fingerprint and cross-validated with the downstream anomaly distribution generated by the candidate failure set: Table 2. Rules for Verifying Diffusion Boundary Truncation

[0036] Furthermore, the diffusion boundary truncation subprocessor also includes a reverse verification subprocessor. Starting from the end boundary of the actual abnormal display partition, the reverse verification subprocessor traverses backward along the directed edge sequence in the reversible topological fingerprint, sequentially reading adjacent verification identifier breakpoints, cross-node address boundaries, and common frame boundaries. It then performs overlap matching between the boundary sequence obtained from the reverse traversal and the transmission diffusion segment, address mismatch segment, and phase drift segment. The end boundary represents the last abnormal node in the abnormal region in the transmission direction, address direction, or phase direction. During the reverse traversal, if a verification identifier breakpoint is read and there is abnormal verification feedback upstream of the breakpoint, the reverse verification subprocessor marks the boundary as the transmission diffusion start point. If a cross-node address boundary is read and the abnormal region exhibits address offset on both sides of the boundary, it is marked as the address mismatch start point. If a common frame boundary is read and the abnormal region shows frame sequence inconsistency, it is marked as the phase drift start point. The fault inference processor only retains the minimum set of faults that satisfy the overlap matching. This embodiment enables the abnormal end boundary to reverse constrain the fault start point, reducing misjudgments caused by the downstream diffusion of fault influence cones.

[0037] In this embodiment, the reverse verification subprocessor uses boundary sequence overlap to calculate the credibility of the candidate failure set. Boundary sequence overlap can be expressed as: ; in, Represents the actual boundary sequence With candidate boundary sequence The degree of overlap, This represents the set of boundary markers obtained by reverse traversal of the actual anomaly region. Let represent the set of boundary markers predicted from the candidate failure set. In the example, the actual boundary sequence contains three types of boundaries: checkpoint breakpoints, cross-node address boundaries, and common frame boundaries. Candidate boundary sequence A contains checkpoint breakpoints and cross-node address boundaries. Their intersection is two boundaries, and their union is three boundaries. Candidate boundary sequence B contains only common frame boundaries, has an intersection of one boundary, and a union of three boundaries. Under the condition of equal matching cost, the fault reasoning processor retains the candidate failure set with high overlap and forms the final minimum failure set by combining the minimum coverage principle.

[0038] In one embodiment, the consistency rewrite subprocessor is further configured with a dual-version mapping table, which includes a currently active mapping table and a pending-commit mapping table. The currently active mapping table stores the frame fragment number, receive control node entry address, pixel partition interpretation address, and refresh phase compensation value of the frame driving the display output. The pending-commit mapping table stores the frame fragment number, receive control node entry address, pixel partition interpretation address, and refresh phase compensation value corresponding to the temporary logical bypass path. When the common frame boundary arrives, the remapping controller writes the mapping version record in the pending-commit mapping table into the currently active mapping table in the topological order from the upstream receive control node to the downstream pixel partition. Before the common frame boundary arrives, the pending-commit mapping table only accepts consistency checks and pre-write checks and does not directly drive the display output. After the common frame boundary arrives, if the frame sequence identifier, fragment boundary, and phase compensation relationship in the pending-commit mapping table are consistent with the minimum fault set, then the update is committed. If any field is inconsistent with the fault inference result, the currently active mapping table remains unchanged. This embodiment avoids incomplete bypass mapping from entering the display output link through dual-version isolation.

[0039] Specifically, the submission process of the dual-version mapping table is executed in topological order. The entry address of the upstream receiving control node is replaced first, followed by the interpretation address of the downstream pixel partition. The refreshed phase compensation value is written together with the interpretation address within the corresponding common frame boundary. During the submission, the consistency rewrite subprocessor compares the frame sequence identifiers in the currently effective mapping table and the mapping table to be submitted. If the frame sequence identifier of the mapping table to be submitted is later than that of the currently effective mapping table and the corresponding frame data fragment has passed the verification, the submission is allowed. If the frame sequence identifier of the mapping table to be submitted is earlier than that of the currently effective mapping table or does not correspond to the current frame data fragment, the submission is rejected. After the submission is completed, the remapping controller updates the version identifier of the currently effective mapping table to the version identifier of the mapping table to be submitted and retains the previous stable version as the basis for rollback. If the verification feedback after submission shows that there is a new transmission anomaly in the bypass path, the remapping controller restores the entry address, interpretation address and phase compensation value according to the previous stable version. In this embodiment, the activation, verification and restoration of the temporary logical bypass path are all completed at the mapping version layer, reducing repeated switching during the repair process.

[0040] Furthermore, the remapping controller is also configured with a bypass cancellation subprocessor. After the faulty transmission side is restored, the bypass cancellation subprocessor writes the probe frame fragment number, the receiving control node entry address, and the refresh phase compensation value of the restored link into a new pending submission mapping table, and forms a parallel mapping record with the temporary logical bypass path in the currently effective mapping table. The parallel mapping record is used to simultaneously save the temporary logical bypass path and the restored link path under the same common frame boundary constraint, so that the restored link can be verified by probe frames before it officially takes over the display output. The probe frame fragment number is distinguishable from the current display frame fragment number. The receiving control node entry address points to the restored link entry. The refresh phase compensation value is regenerated according to the arrival time identifier of the restored link. After the consistency rewrite subprocessor confirms the frame order consistency of the parallel mapping record in the continuous common frame boundary kernel, it cancels the temporary logical bypass path in the reverse topology order from the downstream pixel partition to the upstream receiving control node. In this embodiment, the cancellation process after the faulty transmission side is restored does not directly cover the currently effective bypass path, avoiding new display interruptions caused when the restored link is not yet stable.

[0041] In this embodiment, the bypass revocation process includes probe frame writing, parallel mapping verification, reverse revocation, and stable version update. In the probe frame writing stage, the bypass revocation subprocessor writes the probe frame fragment number of the restored link into the pending submission mapping table, but does not write the probe frame into the current display output area. In the parallel mapping verification stage, the consistency rewriting subprocessor compares the frame sequence identifier, entry address, and phase compensation value of the temporary logical bypass path and the restored link path under the same common frame boundary. If the frame sequence identifier of the restored link path is continuous and the fragment boundary matches the target pixel partition address boundary, then reverse revocation is allowed. In the reverse revocation stage, the temporary logical bypass path is revoked in reverse order according to the topology from the downstream pixel partition to the upstream receiving control node, so that the downstream partition first restores the original address interpretation relationship, and the upstream entry address then restores the original transmission relationship. In the stable version update stage, the restored link path is written into the currently effective mapping table and the temporary logical bypass path record is cleared. In this embodiment, through parallel mapping and reverse revocation, the repaired link regression process and the self-repair submission process are made to correspond, reducing the occurrence of old mapping residues during the recovery period.

[0042] In one comprehensive embodiment, during normal operation, the small-pitch LED display matrix continuously acquires and receives control node data, pixel partition logical addresses, frame data fragmentation order, refresh latch phase, and verification feedback data via the interconnection status acquisition interface. The topology fingerprint processor uses the link sequence encoding subprocessor to generate a directed edge sequence containing fragmentation boundaries, verification identifiers, and arrival time identifiers. It uses the display partition association subprocessor to establish a bidirectional index between pixel partition logical addresses and row / column refresh phases, and binds the address continuity constraint table and phase adjacency constraint table to the same frame sequence identifier. If changes occur in the transmission edge sequence, pixel partition address, or refresh phase between consecutive frames, the fingerprint differential update subprocessor extracts differential fragments and retains stable fragments. When the verification feedback data is abnormal, the fault inference processor enumerates the candidate failure set within the differential segment and its associated stable segment. The influence cone ratio subprocessor generates the downstream abnormal distribution and calculates the matching cost. The diffusion boundary truncation subprocessor divides the abnormal distribution into different abnormal segments based on the verification identifier breakpoint, cross-node address boundary, and common frame boundary. The reverse verification subprocessor traverses backward from the end boundary of the abnormal region and checks the boundary sequence to finally obtain the minimum fault set. The remapping controller generates a temporary logical bypass path based on the minimum fault set, and the consistency rewriting subprocessor writes the entry address, interpretation address, and phase compensation value into the pending mapping table. This embodiment covers the complete processing link from acquisition, modeling, inference to remapping.

[0043] In this embodiment, when an intermittent anomaly occurs in the upstream transmission edge of the third receiving control node, the interconnection status acquisition interface will obtain several pixel partition verification anomalies after the third receiving control node, while the partitions before the third receiving control node remain in normal verification. The topology fingerprint processor maps the anomaly verification feedback data to a reversible topology fingerprint containing the upstream transmission edge of the third receiving control node. The fault inference processor enumerates candidate failure sets such as upstream link failure, receiving control node failure, downstream address interpretation mismatch, and refresh phase drift. The influence cone comparison subprocessor finds that the fault influence cone caused by the upstream link failure matches the actual abnormal area in transmission direction and frame sequence position. The diffusion boundary truncation subprocessor confirms that the abnormal boundary is located near the verification mark breakpoint and does not cross the unchanged address boundary. The reverse verification subprocessor reads the same verification mark breakpoint after traversing backward from the end of the abnormality. Based on this, the fault inference processor determines the upstream transmission edge of the third receiving control node as the minimum fault set. The remapping controller selects an unaffected transmission path to generate a temporary logical bypass path and writes the mapping table to be submitted into the currently effective mapping table in topological order at the common frame boundary. This embodiment can avoid misjudging multiple downstream abnormal pixel partitions as multiple independent fault objects.

[0044] In another application embodiment, when an interpretation offset occurs at a cross-node address boundary but the link verification result is still normal, the anomaly obtained by the interconnection status acquisition interface is mainly manifested as misalignment of adjacent pixel partitions. The topology fingerprint processor maps the abnormal location of the display partition to the address continuity constraint table and the fragment loading boundary. The fault inference processor generates a downstream address interpretation mismatch candidate set during candidate failure enumeration and simultaneously generates an upstream link failure candidate set for comparison. The influence cone comparison subprocessor finds that the link failure candidate set covers more downstream partitions and is inconsistent with the verification identifier breakpoint. The diffusion boundary truncation subprocessor classifies the abnormal distribution into the address mismatch segment according to the cross-node address boundary and deletes the link failure candidate set that does not conform to the actual abnormal boundary according to the exclusive constraint. When generating a temporary logical bypass path, the remapping controller synchronously rewrites the pixel partition interpretation address and frame fragment number so that the frame fragment is interpreted according to the new address boundary when written to the target pixel partition. The phase compensation value and the address interpretation relationship are refreshed and written to the same mapping version record. This embodiment can perform targeted repair in the scenario where the link is connected but the address interpretation is mismatched, avoiding the expansion of the bypass range due to the mistaken belief that the communication link is failed.

[0045] In another application embodiment, when the latch phase of adjacent pixel partitions in a small-pitch LED display matrix shifts, the abnormal feedback may manifest as local flickering or inconsistent frame order. The verification feedback data obtained by the interconnect status acquisition interface does not necessarily show a transmission fragmentation error. The topology fingerprint processor writes the refresh latch phase, grayscale loading order, and common frame boundary into the phase adjacency constraint table. The fault inference processor treats the refresh phase drift as an independent candidate object when enumerating candidate failures, affecting the cone ratio pair subprocessor's generation of downstream abnormal distributions related to the phase adjacency edge. The diffusion boundary truncation subprocessor requires that the phase drift segment must be associated with the common frame boundary or phase adjacency constraint. If the candidate object cannot explain the frame order abnormality location, it is not retained. When the minimum fault set points to the phase drift, the remapping controller does not change the transmission path separately, but writes the refresh phase compensation value and the corresponding pixel partition interpretation address into the pending submission mapping table and submits them uniformly at the common frame boundary. This embodiment can distinguish between refresh timing abnormalities and data transmission abnormalities, so that the repair action corresponds to the actual abnormality source.

[0046] In a preferred embodiment, to ensure data consistency during implementation, the interconnection status acquisition interface adds a common frame sequence identifier to the receiving control node, pixel partition logical address, frame data fragmentation order, refresh latch phase, and verification feedback data acquired within the same frame sequence. The topology fingerprint processor only generates reversible topology fingerprints for data with consistent frame sequence identifiers. If the frame sequence identifier of a certain data item is missing or inconsistent with other data items, it is marked as data to be confirmed and does not participate in the minimum fault set calculation. Data to be confirmed can be merged and checked with new verification feedback data in the next sampling window. When establishing the candidate fault search range, the fault inference processor prioritizes data with consistent frame sequence and uses data to be confirmed as an auxiliary boundary rather than a fault starting point. The remapping controller stores the frame sequence identifiers used in the mapping table to be submitted, so that the mapping version record and the source of the fault inference result maintain a corresponding relationship. In this embodiment, the frame sequence identifier runs through the acquisition, modeling, inference, and rewriting processes, reducing erroneous submissions caused by different frame data being mixed into the same repair decision.

[0047] In a preferred embodiment, the system performs cache management on the reversible topological fingerprint. The cache content includes the directed edge sequence of the most recent consecutive frames, the address continuity constraint table, the phase adjacency constraint table, differential segments, stable segments, and mapping version records. When generating the reversible topological fingerprint of the current frame, the topological fingerprint processor reuses the stable segments and only re-encodes the transmission edge sequence change items, pixel partition address change items, and refresh phase change items. When an anomaly occurs, the fault inference processor can simultaneously read the current frame fingerprint and several historical stable segments to determine whether the anomaly is caused by a recent change or an intermittent anomaly that has existed in the old topology for a long time. When generating a temporary logical bypass path, the remapping controller refers to the currently effective mapping table and the previous stable mapping version. If the current mapping table to be submitted fails the consistency check, it can be rolled back to the previous stable mapping version. The cache management does not involve changes to the physical structure of the display matrix, but only performs versioned storage of control data and topological data. This embodiment enables the self-healing process to maintain a traceable version chain in the continuous frame display scenario.

[0048] In a further embodiment, the remapping controller employs a boundary preservation strategy when generating temporary logical bypass paths. This boundary preservation strategy requires that the address boundary of the target pixel partition must not cross the cross-node address boundary in the address continuity constraint table where no anomalies have occurred, that the refresh phase compensation value must not change the common frame boundary of unaffected adjacent pixel partitions, and that the frame fragment number rewriting relationship must not cover fragment numbers in the currently effective mapping table that are unrelated to anomalies. The bypass path generation subprocessor selects candidate paths from unaffected transmission paths according to the above constraints and calculates the path cost for each candidate path. The consistency rewriting subprocessor writes the selected candidate paths into the pending submission mapping table and then compares the fields of the pending submission mapping table with the currently effective mapping table. If the pending submission mapping table modifies a field that is not reachable from the minimum fault set, the submission is rejected and the path is regenerated. This embodiment limits the bypass range to the fault-affected cone-related area, reducing the disturbance of the repair action to the normal display area.

[0049] In one embodiment, the system maintains the reverse topology order of the self-repair submission phase during the revocation phase after fault recovery. After the bypass revocation subprocessor confirms the recovery of the faulty transmission edge, it does not immediately delete the temporary logical bypass path. Instead, it writes the probe frame fragment number, the receive control node entry address, and the refresh phase compensation value of the recovered link into a new pending submission mapping table, and forms a parallel mapping record with the temporary logical bypass path in the currently effective mapping table. Within the continuous common frame boundary, the interconnect status acquisition interface collects the verification feedback data and arrival time identifier of the recovered link. The consistency rewrite subprocessor checks the consistency between the recovered link path and the temporary logical bypass path in frame order, fragment boundary, and phase compensation. When the parallel mapping record meets the consistency condition, the revocation order starts from the downstream pixel partition. First, the temporary bypass relationship in the pixel partition interpretation address is revoked, then the corresponding refresh phase compensation value is revoked, and then the temporary bypass relationship in the upstream receive control node entry address is revoked. This embodiment ensures that the recovered link undergoes detection and parallel verification before taking over the display output, reducing the probability of triggering anomalies again during the recovery phase.

[0050] In this embodiment, if the recovery link experiences a verification anomaly during the probe frame phase, the bypass cancellation subprocessor retains the temporary logical bypass path in the currently effective mapping table and marks the pending submission mapping table of the recovery link as an unstable version. The unstable version does not participate in the current display output. The fault inference processor can remap the recovery link detection anomaly to the reversible topology fingerprint to determine whether the fault is still located at the original transmission edge. If the recovery link stabilizes within the subsequent common frame boundary, a new pending submission mapping table is generated and the parallel mapping verification is re-executed. If the frame order of the recovery link and the temporary logical bypass path is consistent but the phase compensation value is inconsistent, the consistency rewrite subprocessor adjusts the refresh phase compensation value of the recovery link and keeps the pixel partition interpretation address unchanged until the common frame boundary verification is consistent before entering the reverse order cancellation. This embodiment enables the cancellation process to have a rollback and re-verification mechanism to avoid frequent changes in the mapping version caused by short-term jitter of the recovery link.

[0051] In a feasible integrated configuration, the system's software processing flow is completed by the same display control process or multiple control processes that are synchronized with each other. The interconnection status acquisition interface is responsible for forming original status records with consistent frame order. The topology fingerprint processor is responsible for converting the original status records into reversible topology fingerprints. The fault inference processor is responsible for establishing the candidate fault search range and determining the minimum fault set on the reversible topology fingerprint. The remapping controller is responsible for forming temporary logical bypass paths and submitting dual-version mappings. All data structures can be stored in the running memory or non-volatile configuration area of ​​the control terminal. The receiving control node only needs to interpret the entry address, pixel partition address, and refresh phase compensation value according to the currently effective mapping table. The system does not require the addition of new display matrix structures. If the display matrix reconfigures the partition address or transmission order, the topology fingerprint processor regenerates the differential fragments and stable fragments through the differential update subprocessor. The fault inference processor re-establishes the candidate fault search range based on the new topology fingerprint. This embodiment illustrates that the self-healing interconnection system can be implemented through control data structures and software logic, and has a clear engineering implementation path.

[0052] In this embodiment, the self-healing interconnection system of the small-pitch LED display matrix uses reversible topological fingerprints as the common data basis for fault reasoning and remapping control. The interconnection status acquisition interface provides the receiving control nodes in the same frame order, pixel partition logical addresses, frame data fragmentation order, refresh latch phase, and verification feedback data. The topological fingerprint processor transforms the transmission order, address continuity, and phase adjacency relationship into a graph structure that can be traversed in reverse. The fault reasoning processor determines the minimum fault set through fault influence cones, matching costs, diffusion boundary truncation, and reverse verification. The remapping controller completes repair submission and recovery cancellation through temporary logical bypass paths, same mapping version records, dual-version mapping tables, and bypass cancellation mechanisms. The entire implementation makes anomaly identification, fault location, bypass submission, and recovery cancellation all operate in a closed loop around the same topological version. It can distinguish and process transmission diffusion, address mismatch, and phase drift in the interconnection anomalies of the small-pitch LED display matrix, and reduce the interference of the repair process of local interconnection anomalies on unaffected display areas.

Claims

1. A self-healing interconnection system for a small-pitch LED display matrix, characterized in that, This includes an interconnect status acquisition interface, a topology fingerprint processor, a fault inference processor, and a remapping controller; The interconnection status acquisition interface acquires the receiving control node, pixel partition logical address, frame data fragmentation order, refresh latch phase and verification feedback data from the display matrix; The topology fingerprint processor generates a reversible topology fingerprint based on the receiving control node, the pixel partition logical address, the frame data fragmentation order, and the refresh latch phase. The fault reasoning processor maps the anomaly verification feedback data to the reversible topological fingerprint to determine the fault impact cone and the minimum fault set. The remapping controller generates a temporary logical bypass path based on the minimum fault set, and simultaneously rewrites the address interpretation relationship and refreshes the phase compensation relationship of the corresponding pixel partition.

2. The self-healing interconnection system for a small-pitch LED display matrix according to claim 1, characterized in that, The topology fingerprint processor includes a link sequence encoding subprocessor and a display partition association subprocessor; The link sequence encoding subprocessor encodes the transmission sequence of frame data between each receiving control node into a directed edge sequence, and binds each directed edge sequence to a corresponding fragmentation boundary, check flag, and arrival time flag. The display partition association subprocessor establishes a bidirectional index between the pixel partition logical address and the row and column refresh phase, and writes the bidirectional index into the reversible topological fingerprint, so that any abnormal fragment can be reverse-located to its upstream transmission edge and downstream display partition.

3. The self-healing interconnection system for a small-pitch LED display matrix according to claim 2, characterized in that, The reversible topological fingerprint also includes an address continuity constraint table and a phase adjacency constraint table; The address continuity constraint table records adjacent address segments, cross-node address boundaries, and fragment loading boundaries according to the logical row and column relationship of pixel partitions in the display matrix; The phase adjacency constraint table records the latching phase, grayscale loading order, and common frame boundary of adjacent pixel partitions; When generating the reversible topological fingerprint, the topological fingerprint processor binds the address continuity constraint table and the phase adjacency constraint table to the same frame sequence identifier.

4. The self-healing interconnection system for a small-pitch LED display matrix according to claim 1, characterized in that, The fault reasoning processor includes a candidate failure enumeration subprocessor and an influence cone ratio pair subprocessor; The candidate failure enumeration subprocessor enumerates the candidate failure set formed by receiving control node failure, upstream link failure, downstream address interpretation mismatch and refresh phase drift based on the reversible topology fingerprint enumeration. The influence cone ratio pair subprocessor generates a corresponding downstream anomaly distribution for each candidate failure set, and performs topological matching between the downstream anomaly distribution and the actual anomaly verification feedback data, the display partition anomaly position, and the frame sequence anomaly position to filter the minimum fault set.

5. The self-healing interconnection system for a small-pitch LED display matrix according to claim 1, characterized in that, The remapping controller includes a bypass path generation subprocessor and a consistency rewriting subprocessor; The bypass path generation subprocessor generates a temporary logical bypass path to bypass the faulty transmission edge based on the minimum fault set, the fragmentation bearing relationship of the unaffected transmission path, and the address boundary of the target pixel partition. The consistency rewrite subprocessor writes the frame fragment number, receive control node entry address, pixel partition interpretation address, and refresh phase compensation value corresponding to the temporary logical bypass path into the same mapping version record.

6. The self-healing interconnection system for a small-pitch LED display matrix according to claim 3, characterized in that, The topology fingerprint processor is also equipped with a fingerprint differential update subprocessor; The fingerprint differential update subprocessor extracts the transmission side sequence change item, pixel partition address change item, and refresh phase change item between consecutive frames, keeps the unchanged topological fingerprint segment as a stable segment, and forms the change items into differential segments. When anomaly verification feedback data arrives, the fault reasoning processor prioritizes establishing a candidate fault search range in the differential segment and stable segments that have address continuity constraints or phase adjacency constraints with the differential segment.

7. The self-healing interconnection system for a small-pitch LED display matrix according to claim 4, characterized in that, The influence cone ratio pair subprocessor includes a diffusion boundary truncation subprocessor; The diffusion boundary truncation subprocessor divides the downstream abnormal distribution generated by the candidate failure set into transmission diffusion segment, address mismatch segment and phase drift segment based on the cross-node address boundary, common frame boundary and check flag breakpoint in the reversible topological fingerprint. The fault reasoning processor establishes exclusive constraints between the transmission diffusion segment, the address mismatch segment, and the phase drift segment, and deletes candidate failure sets that are inconsistent with the actual abnormal boundaries based on the exclusive constraints.

8. The self-healing interconnection system for a small-pitch LED display matrix according to claim 5, characterized in that, The consistency rewrite subprocessor is also configured with a dual-version mapping table; The dual-version mapping table includes a currently active mapping table and a mapping table to be submitted. The mapping table to be submitted stores the frame fragment number, the receiving control node entry address, the pixel partition interpretation address, and the refresh phase compensation value corresponding to the temporary logical bypass path. When the common frame boundary arrives, the remapping controller writes the mapping version records in the mapping table to be submitted into the currently effective mapping table in the topological order from the upstream receiving control node to the downstream pixel partition.

9. The self-healing interconnection system for a small-pitch LED display matrix according to claim 7, characterized in that, The diffusion boundary truncation subprocessor also includes a reverse verification subprocessor; The reverse verification subprocessor starts from the end boundary of the actual abnormal display partition, traverses the directed edge sequence in the reversible topological fingerprint in reverse, reads the adjacent verification identifier breakpoints, cross-node address boundaries and common frame boundaries in sequence, and matches the boundary sequence obtained by the reverse traversal with the transmission diffusion segment, the address mismatch segment and the phase drift segment for overlap matching. The fault reasoning processor retains only the minimum set of faults that satisfy the overlap matching.

10. The self-healing interconnection system for a small-pitch LED display matrix according to claim 8, characterized in that, The remapping controller is also equipped with a bypass cancellation subprocessor; After the faulty transmission side is restored, the bypass cancellation subprocessor writes the probe frame fragment number, the receiving control node entry address and the refresh phase compensation value of the restored link into a new pending submission mapping table, and forms a parallel mapping record with the temporary logical bypass path in the currently effective mapping table. After the consistency rewriting subprocessor achieves frame order consistency for the parallel mapping record in the continuous common frame boundary kernel, it cancels the temporary logical bypass path in the topological reverse order from the downstream pixel partition to the upstream receiving control node.

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