Display device

Abstract

This disclosure discloses a display device. The display device may include: a light-emitting element; a driving transistor that drives the light-emitting element; a storage capacitor that samples a threshold voltage of the driving transistor during a sampling period and programs a data voltage during a programming period; and at least one thin-film transistor that transmits at least one of a data voltage, a reference voltage, and a reset voltage, wherein the display device changes the sampling period according to a brightness band.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2025-0009015, filed on January 21, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices. Background Technology

[0004] Organic light-emitting displays (OLEDs) are self-emissive display devices, and therefore, unlike liquid crystal displays (LCDs), they do not require a separate light source, allowing them to be manufactured in a lightweight and thin form. Furthermore, OLEDs are advantageous not only in terms of power consumption due to their low-voltage operation, but also in their excellent color reproduction, response speed, viewing angle, and contrast ratio (CR), and are therefore being researched as a next-generation display technology.

[0005] We continuously improve display devices to provide users with clearer images by increasing screen resolution and brightness. Summary of the Invention

[0006] For the driving transistors and switching transistors in the pixels of the display panel, oxide thin-film transistors (TFTs) are used. This pixel can help achieve low power consumption because oxide TFTs have low shutdown current characteristics.

[0007] Meanwhile, Temperature-to-Limit Sensitivity (TLS) refers to the degree of brightness change based on temperature variations, and is evaluated under both low-grayscale and high-grayscale conditions as one of the items required for product specification management. The display device samples the threshold voltage Vth of the driving transistor during the sampling period, but the same sampling time is applied to all bands, both low and high grayscale, thus failing to meet the TLS optimization requirements for each band.

[0008] In view of this, the inventors of this disclosure have invented a display device that can satisfy the excellent TLS characteristics of the high brightness band and low brightness band in a display panel having pixels using oxide TFTs.

[0009] The objective of embodiments of this disclosure is to provide a display device that can improve TLS characteristics across all brightness bands by applying a sampling time that varies according to the brightness band in a display panel having pixels with applied oxide TFTs.

[0010] In addition to the purposes described above, this disclosure may also have other purposes, which will be readily apparent to those skilled in the art from the following description.

[0011] A display device is provided according to embodiments of the present disclosure. The display device varies the sampling period for sampling the threshold voltage of the driving transistors based on the brightness band in a display panel having pixels using oxide TFTs.

[0012] According to the implementation method, the brightness band can be divided into multiple bands representing a brightness range from low brightness to high brightness, and the sampling period can be set separately for each of the multiple bands.

[0013] According to the implementation method, as the sampling period moves from the low brightness band to the high brightness band, the sampling time period can be changed in a stepwise manner to have a longer duration.

[0014] According to embodiments of this disclosure, a display device can improve the TLS (temperature-luminance sensitivity) characteristics across all brightness bands by varying the sampling period for sampling the threshold voltage of the driving transistors based on the brightness bands in a display panel having pixels with applied oxide TFTs.

[0015] In addition, the display device can optimize the sampling period according to the brightness band by setting the sampling period individually for each of the multiple bands representing a brightness range from low brightness to high brightness.

[0016] In addition, the display device can improve the TLS characteristics of each brightness band by applying the optimal sampling period to each of the multiple bands representing the brightness range.

[0017] In addition, the display device gradually changes the sampling time from low brightness band to high brightness band to have a longer sampling time, so that the sampling time in the low brightness band is shorter and the TLS characteristics can be better, and the sampling time in the high brightness band is longer and the TLS characteristics can be better.

[0018] In addition, the display device can improve image quality by having excellent TLS characteristics that are independent of brightness band, and meet the specifications of display panels with pixels using oxide TFTs.

[0019] In addition to the effects described above, the specific effects of the invention will now be described in conjunction with specific aspects of how the invention is practiced. Attached Figure Description

[0020] Figure 1 This is a block diagram schematically illustrating an organic light-emitting display device according to an embodiment of the present disclosure;

[0021] Figure 2 This is a circuit diagram of pixels in an organic light-emitting display device according to an embodiment of the present disclosure;

[0022] Figure 3This is a timing diagram illustrating the operation of pixels in an organic light-emitting display device according to an embodiment of the present disclosure;

[0023] Figure 4 This indicates that settings are configured individually based on the brightness band. Figure 3 A graph of sampling times;

[0024] Figure 5 This is a graph showing the optimal sampling time in the low-brightness band; and

[0025] Figure 6 This is a graph showing the optimal sampling time in the high-brightness band. Detailed Implementation

[0026] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, are described below with reference to the appendix. Figure 1 As will become apparent when the embodiments are described in detail below. However, this disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. Therefore, these embodiments are described only to complete this disclosure and to fully inform those skilled in the art of the scope of this disclosure.

[0027] The shapes, dimensions, ratios, angles, numbers, etc., disclosed in the accompanying drawings illustrating embodiments of this disclosure are illustrative and are not intended to limit the scope of this disclosure. Throughout the detailed description, similar reference numerals refer to similar components. Furthermore, in describing this disclosure, detailed descriptions of related known technologies will be omitted if it is determined that such detailed descriptions may unnecessarily obscure the essential points of this disclosure. When terms such as "comprising," "including," "having," "configured with," etc., are used in this disclosure, the presence or addition of other elements is permissible unless the term "only" is used. When a component is described using a singular form, it may include the meaning of the plural form unless explicitly stated otherwise.

[0028] It should be noted that any component will be interpreted as including tolerances or error ranges, even if they are not explicitly described.

[0029] When describing the positional relationship between two elements, for example, when using "on," "above," "below," and "adjacent," one or more other elements may be inserted between the two elements unless "exactly," "directly," or "closely" is used.

[0030] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases can also be included, unless the terms “exactly” or “directly” are used.

[0031] When describing the flow of signals, for example, in the case of “signal transmission from node A to node B”, unless the terms “immediately” or “directly” are used, it may include the case of a signal being transmitted from node A to node B via another node.

[0032] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the scope of the technical concept of this disclosure, a first element referred to in the following description may mean a second element.

[0033] The various features of the various embodiments of this disclosure may be coupled or combined with each other in part or in whole to interconnect and operate in various technical ways, and each embodiment may be implemented independently of each other or together in an associated relationship.

[0034] Below, a display device according to an embodiment of the present disclosure is disclosed, wherein temperature luminance sensitivity (TLS) characteristics can be improved for all luminance bands of a display panel having pixels with applied oxide TFTs.

[0035] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 This is a block diagram schematically illustrating an organic light-emitting display device according to an embodiment of the present disclosure.

[0037] Reference Figure 1 The display device 10 includes a display panel 100 having a plurality of pixels P, a controller 200, a gate driving unit 300 that supplies scan signals SC to the plurality of pixels P, a data driving unit 400 that supplies data voltage Vdata to the plurality of pixels P, and a power supply unit 500 that supplies the voltage required to drive the plurality of pixels P.

[0038] In the display panel 100, multiple gate lines GL and multiple data lines DL intersect each other, and each of the multiple pixels P is connected to the gate lines GL and data lines DL. Specifically, a pixel P receives a gate signal from the gate driving unit 300 through the gate line GL, receives a data voltage Vdata from the data driving unit 400 through the data line DL, and receives a high-potential driving voltage ELVDD and a low-potential driving voltage ELVSS from the power supply unit 500.

[0039] Gate line GL supplies scan signal SC and light emission control signal EM, and data line DL supplies data voltage Vdata. Additionally, according to various embodiments, gate line GL may include multiple scan lines SCL supplying scan signal SC and a light emission control signal line EML supplying light emission control signal EM. Furthermore, multiple pixels P may also include power lines VL for receiving reference voltage VREF and reset voltage VAR.

[0040] Additionally, each pixel P includes a light-emitting element and a pixel circuit. The pixel circuit includes multiple switching elements, driving elements, and capacitors. Here, the switching elements and driving elements can be configured using thin-film transistors. In the pixel circuit, the driving elements control the amount of current supplied to the light-emitting element according to the data voltage, thereby adjusting the amount of light emitted by the light-emitting element. Furthermore, the multiple switching elements operate the pixel circuit by receiving scan signals SC supplied through multiple scan lines SCL and light emission control signals EM supplied through the light emission control line EML.

[0041] Display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. Transmissive display panels can be applied to transparent display devices that display images on a screen while allowing real-world background objects to be visible. Display panel 100 can be manufactured as a flexible display panel. Flexible display panels can be implemented as OLED panels using a plastic substrate.

[0042] Multiple touch sensors can be installed on the display panel 100. Touch input can be sensed using individual touch sensors or via pixels P. The touch sensors can be installed on the screen of the display panel as on-cell or add-on types, or implemented as in-cell type touch sensors built into the display panel 100.

[0043] The controller 200 processes the RGB image data input from the host system to suit the size and resolution of the display panel 100, and supplies the processing result to the data driver unit 400. The controller 200 generates a gate control signal GCS and a data control signal DCS using externally input synchronization signals such as a clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync. By supplying the generated gate control signal GCS and data control signal DCS to the gate driver unit 300 and the data driver unit 400, respectively, the controller 200 controls the gate driver unit 300 and the data driver unit 400.

[0044] The controller 200 can be configured to be combined with various processors such as microprocessors, mobile processors, application processors, etc., depending on the device on which it is installed.

[0045] The host system can be any of a television (TV) system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, wearable device, or vehicle system.

[0046] Controller 200 generates signals that allow pixel P to be driven at various refresh rates. The refresh rate can be defined as the number of frames transmitted per second. In other words, controller 200 generates drive-related signals so that pixel P can be driven at a variable refresh rate when operating in Variable Refresh Rate (VRR) mode. For example, controller 200 can simply change the speed of a clock signal or generate a synchronization signal to allow for horizontal or vertical blanking.

[0047] The controller 200 generates a gate control signal GCS for controlling the operation timing of the gate drive unit 300 and a data control signal DSC for controlling the operation timing of the data drive unit 400 based on the timing signals Vsync, Hsync, and DE received from the host system. The controller 200 synchronizes the gate drive unit 300 and the data drive unit 400 by controlling the operation timing.

[0048] The gate driving unit 300 supplies a scan signal SC to the gate line GL according to the gate control signal GCS supplied from the controller 200. The gate driving unit 300 can be disposed on one or both sides of the display panel 100 in a GIP (gate in panel) manner.

[0049] In an organic light-emitting display device, a gate driving unit 300 supplies a scan signal SC and a light-emitting control signal EM to a display panel 100. The scan signal SC may include a scan pulse that oscillates between a gate low voltage VGL and a gate high voltage VGH. The light-emitting control signal EM includes a light-emitting control signal pulse that oscillates between a gate low voltage VEL and a gate high voltage VEH. The scan pulse is synchronized with the data voltage Vdata to select the row of pixel P for which data is to be written. The light-emitting control signal pulse defines the light-emitting time of pixel P.

[0050] The gate driving unit 300 includes at least one light emission control signal driver 310 and at least one scan driving unit 320. The light emission control signal driver 310 outputs a light emission control signal pulse in response to a start pulse and a shift clock from the controller 200, and shifts the light emission control signal pulse according to the shift clock sequence. The scan driving unit 320 outputs a scan pulse in response to a start pulse and a shift clock from the controller 200, and shifts the scan pulse according to the shift clock timing sequence.

[0051] The data drive unit 400 converts image data RGB into data voltage Vdata according to the data control signal DCS supplied from the controller 200, and supplies the converted data voltage Vdata to the pixel P through the data line DL.

[0052] exist Figure 1 In this diagram, the data driver unit 400 is shown as a single unit disposed on one side of the display panel 100, but the number and placement of the data driver units 400 are not limited thereto. The data driver unit 400 may be configured with multiple integrated circuits (ICs) and disposed as multiple separate parts on one side of the display panel 100.

[0053] The power supply unit 500 uses a DC-DC converter to generate the DC power required to drive the pixel array, gate drive unit 300, and data drive unit 400 of the display panel 100. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. The power supply unit 500 can receive a DC input voltage applied from the host system to generate DC voltages, such as gate low voltages VGL and VEL, gate high voltages VGH and VEH, high-level drive voltage ELVDD, low-level drive voltage ELVSS, reset voltage VAR, and reference voltage VREF. Gate low voltages VGL and VEL, and gate high voltages VGH and VEH are supplied to the level shifter and gate drive unit 300. High-level drive voltage ELVDD, low-level drive voltage ELVSS, reset voltage VAR, and reference voltage VREF are supplied to the pixel P.

[0054] Figure 2 This is a circuit diagram of pixels in an organic light-emitting display device according to an embodiment of the present disclosure.

[0055] Reference Figure 2 Each of the multiple pixels P may include a pixel circuit having a driving transistor DT and a light-emitting element OLED connected to the pixel circuit.

[0056] The pixel circuit controls the driving current flowing to the OLED light-emitting element to drive the OLED. The pixel circuit may include a driving transistor DT, second transistors T2 to seventh transistors T7, a storage capacitor Cst, and a compensation capacitor CA.

[0057] Each of the driving transistor DT and the second transistors T2 through T7 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0058] Each of the driving transistor DT and the second transistors T2 through T7 can be a P-type thin-film transistor or an N-type thin-film transistor. Figure 2In this embodiment, the driving transistor DT, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 can be N-type thin-film transistors, and the fifth transistor T5 can be a P-type thin-film transistor. Alternatively, the N-type thin-film transistor can be an oxide thin-film transistor. The P-type thin-film transistor can be a polycrystalline silicon thin-film transistor.

[0059] As described above, each of the plurality of pixels includes a light-emitting element OLED, a driving transistor DT that drives the light-emitting element OLED, a storage capacitor Cst in which one electrode is connected to the gate electrode of the driving transistor DT and the other electrode is connected to the source electrode of the driving transistor DT, and a compensation capacitor CA in which one electrode is connected to the other electrode of the storage capacitor Cst and the source electrode of the driving transistor DT.

[0060] Additionally, each of the plurality of pixels includes: a second transistor T2, one electrode of which is connected to the data voltage Vdata and the other electrode of which is connected to the gate electrode of the driving transistor DT and an electrode of the storage capacitor Cst; a third transistor T3, one electrode of which is connected to the reference voltage VREF and the other electrode of which is connected to the gate electrode of the driving transistor DT and an electrode of the storage capacitor Cst; and a fourth transistor T4, one electrode of which is connected to the anode electrode of the light-emitting element OLED and the other electrode of which is connected to the reset voltage VAR.

[0061] Additionally, each of the plurality of pixels includes: a fifth transistor T5, one electrode of which is connected to the high potential driving voltage ELVDD and the other electrode of which is connected to the drain electrode of the driving transistor DT; a sixth transistor T6, one electrode of which is connected to the source electrode of the driving transistor DT and the other electrode of which is connected to the anode electrode of the light-emitting element OLED; and a seventh transistor T7, one electrode of which is connected to the reference voltage VREF and the other electrode of which is connected to the other electrode of the compensation capacitor CA.

[0062] The driving transistor DT includes a source electrode connected to a first node N1, a gate electrode connected to a second node N2, and a drain electrode connected to a third node N3. The driving transistor DT provides a driving current to the light-emitting element OLED based on the data voltage Vdata applied to the gate electrode.

[0063] The light-emitting element (OLED) includes an anode electrode and a cathode electrode. The anode electrode of the OLED is connected to the fourth node N4, and the cathode electrode is connected to the low-potential driving voltage ELVSS.

[0064] A storage capacitor Cst can be connected or formed between the second node N2 and the first node N1. The storage capacitor Cst can store or hold the data voltage Vdata. Additionally, the storage capacitor Cst can be used to sample the threshold voltage of the driving transistor DT.

[0065] A compensation capacitor CA can be connected or formed between the first node N1 and the fifth node N5. The compensation capacitor CA can be used to maintain the potential of the first node N1 corresponding to the source electrode of the driving transistor DT. Additionally, the compensation capacitor CA can be used together with the storage capacitor Cst to sample the threshold voltage of the driving transistor DT.

[0066] The second transistor T2 may include a first electrode connected to the data line DL (or receiving the data voltage Vdata), a second electrode connected to the second node N2, and a gate electrode for receiving the first scan signal SC1. The second transistor T2 can be turned on in response to the first scan signal SC1 and can transmit the data voltage Vdata to the second node N2.

[0067] The third transistor T3 may include a first electrode for receiving a reference voltage VREF, a second electrode connected to the second node N2, and a gate electrode for receiving a second scan signal SC2. The third transistor T3 may be turned on in response to the second scan signal SC2 and may transmit the reference voltage VREF to the second node N2.

[0068] The fourth transistor T4 may include a first electrode receiving a reset voltage VAR, a second electrode connected to the fourth node N4, and a gate electrode receiving a first light-emitting control signal EM1. The fourth transistor T4 may be turned on in response to the first light-emitting control signal EM1 and may transmit the reset voltage VAR to the fourth node N4.

[0069] The fifth transistor T5 may include a first electrode receiving a high-potential drive voltage ELVDD, a second electrode connected to the third node N3, and a gate electrode receiving a first light-emitting control signal EM1. The fifth transistor T5 may be turned on in response to the first light-emitting control signal EM1 and may transmit the high-potential drive voltage ELVDD to the third node N3.

[0070] The sixth transistor T6 may include a first electrode connected to the first node N1, a second electrode connected to the fourth node N4, and a gate electrode for receiving the second light-emitting control signal EM2. The sixth transistor T6 can be turned on in response to the second light-emitting control signal EM2, and can transmit the driving current controlled by the driving transistor DT to the light-emitting element OLED through the fourth node N4. Additionally, the sixth transistor T6 can be turned on in response to the second light-emitting control signal EM2, and can transmit the reset voltage VAR transmitted by the fourth transistor T4 to the first node N1.

[0071] The seventh transistor T7 may include a first electrode for receiving a reference voltage VREF, a second electrode connected to the fifth node N5, and a gate electrode for receiving a third scan signal SC3. The seventh transistor T7 may be turned on in response to the third scan signal SC3 and may transmit the reference voltage VREF to the fifth node N5.

[0072] The display device according to embodiments of this disclosure can operate as a variable refresh rate (VRR) mode display device. VRR mode allows pixels to operate at a constant frequency, operate at a refresh rate with an increased update data voltage Vdata when high-speed pixel driving is required, or operate at a reduced refresh rate when reduced power consumption or low-speed pixel driving is required.

[0073] Depending on the refresh rate, each of the plurality of pixels P may execute only a refresh frame drive, or a combination of a refresh frame drive and an anode reset frame drive. In this disclosure, a refresh frame may be defined as a period during which the data voltage Vdata is updated, and an anode reset frame may be defined as a period during which the data voltage Vdata is held and not updated. In this disclosure, a setup period may be defined as a period during which the combination of refresh frames and anode reset frames is repeated.

[0074] For example, when driving at a refresh rate of 120 Hz, the drive can be executed 120 times per second using only refresh frames. One refresh frame duration is 1 / 120 = 8.33 ms, and one setting duration is also 8.33 ms.

[0075] Additionally, when driving at a 60 Hz refresh rate, the driving can be performed by alternating between refresh frames and anode reset frames 60 times per second. A refresh frame period and an anode reset frame period are each 0.5 / 60 = 8.33 ms, and a setup period is 16.66 ms.

[0076] Additionally, when driving at a 1 Hz refresh rate, driving can be performed in one second with one refresh frame and 119 anode reset frames. One refresh frame period and one anode reset frame period are 1 / 120 = 8.33 ms, and one setup period is 1 second.

[0077] A refresh frame charges the new data voltage Vdata to apply the new data voltage Vdata to the drive transistor DT, while an anode reset frame holds and uses the data voltage Vdata from the previous frame. An anode reset frame can also be called a hold frame, in the sense that the data voltage Vdata from the previous frame is held and used as is.

[0078] First, the driving of the light-emitting elements and pixel circuits for refreshing the frame will be described.

[0079] Figure 3 This is a timing diagram illustrating the operation of pixels in an organic light-emitting display device according to an embodiment of the present disclosure. (Refer to...) Figure 3 The frame refresh operation can include the initialization period, sampling period, programming period, and emission period.

[0080] Reference Figure 2 and Figure 3 The operation of the pixel circuit can include an initialization period during the refresh frame. This initialization period is used to initialize the first node N1, the second node N2, the fourth node N4, and the fifth node N5 of the pixel circuit. During this initialization period, the storage capacitor Cst connected to the second node N2 and the gate electrode of the driving transistor DT can be initialized; the source electrode of the driving transistor DT connected to the first node N1 can be initialized; the anode electrode of the light-emitting element OLED connected to the fourth node N4 can be initialized; and the compensation capacitor CA connected to the fifth node N5 can be initialized.

[0081] During the initialization period, the second scan signal SC2, the third scan signal SC3, the first light emission control signal EM1, and the second light emission control signal EM2 are applied with high voltages, and the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned on. When the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned on, the second node N2 and the fifth node N5 can be initialized to the reference voltage VREF, and the fourth node N4 and the first node N1 can be initialized to the reset voltage VAR.

[0082] The operation of the pixel circuitry may include a sampling period during the refresh frame. This sampling period is used to sample the threshold voltage Vth of the driving transistor DT. During this sampling period, the threshold voltage Vth of the driving transistor DT can be sampled using the storage capacitor Cst and the compensation capacitor CA.

[0083] During the sampling period, the second scan signal SC2 and the third scan signal SC3 are at high voltage; the first light emission control signal EM1 is applied at a low voltage; and the third transistor T3, the fifth transistor T5, the seventh transistor T7, and the driving transistor DT are turned on. When the third transistor T3, the fifth transistor T5, the seventh transistor T7, and the driving transistor DT are turned on, the high-potential driving voltage ELVDD is transmitted to the third node N3, and the second node N2 and the fifth node N5 are held at the reference voltage VREF, so that the threshold voltage of the driving transistor DT can be transmitted to the first node N1 and sampled.

[0084] The operation of the pixel circuitry can include a programming period during the refresh frame. The programming period is the time during which the data voltage Vdata is stored in the storage capacitor Cst.

[0085] During the programming period, the first scan signal SC1, the third scan signal SC3, and the first light emission control signal EM1 are applied with high voltage, and the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on. The first scan signal SC1 may include an odd first scan signal SC1_ODD provided to odd-numbered gate lines and an even first scan signal SC1_EVEN provided to even-numbered gate lines.

[0086] During the programming phase, when the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on, the data voltage Vdata is transmitted to the second node N2, the reset voltage VAR is transmitted to the fourth node N4, and the fifth node N5 is held at the reference voltage VREF, so that the data voltage Vdata is stored in the storage capacitor Cst.

[0087] The operation of the pixel circuitry may include a light-emitting period during the refresh frame. The light-emitting period is the period in which the OLED emits light with a driving current corresponding to the data voltage Vdata stored in the storage capacitor Cst, while simultaneously offsetting the threshold voltage Vth of the driving transistor DT.

[0088] During the light-emitting period, a low voltage is applied to the first light-emitting control signal EM1, a high voltage is applied to the second light-emitting control signal EM2, and the fifth transistor T5, the sixth transistor T6, and the driving transistor DT are turned on. When the fifth transistor T5, the sixth transistor T6, and the driving transistor DT are turned on, the high-potential driving voltage ELVDD is transmitted to the third node N3, and the driving current corresponding to the data voltage Vdata is provided to the light-emitting element OLED.

[0089] Next, the driving of the light-emitting elements and pixel circuits of the anode reset frame will be described.

[0090] The operation of the pixel circuitry can include an anode reset period during the anode reset frame. The anode reset frame is the period during which the data voltage Vdata of the refresh frame is held and used as is. Therefore, unlike the refresh frame, the initialization period, sampling period, and programming period are unnecessary for the anode reset frame.

[0091] During the anode reset period, the first light emission control signal EM1 and the second light emission control signal EM2 are applied with high voltages, and the fourth transistor T4 and the sixth transistor T6 are turned on. When the fourth transistor T4 and the sixth transistor T6 are turned on, the first node N1 and the fourth node N4 can be reset to the reset voltage VAR, and the second node N2 can be held at the data voltage Vdata.

[0092] Additionally, the operation of the pixel circuitry may include a light-emitting period during the anode reset frame. The operation of the light-emitting period during the anode reset frame is the same as the operation of the light-emitting period during the refresh frame.

[0093] Figure 4 This indicates that settings are configured individually based on the brightness band. Figure 3 A graph showing the sampling time.

[0094] In such Figure 2 In the pixel structure using oxide TFTs shown, the optimal conditions for the sampling time ST to satisfy the excellent TLS characteristics of the high-brightness band and the low-brightness band are different. For example... Figure 4 As shown, this disclosure aims to improve TLS features across all luma bands by applying optimal sampling times to each luma band.

[0095] The brightness bands can be divided into multiple bands, Band1, Band2, Band3, ..., Band13, representing a brightness range from low to high brightness, and the sampling time can be set individually for each of the multiple bands. For example, a first sampling time ST1 can be set for the first band Band1; a second sampling time ST2 can be set for the second band Band2; a third sampling time ST3 can be set for the third band Band3; and a thirteenth sampling time ST13 can be set for the thirteenth band Band13. Here, when the first band Band1 is a low brightness band and the thirteenth band Band13 is a high brightness band, the sampling time can be set so that the sampling time becomes longer as it moves from low brightness band to high brightness band. That is, the sampling time can be shortened in the low brightness band and lengthened in the high brightness band.

[0096] With the third transistor T3 in the ON state, the ON period of the fifth transistor T5 can be defined as the sampling period, and the sampling period can be changed by controlling the ON time of the fifth transistor T5 according to the brightness band. That is, the sampling time used to sense the threshold voltage of the driving transistor DT represents the period during which both the second scan signal SC2 and the first light emission control signal EM1 are ON. Since the third transistor T3 is an NMOS TFT, it is ON when the second scan signal SC2 is at a high logic level, and since the fifth transistor T5 is a PMOS TFT, it is ON when the first light emission control signal EM1 is at a low logic level.

[0097] In display panels with pixels using oxide TFTs, shorter sampling times result in better TLS in the low-brightness band, while longer sampling times result in better TLS in the high-brightness band. The following equation represents the TLS calculation equation.

[0098]

[0099] Where T1 and T2 represent the evaluation temperature conditions, luminance@T1 indicates the luminance at temperature T1, and luminance@T2 indicates the luminance at temperature T2.

[0100] As described above, the display device of this disclosure can apply an optimal sampling time for each brightness band, thereby improving TLS characteristics across all brightness bands. The sampling time can be shortened in low brightness bands and lengthened in high brightness bands.

[0101] Figure 5 This is a graph showing the optimal sampling time in the low-brightness band. Figure 6 This is a graph showing the optimal sampling time in the high-brightness band.

[0102] Reference Figure 5 When data voltages corresponding to image data W11, W23, W35, W87, and W255 are applied under low-brightness conditions (e.g., 10 nits (25-10°C)), the TLS characteristics of the low-brightness band can be improved by applying a sampling time of 6H. Here, image data W11, W23, W35, and W87 represent grayscale values ​​11, 23, 35, and 87, respectively, and image data W255 represents grayscale value 255 (white). Furthermore, 6H represents six times one horizontal period.

[0103] Additionally, refer to Figure 6When data voltages corresponding to image data W4, W7, W28, W82, W193, and W255 are applied under high-brightness conditions (e.g., 1200 nits (25-10°C)), applying a sampling time of 14H improves the TLS characteristics of the high-brightness band. Here, image data W4, W7, W28, W82, and W193 represent grayscale values ​​4, 7, 28, 82, and 193, respectively, and image data W255 represents a grayscale value of 255 (white). Furthermore, 14H represents 14 times one horizontal period.

[0104] As described above, the display device can shorten the sampling time in the low brightness band and lengthen the sampling time in the high brightness band, thereby improving the TLS characteristics of each band.

[0105] A display device according to an embodiment of the present disclosure includes: a light-emitting element; a driving transistor that drives the light-emitting element; a storage capacitor that samples a threshold voltage of the driving transistor during a sampling period and programs a data voltage during a programming period; and at least one thin-film transistor that transmits at least one of a data voltage, a reference voltage, and a reset voltage, and the display device changes the sampling period according to a brightness band.

[0106] According to the implementation method, the brightness band can be divided into multiple bands representing a brightness range from low brightness to high brightness, and the sampling period can be set separately for each of the multiple bands.

[0107] According to the implementation method, as the sampling period moves from the low brightness band to the high brightness band, the sampling time period can be changed in a stepwise manner to have a longer duration.

[0108] According to the implementation, the driving transistor and at least one thin-film transistor can be an N-type thin-film transistor.

[0109] According to an embodiment, the display device may further include a compensation capacitor, one electrode of which is connected to one electrode of a storage capacitor and the source electrode of a driving transistor, and the other electrode of which is connected to a reference voltage.

[0110] According to an embodiment, at least one thin-film transistor may include: a first transistor, one electrode of which is connected to a data voltage and the other electrode of which is connected to the gate electrode of a driving transistor and the other electrode of a storage capacitor; a second transistor, one electrode of which is connected to a reference voltage and the other electrode of which is connected to the gate electrode of the driving transistor and the other electrode of the storage capacitor; a third transistor, one electrode of which is connected to the anode electrode of a light-emitting element and the other electrode of which is connected to a reset voltage; a fourth transistor, one electrode of which is connected to a high-potential driving voltage and the other electrode of which is connected to the drain electrode of the driving transistor; a fifth transistor, one electrode of which is connected to the source electrode of the driving transistor and the other electrode of which is connected to the anode electrode of the light-emitting element; and a sixth transistor, one electrode of which is connected to the reference voltage and the other electrode of which is connected to the other electrode of a compensation capacitor.

[0111] According to the implementation method, the driving transistor, the first transistor, the second transistor, the third transistor, the fifth transistor, and the sixth transistor can be N-type thin-film transistors, and the fourth transistor can be a P-type thin-film transistor.

[0112] According to the implementation, when the second transistor is in the conducting state, the conducting period of the fourth transistor can be defined as the sampling period, and the sampling period can be changed by controlling the conducting time of the fourth transistor according to the brightness band.

[0113] According to the implementation, in the on state of the second transistor, the third transistor, and the fifth transistor, the initialization period can be defined as the period from the on time of the sixth transistor to the off time of the fifth transistor.

[0114] According to the implementation, during the initialization period, the gate electrode of the driving transistor and the other electrode of the compensation capacitor can be initialized to a reference voltage, and the anode electrode of the light-emitting element and the source electrode of the driving transistor can be initialized to a reset voltage.

[0115] A display device according to an embodiment of the present disclosure includes: a display panel having a plurality of pixels, each of the plurality of pixels including: a light-emitting element; a driving transistor driving the light-emitting element; a storage capacitor having one electrode connected to the gate electrode of the driving transistor and another electrode connected to the source electrode of the driving transistor; a compensation capacitor having one electrode connected to the other electrode of the storage capacitor and the source electrode of the driving transistor; a first transistor having one electrode connected to a data voltage and another electrode connected to the gate electrode of the driving transistor and one electrode of the storage capacitor; and a second transistor having one electrode connected to a reference voltage. The second transistor has one electrode connected to the gate electrode of the driving transistor and one electrode of the storage capacitor; the third transistor has one electrode connected to the anode electrode of the light-emitting element and the other electrode connected to the reset voltage; the fourth transistor has one electrode connected to the high-potential driving voltage and the other electrode connected to the drain electrode of the driving transistor; the fifth transistor has one electrode connected to the source electrode of the driving transistor and the other electrode connected to the anode electrode of the light-emitting element; and the sixth transistor has one electrode connected to the reference voltage and the other electrode connected to the other electrode of the compensation capacitor. According to the display device, when the second transistor is in the on state, the on-time of the fourth transistor is defined as the sampling time period, and the sampling time period is changed by controlling the on-time of the fourth transistor according to the brightness band.

[0116] According to the implementation method, the brightness band can be divided into multiple bands representing a brightness range from low brightness to high brightness, and the sampling period can be set separately for each of the multiple bands.

[0117] According to the implementation method, as the sampling period moves from the low brightness band to the high brightness band, the sampling time period can be changed in a stepwise manner to have a longer duration.

[0118] According to the implementation method, the driving transistor, the first transistor, the second transistor, the third transistor, the fifth transistor, and the sixth transistor can be N-type thin-film transistors, and the fourth transistor can be a P-type thin-film transistor.

[0119] According to the implementation, in the on state of the second transistor, the third transistor, and the fifth transistor, the initialization period can be defined as the period from the on time of the sixth transistor to the off time of the fifth transistor.

[0120] According to the implementation, during the initialization period, the gate electrode of the driving transistor and the other electrode of the compensation capacitor can be initialized to a reference voltage, and the anode electrode of the light-emitting element and the source electrode of the driving transistor can be initialized to a reset voltage.

[0121] Although embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, those skilled in the art should understand that the present disclosure is not necessarily limited to the above embodiments, and that the above embodiments can be practiced in various modifications without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical concept of the present disclosure, but rather to illustrate it, and the scope of the technical concept of the present disclosure is not limited by these embodiments. Therefore, it should be understood that the above embodiments are given by way of example only in all respects and are not intended to limit the present disclosure. The scope of protection of this disclosure should be interpreted by the claims, and all technical concepts within the equivalent scope should be interpreted as included within the scope of the rights of this disclosure.

Claims

1. A display device, comprising: Light-emitting elements; A driving transistor that drives the light-emitting element; A storage capacitor that samples the threshold voltage of the driving transistor during a sampling period and programs the data voltage during a programming period; as well as At least one thin-film transistor, wherein the at least one thin-film transistor transmits at least one of the data voltage, reference voltage, and reset voltage. The display device changes the sampling period according to the brightness band.

2. The display device according to claim 1, wherein, The brightness band is divided into multiple bands representing a brightness range from low to high brightness, and the sampling period is set separately for each of the multiple bands.

3. The display device according to claim 2, wherein, As the sampling period transitions from low brightness to high brightness, it is gradually changed to have a longer duration.

4. The display device according to claim 1, wherein, The driving transistor and the at least one thin-film transistor are N-type thin-film transistors.

5. The display device according to claim 1, further comprising: A compensation capacitor, one electrode of which is connected to one electrode of the storage capacitor and the source electrode of the driving transistor, and the other electrode of which is connected to the reference voltage.

6. The display device according to claim 5, wherein, The at least one thin-film transistor includes: A first transistor, one electrode of which is connected to the data voltage, and the other electrode of which is connected to the gate electrode of the driving transistor and the other electrode of the storage capacitor; A second transistor, one electrode of which is connected to the reference voltage, and the other electrode of which is connected to the gate electrode of the driving transistor and the other electrode of the storage capacitor; A third transistor, one electrode of which is connected to the anode electrode of the light-emitting element, and the other electrode of which is connected to the reset voltage; A fourth transistor, one electrode of which is connected to a high-potential drive voltage, and the other electrode of which is connected to the drain electrode of the drive transistor; A fifth transistor, one electrode of which is connected to the source electrode of the driving transistor, and the other electrode of which is connected to the anode electrode of the light-emitting element; and A sixth transistor, one electrode of which is connected to the reference voltage, and the other electrode of which is connected to the other electrode of the compensation capacitor.

7. The display device according to claim 6, wherein, The driving transistor, the first transistor, the second transistor, the third transistor, the fifth transistor, and the sixth transistor are N-type thin-film transistors, and the fourth transistor is a P-type thin-film transistor.

8. The display device according to claim 6, wherein, When the second transistor is in the on state, the on period of the fourth transistor is defined as the sampling period, and the sampling period is changed by controlling the on time of the fourth transistor according to the brightness band.

9. The display device according to claim 6, wherein, When the second transistor, the third transistor, and the fifth transistor are in the on state, the initialization period is defined as the period from the on time of the sixth transistor to the off time of the fifth transistor.

10. The display device according to claim 9, wherein, During the initialization period, the gate electrode of the driving transistor and the other electrode of the compensation capacitor are initialized to the reference voltage, and the anode electrode of the light-emitting element and the source electrode of the driving transistor are initialized to the reset voltage.

11. A display device, comprising: The display panel contains multiple pixels. Each of the plurality of pixels includes: Light-emitting elements; A driving transistor that drives the light-emitting element; A storage capacitor, one electrode of which is connected to the gate electrode of the driving transistor, and the other electrode of which is connected to the source electrode of the driving transistor; A compensation capacitor, one electrode of which is connected to the other electrode of the storage capacitor and the source electrode of the driving transistor; A first transistor, one electrode of which is connected to a data voltage, and the other electrode of which is connected to the gate electrode of the driving transistor and one electrode of the storage capacitor; The second transistor has one electrode connected to a reference voltage and the other electrode connected to the gate electrode of the driving transistor and one electrode of the storage capacitor; A third transistor, one electrode of which is connected to the anode electrode of the light-emitting element, and the other electrode of which is connected to a reset voltage; A fourth transistor, one electrode of which is connected to a high-potential drive voltage, and the other electrode of which is connected to the drain electrode of the drive transistor; A fifth transistor, one electrode of which is connected to the source electrode of the driving transistor, and the other electrode of which is connected to the anode electrode of the light-emitting element; and A sixth transistor, one electrode of which is connected to the reference voltage, and the other electrode of which is connected to the other electrode of the compensation capacitor, and In this context, when the second transistor is in the on state, the on period of the fourth transistor is defined as the sampling period, and the sampling period is changed by controlling the on time of the fourth transistor according to the brightness band.

12. The display device according to claim 11, wherein, The brightness band is divided into multiple bands representing a brightness range from low to high brightness, and the sampling period is set separately for each of the multiple bands.

13. The display device according to claim 12, wherein, As the sampling period transitions from low brightness to high brightness, it is gradually changed to have a longer duration.

14. The display device according to claim 13, wherein, For the low brightness band of 10 nits, the sampling period is set to 6H, and for the high brightness band of 1200 nits, the sampling period is set to 14H.

15. The display device according to claim 11, wherein, The driving transistor, the first transistor, the second transistor, the third transistor, the fifth transistor, and the sixth transistor are N-type thin-film transistors, and the fourth transistor is a P-type thin-film transistor.

16. The display device according to claim 11, wherein, When the second transistor, the third transistor, and the fifth transistor are in the on state, the initialization period is defined as the period from the on time of the sixth transistor to the off time of the fifth transistor.

17. The display device according to claim 16, wherein, During the initialization period, the gate electrode of the driving transistor and the other electrode of the compensation capacitor are initialized to the reference voltage, and the anode electrode of the light-emitting element and the source electrode of the driving transistor are initialized to the reset voltage.

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