Display panel and display device comprising a narrow frame

Abstract

A display device and a display panel are provided. The display device includes: a display panel including a first bezel region and a second bezel region, wherein a display region is located between the first bezel region and the second bezel region; a gate driver disposed in the first bezel region along a first direction; a source driver disposed in the second bezel region along the first direction; a plurality of gate clock supply lines disposed extending in the first bezel region along the first direction and configured to supply a gate clock to the gate driver; a gate output link line extending in an output link region of the display region along a second direction intersecting the first direction and connecting a gate output of the gate driver based on the gate clock to a gate line of the display panel; and a gate clock link line extending in a clock link region of the display region along the second direction and transmitting the gate clock to the gate clock supply line.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of Korean Patent Application No. 10-2025-0011683, filed on January 24, 2025, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] This disclosure relates to display devices, and more particularly to display devices including, but not limited to, narrow bezels. Background Technology

[0004] In display devices, there are known in-panel gate driver (GIP) types in which the gate driver is located in the bezel area (e.g., the left bezel area and / or the right bezel area).

[0005] However, in conventional GIP types, the RC delay of the gate clock increases due to the very large panel load, such as RC load, applied to each gate clock line. When the RC delay of the gate clock increases, the gate output may become distorted.

[0006] Such limitations are particularly pronounced in large-screen display devices.

[0007] The descriptions provided in the discussion of the related art section should not be assumed to be prior art simply because they are mentioned in or associated with this section. The discussion of the related art section may include information describing one or more aspects of the subject art, and the descriptions in this section do not limit the invention. Summary of the Invention

[0008] In order to overcome the above-mentioned limitations of the related technologies, one aspect of the present disclosure is to provide a display device that can reduce the RC delay of the gate clock in the display device.

[0009] To achieve these objectives and other advantages, and for the purposes of this disclosure, as embodied and broadly described herein, a display device includes: a display panel including a first border region and a second border region disposed facing each other, a display area including pixels between the first border region and the second border region; a plurality of gate drivers disposed along a first direction in the first border region; a plurality of source drivers disposed along the first direction in the second border region; a plurality of gate clock supply lines disposed extending along the first direction in the first border region and configured to supply gate clocks to the gate drivers; a plurality of gate output link lines extending along a second direction intersecting the first direction in an output link region of the display area and configured to connect gate outputs of the plurality of gate drivers based on the gate clocks to gate lines of the display panel; and a plurality of gate clock link lines extending along the second direction in a clock link region of the display area and configured to transmit externally input gate clocks to the plurality of gate clock supply lines.

[0010] In another aspect of this disclosure, a display panel is provided, comprising: a first border region and a second border region disposed facing each other, wherein a display area including pixels is located between the first border region and the second border region; a plurality of gate drivers disposed along a first direction in the first border region; a plurality of source drivers disposed along the first direction in the second border region; a plurality of gate clock supply lines disposed extending along the first direction in the first border region and configured to supply gate clock to the gate drivers; and a plurality of gate output links. Multiple gate output link lines extend in the output link region of the display area along a second direction intersecting the first direction and are configured to connect the gate outputs of multiple gate drivers based on the gate clock to the gate lines of the display panel; and multiple gate clock link lines extend in the clock link region of the display area along the second direction and are configured to transmit an externally input gate clock to multiple gate clock supply lines, wherein each of the multiple gate drivers includes multiple gate units configured to generate gate outputs of different phases and supply the gate outputs to the corresponding gate lines of the display panel. Attached Figure Description

[0011] The accompanying drawings may be included to provide a further understanding of this disclosure and may be incorporated into and constitute a part of this disclosure. The drawings illustrate exemplary embodiments of this disclosure and, together with the specification, serve to illustrate various principles of this disclosure. In the drawings:

[0012] Figure 1 A display device according to an exemplary embodiment of the present disclosure is shown;

[0013] Figure 2A and Figure 2B The pixel circuit and its driving timing are shown;

[0014] Figure 3 An example is shown where the clock link region is set between two adjacent output link regions;

[0015] Figure 4A and Figure 4B Another example is shown where the clock link region is set between two adjacent output link regions;

[0016] Figure 5 An example of the arrangement of the gate clock link is shown;

[0017] Figure 6 Another example of the gate clock link arrangement is shown;

[0018] Figure 7 An example is shown in which the starting carry transfer direction of the gate driver according to an exemplary embodiment is set to be opposite to each other relative to the center portion of the notch;

[0019] Figure 8 An example is shown in which the starting carry transfer direction of the gate drivers according to the comparative example is set to be the same as each other;

[0020] Figure 9 An example is shown where the contact positions of a low-resistance-high-resistance bilayer are set differently to compensate for position-based RC delay bias in the gate output; and

[0021] Figure 10 and Figure 11 The principle of compensating for the RC delay deviation between the gate output of gate unit GU1 and the gate output of gate unit GU1676 is described. Detailed Implementation

[0022] In the following description, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification, when adding reference numerals to elements in each drawing, it should be noted that the same reference numerals used to denote the same elements in other drawings may be used for the same elements. In the following description, detailed descriptions of related known functions or configurations will be omitted or may be provided briefly when it is determined that such detailed descriptions would unnecessarily obscure the essential points of the present disclosure.

[0023] The same reference numerals refer to the same elements. Furthermore, for ease of description, the thickness, ratios, and dimensions of each element described herein may be shown as partially enlarged or reduced. For ease of description, the scale of each element shown in the accompanying drawings of this disclosure may differ from the actual scale and is not limited to the scales shown in the drawings.

[0024] In this disclosure, when any element (or region, layer, portion, etc.) is described as being “on”, “connected to”, or “coupled to” another element, this may mean that the element may be directly connected to or coupled to the other element, or that a third element may be disposed therein.

[0025] The term “and / or” can include all one or more combinations that can be defined by the related elements connected by the term.

[0026] The terms used in the first and second instances can be used to describe various elements, but the elements should not be limited by the terms. Terms may be used only for the purpose of distinguishing one element from another. For example, without departing from the technical concept and scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Singular terms may include plural forms unless otherwise indicated.

[0027] The terms “below,” “under,” “above,” “next to,” “adjacent to,” and “above” can be used to describe the relationships between the elements shown in the accompanying drawings. The terms can be relative concepts and can be described relative to the directions shown in the drawings. For example, one or more other elements may be positioned between the elements described by these terms unless “exactly” or “directly” is used. The spatially relative terms “below,” “under,” “below,” “above,” “next to,” “adjacent to,” and “above” can be used herein to readily describe the relationship between one device or element shown in the accompanying drawings and other devices or elements. Thus, for example, with respect to a first device or element, “below” and “under” can be contrasted with “above” and “above.”

[0028] It should be understood that spatial relative terms are terms that include different orientations of elements in use or operation, in addition to those shown in the figures. For example, if a device or element in the figures is flipped, a device or element described as being "below" or "under" other elements may be placed "above" or "on top" other elements. Thus, the exemplary term "below" can include both "below" and "above". Similarly, the exemplary terms "above" or "on top" can include both "above" and "below".

[0029] It should be understood that "include", "comprise", "including" or "comprising" may specify attributes, regions, fixed numbers, steps, processes, elements and / or components, but does not exclude other attributes, regions, fixed numbers, steps, processes, elements and / or components.

[0030] As will be fully understood by those skilled in the art, the features of the various exemplary embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may interoperate with each other and be technically driven in various ways. The exemplary embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0031] Figure 1 A display device according to an exemplary embodiment of the present disclosure is shown.

[0032] like Figure 1 As shown, a display device according to an exemplary embodiment of the present disclosure may include a display panel PNL, a data driver SIC, gate drivers GIP#1 to GIP#5, and a timing controller TCON.

[0033] The display panel PNL may include a display area (active area) AA for displaying images and a non-display area (non-active area) serving as a border area. The non-display area may be set outside the display area AA along the edge of the display panel PNL.

[0034] The display area AA can display the input image corresponding to the image data D-DATA, and the non-display area can include the border area of ​​the display panel PNL where no image is displayed. The border area can include a first border area BZ1 and a second border area BZ2, which are positioned facing each other, with the display area AA located between the first border area BZ1 and the second border area BZ2. Figure 1In the second direction Y shown, the first border region BZ1 can be called the upper border region BZ1, and the second border region BZ2 can be called the lower border region BZ2.

[0035] In the display area AA, multiple data lines extending along the second direction Y ( Figure 1 (Not shown in the image) can intersect with multiple gate lines GL#1 to GL#n extending along the first direction X, and Figure 2A The pixel circuit shown can be positioned in each intersection region defined by the intersections of multiple data lines and multiple gate lines. For example, the pixel circuit can be connected to a data line and a gate line. A gate line may include a first scan line, a second scan line, and an emitter line. In this case, a gate output supplied to a gate line may include a first scan signal, a second scan signal, and an emitter signal.

[0036] In the display area AA, pixels that are adjacent to each other along the first direction X can form a pixel row, and pixels that are adjacent to each other along the second direction Y can form a pixel column. Multiple pixel rows and multiple pixel columns can be set in the display area AA.

[0037] Multiple pixels can be grouped to form a unit pixel. A unit pixel can be configured to implement various colors. When the pixel group used for color implementation is limited to a unit pixel, a unit pixel can be configured to include red (R) pixels, green (G) pixels, and blue (B) pixels, but is not limited to these, and can be configured to include red (R) pixels, green (G) pixels, blue (B) pixels, and white (W) pixels.

[0038] Each pixel may include a light-emitting diode (LED), such as an OLED, as a light-emitting device. The OLED may include an anode electrode, a cathode electrode, and an organic compound layer formed between the anode and cathode electrodes. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emitter layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a pixel current flows in the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) can move to the emitter layer (EML) to generate excitons, and thus, the emitter layer (EML) can emit visible light, but is not limited to this. Furthermore, the organic compound layer may be replaced with an inorganic compound layer.

[0039] Thin-film transistors can be included in pixel circuits, and thin-film transistors can be implemented as comprising low-temperature polycrystalline silicon (LTPS) and / or oxide.

[0040] Gate drivers GIP#1 to GIP#5 can be configured in multiples along the first direction X in the upper frame region BZ1. Gate drivers GIP#1 to GIP#5 can generate gate outputs to be supplied to gate lines GL#1 to GL#n based on a multi-feed scheme, using the gate timing control signal GDC input from the timing controller TCON.

[0041] Each of the gate drivers GIP#1 to GIP#5 may include n gate cells GU1 to GUn to drive n gate lines GL#1 to GL#n. The n gate cells GU1 to GUn can generate gate outputs of different phases and can supply gate outputs to gate lines GL#1 to GL#n.

[0042] To achieve a multi-feed scheme, gate outputs of the same phase can be supplied from GIP#1, GIP#2, GIP#3, GIP#4 and GIP#5 to different positions on the same gate line GL#1 to GL#n.

[0043] For example, the first gate output generated by the gate unit GU1 of gate drivers GIP#1, GIP#2, GIP#3, GIP#4, and GIP#5 can be supplied to five different locations of the first gate line GL#1; the second gate output generated by the gate unit GU2 of gate drivers GIP#1, GIP#2, GIP#3, GIP#4, and GIP#5 can be supplied to five different locations of the second gate line GL#2; and the third gate output generated by the gate unit GU3 of gate drivers GIP#1, GIP#2, GIP#3, GIP#4, and GIP#5 can be supplied to five different locations of the gate line GL#3. Similarly, the nth gate output generated by the gate unit GUn of gate drivers GIP#1, GIP#2, GIP#3, GIP#4, and GIP#5 can be supplied to five different locations of the nth gate line GL#n. Based on such multi-feeding, the panel position-based RC delay deviation of gate outputs with the same phase can be reduced.

[0044] Each of the source driver SICs can be implemented as an integrated circuit (IC), mounted on a conductive film FLM and bonded to the lower bezel region BZ2. Multiple source driver SICs can be arranged in the lower bezel region BZ2 along a first direction X. The source driver SICs can be positioned facing gate drivers GIP#1 to GIP#5, with the display area AA located between the source driver SICs and gate drivers GIP#1 to GIP#5. Gate drivers GIP#1 to GIP#5 and source driver SICs can be separately arranged in the upper bezel region BZ1 and the lower bezel region BZ2, thus preventing excessive widening of the bezel region in either the upper or lower portion.

[0045] Each of the source driver SICs can convert image data D-DATA into a data voltage based on the source timing control signal SDC input from the timing controller TCON, and can supply the data voltage to the data lines of the display panel PNL. Each of the source driver SICs may include a shift register, a latch, a digital-to-analog converter (DAC), and an output buffer.

[0046] Multiple gate clock supply lines CLK-SL can be configured in the upper frame region BZ1. These multiple gate clock supply lines CLK-SL can be configured to extend along a first direction X in the upper frame region BZ1, and can supply the gate clock for gate output to gate drivers GIP#1 to GIP#5.

[0047] In addition to the pixel area containing pixel circuits, the display area AA may also include an output link area (see...). Figure 3 AVL) and clock link area (see AVL) and clock link area (see AVL) Figure 3 ALK).

[0048] Gate output links VL#1 to VL#n can be disposed in the output link region AVL. Gate output links VL#1 to VL#n can extend along a second direction Y intersecting the first direction X, and can connect the gate outputs of gate drivers GIP#1 to GIP#5 to the gate lines GL#1 to GL#n of the display panel PNL. Gate output links VL#1 to VL#n can be multiple times connected to different locations on the same gate line. Gate outputs of the same phase can be supplied to the same gate line through multiple connected gate output links VL#1 to VL#n.

[0049] For example, the first gate output generated by the gate unit GU1 of gate drivers GIP#1, GIP#2, GIP#3, GIP#4 and GIP#5 can be supplied to five different positions of the first gate line GL#1 through the first gate output link line VL#1; the second gate output generated by the gate unit GU2 of gate drivers GIP#1, GIP#2, GIP#3, GIP#4 and GIP#5 can be supplied to five different positions of the second gate line GL#2 through the second gate output link line VL#2; and the third gate output generated by the gate unit GU3 of gate drivers GIP#1, GIP#2, GIP#3, GIP#4 and GIP#5 can be supplied to five different positions of the third gate line GL#3 through the third gate output link line VL#3. Similarly, the nth gate output generated by the gate units GUn of gate drivers GIP#1, GIP#2, GIP#3, GIP#4 and GIP#5 can be supplied to five different locations of the nth gate line GL#n via the nth gate output link line VL#n.

[0050] The gate clock link line CLK-LINK can be located in the clock link region. The gate clock link line CLK-LINK can be configured to extend along the second direction Y and can transmit the gate clock from an externally input gate clock to the gate clock supply line CLK-SL located in the upper frame region BZ1.

[0051] Multiple gate clock input lines CLK-IL can also be configured in the lower border region BZ2. The gate clock input lines CLK-IL can be configured to extend along a first direction X in the lower border region BZ2 and can be connected to the gate clock link line CLK-LINK in the clock link region. The gate clock input lines CLK-IL can receive the gate clock from an external source and then transmit the gate clock to the gate clock link line CLK-LINK.

[0052] The gate clock link line CLK-LINK, located in the clock link area of ​​the display area AA, can be multi-connected to different locations of the same clock supply line CLK-SL located in the first frame area BZ1. Gate clocks of the same phase can be transmitted to the same clock supply line CLK-SL located in the upper frame area BZ1 via the multi-connected gate clock link line CLK-LINK.

[0053] Because the panel load is distributed through a multi-position connection configuration of the gate clock link CLK-LINK for the same clock supply line CLK-SL, the RC delay deviation of gate clocks with the same phase based on panel position can be reduced. The gate clock link CLK-LINK used to reduce the RC delay deviation of gate clocks with the same phase based on panel position can be a component that cannot be predicted from GIP-type display devices of related technologies.

[0054] The timing controller TCON can supply digital image data (D-DATA) transmitted from the host system to the source driver SIC. The timing controller TCON can receive timing signals such as vertical synchronization signal, horizontal synchronization signal, data enable signal, and dot clock from the host system to generate timing control signals for controlling the operation timing of the source driver SIC and gate drivers GIP#1 to GIP#5.

[0055] The timing controller TCON can generate gate timing control signals GDC for controlling the operating timing of gate drivers GIP#1 to GIP#5 and source timing control signals SDC for controlling the operating timing of source driver SIC.

[0056] The host system can be an application processor (AP) used in mobile devices, wearable devices, virtual / augmented reality (VR / AR) devices, ambient smart devices, and in-vehicle devices. Furthermore, the host system can be a motherboard for television systems, set-top boxes, navigation systems, personal computers, and home theater systems, but is not limited to these.

[0057] Figure 2A and Figure 2B The pixel circuit and its driving timing are shown.

[0058] like Figure 2A As shown, a pixel circuit according to an exemplary embodiment of this disclosure may include transistors Ta, Tb, Tc, Td, and Te, a storage capacitor Cst, a driving transistor DT, and a light-emitting device OLED. Transistors Ta, Tb, Tc, Td, and Te, the storage capacitor Cst, and the driving transistor DT may be connected to the light-emitting device OLED. Figure 2A The example shown represents a 6T1C structure with six transistors and one capacitor, but embodiments of this disclosure are not limited to this. For example, 2T1C, 3T1C, 4T1C, 4T2C, etc., are also possible. Furthermore, it may include more or fewer transistors and capacitors.

[0059] Transistor Ta may include a gate electrode that receives a first scan signal S1 via a first sub-scan line GLa, a first electrode that receives a data voltage Vdata via a data line DL, and a second electrode connected to a first node N1. Transistor Ta can transmit the data voltage Vdata to the first node N1 in response to the first scan signal S1 at an on-level.

[0060] The storage capacitor Cst can be connected between the first node N1 and the second node N2, and can store the voltage difference between the voltage of the first node N1 and the voltage of the second node N2.

[0061] The driving transistor DT may include a gate electrode connected to the second node N2, a first electrode receiving a high-level driving voltage VDD, and a second electrode electrically connected to the light-emitting device OLED. The second electrode of the driving transistor DT may be electrically connected to the anode electrode of the light-emitting device OLED. The driving transistor DT may be supplied with a high-level driving voltage VDD to generate a driving current corresponding to the voltage of the second node N2. The magnitude of the driving current may vary depending on the voltage of the second node N2.

[0062] The Tb transistor may include a gate electrode that receives a second scan signal S2 via a second sub-scan line GLb, a second electrode connected to the driving transistor DT and electrically connected to the light-emitting device OLED, and a second electrode connected to the second node N2. The Tb transistor can electrically connect the second electrode of the driving transistor DT to the second node N2 in response to the on-level second scan signal S2. That is, when the Tb transistor is on, the second electrode and the gate electrode of the driving transistor DT can be short-circuited therebetween, and therefore, the driving transistor DT can operate like a diode.

[0063] The transistor Tc may include a gate electrode for receiving a transmit signal EM via a transmit line GLC, a first electrode for receiving a reference voltage Vref, and a second electrode connected to a first node N1. The transistor Tc may supply the reference voltage Vref to the first node N1 in response to a conduction-level transmit signal EM to initialize the first node N1.

[0064] The transistor Td may include a gate electrode for receiving the emission signal EM, a first electrode connected to the second electrode of the driving transistor DT, and a second electrode connected to the anode electrode of the light-emitting device OLED. The transistor Td can supply the driving current generated by the driving transistor DT to the light-emitting device OLED in response to the on-level emission signal EM.

[0065] The transistor Te may include a gate electrode that receives a second scan signal S2, a first electrode that receives a reference voltage Vref, and a second electrode connected to the anode electrode of the light-emitting device OLED. The transistor Te may supply the reference voltage Vref to the anode electrode of the light-emitting device OLED in response to the second scan signal S2 at an on-level, thereby initializing the anode electrode of the light-emitting device OLED.

[0066] like Figure 2B As shown, the operation sequence of the pixel circuit may include an initialization period P1, a programming period P2, a holding period P3, and an emission period P4.

[0067] During the initialization period P1, the second scan signal S2 and the transmit signal EM can be input at the on level, and the first node N1, the second node N2 and the anode electrode of the light-emitting device OLED can be supplied with a reference voltage Vref, and thus can be initialized.

[0068] During programming phase P2, the threshold voltage Vth of the driving transistor DT can be sampled, and the data voltage Vdata can be programmed at the second node N2. Specifically, during programming phase P2, the first scan signal S1 and the second scan signal S2 can be input at an on level, and therefore, the data voltage Vdata can be supplied to the first node N1, and the voltage obtained by summing the driving voltage VDD and the threshold voltage Vth of the driving transistor DT can be supplied to the second node N2 and stored in the storage capacitor Cst.

[0069] During the hold period P3, the first scan signal S1 and the second scan signal S2, as well as the transmit signal EM, can be input at the off level, and therefore, the first node N1 and the second node N2 connected to the storage capacitor Cst can be floated.

[0070] During the emission period P4, the emission signal EM can be input at the on level, and therefore, the driving transistor DT can generate a driving current based on the voltage level of the second node N2 connected to the storage capacitor Cst to supply the driving current to the light-emitting device OLED.

[0071] Figure 3 An example is shown where the clock link region ALK is set between two adjacent output link regions AVL.

[0072] Reference Figure 3 Each gate unit GU1 or GUj (where j can be a natural number of 2 or greater) may include a first scan unit S1U that outputs a first scan signal S1, a second scan unit S2U that outputs a second scan signal S2, and a transmitter unit EMU that outputs a transmitter signal EM.

[0073] In the display area AA, when the output link area AVL with the first gate output link line VL#1 is adjacent to the output link area AVL with the second gate output link line VL#2, the pixel area APX with RGB pixel circuits, the clock link area ALK with the gate clock link line CLK-LINK, and another pixel area APX with RGB pixel circuits can be located between the output link areas AVL. Additionally, as... Figure 3 As shown, the clock link region ALK can be set between two adjacent pixel regions APX. The pixel region APX can be set between the corresponding output link region AVL and the corresponding clock link region ALK.

[0074] The first scan unit S1U included in the gate unit GU1 can selectively receive the four-phase first scan clocks S1CLK1 to S1CLK4 (i.e., as shown in the image). Figure 3Two first gate clocks (S1CLK1 to S1CLK4) shown on the left are used to generate a first scan signal S1, and then the first scan signal S1 can be supplied to the first sub-scan line GLa of the first gate line GL#1 through the output link VLa of the first gate output link VL#1.

[0075] The second scan unit S2U, included in the gate unit GU1, can selectively receive the five-phase second scan clocks S2CLK1 to S2CLK5 (i.e., as shown in the image). Figure 3 Two second gate clocks (S2CLK1 to S2CLK5) shown on the left are used to generate the second scan signal S2, and then the second scan signal S2 can be supplied to the second sub-scan line GLb of the first gate line GL#1 through the output link VLb of the first gate output link VL#1.

[0076] The transmitter unit EMU included in the gate unit GU1 can receive two-phase transmit clocks ECLK1 and ECLK2 (i.e., as shown in the image). Figure 3 ECLK1 to ECLK2 (shown on the left) are used to generate the transmit signal EM, and then the transmit signal EM can be supplied to the transmit line GLc of the first gate line GL#1 through the output link line VLc of the first gate output link line VL#1.

[0077] The first scan unit S1U included in the gate unit GUj can selectively receive the four-phase first scan clocks S1CLK1 to S1CLK4 (i.e., as shown in the image). Figure 3 Two first gate clocks (S1CLK1 to S1CLK4) shown on the right are used to generate the first scan signal S1, and then the first scan signal S1 can be supplied to the first sub-scan line GLa of the gate line GL#j through the output link VLa of the gate output link VL#j.

[0078] The second scan unit S2U included in the gate unit GUj can selectively receive the five-phase second scan clocks S2CLK1 to S2CLK5 (i.e., as shown in the image). Figure 3 Two second gate clocks (S2CLK1 to S2CLK5) shown on the right are used to generate the second scan signal S2, and then the second scan signal S2 can be supplied to the second sub-scan line GLb of the gate line GL#j through the output link line VLb of the gate output link line VL#j.

[0079] The transmitter unit EMU included in the gate cell GUj can receive two-phase transmit clocks ECLK1 and ECLK2 (i.e., as shown in the image). Figure 3ECLK1 to ECLK2 (shown on the right) are used to generate the transmit signal EM, and then the transmit signal EM can be supplied to the emitter line GLc of the gate line GL#j through the output link line VLc of the gate output link line VL#j.

[0080] The four-phase first scan clocks S1CLK1 to S1CLK4, the five-phase second scan clocks S2CLK1 to S2CLK5, and the two-phase transmit clocks ECLK1 and ECLK2 can be supplied to the gate driver via gate clock link lines CLK-LINK in the multiple clock link areas ALK of the display area AA. For example, the two-phase transmit clocks ECLK1 and ECLK2 can be supplied to the corresponding cells of gate cells GU1 and GUj via the gate clock supply line (not shown) in the upper bezel area through the gate clock link lines CLK-LINK in the clock link area ALK. It should be noted that the description of gate cells GU1 and GUj is merely exemplary and can be similarly applied to other gate cells.

[0081] Figure 4A and Figure 4B Another example is shown where the clock link region is set between two adjacent output link regions.

[0082] Reference Figure 4A and Figure 4B Each gate unit GU2j, GU3j or GU4j may include a first scan unit S1U that outputs a first scan signal S1, a second scan unit S2U that outputs a second scan signal S2, and a transmitter unit EMU that outputs a transmitter signal EM.

[0083] like Figure 4A As shown, in the display area AA, when the output link area AVL with the second gate output link line VL#2j is adjacent to the output link area AVL with the third gate output link line VL#3j, the pixel area APX with RGB pixel circuits, the clock link area ALK with the gate clock link line CLK-LINK, and another pixel area APX with RGB pixel circuits can be located between the output link areas AVL. Additionally, as... Figure 4A As shown, the clock link region ALK can be set between two adjacent pixel regions APX.

[0084] In addition, such as Figure 4BAs shown, in the display area AA, when the output link area AVL with the third gate output link line VL#3j is adjacent to the output link area AVL with the fourth gate output link line VL#4j, the pixel area APX with RGB pixel circuits, the clock link area ALK with the gate clock link line CLK-LINK, and another pixel area APX with RGB pixel circuits can be located between the output link areas AVL. Additionally, as... Figure 4B As shown, the clock link region ALK can be set between two adjacent pixel regions APX.

[0085] The first scan unit S1U included in the gate unit GU2j can selectively receive the four-phase first scan clocks S1CLK1 to S1CLK4 (i.e., as shown in the image). Figure 4A Two first gate clocks (S1CLK1 to S1CLK4) shown on the left are used to generate a first scan signal S1, and then the first scan signal S1 can be supplied to the first sub-scan line GLa of gate line GL#2j through the output link VLa of the second gate output link VL#2j.

[0086] The second scan unit S2U, included in the gate unit GU2j, can selectively receive the five-phase second scan clocks S2CLK1 to S2CLK5 (i.e., as shown in the image). Figure 4A Two second gate clocks (S2CLK1 to S2CLK5 shown on the left) are used to generate the second scan signal S2, and then the second scan signal S2 can be supplied to the second sub-scan line GLb of the gate line GL#2j through the output link line VLb of the second gate output link line VL#2j.

[0087] The transmitter unit EMU included in the gate cell GU2j can receive two-phase transmit clocks ECLK1 and ECLK2 (i.e., as shown in the image). Figure 4A ECLK1 to ECLK2 (shown on the left) are used to generate the transmit signal EM, and then the transmit signal EM can be supplied to the transmit line GLc of the gate line GL#2j through the output link line VLc of the second gate output link line VL#2j.

[0088] The first scan unit S1U included in the gate unit GU3j can selectively receive the four-phase first scan clocks S1CLK1 to S1CLK4 (i.e., as shown in the image). Figure 4A Two first gate clocks (S1CLK1 to S1CLK4) shown on the right are used to generate the first scan signal S1, and then the first scan signal S1 can be supplied to the first sub-scan line GLa of the gate line GL#3j through the output link VLa of the third gate output link VL#3j.

[0089] The second scan unit S2U included in the gate unit GU3j can selectively receive the five-phase second scan clocks S2CLK1 to S2CLK5 (i.e., as shown in the image). Figure 4A Two second gate clocks (S2CLK1 to S2CLK5) shown on the right are used to generate the second scan signal S2, and then the second scan signal S2 can be supplied to the second sub-scan line GLb of the gate line GL#3j through the output link VLb of the third gate output link VL#3j.

[0090] The transmitter unit EMU included in the gate cell GU3j can receive two-phase transmit clocks ECLK1 and ECLK2 (i.e., as shown in the image). Figure 4A ECLK1 to ECLK2 (shown on the right) are used to generate the transmit signal EM, and then the transmit signal EM can be supplied to the emitter line GLc of the gate line GL#3j through the output link VLc of the third gate output link VL#3j.

[0091] The first scan unit S1U included in the gate unit GU4j can selectively receive the four-phase first scan clocks S1CLK1 to S1CLK4 (i.e., as shown in the image). Figure 4B Two first gate clocks (S1CLK1 to S1CLK4) shown on the left are used to generate the first scan signal S1, and then the first scan signal S1 can be supplied to the first sub-scan line GLa of the gate line GL#4j through the output link VLa of the fourth gate output link VL#4j.

[0092] The second scanning unit S2U included in GU4j can selectively receive the five-phase second scanning clocks S2CLK1 to S2CLK5 (i.e., as shown in the image). Figure 4B Two second gate clocks (S2CLK1 to S2CLK5 shown on the left) are used to generate the second scan signal S2, and then the second scan signal S2 can be supplied to the second sub-scan line GLb of the gate line GL#4j through the output link VLb of the fourth gate output link VL#4j.

[0093] The transmitter unit EMU included in GU4j can receive two-phase transmit clocks ECLK1 and ECLK2 to generate a transmit signal EM, and then the transmit signal EM can be supplied to the transmitter line GLc of the gate line GL#4j through the output link line VLc of the fourth gate output link line VL#4j.

[0094] The four-phase first scan clocks S1CLK1 to S1CLK4, the five-phase second scan clocks S2CLK1 to S2CLK5, and the two-phase transmit clocks ECLK1 and ECLK2 can be supplied to the gate driver through the gate clock link lines CLK-LINK set in the multiple clock link areas ALK of the display area AA.

[0095] For example, such as Figure 4A In the process, the four-phase first scan clocks S1CLK1 to S1CLK4 can be supplied to the corresponding cells of gate cells GU2j and gate cells GU3j via the gate clock supply line (not shown) in the upper frame area through the gate clock link line CLK-LINK set in the clock link area ALK.

[0096] In addition, such as Figure 4B In the process, the five-phase second scan clocks S2CLK1 to S2CLK5 can be supplied to the corresponding cells of gate cells GU3j and gate cells GU4j via the gate clock supply line (not shown) in the upper frame area through the gate clock link line CLK-LINK set in the clock link area ALK.

[0097] Figure 5 An example of the arrangement of the gate clock link is shown.

[0098] Reference Figure 5 The gate clock link line CLK-LINK, located in the clock link area ALK of the display area AA, can be connected to multiple locations of the same clock supply line located in the upper bezel area BZ1. Gate clocks S1CLK, S2CLK, and ECLK of the same phase can be transmitted to the same clock supply line CLK-SL located in the upper bezel area BZ1 through the multiple-connected gate clock link line CLK-LINK, and thus, the RC load of the gate clock line can be distributed.

[0099] One of the clock link regions ALK can be set between two adjacent output link regions AVL for multi-point arrangement of the gate clock link line CLK-LINK in the display region AA.

[0100] In each of the clock link areas ALK within the display area AA, a first power line and a second power line may be provided to which a high-level drive voltage VDD is supplied, wherein the gate clock link line CLK-LINK is located between the first power line and the second power line. The high-level drive voltage VDD may be a high-level power voltage supplied to the pixel circuit. The first power line and the second power line may be located in the second direction Y.

[0101] The first and second power lines can be positioned between one of the data lines of the display panel and at least one of the gate clock link lines (CLK-LINK). Each of the first and second power lines prevents the gate clock link line (CLK-LINK) from being positioned adjacent to a data line, and therefore minimizes the coupling effect between the data line and the gate clock link line (CLK-LINK). Consequently, distortion of the gate clock due to coupling noise caused by potential changes in each of the data lines can be prevented.

[0102] Figure 6 Another example of the arrangement of the gate clock link is shown.

[0103] Reference Figure 6 This can be omitted in the bottom border area BZ2. Figure 1 The gate clock input line CLK-IL can be used, thus allowing for a further reduction in the lower bezel region BZ2. Alternatively, multiple gate clock links can extend further into the second bezel region BA2 and be connected to an external clock source via a conductive film. In this case, the gate clock link CLK-LINK can extend further into the lower bezel region BZ2, the source driver SiC can be mounted on the conductive film FLM, and the gate clock link CLK-LINK can be connected to an external clock source (e.g., a timing controller) through the remaining dummy area.

[0104] Figure 7 An example is shown in which the starting carry transfer direction of the gate driver according to an exemplary embodiment of the present disclosure is set to be opposite to each other relative to the center portion of the notch. Figure 8 An example is shown in which the starting carry transfer direction of the gate drivers according to the comparative example is set to be the same as each other.

[0105] Reference Figure 7 and Figure 8 The gate driver can be connected to the gate line, wherein the first gate line GL#1, the 1100th gate line GL#1100 and the 1676th gate line GL#1676 are shown as examples.

[0106] Reference Figure 7 The display panel PNL may also include a notch at which the panel resolution (i.e., the vertical resolution of the panel) in the second direction Y is relatively small compared to the normal area. The notch may represent a recessed space of the display panel PNL. The notch may be symmetrical with respect to the center portion CENT in the first direction X.

[0107] The gate driver GIP can be divided into a first group of gate drivers G1-GIP disposed on a first side relative to the center portion CENT of the notch, and a second group of gate drivers G2-GIP disposed on a second side opposite to the first side relative to the center portion CENT of the notch. In the first group of gate drivers G1-GIP, the starting carry transfer direction VST for operation activation of the first group of gate drivers G1-GIP extends from the center portion CENT to the left edge portion 1EZ of the display panel PNL (as shown by the first carry transfer direction C-DIR1), and in the second group of gate drivers G2-GIP, the starting carry transfer direction VST for operation activation of the second group of gate drivers G2-GIP extends from the center portion CENT to the right edge portion 2EZ of the display panel PNL (as shown by the second carry transfer direction C-DIR2).

[0108] In this case, such as Figure 8 In this context, the starting carry transfer direction VST for operational activation of the first group of gate drivers G1-GIP is the same as the starting carry transfer direction VST for operational activation of the second group of gate drivers G2-GIP, and therefore a link-unable region XARY that cannot be connected between the gate output link line and the gate line can be formed near the notch NOTCH. (Refer to...) Figure 8 The starting carry transfer direction VST for the operation activation of all gate driver GIPs is from the right edge portion REZ of the display panel PNL to the left edge portion LEZ of the display panel PNL (as indicated by the carry transfer direction C-DIR).

[0109] The non-linkable region XARY can be supplied with gate outputs via multiple feeds through adjacent output link lines. However, since the non-linkable region XARY has a relatively large RC delay compared to the linkable region, the image quality of the non-linkable region XARY may be degraded.

[0110] On the other hand, such as Figure 7 In this context, when the starting carry transfer direction VST for the operation activation of the first group of gate drivers G1-GIP is opposite to the starting carry transfer direction VST for the operation activation of the second group of gate drivers G2-GIP, it is possible to avoid forming an unlinkable region XARY near the notch that cannot be connected between the gate output link line and the gate line.

[0111] The initial carry transfer direction VST of the first set of gate drivers G1-GIP can be from the center portion CENT of the notch toward the left edge portion 1EZ of the display panel PNL. Furthermore, the initial carry transfer direction VST of the second set of gate drivers G2-GIP can be from the center portion CENT of the notch toward the right edge portion 2EZ of the display panel PNL.

[0112] Figure 9 An example is shown where the contact positions of a low-resistance-high-resistance bilayer are set differently to compensate for position-based RC delay bias in the gate output.

[0113] Reference Figure 9 The gate unit GU1 can supply the first gate outputs S1, S2 and the transmit signal EM to the first gate line GL#1 (i.e., GLa, GLb and GLc) through the first gate output link line VL#1.

[0114] The gate unit GU800 can supply the 800 gate outputs S1, S2 and the transmit signal EM to the 800 gate line GL#800 (i.e., GLa, GLb and GLc) through the 800 gate output link line VL#800.

[0115] The gate unit GU1676 can supply the 1676 gate outputs S1, S2 and the transmit signal EM to the 1676 gate line GL#1676 (i.e., GLa, GLb and GLc) through the 1676 gate output link line VL#1676.

[0116] For example, when the gate output link is implemented as a single layer, the RC load applied to the gate output link can be greater than VL#1 in VL#800 and greater than VL#800 in VL#1676.

[0117] To compensate for the RC load difference between the gate output links, the lengths of the gate output links can be designed to be equal. Each of the gate output links can be designed as a double layer between a high-resistance link LM and a low-resistance link UM, and the contact positions of the high-resistance link LM and the low-resistance link UM can be set differently between the gate output links.

[0118] The resistance of the low-resistance link UM can be less than that of the high-resistance link LM, and the low-resistance link UM and the high-resistance link LM can overlap each other, with an insulating layer between them. The low-resistance link UM can comprise a low-resistance material, and the high-resistance link LM can comprise a high-resistance material. The low-resistance link UM and the high-resistance link LM can have the same linewidth. Alternatively, the low-resistance link UM and the high-resistance link LM can have different linewidths, which can be varied according to actual needs.

[0119] The first gate outputs S1, S2, and EM can be connected to the low-resistance link UM of the first gate output link VL#1. The high-resistance link LM of the first gate output link VL#1 can be connected to the first gate line GL#1 via the first contact portion CT1, and can be connected to the low-resistance link UM of the first gate output link VL#1 via the second contact portion CT2. In the first gate output link VL#1, the interval between the first contact portion CT1 and the second contact portion CT2, which define the RC load, can be DD1.

[0120] Gate outputs S1, S2, and EM of the 800th gate output line can be connected to the low-resistance link UM of the 800th gate output link VL#800. The high-resistance link LM of the 800th gate output link VL#800 can be connected to the 800th gate line GL#800 via the first contact portion CT1, and can be connected to the low-resistance link UM of the 800th gate output link VL#800 via the second contact portion CT2. In the 800th gate output link VL#800, the spacing between the first contact portion CT1 and the second contact portion CT2, which defines the RC load, can be DD2, which is less than DD1.

[0121] Gate outputs S1, S2, and EM of the 1676 gate output link can be connected to the low-resistance link UM of the 1676 gate output link VL#1676. The high-resistance link LM of the 1676 gate output link VL#1676 can be connected to the 1676 gate line GL#1676 via the first contact portion CT1, and can be connected to the low-resistance link UM of the 1676 gate output link VL#1676 via the second contact portion CT2. In the 1676 gate output link VL#1676, the spacing between the first contact portion CT1 and the second contact portion CT2, which defines the RC load, can be less than DD2 by DD3.

[0122] Since the spacing between the first contact portion CT1 and the second contact portion CT2 is designed differently between the gate output links such as DD1, DD2 and DD3, the RC load difference that occurs between the gate output links can be compensated.

[0123] Figure 10 and Figure 11 The principle of compensating for the RC delay deviation between the gate output of gate unit GU1 and the gate output of gate unit GU1676 is described.

[0124] Reference Figure 10 The total resistance Rt of the first gate output link line VL#1 used to transmit the gate output of the gate unit GU1 can be "R1+Rc1+R2+Rc2", the total capacitance Ct of the first gate output link line VL#1 can be "C1+C2+C3", and the total Rc can be "(R1+Rc1+R2+Rc2)". (C1+C2+C3)".

[0125] Reference Figure 11 The total resistance Rt of the 1676th gate output link line VL#1676 used to transmit the gate output of the gate unit GU1676 can be "R4+Rc1+R5+Rc2", the total capacitance Ct of the 1676th gate output link line VL#1676 can be "C1+C2+C3", and the total Rc can be "(R4+Rc1+R5+Rc2)". (C1+C2+C3)".

[0126] Reference Figure 10 and Figure 11 Since the total capacitance Ct of the first gate output link VL#1 is equal to the total capacitance Ct of the 1676th gate output link VL#1676, the RC load difference between the first gate output link VL#1 and the 1676th gate output link VL#1676 can be compensated when “R1+R2” and “R4+R5” are adjusted.

[0127] Therefore, when the gap DD1 between the first contact portion CT1 and the second contact portion CT2 is designed to be relatively large in the first gate output link line VL#1, and the gap DD3 between the first contact portion CT1 and the second contact portion CT2 is designed to be relatively small in the 1676 gate output link line VL#1676, "R1+R2" and "R4+R5" can be similar to each other, and the RC load difference between the first gate output link line VL#1 and the 1676 gate output link line VL#1676 can be compensated at a similar level.

[0128] The display device according to the exemplary embodiments of this disclosure can reduce the RC delay of the gate clock to improve display quality.

[0129] The effects of this disclosure are not limited to those shown in the examples above, and those skilled in the art can understand various other effects based on the contents included in the specification.

[0130] While this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made in the display device of this disclosure without departing from the technical concept and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: The display panel includes a first border area and a second border area that are arranged to face each other, wherein a display area including pixels is located between the first border area and the second border area. A plurality of gate drivers are disposed in the first border region along a first direction; Multiple source drivers are disposed in the second frame region along the first direction; Multiple gate clock supply lines are configured to extend along the first direction in the first frame region and to supply gate clocks to the multiple gate drivers. Multiple gate output links extend in the output link region of the display area along a second direction intersecting the first direction and are configured to connect the gate outputs of the multiple gate drivers based on the gate clock to the gate lines of the display panel; and Multiple gate clock links extend along the second direction in the clock link region of the display area and are configured to transmit the gate clock input from an external source to the multiple gate clock supply lines.

2. The display device according to claim 1, wherein, The multiple gate clock link lines disposed in the clock link area of ​​the display area are connected to different positions of the same clock supply line disposed in the first bezel area, and Gate clocks of the same phase are transmitted to the same clock supply line located in the first frame region via multiple interconnected gate clock link lines.

3. The display device according to claim 1, wherein, The plurality of gate clock link lines disposed in the clock link area of ​​the display area are also connected to a plurality of gate clock input lines disposed to extend along the first direction in the second frame area.

4. The display device according to claim 1, wherein, The multiple gate clock link lines extend further into the second frame region and are connected to an external clock source via a conductive film.

5. The display device according to claim 1, wherein, In the display area, One of the clock link regions is positioned between two adjacent output link regions, and The pixel region is set between the output link region and the corresponding clock link region.

6. The display device according to claim 1, wherein, Each of the plurality of gate drivers includes a plurality of gate units connected to the plurality of gate output links. The multiple gate output links are connected to different locations on the same gate line, and Gate outputs of the same phase are supplied to the same gate line through multiple gate output link lines with multiple connections.

7. The display device according to claim 1, wherein, In each clock link region of the display area, a first power line and a second power line are further configured to extend along the second direction, wherein the plurality of gate clock link lines are between the first power line and the second power line.

8. The display device according to claim 7, wherein, Each of the first power line and the second power line is disposed between one of the data lines of the display panel and at least one of the plurality of gate clock link lines.

9. The display device according to claim 1, wherein, The display panel also includes a notch, at which the panel resolution in the second direction is relatively smaller compared to the normal area. The plurality of gate drivers are divided into a first group of gate drivers disposed on a first side relative to the center portion of the notch, and a second group of gate drivers disposed on a second side opposite to the first side relative to the center portion of the notch. The starting carry transfer direction for activating the operation of the first group of gate drivers is opposite to the starting carry transfer direction for activating the operation of the second group of gate drivers.

10. The display device according to claim 9, wherein, The initial carry transfer direction of the first group of gate drivers is from the center portion of the notch toward the left edge portion of the display panel, and The starting carry transmission direction of the second group of gate drivers is from the center portion of the notch toward the right edge portion of the display panel.

11. The display device according to claim 1, wherein, Each of the plurality of gate output links includes: A low-resistance link line, the low-resistance link line being connected to one of the gate outputs of the plurality of gate drivers; and A high-resistance link line, which is connected to one of the gate lines of the display panel via a first contact portion and to the low-resistance link line via a second contact portion. Wherein, the resistance of the low-resistance link is less than the resistance of the high-resistance link, and The low-resistance link and the high-resistance link overlap each other, and an insulating layer is placed between the low-resistance link and the high-resistance link.

12. The display device according to claim 11, wherein, The low-resistance link and the high-resistance link have the same line width.

13. The display device according to claim 11, wherein, The first gate output link connects the gate output of the first gate unit to the first gate line of the display panel. The second gate output link connects the gate output of the second gate unit to the second gate line of the display panel, and The spacing between the first contact portion and the second contact portion in the second gate output link is different from the spacing between the first contact portion and the second contact portion in the first gate output link.

14. The display device according to claim 13, wherein, The spacing between the first contact portion and the second contact portion in the second gate output link is smaller than the spacing between the first contact portion and the second contact portion in the first gate output link.

15. A display panel, comprising: A first border area and a second border area are set to face each other, wherein a display area including pixels is located between the first border area and the second border area; A plurality of gate drivers are disposed in the first border region along a first direction; Multiple source drivers are disposed in the second frame region along the first direction; Multiple gate clock supply lines are configured to extend along the first direction in the first frame region and to supply gate clocks to the multiple gate drivers. Multiple gate output links extend in the output link region of the display area along a second direction intersecting the first direction and are configured to connect the gate outputs of the multiple gate drivers based on the gate clock to the gate lines of the display panel; and Multiple gate clock links extend along the second direction in the clock link region of the display area and are configured to transmit externally input gate clocks to the multiple gate clock supply lines. Each of the plurality of gate drivers includes a plurality of gate units, which are configured to generate gate outputs of different phases and supply the gate outputs to the corresponding gate lines of the display panel.

16. The display panel according to claim 15, wherein, Gate outputs of the same phase are supplied from the plurality of gate drivers to different locations on the same gate line, and In this configuration, gate clocks of the same phase are transmitted to the same clock supply line located in the first frame region through multiple interconnected gate clock link lines.

17. The display panel according to claim 15, wherein, Each of the plurality of gate output links includes: A low-resistance link line, the low-resistance link line being connected to one of the gate outputs of the plurality of gate drivers; and A high-resistance link line, which is connected to one of the gate lines of the display panel via a first contact portion and to the low-resistance link line via a second contact portion. Wherein, the resistance of the low-resistance link is less than the resistance of the high-resistance link, and The low-resistance link and the high-resistance link overlap each other, and an insulating layer is placed between the low-resistance link and the high-resistance link.

18. The display panel according to claim 17, wherein, The first gate output link connects the gate output of the first gate unit to the first gate line of the display panel. The second gate output link connects the gate output of the second gate unit to the second gate line of the display panel, and The spacing between the first contact portion and the second contact portion in the second gate output link is different from the spacing between the first contact portion and the second contact portion in the first gate output link.

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