Pixel circuit, display panel and display device

Abstract

This application discloses a pixel circuit, a display panel, and a display device. The pixel circuit includes a driving module, a first initialization module, a storage coupling module, and a reference signal writing module. The driving module is electrically connected to a light-emitting element. The first initialization module is connected between the control terminal and the first initialization signal terminal of the driving module. The reference signal writing module is connected between the reference signal terminal and a first terminal of the driving module. The storage coupling module is electrically connected to a second terminal of the driving module and is also electrically connected to the reference signal writing module. The operation of the pixel circuit includes a non-light-emitting stage and a light-emitting stage, the non-light-emitting stage including at least a compensation stage. During the compensation stage, the first initialization module and the reference signal writing module are turned on. According to the embodiments of this application, the stability of the pixel circuit is improved.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a pixel circuit, a display panel, and a display device. Background Technology

[0002] In display products, pixel circuits are used to drive light-emitting elements to emit light. Pixel circuits typically include TFTs (Thin Film Transistors) and capacitors. Light-emitting elements can typically include OLEDs (Organic Light-Emitting Diodes) or other types of light-emitting devices.

[0003] The stability of pixel circuits affects the light emission stability of light-emitting elements. Therefore, how to improve the stability of pixel circuits has been a technical problem that those skilled in the art have been working to solve. Summary of the Invention

[0004] This application provides a pixel circuit, a display panel, and a display device, which can improve the technical problem in the related art where noise introduced during the compensation stage causes deviations in the actual luminous brightness of the light-emitting element, affecting the luminous stability of the display.

[0005] In a first aspect, embodiments of this application provide a pixel circuit, including a driving module, a first initialization module, a storage coupling module, and a reference signal writing module; the driving module is electrically connected to a light-emitting element; the first initialization module is connected between the control terminal and the first initialization signal terminal of the driving module; the reference signal writing module is connected between the reference signal terminal and the first terminal of the driving module; the storage coupling module is electrically connected to the second terminal of the driving module, and the storage coupling module is electrically connected to the reference signal writing module; the operation of the pixel circuit includes a non-light-emitting stage and a light-emitting stage, the non-light-emitting stage including at least a compensation stage; in the compensation stage, the first initialization module and the reference signal writing module are turned on.

[0006] Secondly, embodiments of this application provide a pixel circuit, including: First light-emitting control transistor; The second light-emitting control transistor is electrically connected to the light-emitting element. A driving transistor is electrically connected to a second light-emitting control transistor and a first light-emitting control transistor. The storage capacitor is connected between the gate of the driving transistor and the second electrode of the driving transistor. The coupling capacitor has its first end connected to the second terminal of the driving transistor and its second end electrically connected to the reference signal terminal. The first initialization transistor is connected between the first initialization signal terminal and the gate of the driving transistor; During the compensation phase in the non-light-emitting phase, the first initialization transistor is turned on.

[0007] Thirdly, embodiments of this application provide a display panel including the pixel circuit described in the first or second aspect embodiments.

[0008] Fourthly, embodiments of this application provide a display device, including the display panel described in the third aspect embodiment.

[0009] According to the pixel circuit provided in the embodiments of this application, during the compensation stage, the power signal of the first power signal terminal is no longer introduced, but the reference signal of the reference signal terminal is introduced to set the second terminal of the driving module. The noise of the reference signal terminal is smaller than that of the first power signal terminal, which can reduce the instability of the pixel circuit caused by the external noise brought by the first power signal terminal, improve the potential stability of the second terminal of the driving module, and thus improve the working stability of the pixel circuit and the stability of the light emission brightness of the light-emitting element. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the first structure of the pixel circuit provided in the embodiments of this application; Figure 2 This is a first timing diagram of the pixel circuit provided in the embodiments of this application; Figure 3 This is a schematic diagram of a second structure of the pixel circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of the third structure of the pixel circuit provided in the embodiments of this application; Figure 5 This is a second timing diagram of the pixel circuit provided in the embodiments of this application; Figure 6 This is a schematic diagram of the fourth structure of the pixel circuit provided in the embodiments of this application; Figure 7 This is a schematic diagram of the fifth structure of the pixel circuit provided in the embodiments of this application; Figure 8 This is a schematic diagram of the sixth structure of the pixel circuit provided in the embodiments of this application; Figure 9 This is a schematic diagram of a display panel provided in an embodiment of this application; Figure 10 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0012] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0013] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0014] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0015] In the embodiments of this application, the term "electrical connection" can refer to two components being directly electrically connected, or it can refer to two components being electrically connected via one or more other components.

[0016] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0017] Oxide pixel circuits refer to pixel circuits built around oxide transistors. Taking an oxide pixel circuit as an example, in the non-light-emitting stage, the control terminal voltage of the driving module needs to be set to the initial voltage (such as Vref), and in the compensation stage, the threshold voltage of the driving module needs to be compensated. For example, the voltage at one end of the driving module is set to Vref-Vth, where Vth is the conduction threshold voltage of the driving module when it is turned on.

[0018] In related technologies, a high-level power signal is typically introduced into the first power signal terminal PVDD during the compensation phase to set the voltage at one end of the driving module to Vref-Vth. However, the power signal supplied through the power traces arranged in the display panel (connected to the first power signal terminal PVDD) is affected by the DC voltage drop (i.e., IR Drop) caused by the trace resistance, resulting in abnormal node potentials when the driving module sets the voltage at a certain end. Since the voltage at one end of the driving module directly affects the driving current during the light-emitting phase, it will ultimately lead to a deviation in the actual luminous brightness of the light-emitting element, affecting the luminous stability of the display product.

[0019] To address the aforementioned technical problems, embodiments of this application provide a pixel circuit, a display panel, and a display device. The embodiments of this application will be described below with reference to the accompanying drawings.

[0020] like Figure 1 As shown, the pixel circuit 10 provided in this application embodiment includes a driving module 11, a first initialization module 12, a storage coupling module 13, and a reference signal writing module 14.

[0021] The driving module 11 is electrically connected to the light-emitting element 20; the first initialization module 12 is connected between the control terminal and the first initialization signal terminal Vref of the driving module 11; the reference signal writing module 14 is connected between the reference signal terminal Vdc and the first terminal of the driving module 11; the storage coupling module 13 is electrically connected to the second terminal of the driving module 11, and the storage coupling module 13 is electrically connected to the reference signal writing module 14.

[0022] like Figure 2 As shown, the operation of the pixel circuit includes a non-light-emitting stage NE and a light-emitting stage E. The non-light-emitting stage E includes at least a compensation stage t1. In the compensation stage t1, the first initialization module 12 and the reference signal writing module 14 are turned on.

[0023] For example, the first terminal of the driving module 11 is electrically connected to the first node N1, and the first node N1 is electrically connected to the reference signal writing module 14. Additionally, the first node N1 can be electrically connected to the first power signal terminal PVDD via other modules. The control terminal of the driving module 11 is electrically connected to the second node N2, and the second node N2 is electrically connected to the first initialization module 12. The second terminal of the driving module 11 is electrically connected to the third node N3, and the third node N3 can be electrically connected to the first electrode of the light-emitting element 20 via other modules. The second electrode of the light-emitting element 20 is electrically connected to the second power signal terminal PVEE.

[0024] The reference signal writing module 14 includes a first terminal, a second terminal, and a control terminal. The first terminal of the reference signal writing module 14 is electrically connected to the reference signal terminal Vdc, the second terminal of the reference signal writing module 14 is electrically connected to the first terminal of the drive module 11, and the control terminal of the reference signal writing module 14 is electrically connected to the fourth gate line G4. The storage coupling module 13 can be electrically connected to any one of the first terminal, the second terminal, and the control terminal of the reference signal writing module 14. Figure 1 The diagram illustrates the electrical connection between the storage coupling module 13 and the second terminal of the reference signal writing module 14, but this is not intended to limit the scope of this application.

[0025] The control terminal of the first initialization module 12 can be electrically connected to the second gate line G2, and the control terminal of the reference signal writing module 14 can be electrically connected to the fourth gate line G4.

[0026] Please refer to the reference. Figure 1 and Figure 2 During the compensation phase t1, the second gate line G2 and the fourth gate line G4 provide a conduction level (high level), and the first initialization module 12 and the reference signal writing module 14 are turned on. The first initialization signal at the first initialization signal terminal Vref is transmitted to the control terminal of the drive module 11 via the first initialization module 12. The reference signal at the reference signal terminal Vdc is transmitted to the first terminal of the drive module 11 via the reference signal writing module 14. Thus, the signal at the second terminal of the drive module 11 can be set to Vref-Vth using the reference signal at the reference signal terminal Vdc, where Vref represents the voltage of the first initialization signal and Vth represents the conduction threshold voltage of the drive module 11.

[0027] According to the pixel circuit provided in the embodiments of this application, during the compensation stage, the power signal of the first power signal terminal PVDD is no longer introduced. Instead, the reference signal of the reference signal terminal Vdc is introduced to set the second terminal of the driving module 11. The noise of the reference signal terminal Vdc is smaller than the noise of the first power signal terminal PVDD, which can reduce the instability of the pixel circuit caused by the external noise brought by the first power signal terminal PVDD, improve the potential stability of the second terminal of the driving module 11, and thus improve the working stability of the pixel circuit and the stability of the light emission brightness of the light-emitting element.

[0028] In some embodiments, in conjunction with reference Figure 1 and Figure 2 The pixel circuit 10 also includes a first light-emitting control module 151, which is connected between the first power signal terminal PVDD and the first terminal of the driving module 11. The control terminal of the first light-emitting control module 151 is electrically connected to the first light-emitting control signal line EM1. During the non-light-emitting phase NE, the first light-emitting control signal line EM1 provides a cutoff level (low level), and the first light-emitting control module 151 is disconnected. The first light-emitting control module 151 remains disconnected throughout the entire non-light-emitting phase NE. The compensation phase t1 is located within the non-light-emitting phase NE, and the first light-emitting control module 151 is also disconnected during the compensation phase t1.

[0029] In this embodiment, during the compensation stage t1, the first initialization module 12 and the reference signal writing module 14 are turned on, and the first light emission control module 151 is turned off. This better ensures that when the second terminal of the driving module 11 is set, the power signal of the first power signal terminal PVDD will not be introduced. Instead, the signal of the reference signal terminal Vdc, which has lower noise, is used to set the second terminal of the driving module 11 to Vref-Vth, so as to better ensure the working stability of the pixel circuit.

[0030] In some embodiments, such as Figure 1 and Figure 2 As shown, the pixel circuit 10 may also include a data writing module 16, which is connected between the control terminal and the data signal terminal Vdata of the driving module 11. The control terminal of the data writing module 16 may be electrically connected to the first gate line G1.

[0031] The non-light-emitting phase NE also includes a data writing phase t2. In the data writing phase t2, the first gate line G1 provides a conduction level (high level), the data writing module 16 is turned on, and the data voltage at the data signal terminal Vdata is written to the control terminal of the driving module 11. Within the same non-light-emitting phase NE, the compensation phase t1 precedes the data writing phase t2. The end time of the compensation phase t1 is no later than the start time of the data writing phase t2.

[0032] During the compensation phase t1, the reference voltage of the reference signal terminal Vdc is used to set the second terminal of the drive module 11 to Vref-Vth; during the data writing phase t2, the data voltage of the data signal terminal Vdata is written to the control terminal of the drive module 11; this enables the drive current generated by the drive module 11 to be independent of the threshold voltage Vth, thereby improving the display uniformity of the display product.

[0033] The compensation phase t1 and the data writing phase t2 do not overlap, thus separating the threshold compensation of the driving module 11 from the data voltage writing at the data signal terminal Vdata, preventing mutual constraints between the compensation phase t1 and the data writing phase t2. For example, the duration of the compensation phase t1 is longer than the duration of the data writing phase t2, ensuring sufficient threshold compensation. Of course, in other embodiments, the duration of the data writing phase t2 can be longer than the duration of the compensation phase t1 to ensure sufficient data voltage writing. Alternatively, the duration of the data writing phase t2 can be equal to the duration of the compensation phase t1.

[0034] In addition, during the data writing phase t2, the second gate line G2 provides a cutoff level, and the first initialization module 12 is disconnected. In this way, when the data voltage of the data signal terminal Vdata is written to the control terminal of the drive module 11, the first initialization voltage of the first initialization signal terminal Vref will not be written to the control terminal of the drive module 11, and there will be no signal crosstalk at the control terminal of the drive module 11.

[0035] In some embodiments, during at least a portion of the compensation phase t1, the potential at the control terminal of the drive module 11 is greater than the potential at the second terminal of the drive module 11.

[0036] During compensation phase t1, the first initialization module 12 and the reference signal writing module 14 are turned on. The control terminal potential of the driving module 11 is Vref, the first terminal potential of the driving module 11 is Vdc, and the second terminal potential of the driving module 11 is Vref-Vth. The driving module 11 may include a driving transistor, which may be an N-type oxide transistor. The first initialization voltage of the first initialization signal terminal Vref is a positive voltage, the turn-on threshold voltage Vth of the driving transistor is greater than 0, and Vref > Vref-Vth.

[0037] In this embodiment, for oxide-type driving transistors, the second terminal of the driving transistor can be set using the reference signal terminal Vdc, which has lower noise. Compared to setting it using the first power supply signal terminal PVDD, which has higher noise, this improves the stability of the oxide pixel circuit.

[0038] In some embodiments, such as Figure 1 As shown, the storage coupling module 13 includes a storage unit 131 and a coupling unit 132. The storage unit 131 is connected between the control terminal and the second terminal of the drive module 11. The coupling unit 132 is connected between the second terminal of the drive module 11 and the reference signal writing module 14. The coupling unit 132 can be electrically connected to any one of the first terminal, the second terminal, and the control terminal of the reference signal writing module 14. Figure 1 Taking the electrical connection between the coupling unit 132 and the second terminal of the reference signal writing module 14 as an example, this is not intended to limit this application.

[0039] The storage unit 131 can be used to store the charge written to the control terminal of the drive module 11 to improve the potential stability of the control terminal of the drive module 11, thereby improving the stability of the drive current generated by the drive module 11.

[0040] During the compensation phase t1 and the light emission phase E, the driving module 11 is turned on, and the coupling unit 132 is equivalent to the driven module 11 being short-circuited. The potentials of the first and second terminals of the driving module 11 are clamped, which can reduce the risk of introducing external noise.

[0041] In some embodiments, such as Figure 1 As shown, the first end of the reference signal writing module 14 is electrically connected to the reference signal terminal Vdc, the second end of the reference signal writing module 14 is electrically connected to the first end of the drive module 11, and the control terminal of the reference signal writing module 14 is electrically connected to the fourth gate line G4; the first end of the coupling unit 132 is electrically connected to the second end of the drive module 11, and the second end of the coupling unit 132 is electrically connected to the reference signal writing module 14.

[0042] As an example, such as Figure 1 As shown, the second terminal of coupling unit 132 is electrically connected to the second terminal of reference signal writing module 14. In this example, the second terminal of coupling unit 132 is connected to the signal of reference signal terminal Vdc.

[0043] As another example, such as Figure 3 As shown, the second terminal of coupling unit 132 is electrically connected to the control terminal of reference signal writing module 14. In this example, the second terminal of coupling unit 132 is connected to the signal of the fourth gate line G4.

[0044] As yet another example, such as Figure 4 As shown, the second end of the coupling unit 132 is electrically connected to the first end of the reference signal writing module 14. In this example, the second end of the coupling unit 132 is connected to the signal of the reference signal terminal Vdc.

[0045] In some embodiments, such as Figure 1 or Figure 3 or Figure 4 As shown, the pixel circuit 10 may further include a second light-emitting control module 152, which is connected between the second end of the driving module 11 and the first electrode of the light-emitting element 20. For example, the first end of the second light-emitting control module 152 and the second end of the driving module 11 are connected to a third node N3, the second end of the second light-emitting control module 152 and the first electrode of the light-emitting element 20 are connected to a fourth node N4, and the control terminal of the second light-emitting control module 152 is electrically connected to the second light-emitting control signal line EM2.

[0046] Please refer to the reference. Figure 1 and Figure 2 At least during the compensation phase t1, the second light-emitting control signal line EM2 provides a cutoff level (low level), and the second light-emitting control module 152 is disconnected. This disconnects the second terminal of the driving module 11 from the first pole of the light-emitting element 20, i.e., the third node N3 and the fourth node N4 are disconnected. In this way, the signal of the fourth node N4 during the compensation phase t1 will not affect the setting effect of the second terminal of the driving module 11, so as to ensure that the driving module 11 can perform effective threshold compensation.

[0047] In some embodiments, please refer to the reference Figure 1 and Figure 2 or in conjunction with references Figure 4 and Figure 2 When the second end of the coupling unit 132 is electrically connected to the first or second end of the reference signal writing module 14, the second light emission control module 152 remains disconnected throughout the non-light emission phase NE.

[0048] During the compensation phase t1 within the non-light-emitting phase NE, the first initialization module 12 and the reference signal writing module 14 are turned on; throughout the entire non-light-emitting phase NE, the second light-emitting control module 152 remains off; this better ensures that when the second end of the driving module 11 is set, the signal of the fourth node N4 will not affect the setting effect of the second end of the driving module 11, so as to better ensure that the driving module 11 can perform effective threshold compensation.

[0049] In other embodiments, please refer to the references. Figure 3 and Figure 5 When the second end of the coupling unit 132 is electrically connected to the control end of the reference signal writing module 14, during the non-light emission phase NE and for at least a portion of the time period after the data writing phase t2, the second light emission control module 152 is turned on and the reference signal writing module 14 is turned off.

[0050] For example, the non-light-emitting stage NE includes a fourth stage t4, which follows the data writing stage t2. In the fourth stage t4, the second light-emitting control signal line EM2 provides a conduction level (high level), and the second light-emitting control module 152 is turned on; the fourth gate line G4 provides a cutoff level (low level), and the reference signal writing module 14 is turned off. Additionally, during the fourth stage t4, the data writing module 16 and the first initialization module 12 are disconnected.

[0051] The control terminal of the reference signal writing module 14 is connected to the fourth gate line G4. The signal on the fourth gate line G4 is a transition level (there is a transition between high and low levels). In the fourth stage t4, since the second light-emitting control module 152 is turned on, the third node N3 and the fourth node N4 are turned on. At this time, the fourth node N4 can be electrically connected to a fixed voltage signal terminal. In this way, the first terminal of the coupling unit 132 is connected to the fixed signal terminal, and the coupling unit 132 will not perform coupling. Even if the signal of the fourth gate line G4 transitions in the fourth stage t4, it will not affect the potential of the third node N3. In addition, even if the potential of the third node N3 in the fourth stage t4 changes relative to the potential of the third node N3 in the data writing stage t2, the potential of the second node N2 will also change under the coupling effect of the storage unit 131. And the transition level of the second node N2 and the third node N3 is the same. Therefore, the voltage difference between the second node N2 and the third node N3 is the same in the data writing stage t2 and the fourth stage t4.

[0052] In some embodiments, please refer to the reference Figure 3 and Figure 5 When the second end of the coupling unit 132 is electrically connected to the control end of the reference signal writing module 14, during the non-light-emitting stage NE, the second light-emitting control module 152 switches to the on state before the reference signal writing module 14 switches to the off state.

[0053] For example, the non-light-emitting stage NE includes a fifth time period t5. During the fifth time period t5, the second light-emitting control module 152 is turned on, and the reference signal writing module 14 is turned on. Before the fifth time period t5, the second light-emitting control module 152 is turned off, and the reference signal writing module 14 is turned on. After the fifth time period t5, the second light-emitting control module 152 is turned on, and the reference signal writing module 14 is turned off. In this embodiment, after the data writing stage t2, the second light-emitting control module 152 first switches to the on state. After a certain period of time, the fifth time period t5, the reference signal writing module 14 switches to the off state. This can better ensure that the signal transition of the fourth gate line G4 occurs within the on period of the second light-emitting control module 152, so as to better ensure that the signal transition of the fourth gate line G4 will not affect the potential of the second terminal of the driving module 11.

[0054] In some embodiments, such as Figure 1 , Figure 3 or Figure 4 As shown, the pixel circuit 10 may also include a second initialization module 17, which is connected between the second initialization signal terminal Vini and the first pole of the light-emitting element 20; the non-light-emitting stage NE also includes an initialization stage t3, in which the second initialization module 17 is turned on.

[0055] The control terminal of the second initialization module 17 can be electrically connected to the third gate line G3. During the initialization phase t3, the third gate line G3 provides a conduction level (high level), the second initialization module 17 is turned on, and the second initialization voltage of the second initialization signal terminal Vini is written into the first electrode of the light-emitting element 20 to initialize the potential of the first electrode of the light-emitting element 20.

[0056] For example, the initialization phase t3 overlaps with the compensation phase t1, and the initialization phase t3 overlaps with the data writing phase t2, so that the duration of the initialization phase t3 is relatively long, so as to fully initialize the potential of the first electrode of the light-emitting element 20.

[0057] For example, please refer to the reference. Figure 3 and Figure 5 When the second end of the coupling unit 132 is electrically connected to the control end of the reference signal writing module 14, the initialization stage t3 can overlap at least partially with the compensation stage t1, the data writing stage t2, the fourth stage t4, and the fifth time period t5, so as to further extend the duration of the initialization stage t3, thereby further and fully initializing the potential of the first electrode of the light-emitting element 20.

[0058] In addition, the initialization phase t3 and the fifth time period t5 overlap at least partially. The second initialization signal terminal Vini can be a fixed voltage signal terminal, so that the first terminal of the coupling unit 132 is connected to the fixed voltage signal terminal, so that the signal transition of the fourth gate line G4 will not affect the potential of the second terminal of the drive module 11.

[0059] Based on the same technical concept, embodiments of this application also provide a pixel circuit, such as... Figures 6 to 8 As shown, the pixel circuit 10 includes a first light-emitting control transistor T4, a second light-emitting control transistor T5, a driving transistor T3, a storage capacitor C1, a coupling capacitor C2, and a first initialization transistor T2.

[0060] The first terminal of the first light-emitting control transistor T4 is electrically connected to the first power supply signal terminal PVDD, the second terminal of the first light-emitting control transistor T4 is electrically connected to the first terminal of the driving transistor T3, and the gate of the first light-emitting control transistor T4 is electrically connected to the first light-emitting control signal line EM1.

[0061] The first terminal of the second light-emitting control transistor T5 is electrically connected to the second terminal of the driving transistor T3, the second terminal of the second light-emitting control transistor T5 is electrically connected to the first terminal of the light-emitting element 20, and the gate of the second light-emitting control transistor T5 is electrically connected to the second light-emitting control signal line EM2.

[0062] The first terminal of the first initialization transistor T2 is electrically connected to the first initialization signal terminal Vref, the second terminal of the first initialization transistor T2 is electrically connected to the gate of the driving transistor T3, and the gate of the first initialization transistor T2 is electrically connected to the second gate line G2.

[0063] The storage capacitor C1 is connected between the gate of the driving transistor T3 and the second terminal of the driving transistor T3.

[0064] The first terminal of coupling capacitor C2 is electrically connected to the second terminal of driving transistor T3, and the second terminal of coupling capacitor C2 is electrically connected to the reference signal terminal Vdc.

[0065] Reference Figure 6 and Figure 2 The operation of the pixel circuit 10 includes a non-light-emitting stage NE and a light-emitting stage E. The non-light-emitting stage NE includes a compensation stage t1. In the compensation stage t1, the first initialization transistor T2 is turned on.

[0066] During the compensation phase t1, the second gate line G2 provides a conduction level (high level), the first initialization transistor T2 is turned on, and the first initialization signal at the first initialization signal terminal Vref is transmitted to the gate of the driving transistor T3 via the first initialization transistor T2. At this time, the reference signal at the reference signal terminal Vdc can be transmitted to the first terminal of the driving transistor T3. Thus, the second terminal of the driving transistor T3 can be set to Vref-Vth using the reference signal at the reference signal terminal Vdc, where Vref represents the voltage of the first initialization signal and Vth represents the turn-on threshold voltage of the driving transistor T3.

[0067] According to the pixel circuit provided in the embodiments of this application, during the compensation stage, the power signal of the first power signal terminal PVDD is no longer introduced. Instead, the reference signal of the reference signal terminal Vdc is introduced to set the second terminal of the driving transistor T3. The noise of the reference signal terminal Vdc is smaller than the noise of the first power signal terminal PVDD, which can reduce the instability of the pixel circuit caused by the external noise brought by the first power signal terminal PVDD, improve the potential stability of the second terminal of the driving transistor T3, and thus improve the working stability of the pixel circuit and the stability of the light emission brightness of the light-emitting element.

[0068] In some embodiments, such as Figures 6 to 8 As shown, the pixel circuit 10 also includes a data writing transistor T1. The first terminal of the data writing transistor T1 is electrically connected to the data signal terminal Vdata, the second terminal of the data writing transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate of the data writing transistor T1 is electrically connected to the first gate line G1. Please refer to the reference. Figure 6 and Figure 2The non-light-emitting stage NE includes the data writing stage t2. During the data writing stage, the first gate line G1 provides a conduction level (high level), the data writing transistor T1 is turned on, and the data voltage at the data signal terminal Vdata is written to the gate of the driving transistor T1 to realize the writing of the data signal.

[0069] For example, in the same non-light-emitting stage NE, the compensation stage t1 precedes the data writing stage t2. The end time of the compensation stage t1 is no later than the start time of the data writing stage t2.

[0070] During the compensation phase t1, the second terminal of the driving transistor T1 is set to Vref-Vth using the reference voltage at the reference signal terminal Vdc; during the data writing phase t2, the data voltage at the data signal terminal Vdata is written to the gate of the driving transistor T1; this enables the driving current generated by the driving transistor T1 to be independent of the threshold voltage Vth, thereby improving the display uniformity of the display product.

[0071] In addition, during the data writing phase t2, the second gate line G2 provides a cutoff level, and the first initialization transistor T2 is turned off. In this way, when the data voltage at the data signal terminal Vdata is written to the gate of the driving transistor T3, the first initialization voltage at the first initialization signal terminal Vref will not be written to the gate of the driving transistor T3, and there will be no signal crosstalk at the gate of the driving transistor T3.

[0072] In some embodiments, such as Figures 6 to 8 As shown, the pixel circuit 10 also includes a reference signal writing transistor T7. The first terminal of the reference signal writing transistor T7 is electrically connected to the reference signal terminal Vdc, the second terminal of the reference signal writing transistor T7 is electrically connected to the first terminal of the driving transistor T3, and the gate of the reference signal writing transistor T7 is electrically connected to the fourth gate line G4. Please refer to the reference. Figure 6 and Figure 2 During the compensation phase t1, the reference signal writing transistor T7 is turned on. During the compensation phase t1, both the first initialization module 12 and the reference signal writing transistor T7 are turned on. The first initialization signal at the first initialization signal terminal Vref is transmitted to the gate of the driving transistor T3 via the first initialization transistor T2. At this time, the reference signal at the reference signal terminal Vdc can be transmitted to the first terminal of the driving transistor T3 via the reference signal writing transistor T7. This ensures that the second terminal of the driving transistor T3 is set to Vref-Vth using the reference signal at the reference signal terminal Vdc, which has lower noise, thereby improving the working stability of the pixel circuit and the stability of the light emission brightness of the light-emitting element.

[0073] In some embodiments, such as Figure 6 or Figure 8 as well as Figure 2As shown, the second terminal of the coupling capacitor C2 is connected to either the first or second terminal of the reference signal writing transistor T7. During the entire non-light-emitting phase NE, the second light-emitting control transistor T5 remains disconnected.

[0074] During the compensation phase t1 within the non-light-emitting phase NE, the first initialization transistor T2 and the reference signal writing transistor T7 are turned on; throughout the entire non-light-emitting phase NE, the second light-emitting control transistor T5 remains off; this better ensures that when the second terminal of the driving transistor T3 is set, the signal of the fourth node N4 will not affect the setting effect of the second terminal of the driving transistor T3, so as to better ensure that the driving transistor T3 can be effectively compensated.

[0075] In other embodiments, such as Figure 7 and Figure 5 As shown, the second terminal of the coupling capacitor C2 is electrically connected to the gate of the reference signal writing transistor T7. During the non-light-emitting phase NE and for at least a portion of the time period after the data writing phase t2, the second light-emitting control transistor T5 is turned on.

[0076] For example, the non-light-emitting phase NE includes a fourth phase t4, which follows the data writing phase t2. In the fourth phase t4, the second light-emitting control signal line EM2 provides a conduction level (high level), and the second light-emitting control transistor T5 is turned on; the fourth gate line G4 provides a cutoff level (low level), and the reference signal writing transistor T7 is turned off. Additionally, during the fourth phase t4, the data writing transistor T1 and the first initialization transistor T2 are turned off.

[0077] The control terminal of the reference signal writing transistor T7 is connected to the fourth gate line G4. The signal on the fourth gate line G4 is a transition level (there is a transition between high and low levels). In the fourth stage t4, because the second light-emitting control transistor T5 is turned on, the third node N3 and the fourth node N4 are turned on. At this time, the fourth node N4 can be electrically connected to a fixed voltage signal terminal. In this way, the first end of the coupling capacitor C2 is connected to the fixed signal terminal, and the coupling capacitor C2 will not have a coupling effect. Even if the signal of the fourth gate line G4 transitions in the fourth stage t4, it will not affect the potential of the third node N3. In addition, even if the potential of the third node N3 in the fourth stage t4 changes relative to the potential of the third node N3 in the data writing stage t2, the potential of the second node N2 will also change under the coupling effect of the storage capacitor C1. And the transition value of the second node N2 and the third node N3 is the same. Therefore, the voltage difference between the second node N2 and the third node N3 is the same in the data writing stage t2 and the fourth stage t4.

[0078] For example, the second terminal of the coupling capacitor C2 is electrically connected to the gate of the reference signal writing transistor T7. During the non-light-emitting phase NE, the second light-emitting control transistor T5 switches to the on state before the reference signal writing transistor T7 switches to the off state.

[0079] The non-light-emitting phase NE includes a fifth time period t5. During the fifth time period t5, the second light-emitting control transistor T5 is turned on, and the reference signal writing transistor T7 is turned on. Before the fifth time period t5, the second light-emitting control transistor T5 is turned off, and the reference signal writing transistor T7 is turned on. After the fifth time period, the second light-emitting control transistor T5 is turned on, and the reference signal writing transistor T7 is turned off. In this embodiment, after the data writing phase t2, the second light-emitting control transistor T5 first switches to the on state. After a certain period of time, the fifth time period t5, the reference signal writing transistor T7 switches to the off state. This better ensures that the signal transition of the fourth gate line G4 occurs during the on period of the second light-emitting control transistor T5, so as to better ensure that the signal transition of the fourth gate line G4 does not affect the potential of the second terminal of the driving module 11.

[0080] In some embodiments, such as Figures 6 to 8 As shown, the pixel circuit 10 may further include a second initialization transistor T6, which is connected between the second initialization signal terminal Vini and the first pole of the light-emitting element 20; the non-light-emitting stage NE also includes an initialization stage t3, in which the second initialization transistor T6 is turned on.

[0081] The gate of the second initialization transistor T6 can be electrically connected to the third gate line G3. During the initialization phase t3, the third gate line G3 provides a conduction level (high level), the second initialization transistor T6 is turned on, and the second initialization voltage of the second initialization signal terminal Vini is written into the first electrode of the light-emitting element 20 to initialize the potential of the first electrode of the light-emitting element 20.

[0082] In some embodiments, at least some of the first light-emitting control transistor T4, the second light-emitting control transistor T5, the driving transistor T1, the data writing transistor T1, the first initialization transistor T2, and the second initialization transistor T6 of the pixel circuit 10 are oxide transistors.

[0083] For example, each transistor in a pixel circuit can be an oxide transistor, and an oxide transistor can be an N-type transistor.

[0084] Understandably, the driving module includes a driving transistor T3, the first initialization module includes a first initialization transistor T2, the reference signal writing module includes a reference signal writing transistor T7, the first light emission control module includes a first light emission control transistor T4, the second light emission control module includes a second light emission control transistor T5, the second initialization module includes a second initialization transistor T6, the storage unit includes a storage capacitor C1, and the coupling unit includes a coupling capacitor C2.

[0085] Please refer to the reference. Figure 6 and Figure 2 or in conjunction with references Figure 8 and Figure 2 The working process of the pixel circuit is as follows: During the compensation phase t1, the first initialization transistor T2 and the reference signal writing transistor T7 are turned on. In addition, the second initialization transistor T6 is turned on, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are turned off, the data writing transistor T1 is turned off, the potential of the second node N2 is Vref, the potential of the first node N1 is Vdc, the potential of the third node N3 is Vref-Vth, and the potential of the fourth node N4 is Vini.

[0086] During the data writing phase t2, the data writing transistor T1 is turned on, the first initialization transistor T2 is turned off, the reference signal writing transistor T7 is turned on, the second initialization transistor T6 is turned on, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are turned off, the potential of the second node N2 is Vdata, the potential of the first node N1 is Vdc, the potential of the third node N3 is Vref-Vth+(Vdata-Vref)*C1 / (C1+C2), and the potential of the fourth node N4 is Vini.

[0087] During the light-emitting stage E, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are turned on, driving transistor T3 to generate a drive current I, where I = K*(Vgs - Vth). 2 Vgs represents the voltage difference between the second node N2 and the third node N3, K is a constant, and I = K * ((Vdata - Vref) * C2 / (C1 + C2)). 2 .

[0088] During the light-emitting stage E, the coupling capacitor C2 is short-circuited by the driving transistor T3, and the first node N1 and the third node N3 are clamped by the first power signal terminal PVDD and the second power signal terminal PVEE respectively, so no external noise is introduced.

[0089] Please refer to the reference. Figure 7 and Figure 5 , Figure 7 and Figure 6 The differences include: Figure 7 The second terminal of the intermediate coupling capacitor C2 is connected to the gate of the reference signal writing transistor T7; Figure 5 and Figure 2 The differences include: after the data writing stage t2, the second light-emitting control transistor T5 is turned on first to set the third node N3, and then the reference signal writing transistor T7 is turned off. In this way, the signal transition of the fourth gate line G4 will not affect the third node N3, and the current I of the driving transistor T3 during the light-emitting stage E is still K*((Vdata-Vref)*C2 / (C1+C2)). 2 .

[0090] Based on the same technological concept, such as Figure 9 As shown, this application embodiment also provides a display panel 100, which includes a light-emitting element 20 and a pixel circuit 10 as described in any of the above embodiments.

[0091] The display panel provided in this application embodiment has the beneficial effects of the pixel circuit provided in the above embodiments of this application. For details, please refer to the specific description of the pixel circuit in the above embodiments. This embodiment will not repeat the description here.

[0092] Based on the same technical concept, this application also provides a display device, including the display panel provided in this application. Please refer to... Figure 10 , Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 10 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 10 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0093] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A pixel circuit, characterized in that, It includes a driver module, a first initialization module, a storage coupling module, and a reference signal writing module; The driving module is electrically connected to the light-emitting element; The first initialization module is connected between the control terminal and the first initialization signal terminal of the drive module; The reference signal writing module is connected between the reference signal terminal and the first terminal of the driving module; The storage coupling module is electrically connected to the second terminal of the driving module, and the storage coupling module is also electrically connected to the reference signal writing module. The operation of the pixel circuit includes a non-light-emitting stage and a light-emitting stage, and the non-light-emitting stage includes at least a compensation stage. During the compensation phase, the first initialization module and the reference signal writing module are turned on.

2. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes: The first light-emitting control module is connected between the first power signal terminal and the first terminal of the driving module; During the non-light-emitting phase, the first light-emitting control module is disconnected.

3. The pixel circuit according to claim 2, characterized in that, The pixel circuit also includes: A data writing module is connected between the control terminal and the data signal terminal of the drive module. The non-light-emitting stage also includes a data writing stage, during which the data writing module is turned on; In the same non-light-emitting stage, the compensation stage precedes the data writing stage.

4. The pixel circuit according to claim 1, characterized in that, During at least a portion of the compensation phase, the potential at the control terminal of the drive module is greater than the potential at the second terminal of the drive module.

5. The pixel circuit according to claim 1, characterized in that, The storage coupling module includes: A storage unit is connected between the second end of the drive module and the control end of the drive module; A coupling unit is connected between the second end of the driving module and the reference signal writing module.

6. The pixel circuit according to claim 5, characterized in that, The first end of the reference signal writing module is connected to the reference signal end, and the second end of the reference signal writing module is connected to the first end of the driving module; The coupling unit is connected to the first end of the reference signal writing module, or the coupling unit is connected to the second end of the reference signal writing module, or the coupling unit is connected to the control end of the reference signal writing module.

7. The pixel circuit according to claim 6, characterized in that, The pixel circuit also includes: The second light-emitting control module is connected between the second end of the driving module and the first electrode of the light-emitting element.

8. The pixel circuit according to claim 7, characterized in that, When the coupling unit is connected to the first or second end of the reference signal writing module, the second light emission control module is disconnected during the non-light emission phase.

9. The pixel circuit according to claim 7, characterized in that, When the coupling unit is connected to the control terminal of the reference signal writing module, the second light emission control module is turned on and the reference signal writing module is turned off for at least a portion of the time period after the data writing phase in the non-light emission phase.

10. The pixel circuit according to claim 9, characterized in that, During the non-light-emitting phase, the second light-emitting control module switches to the on state before the reference signal writing module switches to the off state.

11. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes a second initialization module, which is connected between the second initialization signal terminal and the first electrode of the light-emitting element; The non-light-emitting stage also includes an initialization stage, in which the second initialization module is turned on.

12. A pixel circuit, characterized in that, include: First light-emitting control transistor; The second light-emitting control transistor is electrically connected to the light-emitting element; A driving transistor, wherein the driving transistor is electrically connected to the second light-emitting control transistor and the first light-emitting control transistor; A storage capacitor is connected between the gate of the driving transistor and the second electrode of the driving transistor; A coupling capacitor, wherein the first end of the coupling capacitor is connected to the second terminal of the driving transistor, and the second end of the coupling capacitor is electrically connected to the reference signal terminal; A first initialization transistor is connected between a first initialization signal terminal and the gate of the driving transistor; During the compensation phase in the non-light-emitting phase, the first initialization transistor is turned on.

13. The pixel circuit according to claim 12, characterized in that, The pixel circuit also includes: A data writing transistor is connected between the data signal terminal and the gate of the driving transistor; During the data writing phase in the non-light-emitting phase, the data writing transistor is turned on.

14. The pixel circuit according to claim 12, characterized in that, The pixel circuit also includes: A reference signal writing transistor is provided, wherein the first terminal of the reference signal writing transistor is connected to the reference signal terminal, and the second terminal of the reference signal writing transistor is connected to the first terminal of the driving transistor. During the compensation phase, the reference signal writing transistor is turned on.

15. The pixel circuit according to claim 14, characterized in that, The second terminal of the coupling capacitor is connected to the second or first terminal of the reference signal writing transistor. During the non-light-emitting phase, the second light-emitting control transistor is turned off.

16. The pixel circuit according to claim 14, characterized in that, The second end of the coupling capacitor is connected to the gate of the reference signal writing transistor; The second light-emitting control transistor is turned on for at least a portion of the time following the data writing phase in the non-light-emitting phase.

17. The pixel circuit according to claim 12, characterized in that, In the pixel circuit, at least some of the transistors, including the first light-emitting control transistor, the second light-emitting control transistor, the driving transistor, and the first initialization transistor, are oxide transistors.

18. A display panel, characterized in that, Includes the pixel circuit according to any one of claims 1-17.

19. A display device, characterized in that, Includes the display panel as described in claim 18.

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