Pixel circuit, driving method thereof and display panel

Abstract

This application provides a pixel circuit and its driving method, as well as a display panel. The pixel circuit includes: a first terminal of a driving module electrically connected to a first power line, and a second terminal of the driving module electrically connected to a second power line; a first terminal of a gating module electrically connected to the second terminal of the driving module, and a control terminal of the gating module electrically connected to the control terminal of the driving module; a first terminal of a first light-emitting module electrically connected to the second terminal of the driving module, and the second terminal of the first light-emitting module electrically connected to the second power line; a first terminal of a second light-emitting module electrically connected to the second terminal of the gating module, and the second terminal of the second light-emitting module electrically connected to the second power line; the gating module is used to control the second light-emitting module to emit light or turn off. In low-brightness display, the starting speed of the first light-emitting module is faster than the starting speed when the first and second light-emitting modules are combined, thus improving the color shift caused by low-brightness, low-grayscale display.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel circuit and its driving method, and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display panels needs improvement. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above technical background, this application provides a pixel circuit and its driving method, as well as a display panel, which aims to improve the performance of the display panel.

[0005] This application provides a pixel circuit, including:

[0006] The drive module has a first end electrically connected to the first power line and a second end electrically connected to the second power line. The drive module is used to generate drive current. The gating module has its first terminal electrically connected to the second terminal of the drive module, and its control terminal is electrically connected to the control terminal of the drive module. The first light-emitting module is electrically connected between the driving module and the second power line. The first end of the first light-emitting module is electrically connected to the second end of the driving module, and the second end of the first light-emitting module is electrically connected to the second power line. The second light-emitting module is electrically connected between the gating module and the second power line. The first end of the second light-emitting module is electrically connected to the second end of the gating module, and the second end of the second light-emitting module is electrically connected to the second power line. The gating module is used to control the second light-emitting module to light up or turn off.

[0007] In one embodiment, the driving module includes a first transistor, the first electrode of the first transistor serving as a first terminal of the driving module, the second electrode of the first transistor serving as a second terminal of the driving module, and the gate of the first transistor serving as a control terminal of the driving module; the gating module includes a second transistor, the first electrode of the second transistor serving as a first terminal of the gating module, the second electrode of the second transistor serving as a second terminal of the gating module, and the gate of the second transistor serving as a control terminal of the gating module. The turn-on level of the first transistor is the same as that of the second transistor; Furthermore, the semiconductor materials of both the first transistor and the second transistor include low-temperature polycrystalline silicon.

[0008] In one embodiment, it further includes a threshold compensation module, a first light emission control module, and a second light emission control module; The first end of the threshold compensation module is electrically connected to the control end of the drive module, the second end of the threshold compensation module is electrically connected to the second end of the drive module, and the control end of the threshold compensation module is electrically connected to the second scan line. The first light-emitting control module is electrically connected between the driving module and the first power line. The first end of the first light-emitting control module is electrically connected to the first power line. The second end of the first light-emitting control module is electrically connected to the first end of the driving module. The control end of the first light-emitting control module is electrically connected to the light-emitting control scan line. The second light-emitting control module is electrically connected between the driving module and the first light-emitting module. The first end of the second light-emitting control module is electrically connected to the second end of the driving module, the second end of the second light-emitting module is electrically connected to the first end of the first light-emitting module, and the control end of the second light-emitting module is electrically connected to the light-emitting control scan line. Furthermore, the threshold compensation module includes a third transistor, the first terminal of the third transistor serves as the first terminal of the threshold compensation module, the second terminal of the third transistor serves as the second terminal of the threshold compensation module, and the gate of the third transistor serves as the control terminal of the threshold compensation module. The first light-emitting control module includes a fourth transistor, the first electrode of the fourth transistor serves as the first terminal of the first light-emitting control module, the second electrode of the fourth transistor serves as the second terminal of the first light-emitting control module, and the gate of the fourth transistor serves as the control terminal of the first light-emitting control module. The second light-emitting control module includes a fifth transistor. The first electrode of the fifth transistor serves as the first terminal of the second light-emitting control module, the second electrode of the fifth transistor serves as the second terminal of the second light-emitting control module, and the gate of the fifth transistor serves as the control terminal of the second light-emitting control module.

[0009] In one embodiment, the first end of the gating module is electrically connected to the first end of the second light-emitting control module; or, The first terminal of the gating module is electrically connected to the second terminal of the second light-emitting control module.

[0010] In one embodiment, it further includes a first reset module and a second reset module; The first terminal of the first reset module is electrically connected to the first initialization signal line, the second terminal of the first reset module is electrically connected to the control terminal of the drive module, and the control terminal of the first reset module is electrically connected to the first scan line. The first terminal of the second reset module is electrically connected to the second initialization signal line, the second terminal of the second reset module is electrically connected to the first terminal of the first light-emitting module, and the control terminal of the second reset module is electrically connected to the third scan line. Furthermore, the start time of the conduction level transmitted by the first scan line electrically connected to the first reset module is not later than the start time of the conduction level transmitted by the third scan line electrically connected to the second reset module. Furthermore, the pulse width of the conduction level transmitted by the third scan line electrically connected to the second reset module is greater than the pulse width of the conduction level transmitted by the first scan line electrically connected to the first reset module. Furthermore, the start time of the conduction level transmitted by the first scan line electrically connected to the first reset module is the same as the start time of the conduction level transmitted by the third scan line electrically connected to the second reset module. or, The end time of the conduction level transmitted by the first scan line electrically connected to the first reset module is the same as the start time of the conduction level transmitted by the third scan line electrically connected to the second reset module. Furthermore, the conduction level transmitted by the first scan line electrically connected to the first reset module is prior to and does not overlap with the conduction level transmitted by the second scan line electrically connected to the threshold compensation module; the start time of the conduction level transmitted by the third scan line electrically connected to the second reset module is prior to the start time of the conduction level transmitted by the second scan line electrically connected to the threshold compensation module; and the end time of the conduction level transmitted by the third scan line electrically connected to the second reset module is prior to the end time of the conduction level transmitted by the second scan line electrically connected to the threshold compensation module. Furthermore, the first reset module includes a sixth transistor, the first terminal of the sixth transistor serves as the first terminal of the first reset module, the second terminal of the sixth transistor serves as the second terminal of the first reset module, and the gate of the sixth transistor serves as the control terminal of the first reset module. The second reset module includes an eighth transistor, the first terminal of the eighth transistor serves as the first terminal of the second reset module, the second terminal of the eighth transistor serves as the second terminal of the second reset module, and the gate of the eighth transistor serves as the control terminal of the second reset module.

[0011] In one embodiment, a third reset module is also included; The first terminal of the third reset module is electrically connected to the second initialization signal line, the second terminal of the third reset module is electrically connected to the first terminal of the second light-emitting module, and the control terminal of the third reset module is electrically connected to the third scan line. Furthermore, the third reset module includes a ninth transistor, the first terminal of the ninth transistor serves as the first terminal of the third reset module, the second terminal of the ninth transistor serves as the second terminal of the third reset module, and the gate of the ninth transistor serves as the control terminal of the third reset module; the conduction level of the ninth transistor is the same as the conduction level of the eighth transistor. Furthermore, the conduction level of the third transistor is the same as that of the eighth transistor, and the signal transmitted by the second scan line is multiplexed into the signal transmitted by the third scan line.

[0012] In one implementation, it further includes a data writing module and a storage module; The first end of the data writing module is electrically connected to the data voltage signal line, the second end of the data writing module is electrically connected to the first end of the drive module, and the control end of the data writing module is electrically connected to the second scan line. The first end of the storage module is electrically connected to the first power line, and the second end of the storage module is electrically connected to the control end of the drive module. Furthermore, the data writing module includes a seventh transistor, the first terminal of the seventh transistor serves as the first terminal of the data writing module, the second terminal of the seventh transistor serves as the second terminal of the data writing module, and the gate of the seventh transistor serves as the control terminal of the data writing module. The storage module includes a storage capacitor, with the first terminal of the storage capacitor serving as the first terminal of the storage module and the second terminal of the storage capacitor serving as the second terminal of the storage module. The turn-on level of the seventh transistor is the same as that of the third transistor.

[0013] This application embodiment also provides a display panel including the pixel circuit described above. The display panel includes a low-brightness display mode and a high-brightness display mode. In the low-brightness display mode, the gating module is turned off, the second light-emitting module is turned off, and the first light-emitting module emits light. In the high-brightness display mode, the gating module is turned on, and both the second light-emitting module and the first light-emitting module emit light.

[0014] In one embodiment, the first light-emitting module and the second light-emitting module are located in the same pixel repeating unit; Furthermore, the light emission color of the first light-emitting module is the same as that of the second light-emitting module; Furthermore, the light emission color of both the first light-emitting module and the second light-emitting module is green; Furthermore, the first light-emitting module includes a first sub-pixel, and the second light-emitting module includes a second sub-pixel, wherein the pixel aperture area of ​​the first sub-pixel is the same as the pixel aperture area of ​​the second sub-pixel.

[0015] This application embodiment also provides a pixel circuit driving method for driving the aforementioned pixel circuit, the method comprising: In low brightness display mode, the driving module generates a first driving current according to the first potential of the control terminal of the driving module, the gating module responds to the first potential of the control terminal of the driving module and turns off, and the first driving current drives the first light-emitting module to emit light. In high-brightness display mode, the driving module generates a second driving current according to the second potential of the control terminal of the driving module. The gating module responds to the second potential of the control terminal of the driving module and turns on. The second driving current drives the first light-emitting module and the second light-emitting module to emit light simultaneously.

[0016] The technical solution provided in this application divides a light-emitting module into a first light-emitting module and a second light-emitting module. The area of ​​the first light-emitting module is smaller than the area of ​​the first light-emitting module and the second light-emitting module combined. Therefore, the parasitic capacitance of the first light-emitting module is smaller than the parasitic capacitance of the first light-emitting module and the second light-emitting module combined. When displaying at low brightness, the lighting speed of the first light-emitting module is faster than the lighting speed of the first light-emitting module and the second light-emitting module combined, thus improving the color shift caused by low brightness and low grayscale display.

[0017] It should be understood that the description in this section is not intended to identify key or important features of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a pixel circuit in the prior art; Figure 2 This is another pixel circuit in the prior art; Figure 3 for Figure 2 The timing diagram of the pixel circuit shown is as follows; Figure 4 A pixel circuit architecture diagram provided for an embodiment of this application; Figure 5 This is a schematic diagram of pixel arrangement provided in an embodiment of this application; Figure 6 Another pixel circuit architecture diagram provided in the embodiments of this application; Figure 7 A pixel circuit driving timing diagram provided in an embodiment of this application; Figure 8A pixel circuit structure diagram provided in an embodiment of this application; Figure 9 A schematic diagram of the current before and after the green sub-pixel is segmented under highlighted display; Figure 10 This is a schematic diagram of the current before and after the green sub-pixel is segmented under low brightness display. Figure 11 Another pixel circuit architecture diagram provided in the embodiments of this application; Figure 12 Another pixel circuit structure diagram provided in the embodiments of this application; Figure 13 Another pixel circuit architecture diagram provided in the embodiments of this application; Figure 14 Another pixel circuit structure diagram provided in the embodiments of this application; Figure 15 Another pixel circuit driving timing diagram provided in the embodiments of this application; Figure 16 Another pixel circuit driving timing diagram provided in the embodiments of this application; Figure 17 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0023] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0024] For certain elements, terms such as "above" or "over" are sometimes used when describing the position of an element located in the Z direction, and "below" or "under" are used when describing the position of an element located in the opposite direction. Furthermore, when using terms such as "above," "over," "below," "under," and "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly connected, but also the state where the two elements are separated by a gap or other elements. Moreover, the terms "first," "second," and "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance or order. At least one may include one or more. At least part may include part or all. The first direction and the second direction intersect, for example, they may be perpendicular. At least one may include one or more. Connections may include direct connections or indirect connections. Equal or identical means equal or identical within a reasonable range of errors such as manufacturing errors, process errors, and measurement errors. The transistor may be a P-type transistor or an N-type transistor. A P-type transistor is turned on when its gate is connected to a low level and turned off when its gate is connected to a high level. An N-type transistor is turned on when its gate is connected to a high level and turned off when its gate is connected to a low level.

[0025] With the continuous development of display panel technology, the types and methods of display panels are becoming increasingly diverse, and people's demands for display panels in various scenarios are also increasing. In a display panel, pixel circuits provide driving current to the light-emitting devices. The pixel circuits can be... Figure 1The pixel circuit shown is a typical 2T1C pixel circuit, including a driving transistor M1, a data writing transistor M2, a storage capacitor C, and a light-emitting device. The first terminal of the driving transistor M1 is connected to the power supply voltage Vdd, the second terminal of the driving transistor M1 is electrically connected to the anode of the light-emitting device, the cathode of the light-emitting device is connected to the power supply voltage VSS, the gate of the driving transistor M1 is electrically connected to the first terminal of the data writing transistor M2, the second terminal of the data writing transistor M2 is connected to the data voltage Vdata, and the gate of the data writing transistor M2 is connected to the first gate signal Scan1. The first terminal of the storage capacitor C is electrically connected to the gate of the driving transistor M1, and the second terminal of the storage capacitor C is connected to the power supply voltage Vdd. The driving transistor M1 generates a driving current based on the data voltage Vdata at its gate to drive the light-emitting device to emit light.

[0026] However, the 2T1C pixel circuit lacks threshold compensation, resulting in poor display quality. Therefore, the 7T1C pixel circuit with threshold compensation was further developed, such as... Figure 2As shown, the pixel circuit 7T1C includes a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, a gate reset transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, an anode reset transistor M7, a storage capacitor C, and a light-emitting device. The first terminal of the first light-emitting control transistor M5 is connected to the power supply voltage Vdd. The second terminal of the first light-emitting control transistor M5 is electrically connected to the first terminal of the driving transistor M1. The second terminal of the driving transistor M1 is electrically connected to the first terminal of the second light-emitting control transistor M6. The second terminal of the second light-emitting control transistor M6 is electrically connected to the anode of the light-emitting device. The gates of both the first and second light-emitting control transistors are connected to the control signal em. The cathode of the light-emitting device is connected to the power supply voltage VSS. The first terminal of the data writing transistor M2 is connected to the data voltage Vdata. The second terminal of the data writing transistor M2 is electrically connected to the first terminal of the driving transistor M1. The gate of the data writing transistor M2 is connected to the first gate signal scan1. The first terminal of the threshold compensation transistor M3 is electrically connected to the gate of the driving transistor M1. The second terminal of threshold compensation transistor M3 is electrically connected to the second terminal of driving transistor M1. The gate of threshold compensation transistor M3 is connected to the first gate signal scan1. The first terminals of gate reset transistor M4 and anode reset transistor M7 are both connected to the reset voltage vref. The second terminal of gate reset transistor M4 is electrically connected to the gate of driving transistor M1. The second terminal of anode reset transistor M7 is electrically connected to the anode of the light-emitting device. The gate of gate reset transistor M4 is connected to the second gate signal scan2. The gate of anode reset transistor M7 is connected to the first gate signal scan1. The first terminal of storage capacitor C is electrically connected to the gate of driving transistor M1. The second terminal of storage capacitor C is connected to the power supply voltage vdd. Driving transistor M1 generates a driving current according to the data voltage vdata of its gate to drive the light-emitting device to emit light.

[0027] Figure 3 for Figure 2 The timing diagram of the pixel circuit shown is illustrated below. The operation process of the pixel circuit is described as follows: Initial stage P0: This stage is the light-emitting stage of the previous display frame. The second gate signal scan2 and the first gate signal scan1 are both at high level, the control signal em is at low level, the driving transistor M1, the first light-emitting control transistor M5, and the second light-emitting control transistor M6 are turned on, and the other transistors are turned off. The driving transistor M1 generates a driving current to drive the light-emitting device to emit light.

[0028] Reset Phase P1: Control signal em and the first gate signal scan1 are both high, the second gate signal scan2 is low, gate reset transistor M4 is turned on, the gate of driving transistor M1 is reset, and the potential of the gate of driving transistor M1 is V. G=vref; During the write and compensation phase P2: the control signal em and the second gate signal scan2 are both high, the first gate signal scan1 is low, the anode reset transistor M7 is turned on, the anode of the light-emitting device is reset, and the anode potential V of the light-emitting device is... Anode =vref, the driving transistor M1, the data writing transistor M2, and the threshold compensation transistor M3 are turned on. The data voltage signal vdata passes sequentially through the data writing transistor M2, the driving transistor M1, and the threshold compensation transistor M3, charging the gate of the driving transistor M1 until the potential V of the gate of the driving transistor M1 is reached. G =vdata+Vth, and this potential is stored in the storage capacitor C.

[0029] Light-emitting stage P3: This stage is the light-emitting stage of the current display frame. The second gate signal scan2 and the first gate signal scan1 are both high, and the control signal em is low. Driving transistor M1, the first light-emitting control transistor M5, and the second light-emitting control transistor M6 are turned on, while the remaining transistors are turned off, driving the light-emitting device to emit light. At this time, the light-emitting current... I OLED =(1 / 2) μ Cox (W / L) [(vdata+Vth)-vdd-Vth]^2 =(1 / 2) μ Cox (W / L) (vdata-vdd)^2 Among them, (1 / 2) μ Cox (W / L) is a fixed constant.

[0030] However, in existing solutions, the light-emitting devices have relatively large parasitic capacitance, resulting in a slow turn-on speed when displaying at low brightness. Due to the special properties of the green light-emitting device material, the parasitic capacitance of the green light-emitting device is larger than that of the red and blue light-emitting devices for the same area, making the turn-on speed of the green light-emitting device slower than that of the red and blue light-emitting devices. This leads to problems such as color shift, color unevenness, and ghosting when displaying at low brightness and low grayscale. The pixel circuit mentioned above is difficult to solve this problem. Therefore, this application proposes the following solution.

[0031] This application provides a pixel circuit. Figure 4 A pixel circuit architecture diagram provided for an embodiment of this application, such as Figure 4As shown, the pixel circuit includes a driving module 100, which is mainly used to generate a driving current to drive the corresponding light-emitting module to emit light. In this embodiment, the light-emitting module includes an OLED light-emitting device, but it can also be other types of light-emitting devices. The driving current drives the OLED light-emitting device to emit light. Specifically, the first end of the driving module 100 is electrically connected to the first power line, and the second end of the driving module 100 is electrically connected to the second power line. The first power line transmits a first power supply voltage VDD, and the second power line transmits a second power supply voltage VSS. The voltage value of the first power supply voltage VDD is greater than the voltage value of the second power supply voltage VSS. The driving module 100 operates under the action of the first power supply voltage VDD and the second power supply voltage VSS. A gating module 103 is used to turn on and off under set conditions. The first end of the gating module 103 is electrically connected to the second end of the driving module 100, and the control end of the gating module 103 is electrically connected to the control end of the driving module 100. That is, the control end of the gating module 103 and the control end of the driving module 100 are shared. The same potential; for example, in this embodiment, the light-emitting module includes a first light-emitting module 101 and a second light-emitting module 102, namely a first OLED light-emitting device D1 and a second OLED light-emitting device D2. The first light-emitting module 101 is electrically connected between the driving module 100 and the second power line. The first end of the first light-emitting module 101 is electrically connected to the second end of the driving module 100, and the second end of the first light-emitting module 101 is electrically connected to the second power line. Specifically, the second end of the driving module 100 transmits a driving current to the anode of the first OLED light-emitting device D1, and the cathode of the first OLED light-emitting device D1 is connected to the second power supply voltage VSS. The second light-emitting module 102 is electrically connected between the gating module 103 and the second power line. The first end of the second light-emitting module 102 is electrically connected to the second end of the gating module 103, and the second end of the second light-emitting module 102 is connected to the second power line. Specifically, the second end of the gating module 103 transmits a driving current to the anode of the second OLED light-emitting device D2, and the cathode of the second OLED light-emitting device D2 is connected to the second power supply voltage VSS.The gating module 103 controls the second light-emitting module 102 to light up or turn off. The on / off state of the gating module 103 is determined by the display mode. In high-brightness display mode, the driving module 100 needs to output a large driving current, which drives the first light-emitting module 101 to light up. The control terminal of the gating module 103 is affected by the voltage at the control terminal of the driving module 100, so the gating module 103 is in a conducting state. The driving current output from the second terminal of the driving module 100 is transmitted to the second light-emitting module 102 through the gating module 103, and the driving current drives the second light-emitting module 102. The light-emitting module 102 emits light, meaning that the first light-emitting module 101 and the second light-emitting module 102 emit light simultaneously. In low-brightness display mode, the driving module 100 needs to output a small driving current. This driving current drives the first light-emitting module 101 to emit light. The control terminal of the selection module 103 is affected by the voltage at the control terminal of the driving module 100. The selection module 103 is in an off state, and the driving current output from the second terminal of the driving module 100 cannot be transmitted to the second light-emitting module 102 through the selection module 103 to make it emit light. Therefore, only the first light-emitting module 101 emits light. Since the area of ​​the first light-emitting module 101 is smaller than the combined area of ​​the first light-emitting module 101 and the second light-emitting module 102, the parasitic capacitance of the first light-emitting module 101 is smaller than the parasitic capacitance when the first light-emitting module 101 and the second light-emitting module 102 are combined. Therefore, in low-brightness display mode, the starting speed of the first light-emitting module 101 is faster than the starting speed when the first light-emitting module 101 and the second light-emitting module 102 are combined.

[0032] For example, Figure 5 A pixel arrangement diagram provided for an embodiment of this application, such as Figure 5As shown, a pixel repeating unit includes a red sub-pixel R, a blue sub-pixel B, a green sub-pixel G1, and a green sub-pixel G2. The pixel arrangement is not limited. The green sub-pixels G1 and G2 are obtained by dividing a green sub-pixel G. The sum of the areas of the green sub-pixels G1 and G2 is equal to the area of ​​the green sub-pixel G. The anodes of the green sub-pixels G1 and G2 are independent and not connected. In this design, the first OLED light-emitting device D1 is a green sub-pixel G1, and the second OLED light-emitting device D2 is a green sub-pixel G2. Due to the special properties of the green light-emitting device material, the parasitic capacitance of the green sub-pixel G is greater than that of the red sub-pixel R and the blue sub-pixel B. This results in the green sub-pixel G lighting up slower than the red sub-pixel R and the blue sub-pixel B in low-brightness displays. When the green sub-pixel G is divided into green sub-pixels G1 and G2, the areas of both green sub-pixels G1 and G2 are smaller than the area of ​​the green sub-pixel G. Consequently, the parasitic capacitance of the green sub-pixel G1 is reduced, leading to a faster lighting up speed of the green sub-pixel G1 in low-brightness displays. This reduces the difference in lighting speed between the green sub-pixel and the red and blue sub-pixels, thus improving issues such as color shift, color unevenness, and ghosting that occur in low-brightness, low-grayscale displays.

[0033] In one embodiment, Figure 8 A pixel circuit structure diagram provided for an embodiment of this application, such as Figure 8As shown, the driving module 100 includes a first transistor T1, the first electrode of the first transistor T1 serves as the first terminal of the driving module 100, the second electrode of the first transistor T1 serves as the second terminal of the driving module 100, and the gate of the first transistor T1 serves as the control terminal of the driving module 100; the gating module 103 includes a second transistor T2, the first electrode of the second transistor T2 serves as the first terminal of the gating module 103, the second electrode of the second transistor T2 serves as the second terminal of the gating module 103, and the gate of the second transistor T2 serves as the control terminal of the gating module 103. In this configuration, the conduction level of the first transistor T1 is the same as that of the second transistor T2. For example, both transistors T1 and T2 are P-type transistors. The semiconductor materials of both transistors T1 and T2 include low-temperature polycrystalline silicon. P-type transistors conduct at low levels. In high-brightness display mode, the first transistor T1 needs to output a larger drive current. At this time, the gate voltage of the first transistor T1 is low. Since the second transistor T2 is also a P-type transistor, its gate is affected by the low gate voltage of the first transistor T1, and thus, the second transistor T2 is in a conducting state. The drive current output from the second terminal of the first transistor T1 is transmitted to the second OLED light-emitting device D2 through the second transistor T2. The first OLED light-emitting device D1 and the second... OLED light-emitting device D2 emits light simultaneously. In low-brightness display mode, the first transistor T1 needs to output a smaller driving current. At this time, the gate voltage of the first transistor T1 is relatively high. Since the second transistor T2 is also a P-type transistor, the gate of the second transistor T2 is affected by the high gate voltage of the first transistor T1. The second transistor T2 is in the off state, and the driving current output from the second terminal of the first transistor T1 cannot be transmitted to the second OLED light-emitting device D2 through the second transistor T2. The second OLED light-emitting device D2 is turned off, and only the first OLED light-emitting device D1 emits light, that is, only the green sub-pixel G1 emits light. This makes the lighting speed of the green sub-pixel G1 faster, reduces the difference in lighting speed between the green sub-pixel and the red sub-pixel R and the blue sub-pixel B, and improves the display effect of low brightness and low grayscale. It should be noted that in this embodiment, the first transistor T1 and the second transistor T2 can also be N-type transistors. The semiconductor materials of the first transistor T1 and the second transistor T2 both include metal oxide. The structure of the pixel circuit and its driving timing need to be adapted. The working principle and effect are the same as those in the above embodiment, and will not be repeated here.

[0034] In one embodiment, Figure 6 Another pixel circuit architecture diagram provided for embodiments of this application, such as Figure 6As shown, the pixel circuit also includes a threshold compensation module 105, a first light emission control module 106, and a second light emission control module 107. The first end of the threshold compensation module 105 is electrically connected to the control terminal of the driving module 100, and the second end of the threshold compensation module 105 is electrically connected to the second end of the driving module 100. The control terminal of the threshold compensation module 105 is electrically connected to the second scan line, and a second scan signal S2 is transmitted on the second scan line. The first light emission control module 106 is electrically connected between the driving module 100 and the first power line, and the first end of the first light emission control module 106 is electrically connected to the first power line. The second terminal of the first light-emitting control module 106 is electrically connected to the first terminal of the driving module 100. The control terminal of the first light-emitting control module 106 is electrically connected to the light-emitting control scan line, and the light-emitting control signal EM is transmitted on the light-emitting control scan line. The second light-emitting control module 107 is electrically connected between the driving module 100 and the first light-emitting module 101. The first terminal of the second light-emitting control module 107 is electrically connected to the second terminal of the driving module 100, the second terminal of the second light-emitting control module 107 is electrically connected to the first terminal of the first light-emitting module 101, and the control terminal of the second light-emitting control module 107 is electrically connected to the light-emitting control scan line. The first terminal of the gating module 103 is electrically connected to the second terminal of the second light-emitting control module 107.

[0035] Continue to refer to Figure 6 The pixel circuit also includes a first reset module 108 and a second reset module 110. The first terminal of the first reset module 108 is electrically connected to a first initialization signal line, which transmits a first initialization voltage Vref1. The second terminal of the first reset module 108 is electrically connected to the control terminal of the drive module 100 and to a first scan line, which transmits a first scan signal S1. The first terminal of the second reset module 110 is electrically connected to a second initialization signal line, which transmits a second initialization voltage Vref2. The second terminal of the second reset module 110 is electrically connected to the first terminal of the first light-emitting module 101 and to a third scan line, which transmits a third scan signal S3. The voltage value of the first initialization voltage Vref1 is less than the voltage value of the second initialization voltage Vref2. Since the first terminal of the gating module 103 is electrically connected to the second terminal of the second light-emitting control module 107, the gating module 103 is in the conducting state in the high-brightness display mode. The second initialization voltage Vref2 is transmitted through the gating module 103 to the first terminal of the second light-emitting module 102 to initialize it, which saves transistors, helps to optimize the layout space, and improves PPI.

[0036] In one embodiment, the start time of the conduction level transmitted by the first scan line electrically connected to the first reset module 108 is no later than the start time of the conduction level transmitted by the third scan line electrically connected to the second reset module 110, and the start time of the conduction level in the first scan signal S1 is no later than the start time of the conduction level in the third scan signal S3. In this embodiment, both the first reset module 108 and the second reset module 110 include P-type transistors. Figure 7 A pixel circuit driving timing diagram provided for an embodiment of this application, such as Figure 7 As shown, the start time of the low level in the first scan signal S1 is no later than the start time of the low level in the third scan signal S3, making the timing of the third scan signal S3 flexible and adjustable.

[0037] In one embodiment, the pulse width of the conduction level transmitted by the third scan line electrically connected to the second reset module 110 is greater than the pulse width of the conduction level transmitted by the first scan line electrically connected to the first reset module 108. That is, the pulse width of the low level in the third scan signal S3 is greater than the pulse width of the low level in the first scan signal S1, which increases the anode initialization time and is beneficial to improving the afterimage effect.

[0038] Furthermore, the start time of the conduction level transmitted by the first scan line electrically connected to the first reset module 108 is the same as the start time of the conduction level transmitted by the third scan line electrically connected to the second reset module 110. That is, the start time of the low level in the first scan signal S1 is the same as the start time of the low level in the third scan signal S3, which can maximize the anode initialization time and improve the afterimage effect. or, The end time of the conduction level transmitted by the first scan line electrically connected to the first reset module 108 is the same as the start time of the conduction level transmitted by the third scan line electrically connected to the second reset module 110. That is, the end time of the low level in the first scan signal S1 is the same as the start time of the low level in the third scan signal S3, so that the gate initialization process and the anode initialization process are performed independently and do not interfere with each other.

[0039] Preferably, the conduction level transmitted by the first scan line electrically connected to the first reset module 108 is prior to and does not overlap with the conduction level transmitted by the second scan line electrically connected to the threshold compensation module 105, that is, the low level in the first scan signal S1 is prior to and does not overlap with the low level in the second scan signal S2. The start time of the conduction level transmitted by the third scan line electrically connected to the second reset module 110 is prior to the start time of the conduction level transmitted by the second scan line electrically connected to the threshold compensation module 105, that is, the start time of the low level in the third scan signal S3 is prior to the start time of the low level in the second scan signal S2. The end time of the conduction level transmitted by the third scan line electrically connected to the second reset module 110 is prior to the end time of the conduction level transmitted by the second scan line electrically connected to the threshold compensation module 105, that is, the end time of the low level in the third scan signal S3 is prior to the end time of the low level in the second scan signal S2. Figure 15 As shown, the low level of the third scan signal S3 can be flexibly designed between the start time of the low level in the first scan signal S1 and the end time of the low level in the second scan signal S2, reducing the design difficulty and making it easier to adjust the timing according to actual needs.

[0040] Continue to refer to Figure 6 The pixel circuit also includes a data writing module 109 and a storage module 104. The first end of the data writing module 109 is electrically connected to the data voltage signal line, and the data voltage Vdata is transmitted on the data voltage signal line. The second end of the data writing module 109 is electrically connected to the first end of the driving module 100. The control end of the data writing module 109 is electrically connected to the second scan line. The data writing module 109 transmits the data voltage Vdata to the first end of the driving module 100 in response to the conduction level in the second scan signal S2. The first end of the storage module 104 is electrically connected to the first power line. The second end of the storage module 104 is electrically connected to the control end of the driving module 100. The storage module 104 maintains the potential of the control end of the driving module 100.

[0041] Continue to refer to Figure 8In this embodiment, the threshold compensation module 105 includes a third transistor T3, the first electrode of the third transistor T3 serves as the first terminal of the threshold compensation module 105, the second electrode of the third transistor T3 serves as the second terminal of the threshold compensation module 105, and the gate of the third transistor T3 serves as the control terminal of the threshold compensation module 105; the first light-emitting control module 106 includes a fourth transistor T4, the first electrode of the fourth transistor T4 serves as the first terminal of the first light-emitting control module 106, the second electrode of the fourth transistor T4 serves as the second terminal of the first light-emitting control module 106, and the gate of the fourth transistor T4 serves as the control terminal of the first light-emitting control module 106; the second light-emitting control module 107 includes a fifth transistor T5, the first electrode of the fifth transistor T5 serves as the first terminal of the second light-emitting control module 107, the second electrode of the fifth transistor T5 serves as the second terminal of the second light-emitting control module 107, and the gate of the fifth transistor T5 serves as the control terminal of the second light-emitting control module 107; the first reset module 108 includes a sixth transistor T6, the sixth... The first terminal of transistor T6 serves as the first terminal of the first reset module 108, the second terminal of transistor T6 serves as the second terminal of the first reset module 108, and the gate of transistor T6 serves as the control terminal of the first reset module 108; the data writing module 109 includes a seventh transistor T7, the first terminal of transistor T7 serves as the first terminal of the data writing module 109, the second terminal of transistor T7 serves as the second terminal of the data writing module 109, and the gate of transistor T7 serves as the control terminal of the data writing module 109; the second reset module 110 includes an eighth transistor T8, the first terminal of transistor T8 serves as the first terminal of the second reset module 110, the second terminal of transistor T8 serves as the second terminal of the second reset module 110, and the gate of transistor T8 serves as the control terminal of the second reset module 110; the storage module 104 includes a storage capacitor Cst, the first terminal of storage capacitor Cst serves as the first terminal of storage module 104, and the second terminal of storage capacitor Cst serves as the second terminal of storage module 104. The conduction level of the seventh transistor T7 is the same as that of the third transistor T3, meaning that the seventh transistor T7 and the third transistor T3 are both P-type transistors, or the seventh transistor T7 and the third transistor T3 are both N-type transistors.

[0042] In one embodiment, reference Figure 8Taking all transistors as P-type transistors as an example, the first terminal of the first transistor T1 is electrically connected to the second terminal of the fourth transistor T4. The first terminal of the fourth transistor T4 is connected to the first power supply voltage VDD, and the gate of the fourth transistor T4 is connected to the light emission control signal EM. The second terminal of the first transistor T1 is electrically connected to the first terminal of the fifth transistor T5. The second terminal of the fifth transistor T5 is electrically connected to the anode of the first OLED light-emitting device D1, and the gate of the fifth transistor T5 is connected to the light emission control signal EM. The cathode of the first OLED light-emitting device D1 is connected to the second power supply voltage VSS. The storage capacitor Cst is electrically connected between the gate of the first transistor T1 and the first power supply line. The third transistor T3 is electrically connected between the gate of the first transistor T1 and the second terminal of the first transistor T1. The gate of the third transistor T3 is connected to the second scan signal S2. The first terminal of the sixth transistor T6 is connected to the first initialization voltage Vref. 1. The second terminal of the sixth transistor T6 is electrically connected to the gate of the first transistor T1. The gate of the sixth transistor T6 is connected to the first scan signal S1. The first terminal of the second transistor T2 is electrically connected to the second terminal of the fifth transistor T5. The second terminal of the second transistor T2 is electrically connected to the anode of the second OLED light-emitting device D2. The gate of the second transistor T2 is electrically connected to the gate of the first transistor T1. The cathode of the second OLED light-emitting device D2 is connected to the second power supply voltage VSS. The first terminal of the seventh transistor T7 is connected to the data voltage Vdata. The second terminal of the seventh transistor T7 is electrically connected to the first terminal of the first transistor T1. The gate of the seventh transistor T7 is connected to the second scan signal S2. The first terminal of the eighth transistor T8 is connected to the second initialization voltage Vref2. The second terminal of the eighth transistor T8 is electrically connected to the anode of the first OLED light-emitting device D1. The gate of the eighth transistor T8 is connected to the third scan signal S3.

[0043] The following is combined Figure 15 The driving timing pairs in Figure 8 The working process of the mid-pixel circuit is described as follows: Phase 1 t1: This is the first initialization phase. The first scan signal S1 is low, the sixth transistor T6 is turned on, and the other transistors are turned off. The first initialization voltage Vref1 is transmitted to the gate of the first transistor T1 to initialize it. At this time, the gate voltage Vg of the first transistor T1 is Vref1. Second stage t2: This stage is the second initialization stage. The first scan signal S1 jumps to a high level, the third scan signal S3 jumps to a low level, the eighth transistor T8 is turned on, the gate potential of the second transistor T2 is the first initialization voltage Vref1, the first initialization voltage Vref1 is a low voltage, the second transistor T2 is turned on, the other transistors are turned off, and the second initialization voltage Vref2 is transmitted to the anode of the first OLED light-emitting device D1 and the anode of the second OLED light-emitting device D2 to initialize them.

[0044] The third stage t3: This stage is the data writing and threshold compensation stage. The third scan signal S3 jumps to a high level, the second scan signal S2 jumps to a low level, the third transistor T3 and the seventh transistor T7 are turned on, and the other transistors are turned off. The data voltage Vdata is transmitted to the gate of the first transistor T1 through the first and second terminals of the first transistor T1. When the gate voltage Vg of the first transistor T1 = Vdata + Vth, the first transistor T1 is turned off, completing the data writing and threshold compensation. Phase 4 (t4): This is the light-emitting phase. The second scan signal S2 transitions to a high level, and the light-emitting control signal EM transitions to a low level. The fourth transistor T4 and the fifth transistor T5 are turned on. The first power supply voltage VDD is transmitted to the first terminal of the first transistor T1, turning on the first transistor T1. The third transistor T3, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all turned off. The first transistor T1 generates a drive current based on its gate voltage. I = (1 / 2) μ Cox (W / L) (Vdata-VDD)^2 Among them, (1 / 2) μ Cox (W / L) is a fixed constant.

[0045] When the display is in high brightness, the gate voltage of the first transistor T1 should be low, meaning the data voltage Vdata needs to be low. The first transistor T1 has a strong driving capability and a large driving current. Since the gate of the second transistor T2 shares the same potential as the gate of the first transistor T1, the second transistor T2 is in the on state at this time. The driving current drives the first OLED light-emitting device D1 and the second OLED light-emitting device D2 to emit light simultaneously. The first OLED light-emitting device D1 corresponds to the green sub-pixel G1, and the second OLED light-emitting device D2 corresponds to the green sub-pixel G2. Figure 9The diagram illustrates the current distribution before and after green sub-pixel segmentation under high-brightness display. As shown, under high-brightness display, the lighting speed of the segmented green sub-pixels G1 and G2 is the same as that of the unsegmented green sub-pixel G, indicating no significant difference between segmented and unsegmented green sub-pixels. Under low-brightness display, the gate voltage of the first transistor T1 should be higher, meaning the data voltage Vdata needs to be higher. The driving capability of the first transistor T1 is weaker, resulting in a smaller driving current. Since the gate of the second transistor T2 shares the same potential as the gate of the first transistor T1, the second transistor T2 is in the off state, and the driving current only drives the first OLED light-emitting device D1 to emit light. Figure 10 The diagram shows the current before and after the green sub-pixel is divided under low brightness display. As can be seen from the diagram, under low brightness display, the green sub-pixel G1 after division has a faster start-up speed than the green sub-pixel G before division. Therefore, the difference in start-up speed between the green sub-pixel and the red and blue sub-pixels is reduced, which improves the problems of color shift, color unevenness, and ghosting that occur when displaying low brightness and low grayscale.

[0046] In one embodiment, Figure 11 Another pixel circuit architecture diagram provided for embodiments of this application, such as Figure 11 As shown, the pixel circuit also includes a third reset module 111. The first terminal of the third reset module 111 is electrically connected to the second initialization signal line, the second terminal of the third reset module 111 is electrically connected to the first terminal of the second light-emitting module 102, and the control terminal of the third reset module 111 is electrically connected to the third scan line. Specifically, the third reset module 111 includes a ninth transistor T9. The first electrode of the ninth transistor T9 serves as the first terminal of the third reset module 111, the second electrode of the ninth transistor T9 serves as the second terminal of the third reset module 111, and the gate of the ninth transistor T9 serves as the control terminal of the third reset module 111. The conduction level of the ninth transistor T9 is the same as the conduction level of the eighth transistor T8. Figure 12 Another pixel circuit structure diagram provided in the embodiments of this application, such as Figure 12 As shown, the ninth transistor T9 is a P-type transistor. The first terminal of the ninth transistor T9 is connected to the second initialization voltage Vref2, the second terminal of the ninth transistor T9 is electrically connected to the anode of the second OLED light-emitting device D2, and the gate of the ninth transistor T9 is connected to the third scan signal S3. The pixel circuit in this embodiment is also applicable. Figure 15 The pixel circuit driving timing shown is consistent with the operation process. Figure 8 The operation of the pixel circuit shown is the same, except that in the second stage t2, the ninth transistor T9 also controls the second initialization voltage Vref2 to initialize the anode of the second OLED light-emitting device D2.

[0047] In one embodiment, the conduction level of the third transistor T3 is the same as that of the eighth transistor T8, meaning that both the third transistor T3 and the eighth transistor T8 are P-type transistors. In this case, the signal transmitted by the second scan line is multiplexed to the signal transmitted by the third scan line. The gates of both the third transistor T3 and the eighth transistor T8 are connected to the second scan signal S2. The pixel circuit driving timing is as follows: Figure 16 As shown, Figure 12 The working process of the intermediate pixel circuit is as follows: Phase 1 w1: This phase is the first initialization phase. The first scan signal S1 is low, the sixth transistor T6 is turned on, and the other transistors are turned off. The first initialization voltage Vref1 is transmitted to the gate of the first transistor T1 to initialize it. At this time, the gate voltage Vg of the first transistor T1 is Vref1. Phase 2 (w2): This phase is for data writing and threshold compensation. The first scan signal S1 jumps to a high level, the second scan signal S2 jumps to a low level, and the third transistor T3 and the seventh transistor T7 are turned on. The data voltage Vdata is transmitted to the gate of the first transistor T1 through the first and second terminals. When the gate voltage Vg of the first transistor T1 is equal to Vdata + Vth, the first transistor T1 is turned off, completing the data writing and threshold compensation. At the same time, the eighth transistor T8 and the ninth transistor T9 are also turned on. The eighth transistor T8 controls the second initialization voltage Vref2 to initialize the anode of the first OLED light-emitting device D1, and the ninth transistor T9 controls the second initialization voltage Vref2 to initialize the anode of the second OLED light-emitting device D2. Phase 3 w3: This is the luminescence stage, and its process is similar to... Figure 8 The light-emitting stages of the pixel circuits shown are the same, and will not be described again here.

[0048] This embodiment reduces the number of scanning circuits by multiplexing the second scanning signal S2 into the third scanning signal S3, which is beneficial for narrow bezels.

[0049] In one embodiment, Figure 13 Another pixel circuit architecture diagram provided for embodiments of this application, such as Figure 13 As shown, the first terminal of the gating module 103 is electrically connected to the first terminal of the second light-emitting control module 107, that is, the first electrode of the second transistor T2 is electrically connected to the first electrode of the fifth transistor T5, as shown. Figure 14 As shown, Figure 14 Medium pixel circuits are also applicable Figure 15 and Figure 16 The pixel circuit driving timing shown is consistent with the operation process. Figure 12 The operation of the pixel circuit shown is the same, and will not be described again here.

[0050] This application embodiment also provides a display panel, including the pixel circuit of any of the above embodiments. The pixel circuit is used to drive the first light-emitting module 101 and the second light-emitting module 102 to emit light, wherein the second light-emitting module 102 is also controlled by the gating module 103 in the pixel circuit to emit light. The display panel includes a plurality of pixel repeating units. For example, each pixel repeating unit includes a red sub-pixel R, a blue sub-pixel B, a green sub-pixel G1, and a green sub-pixel G2, such as... Figure 5 As shown, green sub-pixels G1 and G2 are obtained by dividing a single green sub-pixel G. The sum of the areas of green sub-pixels G1 and G2 is equal to the area of ​​green sub-pixel G. Furthermore, the anodes of green sub-pixels G1 and G2 are independent and not connected. The first light-emitting module 101 is the green sub-pixel G1, and the second light-emitting module 102 is the green sub-pixel G2. The pixel aperture area of ​​green sub-pixels G1 and G2 can be the same or different.

[0051] The display panel includes a low-brightness display mode and a high-brightness display mode. In the low-brightness display mode, the gating module 103 is turned off, the green sub-pixel G2 is turned off, and the green sub-pixel G1 is illuminated. In the high-brightness display mode, the gating module 103 is turned on, and both the green sub-pixel G2 and the green sub-pixel G1 are illuminated. Due to the special properties of the green light-emitting device material, the parasitic capacitance of the green sub-pixel G is greater than that of the red sub-pixel R and the blue sub-pixel B. This results in the green sub-pixel G lighting up slower than the red sub-pixel R and the blue sub-pixel B in low-brightness displays. In this embodiment, the green sub-pixel G is divided into green sub-pixels G1 and G2. The areas of both green sub-pixels G1 and G2 are smaller than the area of ​​green sub-pixel G, thus reducing the parasitic capacitance of green sub-pixel G1. This makes the green sub-pixel G1 light up faster in low-brightness displays, reducing the difference in lighting speed between the green sub-pixel and the red and blue sub-pixels, and improving problems such as color shift, color unevenness, and ghosting that occur in low-brightness, low-grayscale displays.

[0052] This application also provides a method for driving a pixel circuit, used to drive the pixel circuit in any of the above embodiments, the method comprising: The detailed working process of each stage of the pixel circuit is the same as described in the above embodiments, and will not be repeated here.

[0053] In the low brightness display mode, the driving module 100 generates a first driving current according to the first potential of the control terminal of the driving module 100, and the gating module 103 turns off in response to the first potential of the control terminal of the driving module 100. The first driving current drives the first light-emitting module 101 to emit light. In high-brightness display mode, the driving module 100 generates a second driving current according to the second potential of the control terminal of the driving module 100. The gating module 103 responds to the second potential of the control terminal of the driving module 100 and turns on. The second driving current drives the first light-emitting module 101 and the second light-emitting module 102 to emit light simultaneously.

[0054] This application also provides a display device, including the display panel described above. Figure 17 This is a schematic diagram of the structure of a display device provided in an embodiment of this application, with reference to... Figure 17 In this embodiment, the display device 200 can be a mobile phone or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. This application embodiment does not make any special limitation on this.

[0055] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0056] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pixel circuit, characterized in that, include: A drive module, wherein a first end of the drive module is electrically connected to a first power line and a second end of the drive module is electrically connected to a second power line, and the drive module is used to generate drive current; A gating module, wherein a first terminal of the gating module is electrically connected to a second terminal of the driving module, and a control terminal of the gating module is electrically connected to a control terminal of the driving module; A first light-emitting module is electrically connected between the driving module and the second power line. A first end of the first light-emitting module is electrically connected to a second end of the driving module, and a second end of the first light-emitting module is electrically connected to the second power line. The second light-emitting module is electrically connected between the gating module and the second power line. The first end of the second light-emitting module is electrically connected to the second end of the gating module, and the second end of the second light-emitting module is electrically connected to the second power line. The gating module is used to control the second light-emitting module to light up or turn off.

2. The pixel circuit according to claim 1, characterized in that, The driving module includes a first transistor, the first electrode of the first transistor serving as the first terminal of the driving module, the second electrode of the first transistor serving as the second terminal of the driving module, and the gate of the first transistor serving as the control terminal of the driving module; the gating module includes a second transistor, the first electrode of the second transistor serving as the first terminal of the gating module, the second electrode of the second transistor serving as the second terminal of the gating module, and the gate of the second transistor serving as the control terminal of the gating module. The turn-on level of the first transistor is the same as the turn-on level of the second transistor; Preferably, the semiconductor material of both the first transistor and the second transistor comprises low-temperature polycrystalline silicon.

3. The pixel circuit according to claim 1, characterized in that, It also includes a threshold compensation module, a first light emission control module, and a second light emission control module; The first end of the threshold compensation module is electrically connected to the control end of the drive module, the second end of the threshold compensation module is electrically connected to the second end of the drive module, and the control end of the threshold compensation module is electrically connected to the second scan line. The first light-emitting control module is electrically connected between the driving module and the first power line. The first end of the first light-emitting control module is electrically connected to the first power line. The second end of the first light-emitting control module is electrically connected to the first end of the driving module. The control end of the first light-emitting module is electrically connected to the light-emitting control scan line. The second light-emitting control module is electrically connected between the driving module and the first light-emitting module. The first end of the second light-emitting control module is electrically connected to the second end of the driving module, the second end of the second light-emitting module is electrically connected to the first end of the first light-emitting module, and the control end of the second light-emitting module is electrically connected to the light-emitting control scan line. Preferably, the threshold compensation module includes a third transistor, the first electrode of the third transistor serves as the first terminal of the threshold compensation module, the second electrode of the third transistor serves as the second terminal of the threshold compensation module, and the gate of the third transistor serves as the control terminal of the threshold compensation module. The first light-emitting control module includes a fourth transistor, the first electrode of the fourth transistor serves as the first terminal of the first light-emitting control module, the second electrode of the fourth transistor serves as the second terminal of the first light-emitting control module, and the gate of the fourth transistor serves as the control terminal of the first light-emitting control module. The second light-emitting control module includes a fifth transistor, wherein the first electrode of the fifth transistor serves as the first terminal of the second light-emitting control module, the second electrode of the fifth transistor serves as the second terminal of the second light-emitting control module, and the gate of the fifth transistor serves as the control terminal of the second light-emitting control module.

4. The pixel circuit according to claim 3, characterized in that, The first end of the gating module is electrically connected to the first end of the second light-emitting control module; or, The first end of the gating module is electrically connected to the second end of the second light-emitting control module.

5. The pixel circuit according to claim 4, characterized in that, It also includes a first reset module and a second reset module; The first terminal of the first reset module is electrically connected to the first initialization signal line, the second terminal of the first reset module is electrically connected to the control terminal of the drive module, and the control terminal of the first reset module is electrically connected to the first scan line. The first end of the second reset module is electrically connected to the second initialization signal line, the second end of the second reset module is electrically connected to the first end of the first light-emitting module, and the control end of the second reset module is electrically connected to the third scan line. Preferably, the start time of the conduction level transmitted by the first scan line electrically connected to the first reset module is not later than the start time of the conduction level transmitted by the third scan line electrically connected to the second reset module. Preferably, the pulse width of the conduction level transmitted by the third scan line electrically connected to the second reset module is greater than the pulse width of the conduction level transmitted by the first scan line electrically connected to the first reset module. Preferably, the start time of the conduction level transmitted by the first scan line electrically connected to the first reset module is the same as the start time of the conduction level transmitted by the third scan line electrically connected to the second reset module. or, The end time of the conduction level transmitted by the first scan line electrically connected to the first reset module is the same as the start time of the conduction level transmitted by the third scan line electrically connected to the second reset module. Preferably, the conduction level transmitted by the first scan line electrically connected to the first reset module is prior to and does not overlap with the conduction level transmitted by the second scan line electrically connected to the threshold compensation module; the start time of the conduction level transmitted by the third scan line electrically connected to the second reset module is prior to the start time of the conduction level transmitted by the second scan line electrically connected to the threshold compensation module; and the end time of the conduction level transmitted by the third scan line electrically connected to the second reset module is prior to the end time of the conduction level transmitted by the second scan line electrically connected to the threshold compensation module. Preferably, the first reset module includes a sixth transistor, the first terminal of the sixth transistor serves as the first terminal of the first reset module, the second terminal of the sixth transistor serves as the second terminal of the first reset module, and the gate of the sixth transistor serves as the control terminal of the first reset module. The second reset module includes an eighth transistor, the first terminal of which serves as the first terminal of the second reset module, the second terminal of which serves as the second terminal of the second reset module, and the gate of which serves as the control terminal of the second reset module.

6. The pixel circuit according to claim 5, characterized in that, It also includes a third reset module; The first terminal of the third reset module is electrically connected to the second initialization signal line, the second terminal of the third reset module is electrically connected to the first terminal of the second light-emitting module, and the control terminal of the third reset module is electrically connected to the third scan line. Preferably, the third reset module includes a ninth transistor, the first terminal of the ninth transistor serves as the first terminal of the third reset module, the second terminal of the ninth transistor serves as the second terminal of the third reset module, and the gate of the ninth transistor serves as the control terminal of the third reset module; the conduction level of the ninth transistor is the same as the conduction level of the eighth transistor. Preferably, the conduction level of the third transistor is the same as that of the eighth transistor, and the signal transmitted by the second scan line is multiplexed as the signal transmitted by the third scan line.

7. The pixel circuit according to claim 3, characterized in that, It also includes a data writing module and a storage module; The first end of the data writing module is electrically connected to the data voltage signal line, the second end of the data writing module is electrically connected to the first end of the driving module, and the control end of the data writing module is electrically connected to the second scan line. The first end of the storage module is electrically connected to the first power line, and the second end of the storage module is electrically connected to the control end of the drive module. Preferably, the data writing module includes a seventh transistor, the first terminal of the seventh transistor serves as the first terminal of the data writing module, the second terminal of the seventh transistor serves as the second terminal of the data writing module, and the gate of the seventh transistor serves as the control terminal of the data writing module; The storage module includes a storage capacitor, with the first terminal of the storage capacitor serving as the first terminal of the storage module and the second terminal of the storage capacitor serving as the second terminal of the storage module. The conduction level of the seventh transistor is the same as that of the third transistor.

8. A display panel comprising the pixel circuitry according to any one of claims 1-7, characterized in that, The display panel includes a low-brightness display mode and a high-brightness display mode. In the low-brightness display mode, the gating module is turned off, the second light-emitting module is turned off, and the first light-emitting module emits light. In the high-brightness display mode, the gating module is turned on, and both the second light-emitting module and the first light-emitting module emit light.

9. The display panel according to claim 8, characterized in that, The first light-emitting module and the second light-emitting module are located in the same pixel repeating unit; Preferably, the light emission color of the first light-emitting module is the same as the light emission color of the second light-emitting module; Preferably, the light emission color of the first light-emitting module and the light emission color of the second light-emitting module are both green; Preferably, the first light-emitting module includes a first sub-pixel, the second light-emitting module includes a second sub-pixel, and the pixel aperture area of ​​the first sub-pixel is the same as the pixel aperture area of ​​the second sub-pixel.

10. A method for driving a pixel circuit, used to drive the pixel circuit according to any one of claims 1-7, characterized in that, The method includes: In low brightness display mode, the driving module generates a first driving current according to the first potential of the control terminal of the driving module, and the gating module turns off in response to the first potential of the control terminal of the driving module. The first driving current drives the first light-emitting module to emit light. In high-brightness display mode, the driving module generates a second driving current according to the second potential of the control terminal of the driving module. The gating module responds to the second potential of the control terminal of the driving module and turns on. The second driving current drives the first light-emitting module and the second light-emitting module to emit light simultaneously.

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