Display panel, driving method of display panel, and display device

Abstract

This application relates to a display panel, a driving method for the display panel, and a display device. The display panel includes a source driving circuit, which, during the charging period of each sub-pixel unit, first outputs a compensation voltage of the sub-pixel unit to the corresponding data line, and then outputs the data voltage of the sub-pixel unit to the data line. This allows the energy storage capacitor of the sub-pixel unit to be charged to the data voltage via the driving transistor of the sub-pixel unit connected to the data line, where the compensation voltage is greater than the data voltage. This display panel solves the problem in the prior art where insufficient charging of the energy storage capacitor affects the display effect when the display panel is in high refresh rate mode.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a driving method for the display panel, and a display device. Background Technology

[0002] Currently, Organic Light Emitting Display (OLED) is one of the hot topics in the field of flat panel display research as a new generation of display panels. OLED has advantages such as low energy consumption, low production cost, self-illumination, wide viewing angle and fast response speed.

[0003] In the sub-pixel unit structure of a small-sized organic light-emitting diode (OLED) display panel, the source of the driving transistor is connected to the data line, the gate of the driving transistor is connected to the charging terminal of the energy storage capacitor, and the drain of the driving transistor is also connected to the charging terminal of the energy storage capacitor. The data line charges the energy storage capacitor by outputting a data voltage through the driving transistor. Therefore, during the charging process, the data voltage output by the data line remains constant, while the voltage at the gate of the driving transistor gradually increases. Consequently, the absolute value of the difference between the voltage at the gate and the voltage at the source of the driving transistor gradually decreases. Since the driving transistor is a P-type transistor, based on the characteristics of P-type transistors... It is known that as the absolute value of the difference between the gate voltage and the source voltage of the driving transistor decreases, the absolute value of the current flowing from the drain of the driving transistor to the source decreases, the charge provided by the driving transistor to the storage capacitor slows down, and the rising rate of the charging terminal of the storage capacitor decreases. If the display panel is in high refresh rate mode, the charging period is very short, and the charging terminal of the storage capacitor is prone to insufficient charging. During the light emission period, the voltage at the charging terminal of the energy storage capacitor affects the magnitude of the absolute value of the current flowing from the drain of the driving transistor to the source, which in turn affects the brightness of the organic light-emitting diode, thus affecting the display effect. Summary of the Invention

[0004] This application provides a display panel, a driving method for the display panel, and a display device to solve the problem in the prior art where insufficient charging of the energy storage capacitor affects the display effect when the display panel is in high refresh rate mode.

[0005] In a first aspect, this application provides a display panel, the display panel including: a source driving circuit, the source driving circuit being configured to first output a compensation voltage of the sub-pixel unit to the data line corresponding to the sub-pixel unit during the charging period of each sub-pixel unit, and then output a data voltage of the sub-pixel unit to the data line, so as to charge the energy storage capacitor of the sub-pixel unit to a target voltage through the driving transistor of the sub-pixel unit connected to the data line, the compensation voltage being greater than the data voltage, and the target voltage being the sum of the data voltage and the threshold voltage of the driving transistor.

[0006] Optionally, the display panel further includes: a timing controller; the source driving circuit includes: multiple sub-driving circuits, each sub-driving circuit corresponding to a column of sub-pixel units; each sub-driving circuit includes: a first driving unit and a first switching unit, the output terminal of the first driving unit being connected to a first terminal of the first switching unit, and the second terminal of the first switching unit being connected to a data line corresponding to the sub-driving circuit; a second driving unit and a second switching unit, the output terminal of the second driving unit being connected to a first terminal of the second switching unit, and the second terminal of the second switching unit being connected to the data line; wherein, the charging period includes a first charging sub-period and a second charging sub-period, the end time of the first charging sub-period being the time before the start time of the second charging sub-period; the output terminal of the first driving unit is used to output the complement of the sub-pixel unit during the first charging sub-period of the sub-pixel unit corresponding to the sub-driving circuit. The timing controller is configured to output an enable signal to the controlled terminal of the first switch unit during the first charging sub-period of the sub-pixel unit, thereby connecting the output terminal of the first drive unit and the data line, and to output a disable signal to the controlled terminal of the second switch unit of the sub-drive circuit, thereby disconnecting the connection between the second drive unit and the data line; the timing controller is configured to output the enable signal to the controlled terminal of the second switch unit during the second charging sub-period of the sub-pixel unit, thereby connecting the output terminal of the second drive unit and the data line, and to output the disable signal to the controlled terminal of the switch unit, thereby disconnecting the connection between the output terminal of the first drive unit and the data line.

[0007] Optionally, the display panel further includes: a first gamma circuit and a second gamma circuit. The timing controller is configured to output grayscale data of the compensation voltage of the sub-pixel unit to the input terminal of the first driving unit during a first charging sub-period of the sub-pixel unit, and send a timing control signal of the display gamma voltage to the first gamma circuit, so that the first gamma circuit outputs the display gamma voltage to the reference terminal of the first driving unit, wherein the display gamma voltage is the gamma voltage corresponding to the data voltage of the sub-pixel unit; the timing controller is configured to output the data voltage to the input terminal of the second driving unit during a second charging sub-period of the sub-pixel unit, and send a timing control signal of the display gamma voltage to the second gamma circuit, so that the second gamma circuit outputs the display gamma voltage to the reference terminal of the second driving unit; the first driving unit is configured to convert the grayscale data of the compensation voltage into the compensation voltage based on the display gamma voltage; the second driving unit is configured to convert the grayscale data of the data voltage into the data voltage based on the display gamma voltage.

[0008] Optionally, the display panel further includes: a first gamma circuit and a second gamma circuit. The timing controller is configured to output grayscale data of the data voltage of the sub-pixel unit to the input terminal of the first driving unit during a first charging sub-period of the sub-pixel unit, and send a timing control signal of the compensation gamma voltage to the first gamma circuit, so that the reference terminal of the first driving unit of the first gamma circuit outputs the compensation gamma voltage, wherein the compensation gamma voltage is the gamma voltage corresponding to the compensation voltage. The timing controller is configured to output grayscale data of the data voltage of the sub-pixel unit to the input terminal of the second driving unit during a second charging sub-period of the sub-pixel unit, and send a timing control signal of the display gamma voltage to the second gamma circuit, so that the reference terminal of the second driving unit of the second gamma circuit outputs the display gamma voltage, wherein the display gamma voltage is the gamma voltage corresponding to the data voltage, and the compensation gamma voltage is greater than the display gamma voltage. The first driving unit is configured to convert the grayscale data of the data voltage into the compensation voltage based on the compensation gamma voltage. The second driving unit is configured to convert the grayscale data of the data voltage into the data voltage based on the display gamma voltage.

[0009] Optionally, both the first driving unit and the second driving unit include: an input register module, a data latch module, a level conversion module, a digital-to-analog converter module, and an operational amplifier module. The input terminal of the input register module of the first driving unit is the input terminal of the first driving unit, and the input terminal of the input register module of the second driving unit is the input terminal of the second driving unit. The output terminal of the input register module is connected to the input terminal of the data latch module, the output terminal of the data latch module is connected to the input terminal of the level conversion module, the output terminal of the level conversion module is connected to the input terminal of the digital-to-analog converter module, the output terminal of the digital-to-analog converter module is connected to the input terminal of the operational amplifier module, the reference terminal of the digital-to-analog converter module of the first driving unit is the reference terminal of the first driving unit, the reference terminal of the digital-to-analog converter module of the second driving unit is the reference terminal of the second driving unit, and the output terminal of the operational amplifier module is connected to the corresponding data line.

[0010] Optionally, the timing controller is used to look up the duration of the first charging sub-period and the grayscale data of the compensation voltage of the sub-pixel unit from a first compensation data table during the charging period of the sub-pixel unit, based on the grayscale data of the data voltage of the sub-pixel unit. The first compensation data table contains the mapping relationship between the grayscale data of the data voltage, the duration of the first charging sub-period, and the grayscale data of the compensation voltage.

[0011] Optionally, the timing controller is used to look up the duration of the first charging sub-period and the timing control signal of the compensation gamma voltage of the sub-pixel unit from a second compensation data table during the charging period of the sub-pixel unit, based on the grayscale data of the data voltage of the sub-pixel unit. The second compensation data table contains the mapping relationship between the grayscale data of the data voltage, the duration of the first charging sub-period, and the timing control signal of the compensation gamma voltage.

[0012] Optionally, both the first switching unit and the second switching unit are P-type thin-film transistors.

[0013] Secondly, this application provides a driving method for a display panel, which is applied to any of the aforementioned display panels. The method includes: during the charging period of each sub-pixel unit, a driving source driving circuit first outputs a compensation voltage of the sub-pixel unit to the data line corresponding to the sub-pixel unit, and then outputs the data voltage of the sub-pixel unit to the data line, so as to charge the energy storage capacitor of the sub-pixel unit to a target voltage through the driving transistor of the sub-pixel unit connected to the data line, wherein the compensation voltage is greater than the data voltage, and the target voltage is the sum of the data voltage and the threshold voltage of the driving transistor.

[0014] Thirdly, this application provides a display device, which includes any of the aforementioned display panels.

[0015] In this embodiment, the voltage at the source of the driving transistor is equal to the voltage output by the data line. The higher the voltage output by the data line, the higher the voltage at the source of the driving transistor, and the greater the absolute value of the difference between the voltage at the gate and the source of the driving transistor. Compared to the prior art, where the data line continuously outputs a data voltage during the charging period, this application divides the charging period into two periods. In the first period, the data line outputs a compensation voltage, and in the second period, it outputs a data voltage. The compensation voltage is higher than the data voltage. Therefore, compared to the prior art, in the first period of the charging period, the absolute value of the difference between the voltage at the gate and the source of the driving transistor is greater, resulting in a larger absolute value of the current flowing from the drain of the driving transistor to the source. This leads to a faster charging speed of the energy storage capacitor and a greater rate of voltage rise in the energy storage capacitor. This ensures that even when the organic light-emitting display panel is in a high refresh rate mode, and the charging period is relatively short, the energy storage capacitor can still be charged to the target voltage, guaranteeing the display effect. This solves the problem in the prior art where insufficient charging of the energy storage capacitor affects the display effect when the display panel is in a high refresh rate mode. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0019] Figure 1 This is a schematic diagram of the 7T1C topology of a sub-pixel unit in the prior art; Figure 2 This is a schematic diagram of the current flow direction in the 7T1C topology of the sub-pixel unit during the reset period in the prior art; Figure 3 A schematic diagram of the current flow direction in the 7T1C topology of the sub-pixel unit during the charging period in the prior art; Figure 4This is a schematic diagram of the current flow direction in the 7T1C topology of the sub-pixel unit during the light emission period in the prior art; Figure 5 This is a schematic diagram of the characteristic curves of the driving transistor in a sub-pixel unit in the prior art; Figure 6 This is a schematic diagram of the voltage curve at the charging end of the energy storage capacitor in the sub-pixel unit in the prior art and in the embodiments of this application; Figure 7 A schematic diagram illustrating the structure of a display panel provided in an embodiment of this application; Figure 8 A schematic diagram illustrating the structure of another display panel provided in an embodiment of this application; Figure 9 A schematic diagram illustrating the timing of another display panel provided in an embodiment of this application; The symbols in the attached image are explained as follows: 1. Sub-pixel unit; 2. Source driving circuit; 20. Sub-driving circuit; 200. First driving unit; 210. First switching unit; 220. Second driving unit; 230. Second switching unit; 201. Input register module; 202. Data latch module; 203. Level conversion module; 204. Digital-to-analog conversion module; 205. Operational amplifier module; 3. Timing controller; 40. First gamma circuit; 41. Second gamma circuit. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0022] Currently, the structure of sub-pixel units in small-sized organic light-emitting display panels is generally a 7T1C topology, consisting of 7 transistors and one energy storage capacitor, such as... Figure 1As shown, the first switching transistor T1 controls whether the organic light-emitting diode (OLED) emits light; the driving transistor T2 controls the current reaching the OLED, thereby controlling its brightness; the first reset transistor T3 resets the voltage of the energy storage capacitor C; the voltage compensation transistor T4 compensates for the threshold voltage of the driving transistor T2 (this is prior art and will not be further explained here); the second switching transistor T5 controls when to supply power to the OLED; the charging transistor T6 transmits data voltage to charge the energy storage capacitor C; and the second reset transistor T7 controls the power supply to the OLED. The anode of the OLED is reset. The first switching transistor T1, driving transistor T2, first reset transistor T3, voltage compensation transistor T4, second switching transistor T5, charging transistor T6, and second reset transistor T7 are all P-type transistors. The first reset signal terminal VINT1 is connected to the reset voltage (the reset voltage is negative and less than the data voltage), and the second reset signal terminal VINT2 is also connected to the reset voltage. Each frame period is divided into a reset period, a charging period, and a light emission period. The positive power supply signal terminal ELVDD is connected to a first preset voltage (the first preset voltage is positive), and the negative power supply signal terminal ELVSS is connected to a second preset voltage (the second preset voltage is negative). The working principle of the 7T1C topology is as follows: During the reset period, such as Figure 1 and Figure 2 As shown, Figure 2 The arrows in the diagram indicate the direction of current flow. The symbol "X" indicates that the circuit is off. The first scan line Scan1 outputs an on voltage, which turns on the first reset transistor T3. This causes the first reset signal terminal VINT1 to reset the voltage at the charging terminal p of the storage capacitor C to the reset voltage through the third transistor T3. The voltage at the gate g of the driving transistor T2 is equal to the voltage at the charging terminal p of the energy storage capacitor C, which is also the reset voltage. The data line D does not output voltage. At this time, a stable voltage difference cannot be established between the gate g and the source s of the driving transistor T2. Therefore, the driving transistor T2 is off. The second scan line Scan2 outputs an off voltage (the off voltage is a positive voltage), which turns off the voltage compensation transistor T4, the charging transistor T6, and the second reset transistor T7. The third scan line EM outputs an off voltage, which turns off the first switching transistor T1 and the second switching transistor T5. During the charging period, such as Figure 1 and Figure 3 As shown, Figure 3The arrows in the diagram indicate the direction of current flow. The symbol "X" indicates that the circuit is off. The second scan line Scan2 outputs an on-state voltage (the on-state voltage is negative), which turns on the second reset transistor T7. This causes the second reset signal terminal VINT2 to reset the voltage of the anode of the organic light-emitting diode (OLED) to the reset voltage through the second reset transistor T7. The second scan line Scan2 also outputs an on-state voltage, which turns on the voltage compensation transistor T4 and the charging transistor T6. The data line D outputs the data voltage. At this time, the voltage of the gate g of the driving transistor T2 is the reset voltage, and the voltage of the source s of the driving transistor T2 is the data voltage. The difference between the voltage of the gate g and the voltage of the source s of the driving transistor T2 (the difference between the reset voltage and the data voltage) is less than the threshold voltage of the driving transistor T2. The driving transistor T2 is a P-type transistor, so the driving transistor T2 is turned on. The data line D charges the charging terminal p of the energy storage capacitor C to the data voltage through the charging transistor T6, the driving transistor T2, and the voltage compensation transistor T4, thus raising the voltage of the driving transistor T2 to the data voltage. The first scan line Scan1 and the third scan line EM both output an off-state voltage. During the luminescent period, such as Figure 1 and Figure 4 As shown, Figure 4 The arrows indicate the direction of current flow, and the symbol "X" indicates off. The third scan line EM outputs an on-state voltage, turning on both the first switching transistor T1 and the second switching transistor T5. At this time, the voltage at the gate g of the driving transistor T2 is the data voltage, and the voltage at the source s of the driving transistor T2 is the first preset voltage connected to the positive power supply signal terminal ELVDD. The difference between the voltage at the gate g and the voltage at the source s of the driving transistor T2 (the difference between the data voltage and the first preset voltage) is less than the threshold voltage of the driving transistor T2. Therefore, the driving transistor T2 is turned on, allowing the positive power supply signal terminal ELVDD to supply power to the organic light-emitting diode OLED through the driving transistor T2 and the first switching transistor T1, thereby causing the organic light-emitting diode OLED to emit light. The data line D does not output a data voltage, and both the first scan line Scan1 and the second scan line Scan2 output off-state voltages, turning off the first reset transistor T3, the voltage compensation transistor T4, the charging transistor T6, and the second reset transistor T7.

[0023] See above, such as Figure 1 and Figure 3 As shown, during the charging period, the data voltage output by data line D remains constant. Therefore, the voltage at the source s of driving transistor T2 remains constant, equal to the data voltage. The charging terminal p of the energy storage capacitor C is connected to the gate g of driving transistor T2. The voltage at the gate g of driving transistor T2 gradually rises from the reset voltage to the data voltage. Therefore, during the charging process, the absolute value of the difference between the voltage at the gate g and the voltage at the source s of driving transistor T2 gradually decreases. Figure 5 The characteristic curve of the driving transistor T2, Figure 5 In the middle, V gs The arrow represents the difference between the gate voltage (g) and the source voltage (s) of transistor T2 during charging. gs The changing trend, I ds To drive the current flowing from the drain d to the source s of transistor T2, such as Figure 5 As shown, during the charging process, as V... gs The absolute value of I decreases. ds The absolute value of also decreases, causing the rate at which the driving transistor T2 supplies charge to the storage capacitor C to gradually slow down. Figure 6 S1 in the figure represents the voltage change curve at the charging terminal p of the energy storage capacitor C during the charging period in the prior art, V p This represents the voltage at the charging terminal p of the energy storage capacitor C. During the charging process, the rate at which the driving transistor T2 supplies charge to the storage capacitor C gradually decreases. p The rate of increase gradually decreases. If the organic light-emitting display panel is in high refresh rate mode, the charging period will be relatively short, and the charge on the storage capacitor C may not be fully charged. The characteristic formula of the driving transistor T2 is: In the formula, I ds The current flowing from the drain (d) to the source (s) of transistor T2 affects the luminous intensity of the organic light-emitting diode (OLED). V gs μ is the difference between the gate voltage g and the source voltage s of the driving transistor T2. p The velocity of charge carriers moving within the channel of driving transistor T2 is a fixed value, C. ox Let W be the capacitance per unit area of ​​the gate oxide layer of driving transistor T2, which is a fixed value; let W be the width of the channel of driving transistor T2, which is a fixed value; and let L be the length of the channel of driving transistor T2, which is a fixed value. During the charging period, the voltage of the gate g of driving transistor T2 is the voltage of the charging terminal p of storage capacitor C, and the voltage of the source s of driving transistor T2 is the voltage transmitted by data line D. This is when the charging terminal p of storage capacitor C is fully charged. , , where V th The threshold voltage for driving transistor T2, V p V is the voltage at the charging terminal p of the storage capacitor C. DATA For the voltage transmitted on data line D, during the light-emitting period, the voltage of the gate g of driving transistor T2 is the voltage of the charging terminal p of storage capacitor C, and the voltage of the source s of driving transistor T2 is the first preset voltage. The characteristic formula of driving transistor T2 becomes... In the formula, V ELVDDGiven the first preset voltage, it can be seen that as long as the voltage at the charging terminal p of the energy storage capacitor C can be charged to V during the charging period... data +V th During the luminescence period, I ds V can be achieved data With the corresponding current specifications, the luminous intensity of an organic light-emitting diode (OLED) reaches V. data The corresponding luminous brightness will not affect the display effect. If the voltage at the charging terminal p of the energy storage capacitor C is not charged to V during the charging period... data +V th This will affect the display effect; if it is not achieved, the display effect will be affected.

[0024] To address the technical problem in the prior art where insufficient charging of the energy storage capacitor affects the display effect when the display panel is in high refresh rate mode, this application provides a display panel, a driving method for the display panel, and a display device, which can solve the problem in the prior art where insufficient charging of the energy storage capacitor affects the display effect when the display panel is in high refresh rate mode.

[0025] Figure 7 A display panel provided in an embodiment of this application, such as Figure 7 As shown, the above display panel includes: Source driving circuit 2 is configured to first output the compensation voltage of sub-pixel unit 1 to the data line D corresponding to sub-pixel unit 1 during the charging period of each sub-pixel unit 1, and then output the data voltage of sub-pixel unit 1 to the data line D, so as to charge the energy storage capacitor C of sub-pixel unit 1 to the target voltage through the driving transistor T2 of sub-pixel unit 1 connected to the data line D. The compensation voltage is greater than the data voltage, and the target voltage is the sum of the data voltage and the threshold voltage of the driving transistor.

[0026] Specifically, the display panel includes: multiple sub-pixel units and multiple columns of data lines, with each column of sub-pixel units connected to a column of data lines.

[0027] Specifically, Figure 6 S1 in the figure represents the voltage change curve at the charging terminal p of the energy storage capacitor C during the charging period in the prior art. Figure 6 S2 in the figure represents the voltage change curve at the charging terminal p of the energy storage capacitor C during the charging period in this application, V p This represents the voltage at the charging terminal p of the energy storage capacitor C, such as... Figure 5 and Figure 6 As shown, during the charging process, as V... gs The absolute value of I decreases. ds The absolute value of V decreases. pAs the rise rate decreases, the source voltage of the driving transistor becomes equal to the voltage output from the data line. The higher the voltage output from the data line, the higher the source voltage of the driving transistor. gs The larger the absolute value, the more appropriate the charging time is to divide the charging period into two periods. In the first period, the data line outputs a compensation voltage. Compared to the prior art, the V value in the first period of the charging time in this application is higher. gs The absolute value of I is larger. ds The absolute value is larger, the driving transistor T2 provides charge to the storage capacitor C at a faster rate, and the voltage rise rate of the charging terminal p of the energy storage capacitor C is greater. This ensures that even when the organic light-emitting display panel is in high refresh rate mode and the charging period is relatively short, the voltage of the charging terminal p of the energy storage capacitor can be raised to the target voltage, thus guaranteeing the display effect.

[0028] In the above embodiments, the voltage at the source of the driving transistor is equal to the voltage output by the data line. The higher the voltage output by the data line, the higher the voltage at the source of the driving transistor, and the greater the absolute value of the difference between the voltage at the gate and the source of the driving transistor. Compared with the prior art, where the data line continuously outputs data voltage during the charging period, this application divides the charging period into two periods. In the first period, the data line outputs a compensation voltage, and in the second period, the data line outputs a data voltage. The compensation voltage is higher than the data voltage. Therefore, compared with the prior art, in the first period of the charging period, the absolute value of the difference between the voltage at the gate and the source of the driving transistor is greater, resulting in a larger absolute value of the current flowing from the drain of the driving transistor to the source. This leads to a faster charging speed of the energy storage capacitor and a greater voltage rise rate of the energy storage capacitor. This ensures that even when the organic light-emitting display panel is in a high refresh rate mode and the charging period is relatively short, the energy storage capacitor can still be charged to the target voltage, guaranteeing the display effect. This solves the problem in the prior art where insufficient charging of the energy storage capacitor affects the display effect when the display panel is in a high refresh rate mode.

[0029] In one alternative embodiment, such as Figure 8 and Figure 9 As shown, the display panel further includes: a timing controller 3; the source driving circuit 2 includes: a plurality of sub-driving circuits 20, each of the sub-driving circuits 20 corresponding to a column of the sub-pixel units; the sub-driving circuit 20 includes: The first driving unit 200 and the first switching unit 210 are connected, with the output terminal of the first driving unit 200 connected to the first terminal of the first switching unit 210 and the second terminal of the first switching unit 210 connected to the data line D corresponding to the sub-driving circuit 20. The second driving unit 220 and the second switching unit 230 are connected, with the output terminal of the second driving unit 220 connected to the first terminal of the second switching unit 230 and the second terminal of the second switching unit 230 connected to the data line D. The charging period includes a first charging sub-period M1 and a second charging sub-period M2, and the end time of the first charging sub-period M1 is the time before the start time of the second charging sub-period M2. The output terminal of the first driving unit 200 is used to output the compensation voltage V of the sub-pixel unit during the first charging sub-period M1 of the sub-pixel unit corresponding to the sub-driving circuit 20. c ; The output terminal of the second driving unit 220 is used to output the data voltage V of the sub-pixel unit during the second charging sub-period M2 of the sub-pixel unit. data ; The timing controller 3 is used to output an enable signal to the controlled terminal of the first switch unit 210 during the first charging sub-period M1 of the sub-pixel unit, so that the first switch unit 210 connects the output terminal of the first driving unit 200 and the data line D, and outputs a disable signal to the controlled terminal of the second switch unit 230, so that the second switch unit 230 disconnects the connection between the second driving unit 220 and the data line D. The timing controller 3 is configured to output the enable signal to the controlled terminal of the second switch unit 230 during the second charging sub-period M2 of each sub-pixel unit, so that the second switch unit 230 connects the output terminal of the second drive unit 220 and the data line D, and output the disable signal to the controlled terminal of the first switch unit 210, so that the first switch unit 210 disconnects the connection between the output terminal of the first drive unit 200 and the data line D.

[0030] Specifically, Figure 9 In the diagram, R1 represents the signal at the controlled terminal of the first switching unit 210, and R2 represents the controlled terminal of the second switching unit 230. The turn-on signal is a low-level signal, and the turn-off signal is a high-level signal. In practice, a potentiometer and an analog-to-digital converter are typically installed between the timing controller 3 and the controlled terminal of the first switching unit 210, and between the timing controller 3 and the controlled terminal of the second switching unit 230. The potentiometer is used to boost the voltage, and the analog-to-digital converter converts the digital signal into an analog signal, thereby converting the turn-on signal and the turn-off signal into analog voltages that drive the controlled terminals of the first switching unit 210 and the second switching unit 230.

[0031] Specifically, such as Figure 8As shown, both the first switching unit 210 and the second switching unit 230 are P-type thin-film transistors, designated as T8. The first terminal of the first switching unit is the source of the thin-film transistor T8, the second terminal of the first switching unit is the drain of the thin-film transistor T8, and the controlled terminal of the first switching unit is the gate of the thin-film transistor T8. The second switching unit is similar.

[0032] In this embodiment, as Figure 8 As shown, each sub-driving circuit of the source driving circuit 2 has two internal paths: a compensation path and a display path. The compensation path consists of the first driving unit 200 and the first switching unit 210, while the display path consists of the second driving unit 220 and the second switching unit 230. During the first charging sub-period, the first switching unit 210 is turned on, causing the first driving unit 200 to output a compensation voltage to the data line. During the second charging sub-period, the second switching unit 230 is turned on, causing the second driving unit 220 to output a data voltage to the data line.

[0033] In one alternative embodiment, such as Figure 8 As shown, the above-mentioned display panel further includes: a first gamma circuit and a second gamma circuit. The timing controller 3 is used to output grayscale data of the compensation voltage of the sub-pixel unit to the input terminal of the first driving unit 200 during the first charging sub-period of the sub-pixel unit, and to send a timing control signal of the display gamma voltage to the first gamma circuit, so that the first gamma circuit outputs the display gamma voltage to the reference terminal of the first driving unit 200. The display gamma voltage is the gamma voltage corresponding to the data voltage of the sub-pixel unit. Specifically, each data voltage corresponds to a gamma voltage. The method by which the timing controller 3 finds the grayscale data of the gamma voltage corresponding to each data voltage is existing technology, and therefore will not be explained further.

[0034] The timing controller 3 is used to output the data voltage to the input terminal of the second driving unit 220 and send the timing control signal of the display gamma voltage to the second gamma circuit during the second charging sub-period of the sub-pixel unit, so that the second gamma circuit outputs the display gamma voltage to the reference terminal of the second driving unit 220. The first driving unit 200 is used to convert the grayscale data of the compensation voltage into the compensation voltage based on the display gamma voltage. The second driving unit 220 is used to convert the grayscale data of the data voltage into the data voltage based on the display gamma voltage.

[0035] In this embodiment, as Figure 8As shown, the first driving unit 200 converts the grayscale data received at its input terminal into an analog voltage based on the gamma voltage received at its reference terminal. Similarly, the second driving unit 220, during the first charging sub-period, outputs grayscale data of the compensation voltage of the sub-pixel unit to its input terminal and sends a timing control signal for the display gamma voltage to the first gamma circuit 40, causing the first gamma circuit 40 to output the display gamma voltage to the reference terminal of the first driving unit 200. To display the gamma voltage, the grayscale data of the compensation voltage is converted into the compensation voltage, and the compensation voltage is output to the data line. During the second charging sub-period, the timing controller 3 outputs the grayscale data of the data voltage of the sub-pixel unit to the input terminal of the second driving unit 220, and sends the timing control signal of the display gamma voltage to the second gamma circuit 41, so that the second gamma circuit 41 outputs the display gamma voltage to the reference terminal of the second driving unit 220. Based on the display gamma voltage, the second driving unit 220 converts the grayscale data of the data voltage into the data voltage and outputs the data voltage to the data line.

[0036] In an optional embodiment, the timing controller is used to look up the duration of the first charging sub-period and the grayscale data of the compensation voltage of the sub-pixel unit from a first compensation data table during the charging period of the sub-pixel unit, based on the grayscale data of the data voltage of the sub-pixel unit. The first compensation data table contains the mapping relationship between the grayscale data of the data voltage, the duration of the first charging sub-period, and the grayscale data of the compensation voltage.

[0037] In this embodiment, after the display panel is manufactured, it is debugged to determine the length of the first charging sub-period and the grayscale data of the compensation voltage for each data voltage. This allows the charging terminal of the energy storage capacitor in the sub-pixel unit to be charged to the target voltage, and a first compensation data table is generated. During the operation of the display panel, the timing controller, based on the grayscale data of the data voltage of the sub-pixel unit, looks up the duration of the first charging sub-period and the grayscale data of the compensation voltage of the sub-pixel unit from the first compensation data table during the charging period of the sub-pixel unit.

[0038] In one alternative embodiment, such as Figure 8As shown, the above-mentioned display panel further includes: a first gamma circuit 40 and a second gamma circuit 41. The timing controller 3 is used to output grayscale data of the data voltage of the sub-pixel unit to the input terminal of the first driving unit 200 during the first charging sub-period of the sub-pixel unit, and to send the timing control signal of the compensation gamma voltage to the first gamma circuit 40, so that the first gamma circuit 40 outputs the compensation gamma voltage to the reference terminal of the first driving unit 200. The compensation gamma voltage is the gamma voltage corresponding to the compensation voltage. The timing controller 3 is used to output grayscale data of the data voltage of the sub-pixel unit to the input terminal of the second driving unit 220 during the second charging sub-period of the sub-pixel unit, and to send the timing control signal of the display gamma voltage to the second gamma circuit 41, so that the second gamma circuit 41 outputs grayscale data corresponding to the display gamma voltage to the reference terminal of the second driving unit 220. The display gamma voltage is the gamma voltage corresponding to the data voltage, and the compensation gamma voltage is greater than the display gamma voltage. The first driving unit 200 is used to convert the grayscale data of the data voltage into the compensation voltage based on the compensation gamma voltage. The second driving unit 220 is used to convert the grayscale data of the data voltage into the data voltage based on the display gamma voltage.

[0039] In this embodiment, as Figure 8 As shown, the first driving unit 200 converts the grayscale data received at its input terminal into an analog voltage based on the gamma voltage received at its reference terminal. Similarly, the second driving unit 220, during the first charging sub-period, outputs grayscale data of the sub-pixel unit's data voltage to the input terminal of the first driving unit 200 and sends the aforementioned timing control signal for the compensation gamma voltage to the first gamma circuit 40, causing the first gamma circuit 40 to output a compensation gamma voltage to the reference terminal of the first driving unit 200. The grayscale data of the compensation gamma voltage is converted into a compensation voltage, and the compensation voltage is output to the data line. During the second charging sub-period, the timing controller 3 outputs the grayscale data of the sub-pixel unit's data voltage to the input terminal of the second driving unit 220, and sends the timing control signal of the display gamma voltage to the second gamma circuit 41, so that the second gamma circuit 41 outputs the display gamma voltage to the reference terminal of the second driving unit 220. The second driving unit 220 converts the grayscale data of the data voltage into a data voltage based on the display gamma voltage, and outputs the data voltage to the data line.

[0040] In an optional embodiment, the timing controller is used to look up the duration of the first charging sub-period and the timing control signal of the compensation gamma voltage of the sub-pixel unit from a second compensation data table during the charging period of the sub-pixel unit, based on the grayscale data of the data voltage of the sub-pixel unit. The second compensation data table contains the mapping relationship between the grayscale data of the data voltage, the duration of the first charging sub-period, and the timing control signal of the compensation gamma voltage.

[0041] In this embodiment, after the display panel is manufactured, it is debugged to determine the duration of the first charging sub-period and the timing control signal of the compensation gamma voltage for each data voltage grayscale data. This allows the charging terminal of the energy storage capacitor in the sub-pixel unit to be charged to the target voltage, and a second compensation data table is generated. During the operation of the display panel, the timing controller, based on the grayscale data of the data voltage of the sub-pixel unit, looks up the duration of the first charging sub-period and the timing control signal of the compensation gamma voltage of the sub-pixel unit from the second compensation data table during the charging sub-pixel unit's charging sub-period.

[0042] In one alternative embodiment, such as Figure 8 As shown, both the first drive unit 200 and the second drive unit 220 include: The system comprises an input register module 201, a data latch module 202, a level conversion module 203, a digital-to-analog converter module 204, and an operational amplifier module 205. The input terminal of the input register module 201 of the first driving unit 200 is the input terminal of the first driving unit 200, and the input terminal of the input register module 201 of the second driving unit 220 is the input terminal of the second driving unit 220. The output terminal of the input register module 201 is connected to the input terminal of the data latch module 202, and the output terminal of the data latch module 202 is connected to the level conversion module 205. The input terminal of the level conversion module 203 is connected to the input terminal of the digital-to-analog converter module 204, the output terminal of the digital-to-analog converter module 204 is connected to the input terminal of the operational amplifier module 205, the reference terminal of the digital-to-analog converter module 204 of the first driving unit 200 is the reference terminal of the first driving unit 200, the reference terminal of the digital-to-analog converter module 204 of the second driving unit 220 is the reference terminal of the second driving unit 220, and the output terminal of the operational amplifier module 205 is connected to the corresponding data line.

[0043] Specifically, the digital-to-analog converter module 204 converts the digital signal at the input end into an analog signal based on the signal at the reference end, which is existing technology, so it will not be described in further detail.

[0044] In this embodiment, as Figure 8As shown, the timing signal TP is provided by the timing controller 3. The input register module 201 receives grayscale data from the timing controller 3. When the rising edge of the timing signal TP arrives, the input register module 201 outputs the grayscale data to the data latch module 202. The signal is boosted by the level conversion module 203, converted into an analog signal by the digital-to-analog conversion module 204, and finally increased by the operational amplifier module 205. When the falling edge of the timing signal TP arrives, the operational amplifier module 205 outputs the analog signal to the data line.

[0045] This application provides a driving method for a display panel, which can be used with any of the above-described display panels. The method includes: During the charging period of each sub-pixel unit, the driving source driving circuit first outputs the compensation voltage of the sub-pixel unit to the data line corresponding to the sub-pixel unit, and then outputs the data voltage of the sub-pixel unit to the data line. Through the driving transistor of the sub-pixel unit connected to the data line, the energy storage capacitor of the sub-pixel unit is charged to the target voltage. The compensation voltage is greater than the data voltage. The target voltage is the sum of the data voltage and the threshold voltage of the driving transistor.

[0046] In the above embodiments, the voltage at the source of the driving transistor is equal to the voltage output by the data line. The higher the voltage output by the data line, the higher the voltage at the source of the driving transistor, and the greater the absolute value of the difference between the voltage at the gate and the source of the driving transistor. Compared with the prior art, where the data line continuously outputs data voltage during the charging period, this application divides the charging period into two periods. In the first period, the data line outputs a compensation voltage, and in the second period, the data line outputs a data voltage. The compensation voltage is higher than the data voltage. Therefore, compared with the prior art, in the first period of the charging period, the absolute value of the difference between the voltage at the gate and the source of the driving transistor is greater, resulting in a larger absolute value of the current flowing from the drain of the driving transistor to the source. This leads to a faster charging speed of the energy storage capacitor and a greater voltage rise rate of the energy storage capacitor. This ensures that even when the organic light-emitting display panel is in a high refresh rate mode and the charging period is relatively short, the energy storage capacitor can still be charged to the target voltage, guaranteeing the display effect. This solves the problem in the prior art where insufficient charging of the energy storage capacitor affects the display effect when the display panel is in a high refresh rate mode.

[0047] This application also provides a display device, which includes any of the above-described display panels.

[0048] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0049] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A display panel, characterized by, The display panel includes: A source driving circuit is configured to first output a compensation voltage of the sub-pixel unit to the data line corresponding to the sub-pixel unit during the charging period of each sub-pixel unit, and then output the data voltage of the sub-pixel unit to the data line, so as to charge the energy storage capacitor of the sub-pixel unit to a target voltage through the driving transistor of the sub-pixel unit connected to the data line. The compensation voltage is greater than the data voltage, and the target voltage is the sum of the data voltage and the threshold voltage of the driving transistor.

2. The display panel of claim 1, wherein, The display panel further includes a timing controller, and the source driving circuit includes multiple sub-driving circuits, each sub-driving circuit corresponding to a column of sub-pixel units. The sub-driving circuit includes: A first driving unit and a first switching unit, wherein the output terminal of the first driving unit is connected to the first terminal of the first switching unit, and the second terminal of the first switching unit is connected to the data line corresponding to the sub-driving circuit; The second drive unit and the second switch unit are connected to the first terminal of the second switch unit and the second terminal of the second switch unit are connected to the data line. The charging period includes a first charging sub-period and a second charging sub-period, wherein the end time of the first charging sub-period is the time before the start time of the second charging sub-period. The output terminal of the first driving unit is used to output the compensation voltage of the sub-pixel unit during the first charging sub-period of the sub-pixel unit corresponding to the sub-driving circuit; The output terminal of the second driving unit is used to output the data voltage of the sub-pixel unit during the second charging sub-period of the sub-pixel unit; The timing controller is used to output an enable signal to the controlled terminal of the first switch unit during the first charging sub-period of the sub-pixel unit, so that the first switch unit connects the output terminal of the first driving unit and the data line, and outputs an disable signal to the controlled terminal of the second switch unit of the sub-driving circuit, so that the second switch unit disconnects the connection between the second driving unit and the data line. The timing controller is used to output the enable signal to the controlled terminal of the second switching unit during the second charging sub-period of the sub-pixel unit, so that the second switching unit connects the output terminal of the second driving unit and the data line, and outputs the disable signal to the controlled terminal of the switching unit, so that the first switching unit disconnects the connection between the output terminal of the first driving unit and the data line.

3. The display panel according to claim 2, characterized in that, The display panel further includes a first gamma circuit and a second gamma circuit. The timing controller is used to output grayscale data of the compensation voltage of the sub-pixel unit to the input terminal of the first driving unit during the first charging sub-period of the sub-pixel unit, and to send a timing control signal of the display gamma voltage to the first gamma circuit so that the first gamma circuit outputs the display gamma voltage to the reference terminal of the first driving unit. The display gamma voltage is the gamma voltage corresponding to the data voltage of the sub-pixel unit. The timing controller is used to output the data voltage to the input terminal of the second driving unit during the second charging sub-period of the sub-pixel unit, and to send the timing control signal of the display gamma voltage to the second gamma circuit, so that the second gamma circuit outputs the display gamma voltage to the reference terminal of the second driving unit. The first driving unit is used to convert the grayscale data of the compensation voltage into the compensation voltage based on the display gamma voltage; The second driving unit is used to convert the grayscale data of the data voltage into the data voltage based on the display gamma voltage.

4. The display panel according to claim 2, characterized in that, The display panel further includes: a first gamma circuit and a second gamma circuit. The timing controller is used to output grayscale data of the data voltage of the sub-pixel unit to the input terminal of the first driving unit during the first charging sub-period of the sub-pixel unit, and to send a timing control signal for compensating the gamma voltage to the first gamma circuit so that the reference terminal of the first driving unit of the first gamma circuit outputs the compensated gamma voltage, wherein the compensated gamma voltage is the gamma voltage corresponding to the compensation voltage. The timing controller is used to output grayscale data of the data voltage of the sub-pixel unit to the input terminal of the second driving unit during the second charging sub-period of the sub-pixel unit, and to send a timing control signal for displaying gamma voltage to the second gamma circuit, so that the reference terminal of the second driving unit of the second gamma circuit outputs display gamma voltage, wherein the display gamma voltage is the gamma voltage corresponding to the data voltage, and the compensation gamma voltage is greater than the display gamma voltage. The first driving unit is used to convert the grayscale data of the data voltage into the compensation voltage based on the compensation gamma voltage; The second driving unit is used to convert the grayscale data of the data voltage into the data voltage based on the display gamma voltage.

5. The display panel according to claim 3 or 4, characterized in that, Both the first driving unit and the second driving unit include: The system comprises an input register module, a data latch module, a level conversion module, a digital-to-analog converter module, and an operational amplifier module. The input terminal of the input register module of the first driving unit is the input terminal of the first driving unit, and the input terminal of the input register module of the second driving unit is the input terminal of the second driving unit. The output terminal of the input register module is connected to the input terminal of the data latch module, the output terminal of the data latch module is connected to the input terminal of the level conversion module, the output terminal of the level conversion module is connected to the input terminal of the digital-to-analog converter module, the output terminal of the digital-to-analog converter module is connected to the input terminal of the operational amplifier module, the reference terminal of the digital-to-analog converter module of the first driving unit is the reference terminal of the first driving unit, the reference terminal of the digital-to-analog converter module of the second driving unit is the reference terminal of the second driving unit, and the output terminal of the operational amplifier module is connected to the corresponding data line.

6. The display panel according to claim 3, characterized in that, The timing controller is used to look up the duration of the first charging sub-period and the grayscale data of the compensation voltage of the sub-pixel unit from a first compensation data table during the charging period of the sub-pixel unit, based on the grayscale data of the data voltage of the sub-pixel unit. The first compensation data table contains the mapping relationship between the grayscale data of the data voltage, the duration of the first charging sub-period, and the grayscale data of the compensation voltage.

7. The display panel according to claim 4, characterized in that, The timing controller is used to look up the duration of the first charging sub-period and the timing control signal of the compensation gamma voltage of the sub-pixel unit from a second compensation data table during the charging period of the sub-pixel unit, based on the grayscale data of the data voltage of the sub-pixel unit. The second compensation data table contains the mapping relationship between the grayscale data of the data voltage, the duration of the first charging sub-period and the timing control signal of the compensation gamma voltage.

8. The display panel according to claim 2, characterized in that, Both the first switching unit and the second switching unit are P-type thin-film transistors.

9. A driving method for a display panel, characterized in that, The method is applied to the display panel according to any one of claims 1 to 8, and the method includes: During the charging period of each sub-pixel unit, the driving source driving circuit first outputs the compensation voltage of the sub-pixel unit to the data line corresponding to the sub-pixel unit, and then outputs the data voltage of the sub-pixel unit to the data line. Through the driving transistor of the sub-pixel unit connected to the data line, the energy storage capacitor of the sub-pixel unit is charged to the target voltage. The compensation voltage is greater than the data voltage, and the target voltage is the sum of the data voltage and the threshold voltage of the driving transistor.

10. A display device, characterized in that, The display device includes: the display panel according to any one of claims 1 to 8.

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