Display device and power circuit therefor

Abstract

This disclosure relates to a display device and its power circuitry. The display device includes: a gate shift register for simultaneously driving a pixel using a discharge scan signal of a gate high voltage during a power-off sequence to discharge residual charge in the pixel; a first boost circuit for boosting an input voltage to a boost voltage during a display driving sequence; a second boost circuit for boosting the boost voltage to a gate high voltage; and a switch connected between the first and second boost circuits, wherein the switch remains on during an additional switching period of the second boost circuit, executed after the input voltage drops to an undervoltage lockout (UVLO) level, and the input voltage stored in the first boost circuit and the boost voltage stored in the second boost circuit are applied to the power input terminal of the second boost circuit.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2025-0010480, filed on January 23, 2025, which is incorporated herein by reference as fully set forth herein. Technical Field

[0003] This disclosure relates to display devices and their power circuits. Background Technology

[0004] When the display device is powered off, it releases the residual charge on the display panel, thus ensuring stable on / off characteristics in subsequent display driving and preventing image quality degradation.

[0005] A discharge scan signal with a high gate voltage should be applied to all gate lines of the display panel simultaneously to discharge the panel when power is off.

[0006] The gate high voltage of the discharge scan signal is generated by the power circuit. When power is off, the input voltage supply is cut off, and the boost voltage stored in the power circuit is rapidly discharged. As a result, the level of the gate high voltage generated by the power circuit is insufficient, leading to a deterioration in the panel discharge characteristics. Summary of the Invention

[0007] In order to overcome the above-mentioned problems in the related technologies, the present disclosure provides a display device and its power circuit that can stably regulate the gate high voltage when power is off, and thus improve the panel discharge characteristics.

[0008] To achieve these objectives and other advantages, and for the purposes of this disclosure as embodied and broadly described herein, a display device includes: a display panel including pixels; a gate shift register configured to simultaneously drive the pixels using a discharge scan signal of a gate high voltage during a power-off sequence in which the supply of an input voltage is removed, to discharge residual charge in the pixels; and a power circuit including: a first boost circuit configured to boost the input voltage to a boost voltage during a display driving sequence prior to the power-off sequence; and a second boost circuit. The circuit includes a second boost circuit configured to boost the voltage to a gate high voltage; and an ISO switch connected between the first and second boost circuits, wherein the ISO switch remains on during an additional switching period of the second boost circuit, which generates a discharge scan signal after the input voltage drops to an undervoltage lockout (UVLO) level in a power-down sequence, and the input voltage stored in the first capacitor of the first boost circuit and the boost voltage stored in the second capacitor of the second boost circuit are applied to the power input terminal of the second boost circuit.

[0009] In another aspect of this disclosure, a power circuit for a display device includes: a first boost circuit configured to boost an input voltage to a boost voltage in a display driving sequence; a second boost circuit configured to boost the boost voltage to a gate high voltage; and an ISO switch connected between the first and second boost circuits, wherein, in a power-off sequence where the input voltage supply is deactivated, during an additional switching period of the second boost circuit, performed after the input voltage drops to an undervoltage lockout (UVLO) level, to generate a gate high voltage for discharging residual charge in all pixels included in the display panel, the ISO switch remains on, and the input voltage stored in a first capacitor of the first boost circuit and the boost voltage stored in a second capacitor of the second boost circuit are applied to the power input terminal of the second boost circuit. Attached Figure Description

[0010] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0011] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure;

[0012] Figure 2 This is a diagram illustrating the connection configuration between a timing controller, a power circuit, and a scan driver according to an embodiment of this disclosure;

[0013] Figure 3 This is a diagram illustrating the panel discharge operation performed during a power-off sequence;

[0014] Figure 4 This is a diagram illustrating an example of generating a sufficient level of VGH output while maintaining a high gate voltage regulation characteristic during the VGH extra switching period of a power-down sequence;

[0015] Figure 5 This is a functional block diagram of a power circuit capable of stably adjusting the gate high voltage during power failure, according to an embodiment of the present disclosure.

[0016] Figure 6 This is a schematic equivalent circuit diagram of a power circuit capable of stably adjusting the high voltage of the gate during power failure, according to an embodiment of the present disclosure.

[0017] Figure 7 This is a diagram showing the configuration of the second boost circuit for the additional switching operation of the VGH in the power-down sequence;

[0018] Figure 8 This is a diagram illustrating an example of how the input power capacity of the second boost circuit increases during the additional VGH switching period of a power-down sequence to stabilize the gate high voltage.

[0019] Figure 9 It is a diagram showing the operating state of a power circuit during a power outage sequence;

[0020] Figure 10 This is a graph showing a comparison of the output levels of the gate high voltage with respect to the input power capacity of the second boost circuit;

[0021] Figure 11 This is a diagram illustrating an example of how the boost voltage and gate high voltage are gradually increased through the ISO switch during the power-up sequence;

[0022] Figure 12 This is a diagram illustrating an example where the switch HS in the first boost circuit is replaced with a Schottky diode; and

[0023] Figure 13 This is a diagram illustrating an example where the switch HS of the first boost circuit has been replaced with an NMOS transistor. Detailed Implementation

[0024] In the following description, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification, when adding reference numerals to elements in each drawing, it should be noted that similar reference numerals already used to represent similar elements in other drawings will be used wherever possible. In the following description, detailed descriptions of related known functions or configurations will be omitted where it is determined that they would unnecessarily obscure the essential points of the present disclosure.

[0025] Similar reference numerals denote similar elements. Additionally, for ease of description, the thickness, ratios, and dimensions of each element described herein are shown as partially enlarged or reduced. For ease of description, the scale of each element shown in the accompanying drawings of this disclosure may differ from, but is not limited to, the scales shown in the drawings.

[0026] In this disclosure, when any element (or region, layer, part, etc.) is described as "on top of another element", "connected" or "coupled" to another element, this may mean that the element can be directly connected / coupled to the other element, or that a third element can be placed therein.

[0027] The term "and / or" can include all combinations of one or more combinations that can be defined by the relevant elements.

[0028] Terms like "first" and "second" can be used to describe various elements, but the elements should not be limited by the term. The term can be used only to distinguish one element from another. For example, without departing from the spirit and scope of the inventive concept, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element. Unless otherwise stated, singular terms may include plural forms.

[0029] The terms “below,” “under,” “above,” and “over” can be used to describe the relationship between the elements shown in the accompanying drawings. These terms can be relative concepts and can be described relative to the direction shown in the drawings. For example, one or more other elements may be positioned between two elements unless “exactly” or “directly” is used. The spatially relative terms “below,” “lower,” “lower,” “above,” and “upper” can be used herein to readily describe the relationship between one device or element and other devices or elements as shown in the accompanying drawings. Thus, for example, “below” and “lower” can be the opposite of “above” and “upper” relative to a first element.

[0030] It should be understood that spatial relative terms are terms that include not only the orientations shown in the figures but also the different orientations of elements in use or operation. For example, if the device in the figures is flipped over, an element described as being "below" or "under" other elements can be placed "above" other elements. Thus, the exemplary term "lower" can include both "lower" and "upper" orientations. Similarly, the exemplary term "above" or "upper" can include both "upper" and "lower" orientations.

[0031] It should be understood that "include", "comprise", "including" or "comprising" means specifying a property, area, fixed number, step, process, element and / or component, but does not exclude other properties, areas, fixed number, steps, processes, elements and / or components.

[0032] Features of the various embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may interact with and be technically driven by each other in various ways, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be implemented independently of each other or may be implemented together in an interdependent relationship.

[0033] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0034] like Figure 1 As shown, a display device according to an embodiment of this disclosure may include a host system 110, a timing controller 120, a scan driver 130, a data driver 140, a display panel 150, and a power circuit 180. Depending on the implementation type of the display device, the timing controller 120 and the data driver 140 may be integrated into a single integrated circuit (IC).

[0035] The host system 110 can output various types of timing signals, as well as image data supplied from external sources or stored in its memory. The host system 110 can supply image data and timing signals to the timing controller 120.

[0036] The timing controller 120 can output a gate timing control signal GDC for controlling the operating timing of the scan driver 130 and a data timing control signal DDC for controlling the operating timing of the data driver 140 based on timing signals. The timing controller 120 can supply the data timing control signal DDC and image data DATA to the data driver 120. The timing controller 120 can be implemented as an IC and can be mounted on a printed circuit board (PCB), but is not limited thereto.

[0037] The scan driver 130 can output a scan signal based on the gate timing control signal GDC supplied from the timing controller 120. The scan driver 130 can supply the scan signal to the sub-pixels included in the display panel 150 through gate lines GL1 to GLm. The scan driver 130 can be implemented as an IC type, or it can be directly formed on the display panel 150 as a gate-in-panel (GIP) type, but is not limited thereto.

[0038] The data driver 140 can sample and latch image data DATA based on the data timing control signal DDC supplied from the timing controller 120, and can map the latched data to a gamma-compensated voltage to generate an analog data voltage. The data driver 140 can supply the data voltage to the sub-pixels included in the display panel 150 via data lines DL1 to DLn. The data driver 140 can be implemented as an IC type and can be mounted on the display panel 150 or a PCB, but is not limited thereto.

[0039] The power circuit 180 can generate high-level pixel power and low-level pixel power based on the externally supplied DC input voltage Vin. The power circuit 180 can also generate the gate high voltage VGH and gate low voltage VGL required to drive the scan driver 130 and the power voltage required to drive the data driver 140 based on the input voltage Vin.

[0040] The display panel 150 can be implemented as a liquid crystal display panel. The display panel 150 may include an upper substrate and a lower substrate opposite to each other, with liquid crystal cells Clc disposed therebetween. In the display panel 150, an image corresponding to image data can be displayed on a pixel array area arranged in a matrix type. The pixel array may include a thin-film transistor (TFT) array formed in the lower substrate and a color filter array formed in the upper substrate. A color filter can be formed in the TFT array on the lower substrate using a TFT-on-OT (COT) process.

[0041] In the TFT array, a TFT can be formed in each pixel region of the pixel region defined by the intersection of data lines DL1 to DLn and gate lines GL1 to GLm. The TFT can supply a data voltage transmitted via the data lines to the pixel electrode 1 of the liquid crystal cell Clc in response to a scan signal transmitted via the gate lines. Based on the TFT, the liquid crystal cell Clc of each sub-pixel SP can be driven by the voltage difference between the pixel electrode 1, which is charged using the data voltage, and the common electrode 2, to which a common voltage Vcom is applied. The common voltage Vcom can be supplied to the common electrode 2 formed in the sub-pixel SP via a common voltage supply line. A storage capacitor Cst that maintains the liquid crystal cell charging voltage during a frame cycle can be connected to the liquid crystal cell Clc. The color filter array can include a color filter and a black matrix. A polarizer can be attached to each of the upper and lower glass substrates of the display panel 150, and an alignment layer for setting a pre-tilt angle of the liquid crystal can be formed therein.

[0042] Figure 2 This is a diagram illustrating the connection configuration between a timing controller, power circuitry, and scan driver according to an embodiment of this disclosure. Figure 3 This is a diagram illustrating the panel discharge operation performed during a power-off sequence.

[0043] Reference Figure 2 and Figure 3 The scan driver 130 may include a level shifter 135 and a gate shift register 131.

[0044] The level shifter 135 can generate a gate clock GCLK based on the on-clock and off-clock included in the gate timing control signal GDC input from the timing controller 120, and the gate high voltage VGH and gate low voltage VGL input from the power circuit 180. The gate clock GCLK can have different phases and can be supplied to the gate shift register 131 through different clock lines.

[0045] The power circuit 180 can generate a gate high voltage VGH during a power-off sequence in which the supply of the input voltage Vin is released (or cut off), and can supply the gate high voltage VGH to the level shifter 135. The level shifter 135 can supply the gate all high signal, which varies between the gate low voltage VGL and the gate high voltage VGH during the power-off sequence, to the gate shift register 131.

[0046] The drive sequence of the display device can be classified as: a power-on sequence in which the supply of input voltage Vin to the power circuit 180 is turned on, a power-off sequence in which the supply of input voltage Vin to the power circuit 180 is turned off (or cut off), and a display drive sequence set between the power-on sequence and the power-off sequence.

[0047] In the display driving sequence, the gate shift register 131 can receive the gate clock GCLK from the level shifter 135 via multiple clock lines. The gate shift register 131 can receive the start signal VST from the level shifter 135 via the start line.

[0048] The gate shift register 131 may include multiple gate stages STG1 to STGm connected to each other in an associative manner, and may generate scan signals SCAN1 to SCANm based on the gate clock GCLK and the start signal VST. The output terminals of the gate stages STG1 to STGm may be connected to the gate lines GL1 to GLm of the display panel 150, and may supply phase-sequentially shifted scan signals SCAN1 to SCANm to the gate lines.

[0049] During the power-off sequence, the gate shift register 131 can generate a discharge scan signal D-SCAN of the gate high voltage VGH based on the gate full-high signal supplied from the level shifter 135, and can simultaneously supply the discharge scan signal D-SCAN to the gate lines GL1 to GLm of the display panel 150. For example, the voltage level of the discharge scan signal D-SCAN can have a voltage level amplitude that enables the TFT of the sub-pixel SP to be fully turned on.

[0050] During the power-off sequence, all TFTs of the display panel 150 can be turned on simultaneously by the discharge scan signal D-SCAN of the gate high voltage VGH, and thus the residual charge of the sub-pixel SP can be released through the data lines DL1 to DLn.

[0051] Figure 4 This is a diagram illustrating an example of generating a sufficiently high level of VGH output while maintaining the regulation characteristics of a high gate voltage during the additional switching period of the VGH in a power-down sequence.

[0052] Reference Figure 4 When the supply of input voltage Vin to the power circuit is cut off during a power-down sequence, the natural discharge of input voltage Vin can be performed in the power circuit. Even when input voltage Vin drops to the undervoltage lockout level UVLO (UVLO_F), the power circuit can generate a gate high voltage discharge scan signal D-SCAN through an additional switching operation during the VGH additional switching period.

[0053] In the display driving sequence, the power circuit can boost the input voltage Vin to obtain a boost voltage, and can further boost the boost voltage to generate a gate high voltage VGH. The input voltage Vin and the boost voltage can be stored in the capacitors of the power circuit.

[0054] When an additional switching operation for generating the gate high voltage VGH is performed during a power-down sequence, the boost voltage stored in the capacitors of the power circuit can be rapidly discharged. Based on this rapid discharge, if the VGH regulation characteristics are not maintained during the additional VGH switching period, the power circuit may output an insufficient gate high voltage VGH'. During the power-down sequence, this insufficient gate high voltage VGH' may be applied to the discharge scan signal D-SCAN, potentially causing the TFTs of the sub-pixel SP to fail to conduct, and consequently, degrading the panel's discharge characteristics.

[0055] In the following description, this disclosure allows both the input voltage Vin and the boost voltage to be applied to the power input terminal of the boost circuit performing the additional switching operation during the power-down sequence, thereby enhancing the VGH boost voltage to improve the VGH regulation characteristics during the additional VGH switching period. Therefore, this disclosure allows a sufficiently high gate high voltage VGH to be applied to the discharge scan signal D-SCAN to improve the panel's discharge characteristics during the power-down sequence.

[0056] Figure 5 This is a functional block diagram of a power circuit capable of stably adjusting the gate high voltage during power failure, according to an embodiment of the present disclosure. Figure 6 This is a schematic equivalent circuit diagram of a power circuit capable of stably adjusting the gate high voltage during power failure, according to an embodiment of the present disclosure.

[0057] Reference Figure 5 and Figure 6 The power circuit 180 may include a first boost circuit BC1, a second boost circuit BC2, and an ISO switch ISO connected between the first boost circuit BC1 and the second boost circuit BC2. The power circuit 180 may also include a boost voltage discharge switch DIS connected to the power input terminal INT of the second boost circuit BC2. The power circuit 180 may also include an overcurrent protection circuit OCP.

[0058] The first boost circuit BC1 may include a first capacitor C1, an inductor L1, a switch LS1, and a switch HS.

[0059] The first capacitor C1 can be connected between the input voltage Vin terminal and the ground voltage source GND. The inductor L1 can be connected to the input voltage Vin terminal and node N1. The first electrode (one of the source and drain) of switch LS1 can be connected to node N1, and the second electrode (the other of the source and drain) of switch LS1 can be connected to the ground voltage source GND. The first electrode of switch HS can be connected to node N1, and the second electrode of switch HS can be connected to node N2. Each of switches LS1 and HS can be implemented as a PMOS transistor.

[0060] The second boost circuit BC2 may include a second capacitor C2, an inductor L2, a switch LS2, a diode D, and a third capacitor C3.

[0061] The second capacitor C2 can be connected between the power input terminal INT of the second boost circuit BC2 and the ground voltage source GND. The inductor L2 can be connected to the power input terminal INT and node N3. The first electrode of the switch LS2 can be connected to node N3, and the second electrode of the switch LS2 can be connected to the ground voltage source GND. The anode electrode of the diode D can be connected to node N3, and the cathode electrode of the diode D can be connected to node N4. The switch LS2 can be implemented as a PMOS transistor. The third capacitor C3 can be connected between node N4 and the ground voltage source GND. Node N4, which serves as the output terminal of the second boost circuit BC2, can be connected to the gate high voltage VGH input terminal of the level shifter 135.

[0062] The first electrode of the ISO switch ISO can be connected to node N2, and the second electrode of the ISO switch ISO can be connected to the power input terminal INT of the second boost circuit BC2. The ISO switch ISO can be implemented as an NMOS transistor. The ISO switch ISO can be the switch required for the sequential control of the power voltages VCC, AVDD, and VGH needed for panel driving in the power-on sequence. In particular, the ISO switch ISO can remain on in the power-off sequence to achieve an OR-ing input of the input voltage Vin and the boost voltage AVDD, and thus enhance the input power required for the additional VGH switching operation of the second boost circuit BC2. This will be described in detail below. The first electrode of the boost voltage discharge switch DIS can be connected to the power input terminal INT of the second boost circuit BC2, and the second electrode of the boost voltage discharge switch DIS can be connected to the ground voltage source GND. When performing the additional VGH switching operation of the second boost circuit BC2, the boost voltage discharge switch DIS can be turned off, and thus slow down the discharge rate of the boost voltage AVDD in the power-off sequence. The overcurrent protection circuit OCP can be connected to the second electrode of switch LS2. The overcurrent protection circuit OCP can detect whether the current flowing in the second boost circuit BC2 is greater than the predetermined upper limit of current.

[0063] In the display driving sequence, the first boost circuit BC1 can boost the input voltage Vin of the first capacitor C1 to a boost voltage AVDD, so that the boost voltage AVDD is stored in the second capacitor C2 of the second boost circuit BC2. For example, the input voltage Vin can be 5 V, and the boost voltage AVDD can be 12 V.

[0064] For boost operation, switches LS1 and HS can be alternately turned on or off relative to each other. When switch LS1 is on, a current path is formed through the terminals of the input voltage Vin, inductor L1, and switch LS1, and current can therefore accumulate in inductor L1. At this time, switch HS can be turned off. On the other hand, when switch LS1 is off, switch HS can be on, and the current accumulated in inductor L1 can be stored in the second capacitor C2 of the second boost circuit BC2 through switches HS and ISO. This on / off operation can be repeated, and therefore, the boost voltage AVDD, which is the result of boosting the input voltage Vin, can be stored in the second capacitor C2.

[0065] In the display driving sequence, the second boost circuit BC2 can boost the boost voltage AVDD of the second capacitor C2 to the gate high voltage VGH to store the boosted voltage in the third capacitor C3. For example, the boost voltage AVDD can be 12V and the gate high voltage VGH can be 30V.

[0066] For boost operation, switch LS2 can be repeatedly turned on and off. When switch LS2 is on, a current path can be formed through the power input terminal INT, inductor L2, and switch LS2, and current can therefore accumulate in inductor L2. At this time, diode D can be turned off. On the other hand, when switch LS2 is off, diode D can be turned on, and the current accumulated in inductor L2 can be stored in the third capacitor C3 via diode D. This on / off operation can be repeated, and therefore, the gate high voltage VGH, which is the result of boosting the voltage AVDD, can be stored in the third capacitor C3.

[0067] A gate high voltage VGH can be supplied to the VGH input terminal of level shifter 135. Level shifter 135 may include a pull-up transistor PU and a pull-down transistor PD connected between its VGH input terminal and VGL input terminal. The pull-up transistor PU may be implemented as an NMOS transistor, and the pull-down transistor PD may be implemented as a PMOS transistor. The gate high voltage VGH can be supplied to gate shift register 131 through the connection node between the pull-up transistor PU and the pull-down transistor PD.

[0068] Furthermore, during the power-down sequence, the input voltage Vin supplied to the first boost circuit BC1 is cut off, and the input voltage Vin of the first capacitor C1 can discharge naturally. When the input voltage Vin decreases to the UVLO_F level through natural discharge, the boost operation of the first boost circuit BC1 is disabled, and the second boost circuit BC2 can further maintain boost operation during the VGH additional switching period (i.e., VGH additional switching operation), thereby outputting the gate high voltage VGH of the discharge scan signal.

[0069] During the additional VGH switching period of the power-off sequence, switches LS1 and HS can be turned off, and switch ISO can remain on. Therefore, one electrode of the first capacitor C1 and the second capacitor C2 (which serves as the power input terminal INT of the second boost circuit BC2) can be connected to each other via inductor L1 and the body diode of switch HS. Thus, during the additional VGH switching period, when the boost voltage AVDD of the second capacitor C2 discharges and becomes lower than the input voltage Vin, the input voltage Vin stored in the first capacitor C1 can charge the second capacitor C2. Therefore, during the additional VGH switching period, when switch ISO remains on, both the first capacitor C1 and the second capacitor C2 can be connected to the power input terminal INT of the second boost circuit BC2 to form an OR circuit, thus boosting the input voltage of the second boost circuit BC2. Here, the OR circuit is a circuit that always selects the power input with the higher voltage when two or more power inputs are present and supplies that power input to the load.

[0070] During the additional switching period of VGH in the power-off sequence, when the boost voltage discharge switch DIS is forcibly turned off, the discharge rate of the boost voltage AVDD stored in the second capacitor C2 will be relatively reduced, for example, proportionally reduced, and thus stable regulation of the gate high voltage VGH can be achieved.

[0071] Figure 7 This is a diagram showing the configuration of the second boost circuit for the additional switching operation of the VGH in the power-down sequence.

[0072] Reference Figure 7 The second boost circuit BC2 may include a driver DRV for additional switching operations of VGH, a comparator COMP, an error amplifier E-AMP, and a resistor string including R1 and R2.

[0073] The error amplifier E-AMP can amplify the voltage difference between the voltage Vx divided by the resistor series R1 and R2 and the reference voltage Vref to output the error amplification voltage.

[0074] The comparator COMP compares the sensed voltage corresponding to the current flowing in the second electrode of switch LS2 with the error amplification voltage from error amplifier E-AMP to output a square wave signal with varying duty cycle.

[0075] The driver DRV can be enabled during operation based on the VGH enable signal VGH_Enable, which is supplied further during the additional VGH switching period. The driver DRV can increase the gate high voltage VGH proportionally to the increase in the duty cycle of the square wave signal from the comparator COMP input.

[0076] Figure 8 This is a diagram illustrating an example of how the input power capacity of the second boost circuit increases to stabilize the gate high voltage during the additional VGH switching period of a power-down sequence. Figure 9 It is a diagram showing the operating state of a power circuit during a power outage sequence.

[0077] Reference Figure 8 and Figure 9 In the power-down sequence, the discharge of the input voltage Vin can begin from the moment To when the supply of the input voltage Vin is cut off. The amount of time after the input voltage Vin drops to the UVLO_F level can be the additional VGH switching period of the second boost circuit.

[0078] During the VGH additional switching period, an additional VGH switching operation can be performed, including the switch LS2 in the second boost circuit. During the VGH additional switching period, the ISO switch ISO can remain on, and the input voltage Vin stored in the first capacitor C1 of the first boost circuit and the boost voltage AVDD stored in the second capacitor C2 of the second boost circuit can be applied to the power input terminal INT of the second boost circuit, thus enabling an OR input of the boost voltage AVDD and the input voltage Vin.

[0079] In other words, during the VGH additional switching period, the boost voltage AVDD of the second capacitor C2, which decreases at the first discharge slope SL1, and the input voltage Vin of the first capacitor C1, which decreases at the second discharge slope SL2, which is less than the first discharge slope SL1, can be applied to the power input terminal INT of the second boost circuit.

[0080] During the additional switching period of VGH, the second boost circuit can boost the boost voltage AVDD, which is higher than the input voltage Vin, to the gate high voltage VGH through the additional switching operation until the crossover time CT when the first discharge slope SL1 and the second discharge slope SL2 intersect.

[0081] Furthermore, after the crossover time CT (or, after the crossover time CT), an OR voltage Vor that is higher than the boost voltage AVDD and lower than the input voltage Vin can be applied to the power input terminal INT of the second boost circuit, and this OR voltage Vor can be boosted to the gate high voltage VGH by an additional switching operation.

[0082] The voltage Vor can be the combined voltage of the boost voltage AVDD at the power input terminal INT of the second boost circuit and the input voltage Vin. During the additional switching period of VGH, in the period after the crossover time CT, the voltage Vor can decrease at a third discharge slope SL3 that is less than the first discharge slope SL1 and greater than the second discharge slope SL2, and thus can enhance the input power of the second boost circuit.

[0083] Furthermore, during the additional VGH switching period, the upper current limit of the overcurrent protection circuit OCP can be set higher in the power-down sequence than in the display drive sequence to more stably regulate the gate high voltage VGH. The overcurrent protection circuit OCP can limit the current flowing in the second boost circuit (i.e., switch LS2) to no more than a predetermined upper current limit. During the additional VGH switching period, since the input current increases as the input voltage Vin decreases, for example, to a level where the input voltage Vin is low, the shutdown function of the overcurrent protection circuit OCP for shutting down the power circuit can be pre-adjusted to be disabled. The overcurrent protection circuit OCP can only perform the operation of limiting the overcurrent to below the upper current limit, and therefore, the problem of the second boost circuit being unexpectedly shut down due to overcurrent during the additional VGH switching period can be prevented.

[0084] The upper limit of the overcurrent protection circuit OCP can be adjusted within a predetermined current range. The upper limit of the overcurrent protection circuit OCP can be set to its maximum value in the power-off sequence and can be set to a value less than the maximum value in the display drive sequence.

[0085] To ensure the stability of additional VGH switching operations, the overcurrent protection circuit OCP can be enabled only in the display drive sequence and disabled in the power-off sequence.

[0086] Figure 10 This is a graph showing a comparison of the output levels of the gate high voltage with respect to the input power capacity of the second boost circuit.

[0087] like Figure 10 As shown in Case 1, when only the boost voltage AVDD is used as the input power of the second boost circuit, the stable regulation of the gate high voltage VGH may be impossible due to the rapid discharge of the boost voltage AVDD during the additional switching period of VGH, and the level of the gate high voltage VGH output from the second boost circuit may drop below the normal level.

[0088] On the other hand, such as Figure 10As shown in Case 2, when the input power of the second boost circuit is enhanced by the OR input of the boost voltage AVDD and the input voltage Vin, the rapid discharge of the boost voltage AVDD during the additional switching period of VGH can be prevented, the stable regulation of the gate high voltage VGH can be made, and the level of the gate high voltage VGH output from the second boost circuit can be kept at a normal level.

[0089] Figure 11 This is a diagram illustrating an example of how the boost voltage and gate high voltage are gradually increased through the ISO switch during the power-up sequence.

[0090] As described above, the ISO switch ISO of the power circuit can remain on during a power-off sequence to enable the OR input of the boost voltage AVDD and the input voltage Vin.

[0091] In addition, such as Figure 11 As shown, the ISO switch ISO can remain in a slightly on state for a certain period of time during the power-on sequence, and then can change to a fully on state. Based on the gradual on-state operation of the ISO switch ISO, the boost voltage AVDD can gradually rise to the target level via the pre-charge level, and in addition, the gate high voltage VGH can gradually shift upward toward the target level.

[0092] As mentioned above, in the power-on sequence, the stepwise sequential control of the power voltages VCC, AVDD, and VGH may require the ISO switch ISO.

[0093] Figure 12 This is a diagram illustrating an example where the switch HS in the first boost circuit has been replaced with a Schottky diode. Figure 13 This is a diagram illustrating an example where the switch HS of the first boost circuit has been replaced with an NMOS transistor.

[0094] and Figure 6 In comparison, Figure 12 In the power circuit 180, the switch HS of the first boost circuit BC1 can be replaced with a Schottky diode STD. When the switch HS of the first boost circuit BC1 is replaced with a Schottky diode STD, the performance of the circuit can be improved because the Schottky diode STD, based on its superior current transfer capability compared to the body diode of the switch HS, is superior.

[0095] and Figure 6 In comparison, Figure 13 In the power circuit 180, the switch HS of the first boost circuit BC1 can be replaced with an NMOS transistor. The on / off state of switches LS1 and HS can be controlled by a single control signal, and therefore, manufacturing costs may be advantageous.

[0096] This disclosure allows for the enhancement of the input power of a second boost circuit included in the power circuit via an OR input of the input voltage and the boost voltage during a power-down sequence. Therefore, this invention can prevent rapid discharge of the input power during additional VGH switching periods and thus enables stable regulation of the gate high voltage, thereby improving panel discharge characteristics.

[0097] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0098] While this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A display device, comprising: A display panel, the display panel comprising pixels; A gate shift register is configured to simultaneously drive the pixel using a discharge scan signal of a high gate voltage during a power-off sequence in which the input voltage supply is removed, so as to discharge the residual charge of the pixel. as well as A power circuit comprising: a first boost circuit configured to boost the input voltage to a boost voltage in a display driving sequence prior to the power-off sequence; a second boost circuit configured to boost the boost voltage to the gate high voltage; and a switch connected between the first boost circuit and the second boost circuit. During the additional switching period of the second boost circuit used to generate the discharge scan signal, which is executed after the input voltage drops to the undervoltage lockout (UVLO) level in the power-down sequence, The switch remains in the ON state, and The input voltage stored in the first capacitor of the first boost circuit and the boost voltage stored in the second capacitor of the second boost circuit are applied to the power input terminal of the second boost circuit.

2. The display device according to claim 1, wherein, During the additional switching period of the second boost circuit, the boost voltage of the second capacitor, which decreases at a first discharge slope, and the input voltage of the first capacitor, which decreases at a second discharge slope less than the first discharge slope, are applied to the power input terminal of the second boost circuit.

3. The display device according to claim 2, wherein, During the additional switching period, the second boost circuit boosts the boost voltage, which is higher than the input voltage, to the gate high voltage through the additional switching operation until the crossover time when the first discharge slope and the second discharge slope intersect, and from the crossover time after the crossover time, the second boost circuit boosts the OR voltage, which is higher than the boost voltage and lower than the input voltage, to the gate high voltage through the additional switching operation.

4. The display device according to claim 3, wherein, The voltage is the combined voltage of the boost voltage at the power input terminal of the second boost circuit and the input voltage.

5. The display device according to claim 3, wherein, During the period following the crossover time of the additional switching period, the OR voltage decreases at a third discharge slope that is less than the first discharge slope and greater than the second discharge slope.

6. The display device according to claim 1 further includes a boost voltage discharge switch, the boost voltage discharge switch being connected to the power input terminal of the second boost circuit. in, During the additional switching period, the boost operation of the first boost circuit is disabled, and the boost voltage discharge switch is turned off.

7. The display device according to claim 1, further comprising an overcurrent protection circuit, the overcurrent protection circuit being configured to detect whether the current flowing in the second boost circuit exceeds a predetermined upper current limit. in, The predetermined upper limit of the overcurrent protection circuit is higher in the power-off sequence than in the display driving sequence preceding the power-off sequence.

8. The display device according to claim 7, wherein, During the power outage sequence, the shut-off function of the overcurrent protection circuit for shutting down the power circuit is disabled.

9. A power circuit for a display device, the power circuit comprising: A first boost circuit is configured to boost the input voltage to a boost voltage in a display driving sequence; A second boost circuit is configured to boost the boost voltage to a gate high voltage. as well as A switch, wherein the switch is connected between the first boost circuit and the second boost circuit, Specifically, during the additional switching period of the second boost circuit, which generates a gate high voltage for discharging residual charges in all pixels included in the display panel, after the input voltage drops to the undervoltage lockout (UVLO) level, in the power-off sequence where the input voltage supply is released, The switch remains in the ON state, and The input voltage stored in the first capacitor of the first boost circuit and the boost voltage stored in the second capacitor of the second boost circuit are applied to the power input terminal of the second boost circuit.

10. The power circuit according to claim 9, wherein, During the additional switching period of the second boost circuit, the boost voltage of the second capacitor, which decreases at a first discharge slope, and the input voltage of the first capacitor, which decreases at a second discharge slope less than the first discharge slope, are applied to the power input terminal of the second boost circuit.

11. The power circuit according to claim 10, wherein, During the additional switching period, the second boost circuit boosts the boost voltage, which is higher than the input voltage, to the gate high voltage through the additional switching operation until the crossover time when the first discharge slope and the second discharge slope intersect, and from the crossover time after the crossover time, the second boost circuit boosts the OR voltage, which is higher than the boost voltage and lower than the input voltage, to the gate high voltage through the additional switching operation.

12. The power circuit according to claim 11, wherein, The voltage is the combined voltage of the boost voltage at the power input terminal of the second boost circuit and the input voltage.

13. The power circuit according to claim 11, wherein, During the period following the crossover time of the additional switching period, the OR voltage decreases at a third discharge slope that is less than the first discharge slope and greater than the second discharge slope.

14. The power circuit according to claim 9 further includes a boost voltage discharge switch, the boost voltage discharge switch being connected to the power input terminal of the second boost circuit; in, During the additional switching period, the boost operation of the first boost circuit is disabled, and the boost voltage discharge switch is turned off.

15. The power circuit of claim 9 further includes an overcurrent protection circuit, the overcurrent protection circuit being configured to detect whether the current flowing in the second boost circuit is greater than a predetermined upper current limit. in, The predetermined upper limit of the overcurrent protection circuit is higher in the power-off sequence than in the display driving sequence preceding the power-off sequence.

16. The power circuit of claim 15, wherein, During the power outage sequence, the shut-off function of the overcurrent protection circuit for shutting down the power circuit is disabled.

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