A gate driving circuit, display panel and driving method

Abstract

This application provides a gate driving circuit, a display panel, and a driving method. The gate driving circuit includes: a driving module connected to a first control signal terminal, a first input terminal, and an output terminal, configured to control the first input terminal to provide a first driving signal to the output terminal based on a first control signal from the first control signal terminal; and a compensation module connected to a second control signal terminal, a second input terminal, a common terminal, and an output terminal, configured to control the second input terminal to provide a second driving signal to the output terminal based on a second control signal from the second control signal terminal and a pull-down common voltage from the common terminal when a transition occurs in the data line signal of the currently scanned pixel row, so that the voltage value of the first target driving signal after the superposition of the first driving signal and the second driving signal is lower than the voltage value of the second target driving signal of the pixel row where no transition occurs in the data line signal, thereby improving H-crosstalk and having no impact on image retention.

Description

Technical Field

[0001] This application relates to the field of display, and more particularly to a gate driving circuit, a display panel, and a driving method. Background Technology

[0002] Liquid crystal displays (LCDs) are prone to horizontal crosstalk (H-crosstalk) during image display, which is the appearance of stripes with abnormal or uneven brightness in the horizontal direction of the screen, thus affecting the image quality.

[0003] To mitigate or eliminate H-crosstalk, related improvement solutions focus on adjusting the brightness of positive and negative frames when Vcom fluctuates. However, while reducing H-crosstalk, these solutions often introduce new display anomalies, such as image sticking.

[0004] Therefore, it is difficult for related technologies to simultaneously suppress H-crosstalk and eliminate image retention in the same display driver solution, and there is a technical contradiction between the two that restricts each other. Summary of the Invention

[0005] This application provides a gate driving circuit, a display panel, and a driving method to solve or alleviate one or more technical problems in the prior art.

[0006] As one aspect of the embodiments of this application, this application provides a gate driving circuit, including:

[0007] The driving module is connected to the first control signal terminal, the first input terminal and the output terminal respectively, and is configured to control the first input terminal to provide a first driving signal to the output terminal based on the first control signal provided by the first control signal terminal.

[0008] The compensation module, connected to the second control signal terminal, the second input terminal, the common terminal, and the output terminal respectively, is configured to, when a transition occurs in the data line signal of the currently scanned pixel row, control the second input terminal to provide a second driving signal to the output terminal based on the second control signal provided by the second control signal terminal and the pull-down common voltage provided by the common terminal, so that the voltage value of the first target driving signal after the superposition of the first driving signal and the second driving signal is lower than the voltage value of the second target driving signal of the pixel row where the data line signal has not transitioned.

[0009] In some embodiments, the compensation module includes a first transistor, a second transistor, and a capacitor.

[0010] In some embodiments, the second control signal terminal includes a first sub-control signal terminal and a second sub-control signal terminal, the first terminal of the first transistor is connected to the output terminal, the second terminal of the first transistor is connected to the first terminal of the second transistor, and the control terminal of the first transistor is connected to the first sub-control signal terminal.

[0011] The control terminal of the second transistor is connected to the second sub-control signal terminal, and the second electrode of the second transistor is connected to the second input terminal;

[0012] The first terminal of the capacitor is connected to the control terminal of the first transistor, and the second terminal of the capacitor is connected to the common terminal.

[0013] In some embodiments, the second input terminal and the first sub-control signal terminal are respectively connected to data lines that are not connected to valid pixels in the non-display area to obtain the voltage value provided by the data lines that are not connected to valid pixels.

[0014] In some embodiments, the voltage value provided by the first input terminal is less than the voltage value provided by the second input terminal, and the voltage value provided by the first sub-control signal terminal is not lower than the turn-on voltage of the first transistor.

[0015] In some embodiments, the voltage provided by the first input terminal is 34V, the voltage provided by the second input terminal is 40V, and the voltage provided by the first sub-control signal terminal is 15V.

[0016] In some embodiments, the driving module includes a third transistor, the first terminal of which is connected to the output terminal, the second terminal of which is connected to the first input terminal, and the control terminal of which is connected to the first control signal terminal.

[0017] In some embodiments, the first control signal terminal and the second sub-control signal terminal are the same control signal terminal.

[0018] As one aspect of this application, this application provides a display panel including the gate driving circuit described in any of the above embodiments.

[0019] As another aspect of the embodiments of this application, the embodiments of this application provide a driving method applied to the gate driving circuit described in any of the above embodiments, the method comprising: including:

[0020] A first control signal is provided to the first control signal terminal in the gate drive circuit, so that the drive module controls the first input terminal to provide a first drive signal to the output terminal based on the first control signal;

[0021] A second control signal is provided to the second control signal terminal in the gate driving circuit so that when the data line signal of the currently scanned pixel row changes, the compensation module controls the second input terminal to provide a second driving signal to the output terminal based on the second control signal and the pull-down common voltage provided by the common terminal, so that the voltage value of the first target driving signal after the first driving signal and the second driving signal are superimposed is lower than the voltage value of the second target driving signal of the pixel row where the data line signal has not changed.

[0022] The gate driving circuit provided in this application embodiment includes: a driving module, which is connected to a first control signal terminal, a first input terminal, and an output terminal respectively, and is configured to control the first input terminal to provide a first driving signal to the output terminal based on a first control signal provided by the first control signal terminal; and a compensation module, which is connected to a second control signal terminal, a second input terminal, a common terminal, and the output terminal respectively, and is configured to control the second input terminal to provide a second driving signal to the output terminal based on a second control signal provided by the second control signal terminal and a pull-down common voltage provided by the common terminal when a transition occurs in the data line signal of the currently scanned pixel row, so that the voltage value of the first target driving signal after the superposition of the first driving signal and the second driving signal is lower than the voltage value of the second target driving signal of the pixel row where the data line signal has not transitioned. In other words, when a transition occurs in the data line signal of the currently scanned pixel row, the compensation module can feed back the pull-down common voltage provided by the common terminal to the output terminal. This results in the output driving signal voltage being lower than the driving signal voltage of the pixel row where the data line signal has not transitioned, thereby reducing the charging rate of that pixel row and further reducing its brightness to mitigate the H-crosstalk phenomenon. Furthermore, compared to related technical solutions that adjust the brightness of positive and negative frames to reduce or eliminate the H-crosstalk phenomenon when the common voltage Vcom fluctuates, the embodiments of this application have no effect on image retention.

[0023] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of this application will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0024] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0025] Figure 1This diagram illustrates a faulty H-crosstalk.

[0026] Figure 2 The diagram shows the corresponding timing of the positive frame data line, the negative frame data line, and Vcom.

[0027] Figure 3 A schematic diagram of a gate drive circuit structure according to an embodiment of this application is shown.

[0028] Figure 4 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application.

[0029] Figure 5 This is a schematic diagram of another gate driving circuit provided in an embodiment of this application.

[0030] Figure 6 This is a schematic diagram of another gate driving circuit provided in an embodiment of this application.

[0031] Figure 7 This is a schematic diagram of another gate drive circuit provided in an embodiment of this application.

[0032] Figure 8 This is a timing diagram of a gate drive circuit provided in an embodiment of this application.

[0033] Figure 9 This is a flowchart of a driving method according to an embodiment of this application. Detailed Implementation

[0034] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0035] H-Crosstalk is a horizontal display anomaly caused by signal interference between adjacent data lines in display panels (such as Liquid Crystal Display (LCD), Organic Light-Emitting Diode (OLED), Micro Light-Emitting Diode (Micro-LED), and Electronic Ink Display / Electronic Pulse Display (EPD)). Since data lines are typically routed and drive pixel columns vertically, this crosstalk primarily affects horizontally adjacent pixels, manifesting as horizontal brightness or color deviations. Typical problems with H-Crosstalk can be summarized as follows: Firstly, it manifests as horizontal blurring or edge ghosting. In high-contrast images (such as vertical black and white stripes), the brightness of one column of pixels "overflows" to adjacent columns, resulting in blurred edges or duplicated images. On the other hand, it manifests as color shift, where crosstalk occurs between red, green, and blue (RGB) subpixels, causing color halos at edges, such as white edges appearing reddish or bluish. Furthermore, it results in decreased image sharpness, especially in scenes displaying text or fine lines, where edges are not sharp enough, affecting detail resolution. Finally, it manifests as a mura-like uneven display phenomenon, where localized areas exhibit hazy, striped, or other mura-like defects in brightness or color.

[0036] Figure 1 A schematic diagram of an existing H-crosstalk defect is shown. Taking an existing column / Z flip drive product as an example, data lines A1 and A2 correspond to the positive frame data line and the negative frame data line, respectively. When the data line signal switches from the voltage corresponding to grayscale L127 to the voltage corresponding to grayscale L255, the corresponding timing of the common voltage Vcom provided by data lines A1, A2, and the common terminal is as follows: Figure 2As shown. Due to the coupling capacitance between the data line and the common electrode, the transition of the data line signal will pull the potential of Vcom. Specifically, the transition of the positive frame data line pulls Vcom upward, and the transition of the negative frame data line pulls Vcom downward. Given that the nominal voltage of the common electrode is approximately 7V and it is in a passive high-resistance state, the combined effect of the positive and negative frames in existing column flip products results in an overall downward pull on Vcom. When Vcom is pulled down, since the brightness of the liquid crystal pixel is determined by the differential voltage (differential voltage = data voltage - Vcom), the decrease in Vcom voltage will lead to an increase in the differential voltage. This causes the brightness of the currently scanned pixel row to be higher than that of the rows above and below when charging, resulting in the H-crosstalk phenomenon. Existing improvement solutions usually adopt methods such as adjusting the display data code value (Code adjustment), adjusting the common electrode voltage (Vcom adjustment), or compensating by detecting the voltage of the corresponding binding point on the screen, in order to adjust the brightness of the positive and negative frames when Vcom fluctuates (Ripple), thereby reducing or eliminating H-crosstalk. However, this solution causes Vcom to deviate from its optimal setting, disrupting the symmetry between positive and negative frames and exacerbating the accumulation of direct current bias (DC), which in turn leads to more severe image retention. Therefore, in existing technologies, there is a technical contradiction between H-crosstalk and image retention suppression, which cannot be simultaneously addressed.

[0037] In view of this, embodiments of this application propose a gate driving circuit for sequentially outputting row scan driving signals and applying these driving signals to the gate terminals of switching transistors on each row of pixels in the display panel via gate lines to control the switching transistors to turn on or off. When the driving signal turns on the switching transistors, the grayscale voltage on the data line is transmitted to the pixel electrode through the switching transistors. When the driving signal is withdrawn, the switching transistors turn off, and the pixel electrode maintains the grayscale voltage until the next scan cycle, thereby realizing row-by-row writing and maintaining pixel display data.

[0038] The gate driving circuit in this application embodiment can adopt an array-type integrated driving structure (Gate Driver On Array, GOA), that is, the driving circuit unit is directly integrated on the array substrate of the display panel, thereby eliminating the need for a separate external gate driving IC, reducing design costs and shrinking the bezel width of the display module. Figure 3 As shown, the cascaded gate drive circuit consists of multiple gate arrays (GOAs). Figure 3This example uses three GOAs, but in practical applications, any number of GOAs can be set according to the number of rows and size of the display panel. Each GOA is integrated in a different area of ​​the display panel array substrate and is responsible for outputting row scan drive signals to its corresponding pixel row. In the cascaded structure, after completing the scan of its assigned pixel row, the upstream GOA transmits the start signal, clock signal, and level signal to the downstream GOA, enabling the downstream GOA to continue outputting scan signals for subsequent pixel rows. Through the sequential relay work of multiple GOAs, the entire display panel can be driven by full-row sequential scanning. In this embodiment, a compensation module is added to the GOA to improve the H-crosstalk phenomenon.

[0039] Figure 4 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application.

[0040] like Figure 4 As shown, it includes: a driving module 410, which is connected to a first control signal terminal Ctl1, a first input terminal IN1, and an output terminal Gout, and is configured to control the first input terminal IN1 to provide a first driving signal to the output terminal Gout based on a first control signal provided by the first control signal terminal Ctl1; and a compensation module 420, which is connected to a second control signal terminal Ctl2, a second input terminal IN2, a common terminal COM, and an output terminal Gout, and is configured to control the second input terminal IN2 to provide a second driving signal to the output terminal Gout based on a second control signal provided by the second control signal terminal Ctl2 and a pull-down common voltage Vcom provided by the common terminal COM when a transition occurs in the data line signal of the currently scanned pixel row, so that the voltage value of the first target driving signal after the superposition of the first driving signal and the second driving signal is lower than the voltage value of the second target driving signal of the pixel row where the data line signal has not transitioned.

[0041] Optionally, in this embodiment, the first input terminal IN1 and the second input terminal IN2 can receive active voltage inputs. For example, the first input terminal IN1 can receive existing active input signals within the GOA, such as clock pulse voltage (CLK), which can synchronize the row scan timing of the gate drive circuit and the data loading timing of the data drive circuit. The second input terminal IN2 can receive voltages provided by data lines not connected to valid pixels in the non-display area to provide a constant voltage value, thereby achieving stable driving and performance optimization of specific circuits without affecting the display of valid pixels.

[0042] It is understood that, in this embodiment of the application, when a transition occurs in the data line signal of the currently scanned pixel row, the active voltage divider circuit composed of the driving module 410 and the compensation module 420 can control the voltage value of the output terminal Gout to tilt towards a lower voltage, so as to suppress the crosstalk effect caused by the data line signal transition. When no transition occurs in the data line signal of the currently scanned pixel row, the active voltage divider circuit composed of the driving module 410 and the compensation module 420 controls the voltage value of the output terminal Gout to recover to a higher voltage, so that the gate drive signal returns to the normal working level, ensuring stable circuit operation.

[0043] Figure 4 When a transition occurs in the data line signal of the currently scanned pixel row, the compensation module 420 can feed back the pull-down common voltage Vcom provided by the common terminal COM to the output terminal Gout. This results in the voltage value of the drive signal ultimately output by Gout being lower than the voltage value of the drive signal for pixel rows where the data line signal has not transitioned. This reduces the charging rate of that pixel row and further reduces its brightness, thus mitigating the H-crosstalk phenomenon. Furthermore, compared to related technical solutions that adjust the brightness of positive and negative frames when Vcom fluctuates to reduce or eliminate the H-crosstalk phenomenon, this embodiment has no effect on image retention.

[0044] It should be noted that the transistors used in the embodiments of this application can all be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their sources and drains are interchangeable. In the embodiments of this invention, the source (source electrode) is referred to as the first electrode, and the drain (drain electrode) is referred to as the second electrode; alternatively, the drain can be referred to as the first electrode, and the source as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is designated as the gate (also called the gate electrode or control terminal), the signal input terminal as the source, and the signal output terminal as the drain.

[0045] Figure 5 This is a schematic diagram of another gate driving circuit provided in an embodiment of this application.

[0046] like Figure 5 As shown, the second control signal terminal Ctl2 connected to the compensation module 420 includes a first sub-control signal terminal Ctl2_1 and a second sub-control signal terminal Ctl2_2. Optionally, the first sub-control signal terminal Ctl2_1 can provide a constant voltage signal as a stable reference potential, enabling the compensation module 320 to accurately reflect fluctuations in Vcom. The second sub-control signal terminal Ctl2_2 can provide a pulse-type control signal, synchronously following the GOA line scan timing.

[0047] In this embodiment, the compensation module 420 is connected to the first sub-control signal terminal Ctl2_1, the second sub-control signal terminal Ctl2_2, the second input terminal IN2, the common terminal COM, and the output terminal Gout, respectively. It is configured to control the second input terminal IN2 to provide a second driving signal to the output terminal Gout when a transition occurs in the data line signal of the currently scanned pixel row. This is based on the first sub-control signal provided by the first sub-control signal terminal Ctl2_1, the second sub-control signal provided by the second sub-control signal terminal Ctl2_2, and the pull-down common voltage Vcom provided by the common terminal COM. This ensures that the voltage value of the first target driving signal, which is the sum of the first driving signal and the second driving signal, is lower than the voltage value of the second target driving signal for pixel rows where no transition occurs in the data line signal, thereby improving the H-crosstalk phenomenon.

[0048] It is understood that the specific circuit structure of the compensation module 420 is not limited in the embodiments of this application. Any component or combination of components that can control the second input terminal IN2 to provide a second driving signal to the output terminal Gout based on the second control signal provided by the second control signal terminal Ctl2 and the pull-down common voltage Vcom provided by the common terminal COM when the data line signal of the currently scanned pixel row changes, so that the voltage value of the first target driving signal after the superposition of the first driving signal and the second driving signal is lower than the voltage value of the second target driving signal of the pixel row where the data line signal has not changed, are all within the protection scope of the embodiments of this application.

[0049] Figure 6 This is a schematic diagram of another gate driving circuit provided in an embodiment of this application.

[0050] like Figure 6 As shown, the compensation module 420 includes a first transistor T1, a second transistor T2, and a capacitor C. The driving module 410 includes a third transistor T3.

[0051] Optionally, the first terminal of the first transistor T1 is connected to the output terminal Gout, the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2, and the control terminal of the first transistor T1 is connected to the first sub-control signal terminal Ctl2_1; the control terminal of the second transistor T2 is connected to the second sub-control signal terminal Ctl2_2, and the second terminal of the second transistor T2 is connected to the second input terminal IN2; the first terminal of capacitor C is connected to the control terminal of the first transistor T1, and the second terminal of capacitor C is connected to the common terminal COM. The first terminal of the third transistor T3 is connected to the output terminal Gout, the second terminal of the third transistor T3 is connected to the first input terminal IN1, and the control terminal of the third transistor T3 is connected to the first control signal terminal Ctl1. In this example, the first control signal terminal Ctl1 and the second sub-control signal terminal Ctl2_2 are the same control signal terminal, which ensures that the turn-on and turn-off timings of the second transistor T2 and the third transistor T3 are completely synchronized, and simplifies the circuit wiring.

[0052] Additionally, in this example, the voltage provided by the first input terminal IN1 is typically lower than the voltage provided by the second input terminal IN2. The voltage provided by the first sub-control signal terminal Ctl2_1 is not lower than the turn-on voltage of the first transistor T1. For example, the voltage provided by the first input terminal IN1 is 34V, the voltage provided by the second input terminal IN2 is 40V, and the voltage provided by the first sub-control signal terminal Ctl2_1 is 15V.

[0053] When a jump occurs in the data line signal of the currently scanned pixel row, the first control signal terminal Ctl1 and the second sub-control signal terminal Ctl2_2 provide a high-level voltage. The second transistor T2 and the third transistor T3 turn on, and Vcom is pulled and fluctuates. The Vcom voltage value drops. Utilizing the coupling characteristic that the voltage across capacitor C cannot change abruptly, the control terminal voltage of the first transistor T1 is pulled down, becoming lower than the turn-on voltage of the first transistor T1. The equivalent resistance of the first transistor T1 increases. In the voltage divider circuit composed of the first transistor T1, the second transistor T2, and the third transistor T3, the voltage value at the output terminal Gout decreases, the charging rate of the currently scanned pixel row decreases, and the brightness decreases.

[0054] When scanning and charging other rows of pixels, the common voltage Vcom remains stable and without fluctuation. The potential of the output terminal Gout does not decrease due to changes in Vcom, thereby keeping the pixel brightness stable and reducing the brightness difference between the boundary row and other rows, thus improving the effect of horizontal crosstalk (H-crosstalk).

[0055] Optionally, in this embodiment, when the output terminal Gout is in the off state, the first control signal output by the first control signal terminal Ctl1 is at a low level to turn off the second transistor T2. Even if the first transistor T1 is turned on, the output terminal Gout will still be pulled down to the gate low level voltage VGL to ensure that the voltage of the pixel capacitor remains unaffected.

[0056] In addition, such as Figure 6 The driving circuit shown in this application, compared with simple capacitive coupling, utilizes the unidirectional conduction characteristic of transistors to achieve unidirectional potential pull of the common voltage Vcom on Gout, while Gout does not pull Vcom in the reverse direction, effectively avoiding the problem of introducing additional noise to Vcom and having no significant impact on the afterimage phenomenon.

[0057] Optionally, in this embodiment, the second input terminal IN2 and the first sub-control signal terminal Ctl2_1 are respectively connected to the data lines of non-display areas that are not connected to valid pixels, so as to obtain the voltage value provided by the data lines of non-display areas that are not connected to valid pixels. That is, by reusing the existing wiring resources of the display panel to continuously obtain a stable preset voltage, the existing formed circuit of the driving circuit is fully utilized to provide the required working signal, reducing the circuit space occupied and reducing the number of components and wiring complexity.

[0058] The following example illustrates the embodiments of this application, using the following scenario: the first input terminal IN1 provides a high-potential CLK signal (34V), the first control signal terminal Ctl1 provides an in-plane driving signal PU, the second input terminal IN2 provides non-display data (Dummary data) V1 (V1=40V), the first sub-control signal terminal Ctl2_1 provides non-display data (Dummary data) V2 (V2=15V), the second sub-control signal terminal Ctl2_2 is PU, and the common terminal provides a common voltage Vcom. The driving relationship of the pixels, including the fourth transistor T4, is also used as an example.

[0059] This example adds a compensation module to the original drive circuit to achieve the following: Figure 7 The in-plane driving circuit shown is illustrated. The capacitor C consists of a metal layer at a common terminal and a gate metal layer of the first transistor T1, separated by an insulating dielectric layer to form a planar capacitor structure. The gate of the first transistor T1 is connected to V2, its source is connected to the drain of T2, and its drain is connected to Gout. The gate of T2 is connected to PU, its source to V1, and its drain to the source of T1. The gate of the third transistor T3 within the existing GOA unit is connected to PU, its source to CLK, and its drain to Gout.

[0060] V1 has a constant voltage of 40V, and V2 has a constant voltage of 15V. When charging reaches the data line voltage transition, the PU point is at a high potential, T3 and T2 are turned on, Vcom is pulled up, creating a ripple effect, and the Vcom voltage drops. Due to the presence of capacitor C, the gate voltage V2 of T1 is pulled low, the equivalent resistance of T1 increases, and in the voltage divider circuit composed of T1, T2, and T3, the Gout point voltage decreases, resulting in a decrease in the charging rate of that line and a decrease in brightness. In this example, the timing diagram of the above driving circuit is as follows: Figure 8 As shown. When Vcom is pulled down, V2 is pulled low, V1 remains unchanged, and under the drive of the high potential of PU, Gout decreases (specifically as shown). Figure 8 (As indicated by the arrow).

[0061] This application also provides a display panel, which may include the driving circuit of any embodiment of this application.

[0062] Optionally, the aforementioned display panel can be applied to, but is not limited to, the following electronic products or components: mobile phones (smartphones, foldable phones, etc.), tablet computers, televisions (LCD TVs, OLED TVs, etc.), monitors (desktop monitors, industrial monitoring screens, etc.), laptops, digital photo frames, navigators, in-vehicle displays, smart home control screens, wearable devices (smartwatches, Virtual Reality / Augmented Reality (AR) glasses, etc.), and any other electronic products or components with display functions. Through the driving circuit scheme of this application embodiment, the above devices can reduce interline brightness differences, improve horizontal crosstalk, and reduce image retention when displaying high-speed moving images, complex color-level images, or long-term static images, thereby improving image clarity and consistency.

[0063] Figure 9 This is a schematic diagram of a driving method according to an embodiment of this application.

[0064] like Figure 9 As shown, this application provides a driving method applied to the gate driving circuit provided in any embodiment of this application. The method includes:

[0065] S902 provides a first control signal to the first control signal terminal in the gate drive circuit, so that the drive module controls the first input terminal to provide a first drive signal to the output terminal based on the first control signal;

[0066] S904, a second control signal is provided to the second control signal terminal in the gate drive circuit so that when the data line signal of the currently scanned pixel row changes, the compensation module controls the second input terminal to provide a second drive signal to the output terminal based on the second control signal and the pull-down common voltage provided by the common terminal, so that the voltage value of the first target drive signal after the superposition of the first drive signal and the second drive signal is lower than the voltage value of the second target drive signal of the pixel row where the data line signal has not changed.

[0067] Through steps S902-S904, a first control signal is provided to the first control signal terminal in the gate driving circuit, so that the driving module controls the first input terminal to provide a first driving signal to the output terminal based on the first control signal. A second control signal is provided to the second control signal terminal in the gate driving circuit, so that when the data line signal of the currently scanned pixel row changes, the compensation module controls the second input terminal to provide a second driving signal to the output terminal based on the second control signal and the pull-down common voltage provided by the common terminal, so that the voltage value of the first target driving signal after the superposition of the first driving signal and the second driving signal is lower than the voltage value of the second target driving signal of the pixel row where the data line signal has not changed. That is, when the data line signal of the currently scanned pixel row changes, the compensation module can feed back the pull-down common voltage provided by the common terminal to the output terminal, so that the voltage value of the driving signal finally output by the output terminal is lower than the voltage value of the driving signal of the pixel row where the data line signal has not changed, thereby reducing the charging rate of the pixel row and further reducing the brightness of the pixel row to improve the H-crosstalk phenomenon. In addition, compared with related technical solutions that adjust the brightness of positive and negative frames to reduce or eliminate H-crosstalk phenomenon when Vcom fluctuates, the embodiments of this application have no effect on image retention.

[0068] In this embodiment, the second control signal terminal connected to the compensation module includes a first sub-control signal terminal and a second sub-control signal terminal. Optionally, the first sub-control signal terminal can provide a constant voltage signal as a stable reference potential, enabling the compensation module to accurately reflect fluctuations in Vcom. The second sub-control signal terminal can provide a pulse-type control signal, synchronously following the GOA row scan timing. The above method further includes: providing a first sub-control signal to the first sub-control signal terminal in the gate drive circuit and providing a second sub-control signal to the second sub-control signal terminal, so that when the data line signal of the currently scanned pixel row experiences a jump, the compensation module controls the second input terminal to provide a second driving signal to the output terminal based on the first sub-control signal provided by the first sub-control signal terminal, the second sub-control signal provided by the second sub-control signal terminal, and the pull-down common voltage provided by the common terminal, so that the voltage value of the first target driving signal after the superposition of the first driving signal and the second driving signal is lower than the voltage value of the second target driving signal of the pixel row where the data line signal has not experienced a jump, thereby improving the H-crosstalk phenomenon.

[0069] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0070] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0071] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0072] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0073] It should be noted that although the steps of the method in this application are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps. The above drawings are merely illustrative of the processes included in the method according to exemplary embodiments of this application and are not intended to be limiting. It is readily understood that the processes shown in the above drawings do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be performed synchronously or asynchronously in multiple modules, for example.

[0074] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0075] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A gate driving circuit, characterized in that, include: The driving module is connected to the first control signal terminal, the first input terminal and the output terminal respectively, and is configured to control the first input terminal to provide a first driving signal to the output terminal based on the first control signal provided by the first control signal terminal. The compensation module, connected to the second control signal terminal, the second input terminal, the common terminal, and the output terminal respectively, is configured to, when a transition occurs in the data line signal of the currently scanned pixel row, control the second input terminal to provide a second driving signal to the output terminal based on the second control signal provided by the second control signal terminal and the pull-down common voltage provided by the common terminal, so that the voltage value of the first target driving signal after the superposition of the first driving signal and the second driving signal is lower than the voltage value of the second target driving signal of the pixel row where the data line signal has not transitioned.

2. The gate driving circuit according to claim 1, characterized in that, The compensation module includes a first transistor, a second transistor, and a capacitor.

3. The gate driving circuit according to claim 2, characterized in that, The second control signal terminal includes a first sub-control signal terminal and a second sub-control signal terminal. The first terminal of the first transistor is connected to the output terminal, the second terminal of the first transistor is connected to the first terminal of the second transistor, and the control terminal of the first transistor is connected to the first sub-control signal terminal. The control terminal of the second transistor is connected to the second sub-control signal terminal, and the second electrode of the second transistor is connected to the second input terminal; The first terminal of the capacitor is connected to the control terminal of the first transistor, and the second terminal of the capacitor is connected to the common terminal.

4. The gate driving circuit according to claim 3, characterized in that, The second input terminal and the first sub-control signal terminal are respectively connected to the data lines of non-display areas that are not connected to valid pixels, so as to obtain the voltage value provided by the data lines of non-display areas that are not connected to valid pixels.

5. The gate driving circuit according to claim 4, characterized in that, The voltage value provided by the first input terminal is less than the voltage value provided by the second input terminal, and the voltage value provided by the first sub-control signal terminal is not lower than the turn-on voltage of the first transistor.

6. The gate driving circuit according to claim 5, characterized in that, The voltage provided by the first input terminal is 34V, the voltage provided by the second input terminal is 40V, and the voltage provided by the first sub-control signal terminal is 15V.

7. The gate driving circuit according to claim 1, characterized in that, The driving module includes a third transistor, the first terminal of which is connected to the output terminal, the second terminal of which is connected to the first input terminal, and the control terminal of which is connected to the first control signal terminal.

8. The gate driving circuit according to any one of claims 1 to 7, characterized in that, The first control signal terminal and the second sub-control signal terminal are the same control signal terminal.

9. A display panel, characterized in that, Includes the driving circuit as described in any one of claims 1 to 8.

10. A driving method, characterized in that, The method, applied to the gate drive circuit according to any one of claims 1 to 8, comprises: A first control signal is provided to the first control signal terminal in the gate drive circuit, so that the drive module controls the first input terminal to provide a first drive signal to the output terminal based on the first control signal; A second control signal is provided to the second control signal terminal in the gate driving circuit so that when the data line signal of the currently scanned pixel row changes, the compensation module controls the second input terminal to provide a second driving signal to the output terminal based on the second control signal and the pull-down common voltage provided by the common terminal, so that the voltage value of the first target driving signal after the first driving signal and the second driving signal are superimposed is lower than the voltage value of the second target driving signal of the pixel row where the data line signal has not changed.

Images