A gate driving circuit and a display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel. The gate driving circuit comprises N cascaded gate driving units, the nth gate driving unit comprising: a pull-up module configured to charge a driving control node of a current stage; an output module configured to output a stage transmission signal of the current stage and a gate driving signal of the current stage; a control module configured to generate a voltage at a bleeding control node of the current stage under the action of a voltage of a driving control node of the current stage, the stage transmission signal of the current stage and a voltage of a driving control node of the (n+q)th stage; wherein q represents the number of clock signal lines; and a bleeding module configured to pull down the driving control node of the current stage, a stage transmission output end of the current stage or / and a driving output end of the current stage to a low potential under the action of a voltage of the bleeding control node of the current stage. The screen flicker phenomenon after multiple stage transmissions in the gate driving circuit is improved.

Description

Technical Field

[0001] This application belongs to the field of display driving technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] In liquid crystal display technology, multiple cascaded array substrate row driver (GOA) cells are driven using a line-by-line scanning method. The clock signal of the GOA cell is propagated at regular intervals, and within one frame, a single clock signal generates multiple waveforms. When the clock signal returns, a high-level signal is generated due to parasitic capacitance between the clock signal receiver and the pull-up control node (commonly known as the Q point). This causes a brief output of the gate drive signal and the propagation signal. As the propagation accumulates to a certain extent, the potential of the gate drive signal increases to the level driving the pixel, resulting in screen flicker.

[0003] Therefore, how to improve the screen flicker phenomenon after multiple stages in the gate drive circuit is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel, which solves the screen flicker problem caused by multiple stages of transmission in the gate driving circuit.

[0005] In a first aspect, this application provides a gate driving circuit comprising N cascaded gate driving units. The nth-stage gate driving unit includes: a pull-up module connected to the current stage's drive control node, configured to charge the current stage's drive control node in response to the output signal of the nth-stage gate driving unit; an output module connected to the current stage's drive control node and the current stage's clock signal line, configured to output the current stage's stage transmission signal and the current stage's gate driving signal under the influence of the voltage on the current stage's drive control node and the current stage's clock signal; and a control module connected to the stage transmission output terminal or drive output terminal of the output module, and also connected to the current stage's drive control node, the (n+q)th stage's drive control node, and the current stage's discharge control node, configured to... The following describes a process: under the influence of the voltage of the current stage's drive control node, the stage transmission signal of the current stage, and the voltage of the (n+q)th stage's drive control node, or under the influence of the voltage of the current stage's drive control node, the gate drive signal of the current stage, and the voltage of the (n+q)th stage's drive control node, a voltage is generated on the discharge control node of the current stage; where q represents the number of clock signal lines; the discharge module, connected to the discharge control node of the current stage, and also connected to the drive control node of the current stage, the stage transmission output terminal of the output module, and / or the drive output terminal of the output module, is configured to: under the influence of the voltage of the discharge control node of the current stage, pull down the drive control node of the current stage, the stage transmission output terminal of the current stage, and / or the drive output terminal of the current stage to a low potential.

[0006] Optionally, the control module includes: a first control submodule, connected to the current stage's drive control node and the current stage's precharge control node, and also connected to the stage transmission output terminal or drive output terminal of the output module, configured to generate a voltage at the current stage's precharge control node under the action of the voltage of the current stage's drive control node and the stage transmission signal of the current stage, or under the action of the voltage of the current stage's drive control node and the gate drive signal of the current stage; and a second control submodule, connected to the current stage's precharge control node, the (n+q)th stage's drive control node, and the current stage's discharge control node, configured to generate a voltage at the current stage's discharge control node under the action of the voltage of the current stage's precharge control node and the voltage of the (n+q)th stage's drive control node.

[0007] Optionally, the first control submodule includes: a first transistor and a first capacitor; the control terminal of the first transistor is connected to the stage transmission output terminal or drive output terminal of the output module, the first terminal of the first transistor is connected to the drive control node of the current stage, the second terminal of the first transistor is connected to the first terminal of the first capacitor, and the first terminal of the first capacitor is connected to the precharge control node of the current stage.

[0008] Optionally, the second control submodule includes: a second transistor; the control terminal of the second transistor is connected to the drive control node of the (n+q)th stage, the first terminal of the second transistor is connected to the precharge control node of the current stage, and the second terminal of the second transistor is connected to the discharge control node of the current stage.

[0009] Optionally, the discharge module includes: a third transistor; the control terminal of the third transistor is connected to the discharge control node of the current stage, the first terminal of the third transistor is connected to the drive control node of the current stage, the stage transmission output terminal of the output module, and / or the drive output terminal of the output module, and the second terminal of the third transistor is connected to a low-level terminal.

[0010] Optionally, the nth gate drive unit further includes a reset module, which is connected to the reset control terminal and the discharge control node of the current stage, and is configured to reset the discharge control node of the current stage under the action of the reset control signal during the vertical blanking period.

[0011] Optionally, the reset module includes: a fourth transistor; the control terminal of the fourth transistor is connected to the reset control terminal, the first terminal of the fourth transistor is connected to the discharge control node of the current stage, and the second terminal of the fourth transistor is connected to a low-level terminal.

[0012] Optionally, the output module includes: a fifth transistor, a sixth transistor, and a second capacitor; the control terminal of the fifth transistor, the control terminal of the sixth transistor, and the first terminal of the second capacitor are connected to the drive control node of the current stage; the first terminal of the fifth transistor is connected to the clock signal line of the current stage; and the second terminal of the fifth transistor serves as the stage's output terminal; the second terminal of the sixth transistor is connected to the second terminal of the second capacitor and serves as the drive output terminal.

[0013] Optionally, the pull-up module includes: a seventh transistor; the control terminal of the seventh transistor is connected to the stage output terminal of the ni-th stage output module, the first terminal of the seventh transistor is connected to the drive output terminal of the ni-th stage output module, and the second terminal of the seventh transistor is connected to the drive control node of the current stage.

[0014] In a second aspect, this application provides a display panel including a display area and a non-display area, wherein the display area includes a plurality of scan lines, and the non-display area includes a gate driving circuit as described in any one of the first aspects, and the output module of the gate driving circuit is connected to at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] This application sets up a control module and a bleeder module. The current stage will return a clock signal. When the control module receives the voltage on the current stage's drive control node and the current stage's transmission signal, or receives the current stage's drive control node and the current stage's gate drive signal, it can store the control voltage. Under the action of the n+q stage's drive voltage, a voltage is generated on the current stage's bleeder control node to act on the bleeder module. The bleeder module pulls down the current stage's drive control node, the current stage's transmission output terminal, and / or the current stage's drive output terminal to a low potential. This can prevent the tiny high-level signal generated by the output module during the non-scanning phase from being transmitted, thereby avoiding screen flicker on the display panel. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 A schematic diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0019] Figure 2 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown.

[0020] Figure 3 The diagram shows a waveform of a gate driving unit provided in an embodiment of this application.

[0021] Figure 4 The diagram shows the operating timing of a gate drive circuit according to an embodiment of this application.

[0022] Explanation of reference numerals in the attached figures: 100, Gate drive unit; 110, Pull-up module; 120, Output module; 130, Control module; 131, First control submodule; 132, Second control submodule; 140, Discharge module; 150, Reset module; 160, Pull-down module; T1, First transistor; T2, Second transistor; T3, Third transistor; T4, Fourth transistor; T5, Fifth transistor; T6, Sixth transistor; T7, Seventh transistor; T8, Eighth transistor; T9, Ninth transistor; C1, First capacitor; C2, Second capacitor; Qn, Drive control node of the current stage; Qn+q, Drive control node of the (n+q)th stage; An, Discharge control node of the current stage; Bn, Precharge control node of the current stage; Fn, Stage transmission output terminal of the current stage; Gn, Drive output terminal of the current stage; Reset, Reset control terminal; VSS, Low level terminal. Detailed Implementation

[0023] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0024] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0025] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0026] In liquid crystal display technology, multiple cascaded gate array (GOA) cells are driven using a line-by-line scanning method. The clock signal of the GOA cell is transmitted in stages over a certain period of time. Within one frame, a single clock signal generates multiple waveforms. When the clock signal returns, due to the parasitic capacitance between the clock signal receiver and the pull-up control node (commonly known as the Q point), a high-level signal will be generated, thereby outputting a brief gate drive signal and transmission signal again. For example, in an 8CK circuit with 8 clock signal lines, when CK1~CK8 transmit clock signals to the corresponding GOA driving units in rows 1 to 8, when the GOA unit in row 9 receives the clock signal transmitted by CK1, the GOA unit in row 1 will again receive the clock signal transmitted by CK1. Due to the parasitic capacitance between the gate and drain of the cascade transistor and the driving transistor in the GOA unit, the cascade transistor and the driving transistor will be slightly open, resulting in a brief high-level signal output from the source of the cascade transistor and the source of the driving transistor. This high-level signal is then cascaded and stored in the pre-charge capacitor of the next stage. Due to the influence of the pre-charge capacitor and parasitic capacitance, the degree of slight opening of the cascade transistor and the driving transistor in the next stage will become larger and larger. For example, when the clock signal from row 10 returns to row 2, the potential of the brief gate driving signal and the cascade signal in row 2 will be larger than that in row 1. And so on. As the cascade generation accumulates to a certain extent, the potential of the gate driving signal will increase to drive the pixel, thus producing screen flicker. Therefore, how to improve the screen flicker phenomenon after multiple stages in the gate drive circuit is an urgent problem to be solved.

[0027] Figure 1 A schematic diagram of a gate driving circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 1 As shown, the gate driving circuit includes N cascaded gate driving units 100. The nth stage gate driving unit 100 includes: a pull-up module 110, an output module 120, a control module 130, and a bleeder module 140. The pull-up module 110 is connected to the current stage's drive control node Qn. The output module 120 is connected to the current stage's drive control node Qn and the current stage's clock signal line CKm. The control module 130 is connected to the stage transmission output terminal Fn or the drive output terminal Gn of the output module 120, and is also connected to the current stage's drive control node Qn, the (n+q)th stage's drive control node Qn+q, and the current stage's bleeder control node An. The bleeder module 140 is connected to the current stage's bleeder control node An, and is also connected to the current stage's drive control node Qn, the stage transmission output terminal of the output module 120, and / or the drive output terminal of the output module 120.

[0028] In the diagram, CKm-1, CKm, and CKm+1 represent clock signal lines, Fn-i represents the stage output terminal of the ni-th stage, and Gn-i represents the drive output terminal of the ni-th stage.

[0029] In some embodiments, the pull-up module 110 is configured to charge the current stage drive control node Qn in response to the output signal of the nth stage gate drive unit 100.

[0030] For example, the output signal of the ni-th stage gate unit includes a stage transmission signal and a gate drive signal. When the pull-up module 110 receives the stage transmission signal and / or the gate drive signal from the ni-th stage output module 120, it will be turned on to charge the drive control node Qn of the current stage. The specific signal received by the pull-up module 110 can be set according to actual needs. Specifically, i can be 2.

[0031] In some embodiments, the output module 120 is configured to output the current stage transmission signal and the current stage gate drive signal under the action of the voltage on the current stage drive control node Qn and the current stage clock signal.

[0032] For example, when the current stage's drive control node Qn is precharged and the current stage's clock signal arrives, the output module 120 will be turned on, outputting the current stage's transmission signal for transmission, and outputting the current stage's gate drive signal to drive the pixel or perform transmission.

[0033] In some embodiments, the control module 130 is configured to generate a voltage on the discharge control node An of the current stage under the action of the voltage of the current stage drive control node Qn, the current stage transmission signal and the voltage of the (n+q)th stage drive control node Qn+q, or under the action of the voltage of the current stage drive control node Qn, the current stage gate drive signal and the voltage of the (n+q)th stage drive control node Qn+q; wherein q represents the number of clock signal lines.

[0034] For example, when a voltage exists on the current stage's drive control node Qn, the current stage's transmission signal and gate drive signal will be output simultaneously when the current stage's clock signal arrives. q represents the number of clock signal lines. When a voltage exists on the (n+q)th stage's drive control node Qn+q, it indicates that the (n+q)th stage's drive control node Qn+q has been pre-charged. The (n+q)th stage's clock signal will pass through, and the current stage will return a clock signal. When the control module 130 receives the voltage on the current stage's drive control node Qn and the current stage's transmission signal, or receives the current stage's drive control node Qn and the current stage's gate drive signal, it can store the control voltage. Under the action of the (n+q)th stage's drive voltage, a voltage is generated on the current stage's discharge control node An to act on the discharge module 140. Specifically, q can be 6, meaning the clock signal is 6CK, with 6 clock signal lines.

[0035] In some embodiments, the discharge module 140 is configured to pull down the current stage drive control node Qn, the current stage stage transmission output terminal Fn, and / or the current stage drive output terminal Gn to a low potential under the voltage action of the discharge control node An of the current stage.

[0036] For example, the voltage of the discharge control node An of the current stage is generated when there is a voltage on the drive control node Qn+q of the (n+q)th stage. Even when the clock signal of the (n+q)th stage returns to the current stage, under the action of the voltage of the discharge control node An of the current stage, the drive control node Qn of the current stage is pulled down to a low potential. When the drive control node of the output module 120 is pulled down to a low potential, the output module 120 will not be micro-conducted and will not output a small high-level signal, thus preventing stage transmission. When Fn is pulled down to a low potential, even if the output module 120 is slightly turned on, the current stage's transmission output terminal Fn will not output a small high-level signal, thus preventing transmission. When the current stage's drive output terminal Gn is pulled down to a low potential, even if the output module 120 is slightly turned on, the current stage's drive output terminal Gn will not output a small high-level signal, thus preventing transmission. The pull-up module 110 of the (n+i)th stage will not be turned on, avoiding the accumulation of small high-level signals and thus preventing screen flicker on the display panel.

[0037] Figure 2 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 As shown, the control module 130 includes: a first control submodule 131 and a second control submodule 132; the first control submodule 131 is connected to the current stage drive control node Qn and the current stage precharge control node Bn, and is also connected to the stage transmission output or drive output of the output module 120; the second control submodule 132 is connected to the current stage precharge control node Bn, the n+q stage drive control node Qn+q, and the current stage discharge control node An.

[0038] In some embodiments, the first control submodule 131 is configured to generate a voltage at the precharge control node Bn of the current stage under the action of the voltage of the current stage drive control node Qn and the stage transmission signal of the current stage, or under the action of the voltage of the current stage drive control node Qn and the gate drive signal of the current stage.

[0039] For example, when the first control submodule 131 receives the voltage of the current stage drive control node Qn and the current stage transmission signal, it will be turned on to charge the current precharge control node, or when the first control submodule 131 receives the current stage drive control node Qn and the current stage drive control signal, it will be turned on to charge the current stage precharge control node Bn, and the voltage on the current stage precharge control node Bn will be maintained.

[0040] In some embodiments, the second control submodule 132 is configured to generate a voltage on the discharge control node An of the current stage under the action of the voltage of the precharge control node Bn of the current stage and the voltage of the drive control node Qn+q of the (n+q)th stage.

[0041] For example, when there is a voltage on the drive control node Qn+q of the (n+q)th stage, it indicates that the (n+q)th stage will pass through the clock signal and the current stage clock signal is about to return. Under the action of the voltage of the drive control node Qn+q of the (n+q)th stage and the voltage of the precharge control node Bn of the current stage, a voltage will be generated on the discharge control node An of the current stage to act on the discharge module 140. This causes the discharge module 140 to pull down the drive control node Qn of the current stage, the stage transmission output terminal Fn of the current stage and / or the drive output terminal Gn of the current stage to a low potential when the current stage clock signal returns, thus cutting off the stage transmission.

[0042] Figure 3 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 As shown, the first control submodule 131 includes: a first transistor T1 and a first capacitor C1; the control terminal of the first transistor T1 is connected to the stage transmission output terminal or drive output terminal of the output module 120, the first terminal of the first transistor T1 is connected to the drive control node Qn of the current stage, the second terminal of the first transistor T1 is connected to the first terminal of the first capacitor C1, and the first terminal of the first capacitor C1 is connected to the precharge control node Bn of the current stage.

[0043] For example, Figure 4 A timing diagram of a gate drive circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 3 and Figure 4As shown, a voltage exists at the current stage's drive control node Qn. When the current stage's clock signal passes, the output module 120 will output the current stage's transmission signal and the current stage's gate drive signal. The first terminal of the first transistor T1 will receive the voltage from the current stage's drive control node Qn. The control terminal of the first transistor T1 will receive the current stage's transmission signal or gate drive signal, causing the first transistor T1 to conduct and charge the first capacitor C1, thereby generating a voltage at the current stage's pre-charge control node Bn. In the figure, Gn-2 represents the drive output terminal of the (n-2)th stage, and Fn-2 represents the transmission output terminal of the (n-2)th stage. There is a 1-hour overlap between the clock signals of adjacent stages.

[0044] In some embodiments, please refer to Figure 3 As shown, the second control submodule 132 includes: a second transistor T2; the control terminal of the second transistor T2 is connected to the drive control node Qn+q of the (n+q)th stage, the first terminal of the second transistor T2 is connected to the precharge control node Bn of the current stage, and the second terminal of the second transistor T2 is connected to the discharge control node An of the current stage.

[0045] For example, please refer to Figure 3 and Figure 4 As shown, when there is a voltage on the drive control node Qn+q of the (n+q)th stage, it means that the output module 120 of the (n+q)th stage will receive the clock signal of the (n+q)th stage, the clock signal of the current stage will return, and the control terminal of the second transistor T2 will be turned on when it receives the voltage of the drive control node Qn+q of the (n+q)th stage. At the same time, the first terminal of the second transistor T2 receives the voltage on the precharge control node Bn of the current stage. After the second transistor T2 is turned on, it will generate a voltage on the discharge control node An of the current stage.

[0046] In some embodiments, please refer to Figure 3 As shown, the discharge module 140 includes: a third transistor T3; the control terminal of the third transistor T3 is connected to the discharge control node An of the current stage, the first terminal of the third transistor T3 is connected to the drive control node Qn of the current stage, the stage transmission output terminal of the output module 120 and / or the drive output terminal of the output module 120, and the second terminal of the third transistor T3 is connected to the low-level terminal VSS.

[0047] For example, please refer to Figure 3 and Figure 4As shown, when the clock signal of the (n+q)th stage returns to the current stage, the control terminal of the third transistor T3 will conduct when it receives the voltage on the discharge control node An of the current stage. This will pull down the drive control node Qn of the current stage, the stage transmission output terminal Fn of the current stage, and / or the drive output terminal Gn of the current stage to a low potential. When the drive control node Qn of the current stage is pulled down to a low potential, even if the output module 120 receives the return clock signal, the drive control node Qn of the current stage will be difficult to turn on, making it difficult to output a small high-level signal, thus preventing stage transmission. When the drive output terminal Gn of the current stage is pulled down to a low potential, even if the output module 120 is slightly turned on, the drive output terminal Gn of the current stage will not output a small high-level signal, thus preventing stage transmission. The pull-up module 110 of the (n+i)th stage will not conduct, avoiding the accumulation of small high-level signals and thus preventing screen flickering on the display panel.

[0048] In some embodiments, please refer to Figure 2 As shown, the nth stage gate drive unit 100 further includes a reset module 150, which is connected to the reset control terminal Reset and the discharge control node An of the current stage, and is configured to reset the discharge control node An of the current stage under the action of the reset control signal during the vertical blanking period.

[0049] For example, the reset control terminal Reset can be the signal output terminal of the timing controller. Outputting a reset control signal during the vertical blanking period will not affect the normal scanning process. After resetting the discharge control node An of the current level, the pull-up module 110 and the output module 120 can be driven normally in the next scanning frame without affecting the normal level transmission.

[0050] In some embodiments, please refer to Figure 3 As shown, the reset module 150 includes: a fourth transistor T4; the control terminal of the fourth transistor T4 is connected to the reset control terminal Reset, the first terminal of the fourth transistor T4 is connected to the discharge control node An of the current stage, and the second terminal of the fourth transistor T4 is connected to the low-level terminal VSS.

[0051] For example, when the control terminal of the fourth transistor T4 receives a reset control signal, the fourth transistor T4 will be turned on, thereby pulling down the discharge control node An of the current stage to a low potential. The third transistor T3 in the discharge module 140 will be in the off state and will not pull down the drive control node Qn of the current stage, the stage transmission output terminal Fn of the current stage, or the current drive output terminal to a low potential.

[0052] In some embodiments, please refer to Figure 3As shown, the output module 120 includes: a fifth transistor T5, a sixth transistor T6, and a second capacitor C2; the control terminal of the fifth transistor T5, the control terminal of the sixth transistor T6, and the first terminal of the second capacitor C2 are connected to the drive control node Qn of the current stage; the first terminal of the fifth transistor T5 is connected to the clock signal line CKm of the current stage; and the second terminal of the fifth transistor T5 serves as the stage transmission output terminal; the second terminal of the sixth transistor T6 is connected to the second terminal of the second capacitor C2 and serves as the drive output terminal.

[0053] For example, please refer to Figure 3 and Figure 4 As shown, when the current stage's drive control node Qn is precharged, the voltage of the current stage's drive control node Qn is stored in the second capacitor C2. When the current stage's clock signal arrives, the voltage of the second capacitor C2 will bootstrap the current stage's drive control node Qn, ensuring that the fifth transistor T5 and the sixth transistor T6 are turned on. The second terminal of the fifth transistor T5 outputs the current stage's drive signal, and the second terminal of the sixth transistor T6 outputs the current stage's gate drive signal.

[0054] It should be noted that, due to the parasitic capacitance between the gate and drain of the fifth transistor T5 and the sixth transistor T6, when the fifth transistor T5 and the sixth transistor T6 receive the current stage clock signal returned during the non-scanning period, they may slightly turn on and output a small high-level signal.

[0055] In some embodiments, please refer to Figure 3 As shown, the pull-up module 110 includes: a seventh transistor T7; the control terminal of the seventh transistor T7 is connected to the stage transmission output terminal of the ni-th stage output module 120, the first terminal of the seventh transistor T7 is connected to the drive output terminal of the ni-th stage output module 120, and the second terminal of the seventh transistor T7 is connected to the drive control node Qn of the current stage.

[0056] For example, please refer to Figure 3 and Figure 4 As shown, when the control terminal of the seventh transistor T7 receives the gate drive signal output from the drive output terminal of the nith stage, and the first terminal of the seventh transistor T7 receives the stage transmission signal output from the stage transmission output terminal of the nith stage, the seventh transistor T7 will be turned on to precharge the drive control node Qn of the current stage.

[0057] In some embodiments, please refer to Figure 3As shown, the nth stage gate drive unit 100 further includes a pull-down module 160, which includes an eighth transistor T8 and a ninth transistor T9. The control terminals of the eighth transistor T8 and the ninth transistor T9 are connected to the stage transmission output terminal of the (n+j)th stage. The first terminal of the eighth transistor T8 is connected to the drive control node Qn of the current stage. The second terminal of the eighth transistor T8 and the second terminal of the ninth transistor T9 are connected to the low-level terminal VSS. The first terminal of the ninth transistor T9 is connected to the drive output terminal Gn of the current stage.

[0058] For example, when the control terminals of the eighth transistor T8 and the ninth transistor T9 receive the stage transmission signal output from the stage transmission output terminal of the (n+j)th stage, the eighth transistor T8 and the ninth transistor T9 will be turned on. The eighth transistor T8 pulls down the current stage's drive control node Qn to a low potential, and the ninth transistor T9 pulls down the current stage's drive output terminal Gn to a high potential, ensuring that no gate drive signal is output after the current stage's working period has passed, and that the current stage's drive control node Qn can be charged again when the next scan frame arrives. Specifically, j can be 3.

[0059] In some embodiments, this application also provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the gate driving circuit described above. The output module 120 of the gate driving circuit is connected to at least one scan line.

[0060] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0061] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0062] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes N cascaded gate driving units, and the nth gate driving unit includes: The pull-up module, connected to the current stage's drive control node, is configured to charge the current stage's drive control node in response to the output signal of the ni-th stage's gate drive unit. The output module, connected to the drive control node and clock signal line of the current stage, is configured to output the stage transmission signal and the gate drive signal of the current stage under the action of the voltage on the drive control node and the clock signal of the current stage. A control module, connected to the stage transmission output or drive output of the output module, and also connected to the drive control node of the current stage, the drive control node of the (n+q)th stage, and the discharge control node of the current stage, is configured to generate a voltage on the discharge control node of the current stage under the action of the voltage of the drive control node of the current stage, the stage transmission signal of the current stage, and the voltage of the drive control node of the (n+q)th stage, or under the action of the voltage of the drive control node of the current stage, the gate drive signal of the current stage, and the voltage of the drive control node of the (n+q)th stage; where q represents the number of clock signal lines; The discharge module, connected to the discharge control node of the current stage, and also connected to the drive control node of the current stage, the stage transmission output terminal of the output module, and / or the drive output terminal of the output module, is configured to: pull down the drive control node of the current stage, the stage transmission output terminal of the current stage, and / or the drive output terminal of the current stage to a low potential under the voltage action of the discharge control node of the current stage.

2. The gate driving circuit according to claim 1, characterized in that, The control module includes: The first control submodule, connected to the current stage's drive control node and precharge control node, and also connected to the stage transmission output or drive output of the output module, is configured to generate a voltage at the current stage's precharge control node under the action of the voltage of the current stage's drive control node and the stage transmission signal of the current stage, or under the action of the voltage of the current stage's drive control node and the gate drive signal of the current stage. The second control submodule, connected to the precharge control node of the current stage, the drive control node of the (n+q)th stage, and the discharge control node of the current stage, is configured to generate a voltage on the discharge control node of the current stage under the action of the voltage of the precharge control node of the current stage and the voltage of the drive control node of the (n+q)th stage.

3. The gate driving circuit according to claim 2, characterized in that, The first control submodule includes: a first transistor and a first capacitor; The control terminal of the first transistor is connected to the stage transmission output terminal or drive output terminal of the output module, the first terminal of the first transistor is connected to the drive control node of the current stage, and the second terminal of the first transistor is connected to the first terminal of the first capacitor. The first terminal of the first capacitor is connected to the precharge control node of the current stage.

4. The gate driving circuit according to claim 2, characterized in that, The second control submodule includes: a second transistor; The control terminal of the second transistor is connected to the drive control node of the (n+q)th stage, the first terminal of the second transistor is connected to the precharge control node of the current stage, and the second terminal of the second transistor is connected to the discharge control node of the current stage.

5. The gate driving circuit according to claim 1, characterized in that, The discharge module includes: a third transistor; The control terminal of the third transistor is connected to the discharge control node of the current stage, the first terminal of the third transistor is connected to the drive control node of the current stage, the stage transmission output terminal of the output module, and / or the drive output terminal of the output module, and the second terminal of the third transistor is connected to the low-level terminal.

6. The gate driving circuit according to claim 1, characterized in that, The nth-stage gate driving unit further includes: The reset module, which is connected to the reset control terminal and the discharge control node of the current stage, is configured to reset the discharge control node of the current stage under the action of the reset control signal during the vertical blanking period.

7. The gate driving circuit according to claim 6, characterized in that, The reset module includes: a fourth transistor; The control terminal of the fourth transistor is connected to the reset control terminal, the first terminal of the fourth transistor is connected to the discharge control node of the current stage, and the second terminal of the fourth transistor is connected to the low-level terminal.

8. The gate driving circuit according to claim 1, characterized in that, The output module includes: a fifth transistor, a sixth transistor, and a second capacitor; The control terminal of the fifth transistor, the control terminal of the sixth transistor, and the first terminal of the second capacitor are connected to the drive control node of the current stage. The first terminal of the fifth transistor is connected to the clock signal line of the current stage, and the second terminal of the fifth transistor serves as the transmission output terminal of the stage. The second terminal of the sixth transistor is connected to the second terminal of the second capacitor and serves as the drive output terminal.

9. The gate driving circuit according to claim 1, characterized in that, The pull-up module includes: a seventh transistor; The control terminal of the seventh transistor is connected to the stage output terminal of the ni-th stage output module, the first terminal of the seventh transistor is connected to the drive output terminal of the ni-th stage output module, and the second terminal of the seventh transistor is connected to the drive control node of the current stage.

10. A display panel comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-9, wherein the output module of the gate driving circuit is connected to at least one of the scan lines.

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