A gate driving circuit and a display panel

Abstract

This application belongs to the field of display driving technology, specifically relating to a gate driving circuit and a display panel. The gate driving circuit includes N cascaded gate driving units. The nth gate driving unit includes: a pull-up module configured to charge the driving control node of the current stage in response to the output signal of the (n-i)th gate driving unit; an output module configured to output the stage transmission signal and the gate driving signal of the current stage under the action of the voltage on the driving control node of the current stage and the clock signal of the current stage; and a discharge module connected to the driving control node of the (n+q)th stage, and also connected to the stage transmission output terminal and / or the driving output terminal of the output module, configured to pull down the stage transmission output terminal and / or the driving output terminal of the current stage to a low potential under the action of the voltage on the driving control node of the (n+q)th stage; where q represents the number of clock signal lines. This improves the screen flicker phenomenon after multiple stage transmissions in the gate driving circuit.

Description

Technical Field

[0001] This application belongs to the field of display driver technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] In liquid crystal display technology, multiple cascaded array substrate row driver (GOA) cells are driven using a line-by-line scanning method. The clock signal of the GOA cell is propagated at regular intervals, and within one frame, a single clock signal generates multiple waveforms. When the clock signal returns, a high-level signal is generated due to parasitic capacitance between the clock signal receiver and the pull-up control node (commonly known as the Q point). This causes a brief output of the gate drive signal and the propagation signal. As the propagation accumulates to a certain extent, the potential of the gate drive signal increases to the level driving the pixel, resulting in screen flicker.

[0003] Therefore, how to improve the screen flicker phenomenon after multiple stages in the gate drive circuit is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel, which solves the screen flicker problem caused by multiple stages of transmission in the gate driving circuit.

[0005] In a first aspect, this application provides a gate driving circuit, comprising N cascaded gate driving units. The nth gate driving unit includes: a pull-up module connected to the current stage's drive control node, configured to charge the current stage's drive control node in response to the output signal of the nth gate driving unit; an output module connected to the current stage's drive control node and the current stage's clock signal line, configured to output the current stage's cascade signal and the current stage's gate driving signal under the influence of the voltage on the current stage's drive control node and the current stage's clock signal; and a discharge module connected to the (n+q)th stage's drive control node and also connected to the output module. The block's stage output terminal and / or drive output terminal are connected and configured to: under the voltage of the drive control node of the (n+q)th stage, pull down the stage output terminal and / or drive output terminal of the current stage to a low potential; where q represents the number of clock signal lines, and when there is voltage at the drive control node of the (n+q)th stage, the clock signal line of the current stage will receive a high-level signal; the discharge module includes: a first transistor; the control terminal of the first transistor is connected to the drive control node of the (n+q)th stage, the first terminal of the first transistor is connected to the stage output terminal and / or drive output terminal of the current stage, and the second terminal of the first transistor is connected to a low-level terminal.

[0006] Optionally, the pull-up module includes: a pre-charge submodule connected to the pull-up node of the current stage, configured to charge the pull-up node of the current stage in response to the output signal of the gate drive unit of the ni-th stage; and a switching submodule connected to the drive control node of the ni-th stage, the clock signal line of the ni-th stage, the pull-up node of the current stage, and the drive control node of the current stage, respectively, configured to control the pull-up node of the current stage to connect to the drive control node of the current stage under the action of the voltage of the drive control node of the ni-th stage and the clock signal of the ni-th stage.

[0007] Optionally, the switching submodule includes: a second transistor and a third transistor; the control terminal of the second transistor is connected to the clock signal line of the ni-th stage, the first terminal of the second transistor is connected to the drive control node of the ni-th stage, and the second terminal of the second transistor is connected to the control terminal of the third transistor; the first terminal of the third transistor is connected to the pull-up node of the current stage, and the second terminal of the third transistor is connected to the drive control node of the current stage.

[0008] Optionally, the precharge submodule includes: a fourth transistor; the control terminal of the fourth transistor is connected to the stage output terminal of the ni-th stage output module, the first terminal of the fourth transistor is connected to the drive output terminal of the ni-th stage output module, and the second terminal of the fourth transistor is connected to the pull-up node of the current stage.

[0009] Optionally, the output module includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a bootstrap capacitor; the control terminal of the fifth transistor, the control terminal of the sixth transistor, and the first terminal of the bootstrap capacitor are connected to the drive control node of the current stage; the first terminal of the fifth transistor is connected to the clock signal line of the current stage; the second terminal of the fifth transistor is connected to the control terminal of the seventh transistor, the first terminal of the seventh transistor, and the first terminal of the eighth transistor; the first terminal of the sixth transistor is connected to the clock signal line of the current stage; the second terminal of the sixth transistor is connected to the second terminal of the bootstrap capacitor and serves as the drive output terminal of the current stage; the second terminal of the seventh transistor is connected to the control terminal of the eighth transistor; and the second terminal of the eighth transistor serves as the stage transmission output terminal of the current stage.

[0010] Optionally, the output module includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a bootstrap capacitor, a ninth transistor, and a tenth transistor; the control terminal of the fifth transistor, the control terminal of the sixth transistor, and the first terminal of the bootstrap capacitor are connected to the drive control node of the current stage; the first terminal of the fifth transistor is connected to the clock signal line of the current stage; the second terminal of the fifth transistor is connected to the control terminal of the seventh transistor, the second terminal of the seventh transistor, and the second terminal of the eighth transistor; the first terminal of the sixth transistor is connected to the clock signal line of the current stage; the second terminal of the sixth transistor is connected to the second terminal of the bootstrap capacitor, the control terminal of the ninth transistor, the first terminal of the ninth transistor, and the first terminal of the tenth transistor; the second terminal of the seventh transistor is connected to the control terminal of the eighth transistor; the second terminal of the eighth transistor serves as the stage output terminal of the current stage; the second terminal of the ninth transistor is connected to the control terminal of the tenth transistor; and the second terminal of the tenth transistor serves as the drive output terminal of the current stage.

[0011] Optionally, the output module includes: a first drive output submodule, connected to the clock signal line of the current stage, the drive control node of the current stage, and the output control node of the current stage, configured to generate a voltage on the output control node of the current stage under the action of the clock signal of the current stage and the voltage of the drive control node of the current stage; a second drive output submodule, connected to the output control node of the current stage and the drive control node of the current stage, configured to output the gate drive signal of the current stage under the action of the voltage of the output control node of the current stage and the voltage of the drive control node of the current stage; and a discharge module, also connected to the output control node of the current stage, further configured to pull down the output control node of the current stage to a low potential under the action of the voltage of the drive control node of the (n+q)th stage.

[0012] Optionally, the first drive output submodule includes: a ninth transistor; the control terminal of the ninth transistor is connected to the drive control node of the current stage, the first terminal of the ninth transistor is connected to the clock signal line of the current stage, and the second terminal of the ninth transistor is connected to the output control node of the current stage.

[0013] Optionally, the second drive output submodule includes: a sixth transistor and a bootstrap capacitor; the control terminal of the sixth transistor is connected to the drive control node of the current stage and the first terminal of the bootstrap capacitor, the first terminal of the sixth transistor is connected to the output control node of the current stage, and the second terminal of the sixth transistor is connected to the second terminal of the bootstrap capacitor and serves as the drive control node of the current stage.

[0014] In a second aspect, this application provides a display panel including a display area and a non-display area, wherein the display area includes a plurality of scan lines, and the non-display area includes a gate driving circuit as described in any one of the first aspects, and the output module of the gate driving circuit is connected to at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects: This application sets up a bleeder module. When the output module of the (n+q)th stage receives the clock signal, under the voltage action of the drive control node of the (n+q)th stage, it pulls down the stage transmission output terminal and / or the drive output terminal of the current stage to a low potential. Even if the output module is slightly turned on, it will not output a small high-level signal for stage transmission. The pull-up module of the (n+i)th stage will not be turned on, so the small high-level signal will not accumulate and will not be enough to drive the pixels, thereby avoiding screen flicker on the display panel. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] Figure 1 A schematic diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0018] Figure 2 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown.

[0019] Figure 3 The diagram shows the operating timing of a gate drive circuit according to an embodiment of this application.

[0020] Figure 4 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown.

[0021] Figure 5 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown.

[0022] Figure 6 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown.

[0023] Explanation of reference numerals in the attached figures: 100, Gate drive unit; 110, Pull-up module; 111, Precharge submodule; 112, Switch submodule; 120, Output module; 121, First drive output submodule; 122, Second drive output submodule; 123, Stage transmission output submodule; 130, Discharge module; 140, Pull-down module; T1, First transistor; T2, Second transistor; T3, Third transistor; T4, Fourth transistor; T5, Fifth transistor; T6, Sixth transistor; T7, Seventh transistor; T8, Eighth transistor; T9, Ninth transistor; T10, Tenth transistor; T11, Eleventh transistor; T12, Twelfth transistor; T13, Thirteenth transistor; CC, Bootstrap capacitor; Qn, Pull-up node; Qsn, Drive control node; An, Output control node; VSS, Low-level terminal. Detailed Implementation

[0024] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0025] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0026] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0027] In liquid crystal display technology, multiple cascaded gate array (GOA) cells are driven using a line-by-line scanning method. The clock signal of the GOA cell is transmitted in stages over a certain period of time. Within one frame, a single clock signal generates multiple waveforms. When the clock signal returns, due to the parasitic capacitance between the clock signal receiver and the pull-up control node (commonly known as the Q point), a high-level signal will be generated, thereby outputting a brief gate drive signal and transmission signal again. For example, in an 8CK circuit with 8 clock signal lines, when CK1~CK8 transmit clock signals to the corresponding GOA driving units in rows 1 to 8, when the GOA unit in row 9 receives the clock signal transmitted by CK1, the GOA unit in row 1 will again receive the clock signal transmitted by CK1. Due to the parasitic capacitance between the gate and drain of the cascade transistor and the driving transistor in the GOA unit, the cascade transistor and the driving transistor will be slightly open, resulting in a brief high-level signal output from the source of the cascade transistor and the source of the driving transistor. This high-level signal is then cascaded and stored in the pre-charge capacitor of the next stage. Due to the influence of the pre-charge capacitor and parasitic capacitance, the degree of slight opening of the cascade transistor and the driving transistor in the next stage will become larger and larger. For example, when the clock signal from row 10 returns to row 2, the potential of the brief gate driving signal and the cascade signal in row 2 will be larger than that in row 1. And so on. As the cascade generation accumulates to a certain extent, the potential of the gate driving signal will increase to drive the pixel, thus producing screen flicker. Therefore, how to improve the screen flicker phenomenon after multiple stages in the gate drive circuit is an urgent problem to be solved.

[0028] Figure 1 A schematic diagram of a gate driving circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 1 As shown, the gate driving circuit includes N cascaded gate driving units 100. The nth gate driving unit 100 includes a pull-up module 110, an output module 120, and a bleeder module 130. The pull-up module 110 is connected to the current stage's drive control node Qsn. The output module 120 is connected to the current stage's drive control node Qsn and the current stage's clock signal line CKm. The bleeder module 130 is connected to the (n+q)th stage's drive control node Qsn+q. The bleeder module 130 is also connected to the stage transmission output terminal Fn and / or the drive output terminal Gn of the output module 120.

[0029] It should be noted that in the diagram, CKm-1, CKm, and CKm+1 represent clock signal lines, Fn represents the stage output terminal of the nth stage output module, Gn represents the drive output terminal of the nth stage output module, Fn-i represents the stage output terminal of the nith stage output module, and Gn-i represents the drive output terminal of the nith stage output module. The bleeder module 130 can be connected individually to the stage output terminal Fn of the output module 120, or individually to the drive output terminal Gn of the output module 120, or simultaneously to both the drive output terminal Gn and the stage output terminal Fn of the output module.

[0030] In some embodiments, the pull-up module 110 is configured to charge the current stage's drive control node Qsn in response to the output signal of the ni-th stage gate drive unit 100.

[0031] For example, the output signal of the ni-th stage gate drive unit 100 includes: the stage transmission signal of the ni-th stage and the gate drive signal of the ni-th stage. When the pull-up module 110 receives the stage transmission signal of the ni-th stage and the gate drive signal of the ni-th stage, it will be turned on to charge the drive control node Qsn of the current stage. Specifically, i can be 2.

[0032] In some embodiments, the output module 120 is configured to output the current stage transmission signal and the current stage gate drive signal under the action of the voltage on the current stage drive control node Qsn and the current stage clock signal.

[0033] For example, the current stage's drive control node Qsn is pre-charged with voltage, and when the clock signal of the current stage arrives, the output module 120 will be turned on, outputting the current stage's transmission signal and the current stage's gate drive signal. The current stage's transmission signal acts on the gate drive unit 100 of the adjacent stage, and the current stage's gate drive signal can be used to drive pixels or transmissions.

[0034] In some embodiments, the discharge module 130 is configured to: pull down the stage transmission output terminal and / or the drive output terminal of the current stage to a low potential under the voltage action of the drive control node Qsn+q of the n+q stage; wherein q represents the number of clock signal lines, and when there is voltage at the drive control node of the n+q stage, the clock signal line of the current stage will receive a high-level signal.

[0035] For example, the clock signal line of the nth stage and the clock signal line of the (n+q)th stage are the same clock signal line. When the output module 120 of the (n+q)th stage receives the clock signal, the output module 120 of the current stage (nth stage) will also receive a high-level signal through the clock signal line of the current stage. The output module 120 of the current stage may be slightly turned on and output a small high-level signal for stage transmission. When a voltage exists at the (n+q)th stage drive control node Qsn+q, it indicates that the clock signal of the (n+q)th stage may pass through the (n+q)th stage. Simultaneously, the output module 120 of the current stage may also receive a clock signal (i.e., a high-level signal) through the clock signal line of the current stage. When the discharge module 130 receives the voltage at the (n+q)th stage drive control node Qsn+q, it pulls down the stage transmission output terminal and / or the drive output terminal of the current stage to a low potential. Even if a micro-conduction occurs in the output module 120, it will not output a small high-level signal for stage transmission. The pull-up module 110 of the (n+i)th stage will not conduct, thus preventing the accumulation of the small high-level signal, which will be insufficient to drive the pixel and avoid screen flicker. Specifically, q can be 6, indicating that this embodiment uses a 6CK clock signal, and the number of clock signal lines is 6.

[0036] Figure 2 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 As shown, the discharge module 130 includes: a first transistor T1; the control terminal of the first transistor T1 is connected to the drive control node Qsn+q of the (n+q)th stage, the first terminal of the first transistor T1 is connected to the stage transmission output terminal of the current stage and / or the drive output terminal of the current stage, and the second terminal of the first transistor T1 is connected to the low-level terminal VSS.

[0037] For details, please refer to Figure 2 As shown, the first terminal of the first transistor T1 can be connected to the stage output terminal Fn of the current stage, or to the drive output terminal Gn of the current stage. The first terminal of the first transistor T1 can also be connected to both the drive output terminal Gn and the stage output terminal Fn of the current stage at the same time.

[0038] For example, Figure 3 A timing diagram of a gate drive circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 and Figure 3 As shown, when the control terminal of the first transistor T1 receives the voltage of the (n+q)th stage, the first transistor T1 will be turned on, thereby pulling down the stage transmission output terminal and / or the drive output terminal of the current stage to a low potential. Even if the output module 120 is slightly turned on, it will not output the stage transmission signal and / or the gate drive signal of the current stage. The pull-up module 110 will not be able to receive the stage transmission signal and / or the gate drive signal of the current stage, and thus the pull-up module 110 will not be turned on.

[0039] It should be noted that q can be 6, Qn+6 represents the pull-up node of the (n+6)th stage, and Qsn+6 represents the drive control node of the (n+6)th stage. The clock signals in the figure are clock signals with overlapping periods, that is, the clock signal of the current stage and the clock signal of the nith stage have an overlap period of one clock cycle.

[0040] Figure 4 A schematic diagram of another gate drive circuit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 4 As shown, the pull-up module 110 includes a pre-charge submodule 111 and a switch submodule 112. The pre-charge submodule 111 is connected to the pull-up node Qn of the current stage. The switch submodule 112 is connected to the drive control node Qsn-i of the ni-th stage, the clock signal line CKm-i of the ni-th stage, the pull-up node Qn of the current stage, and the drive control node Qsn of the current stage. Specifically, i can be 2, and the clock signal line CKm-i of the ni-th stage in the figure is represented by CKm-2.

[0041] In some embodiments, the precharge submodule 111 is configured to charge the pull-up node Qn of the current stage in response to the output signal of the nth stage gate drive unit 100.

[0042] For example, when the precharge submodule 111 receives the output signal of the ni-th stage gate drive unit 100, it will be turned on to charge the pull-up node Qn of the current stage to generate a voltage on the pull-up node Qn of the current stage.

[0043] In some embodiments, the switch submodule 112 is configured to control the pull-up node Qn of the current stage to be connected to the drive control node Qsn of the current stage under the action of the voltage of the drive control node Qsn-i of the ni stage and the clock signal of the ni stage.

[0044] For example, by setting the switch submodule 112, during the pre-charge period of the current stage, when the switch submodule 112 receives the voltage of the drive control node Qsn-i of the ni-th stage and the clock signal of the ni-th stage, the switch submodule 112 is turned on, controlling the pull-up node Qn of the current stage to be connected to the drive control node Qsn of the current stage. This ensures that the voltage on the pull-up node Qn of the current stage is transmitted to the drive control node Qsn of the current stage only when the pre-charge period and drive period of the current stage arrive, and remains in the off state during other periods. Even if the output module 120 of the ni-th stage is slightly turned on during the non-working period and outputs a small high-level signal, and the pull-up module 110 of the current stage is slightly turned on, the drive control voltage of the ni-th stage is small at this time, so the switch submodule 112 is difficult to turn on or has a small degree of turn-on. The voltage on the pull-up node Qn of the current stage is difficult to transmit to the drive control node Qsn of the current stage, which can further avoid the accumulation of small high-level signals, thereby further avoiding screen flicker.

[0045] In some embodiments, please refer to Figure 2 As shown, the switch submodule 112 includes: a second transistor T2 and a third transistor T3; the control terminal of the second transistor T2 is connected to the clock signal line CKm-i of the ni-th stage, the first terminal of the second transistor T2 is connected to the drive control node Qsn-i of the ni-th stage, and the second terminal of the second transistor T2 is connected to the control terminal of the third transistor T3; the first terminal of the third transistor T3 is connected to the pull-up node Qn of the current stage, and the second terminal of the third transistor T3 is connected to the drive control node Qsn of the current stage.

[0046] In some embodiments, the precharge submodule 111 includes: a fourth transistor T4; the control terminal of the fourth transistor T4 is connected to the stage transmission output terminal of the ni-th stage output module 120, the first terminal of the fourth transistor T4 is connected to the drive output terminal of the ni-th stage output module 120, and the second terminal of the fourth transistor T4 is connected to the pull-up node Qn of the current stage.

[0047] For example, please refer to Figure 2 and Figure 3As shown, when the control terminal of the second transistor T2 receives the clock signal of the ni-th stage, and the first terminal of the second transistor T2 receives the voltage of the drive control node Qsn-i of the ni-th stage, the first transistor T1 will turn on and output a high-level signal through its second terminal. When the control terminal of the third transistor T3 receives the high-level signal output by the second transistor T2, it will turn on, thereby controlling the pull-up node Qn of the current stage to connect with the drive control node Qsn of the current stage. When the control terminal of the fourth transistor T4 receives the stage transmission signal of the ni-th stage, and the first terminal of the fourth transistor T4 receives the gate drive signal of the ni-th stage, the fourth transistor T4 will turn on, thereby enabling the drive control node Qsn of the current stage to be charged through the pull-up node Qn of the current stage.

[0048] For example, when the control terminal of the second transistor T2 receives the clock signal returned from the ni-th stage, the second transistor T2 receives a small voltage on the drive control node of the ni-th stage, and the second transistor T2 turns on. However, the small voltage output by the second transistor T2 is insufficient to control the third transistor T3 to turn on or to control the degree of turn-on of the third transistor T3. When the control terminal of the fourth transistor T4 receives a small high-level signal output from the stage output terminal of the ni-th stage, and the first terminal of the fourth transistor T4 receives a small high-level signal output from the drive output terminal of the ni-th stage, the fourth transistor T4 will turn on and charge the pull-up node Qn of the current stage. However, since the third transistor T3 is difficult to turn on or to turn on to a small degree, the voltage of the pull-up node Qn of the current stage is difficult to be transmitted to the drive control node Qsn of the current stage, thereby avoiding the accumulation of the small high-level signal.

[0049] In some embodiments, please refer to Figure 2 As shown, the output module 120 includes: a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a bootstrap capacitor CC; the control terminal of the fifth transistor T5, the control terminal of the sixth transistor T6, and the first terminal of the bootstrap capacitor CC are connected to the drive control node Qsn of the current stage; the first terminal of the fifth transistor T5 is connected to the clock signal line CKm of the current stage; the second terminal of the fifth transistor T5 is connected to the control terminal of the seventh transistor T7, the first terminal of the seventh transistor T7, and the first terminal of the eighth transistor T8; the first terminal of the sixth transistor T6 is connected to the clock signal line CKm of the current stage; the second terminal of the sixth transistor T6 is connected to the second terminal of the bootstrap capacitor CC and serves as the drive output terminal Gn of the current stage; the second terminal of the seventh transistor T7 is connected to the control terminal of the eighth transistor T8; and the second terminal of the eighth transistor T8 serves as the stage transmission output terminal Fn of the current stage.

[0050] For example, during the current stage's driving period, there is a voltage on the current stage's driving control node Qsn. When the current stage's clock signal arrives, the voltage of the bootstrap capacitor CC bootstraps the current stage's driving control node Qsn. After the fifth transistor T5 is turned on, it will control the seventh transistor T7 and the eighth transistor T8 to turn on, thereby outputting the current stage's transmission signal. At the same time, since there are parasitic capacitances at the gate and drain of the fifth transistor T5, when the first terminal of the fifth transistor T5 receives the returned clock signal and is slightly turned on, it outputs a small high-level signal. By setting the seventh transistor T7 and the eighth transistor T8, the transmission difficulty of the small high-level signal will be increased, which can prevent the small high-level signal from being transmitted to the pull-up module 110 of the n+i stage, further avoiding the accumulation of the small high-level signal.

[0051] Figure 5 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 5 As shown, the output module 120 includes: a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a bootstrap capacitor CC, a ninth transistor T9, and a tenth transistor T10; the control terminals of the fifth transistor T5 and the sixth transistor T6, and the first terminal of the bootstrap capacitor CC are connected to the current stage's drive control node Qsn; the first terminal of the fifth transistor T5 is connected to the current stage's clock signal line CKm; the second terminal of the fifth transistor T5 is connected to the control terminal of the seventh transistor T7, the first terminal of the seventh transistor T7, and the first terminal of the eighth transistor T8; the first terminal of the sixth transistor T6 is connected to the current stage's clock signal line CKm; the second terminal of the sixth transistor T6 is connected to the second terminal of the bootstrap capacitor CC, the control terminal of the ninth transistor T9, the first terminal of the ninth transistor T9, and the first terminal of the tenth transistor T10; the second terminal of the seventh transistor T7 is connected to the control terminal of the eighth transistor T8; the second terminal of the eighth transistor T8 serves as the current stage's stage output terminal Fn; the second terminal of the ninth transistor T9 is connected to the control terminal of the tenth transistor T10; and the second terminal of the tenth transistor T10 serves as the current stage's drive output terminal.

[0052] For example, please refer to Figure 3 and Figure 5As shown, a voltage exists on the current stage's drive control node Qsn. When the current stage's clock signal arrives, the voltage of the bootstrap capacitor CC bootstraps the current stage's drive control node Qsn, causing the sixth transistor T6 to conduct. This, in turn, controls the ninth transistor T9 and the tenth transistor T10 to conduct, resulting in the tenth transistor T10 outputting the current stage's gate drive signal at its second terminal. Simultaneously, due to parasitic capacitance at the gate and drain of the sixth transistor T6, when the first terminal of the sixth transistor T6 receives the returned clock signal and undergoes a slight conduction, it outputs a small high-level signal. By setting the ninth transistor T9 and the tenth transistor T10, the transmission difficulty of this small high-level signal is increased, hindering its transmission to the (n+i)th stage's pull-up module 110, further preventing the accumulation of small high-level signals. It should be noted that... Figure 5 The working principle of the circuit connection part of the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 is the same as Figure 2 The same applies, so I won't repeat it here.

[0053] Figure 6 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 6 As shown, the output module 120 includes: a first drive output submodule 121, a second drive output submodule 122, and a stage transmission output submodule 123; the first drive output submodule 121 is connected to the clock signal line CKm of the current stage, the drive control node Qsn of the current stage, and the output control node An of the current stage; the second drive output submodule 122 is connected to the output control node An and the drive control node Qsn of the current stage; and the stage transmission output submodule 123 is connected to the drive control node Qsn and the clock signal line CKm of the current stage.

[0054] In some embodiments, the first drive output submodule 121 is configured to generate a voltage on the output control node An of the current stage under the action of the current stage clock signal and the voltage of the current stage drive control node Qsn.

[0055] For example, after precharging the current stage drive control node Qsn, the first drive output submodule 121 will be turned on when it receives the voltage on the current stage drive control node Qsn and the current stage clock signal, generating a voltage on the current stage output control node An.

[0056] In some embodiments, the second drive output submodule 122 is configured to output the gate drive signal of the current stage under the action of the voltage of the output control node An of the current stage and the voltage of the drive control node Qsn of the current stage.

[0057] For example, after the current stage drive control node Qsn is precharged, the second drive output submodule 122 will turn on after receiving the voltage of the current stage drive control node Qsn and the voltage on the current stage output control node An, thereby outputting the gate drive signal of the current stage to refresh the pixel.

[0058] In some embodiments, the discharge module 130 is further configured to pull down the output control node An of the current stage to a low potential under the voltage action of the drive control node Qsn+q of the n+q stage.

[0059] For example, when there is a voltage at the drive control node Qsn+q of the (n+q)th stage, it means that the clock signal of the (n+q)th stage may pass through the (n+q)th stage. At the same time, the output module 120 of the current stage may also receive a high-level signal through the clock signal line CKm of the current stage. When the discharge module 130 receives the voltage at the drive control node Qsn+q of the (n+q)th stage, it pulls down the output control node An of the current stage to a low potential. The second drive output submodule 122 will not be turned on, so that the gate drive signal of the current stage will not be output incorrectly, and the small high-level signal will not be transmitted through the stage, thus avoiding the occurrence of screen flicker.

[0060] In some embodiments, the stage transmission output submodule 123 is configured to output the stage transmission signal of the current stage under the action of the voltage of the current stage drive control node Qsn and the current stage clock signal.

[0061] For example, after the current stage's drive control node Qsn is precharged, when the current stage's clock signal arrives, the stage transmission submodule 123 outputs the current stage's transmission signal to perform stage transmission, which acts on the gate drive unit 100 of the adjacent stage.

[0062] In some embodiments, the stage output submodule 123 includes: a fifth transistor T5, a seventh transistor T7, and an eighth transistor T8. The control terminal of the fifth transistor T5 is connected to the drive control node Qsn of the current stage. The first terminal of the fifth transistor T5 is connected to the clock signal line CKm of the current stage. The second terminal of the fifth transistor T5 is connected to the control terminal of the seventh transistor T7, the first terminal of the seventh transistor T7, and the first terminal of the eighth transistor T8. The second terminal of the seventh transistor T7 is connected to the second terminal of the eighth transistor T8. The second terminal of the eighth transistor T8 serves as the stage output terminal.

[0063] For example, when there is a precharge voltage on the current stage's drive control node Qsn and the clock signal of the current stage arrives, the fifth transistor T5 will be turned on, outputting the current stage's transmission signal. At the same time, the current stage's transmission signal will also control the seventh transistor T7 and the eighth transistor T8 to be turned on, and output the current stage's transmission signal through the second terminal of the eighth transistor T8. By setting the seventh transistor T7 and the eighth transistor T8, when the fifth transistor T5 receives the clock signal during the non-drive period and turns on slightly, the transmission difficulty of the small high-level signal output by the fifth transistor T5 is increased, avoiding the accumulation of small high-level signals that cause screen flicker.

[0064] In some embodiments, the first drive output submodule 121 includes: a ninth transistor T9; the control terminal of the ninth transistor T9 is connected to the drive control node Qsn of the current stage, the first terminal of the ninth transistor T9 is connected to the clock signal line CKm of the current stage, and the second terminal of the ninth transistor T9 is connected to the output control node An of the current stage.

[0065] In some embodiments, the second drive output submodule 122 includes: a sixth transistor T6 and a bootstrap capacitor CC; the control terminal of the sixth transistor T6 is connected to the current stage drive control node Qsn and the first terminal of the bootstrap capacitor CC, the first terminal of the sixth transistor T6 is connected to the current stage output control node An, and the second terminal of the sixth transistor T6 is connected to the second terminal of the bootstrap capacitor CC and serves as the current stage drive control node Qsn.

[0066] For example, when the control terminal of the ninth transistor T9 receives the voltage of the current stage's drive control node Qsn, and the first terminal of the ninth transistor T9 receives the current stage's clock signal, the ninth transistor T9 will conduct, generating a voltage on the current stage's output control node An. Similarly, when the control terminal of the sixth transistor T6 receives the voltage on the current stage's drive control node Qsn, and the first terminal of the sixth transistor T6 receives the voltage on the current stage's output control node An, the sixth transistor T6 will conduct, outputting the current stage's gate drive signal. By setting the ninth transistor T9, when the (n+q)th stage's clock signal returns, the difficulty of turning on the sixth transistor T6 is increased, preventing the sixth transistor T6 from outputting a small high-level signal for stage transmission. Simultaneously, when the control terminal of the first transistor T1 receives the voltage on the (n+q)th stage's drive control node Qsn+q, and the first terminal of the first transistor T1 receives the stage transmission signal from the stage transmission output terminal, it will also conduct, pulling the current stage's output control node An down to a low potential, further preventing the sixth transistor T6 from being turned on by a small level signal.

[0067] In some embodiments, please refer to Figure 2 , Figure 5 and Figure 6As shown, the nth-stage gate drive unit 100 also includes a pull-down module 140, which includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13. The control terminal of the eleventh transistor T11, the control terminals of the twelfth transistor T12 and the thirteenth transistor T13 are connected to the stage transmission output terminal of the (n+j)th-stage output module 120. The first terminal of the eleventh transistor T11 is connected to the drive control node Qsn of the current stage. The second terminal of the eleventh transistor T11, the second terminal of the twelfth transistor T12 and the second terminal of the thirteenth transistor T13 are connected to the low-level terminal VSS. The first terminal of the twelfth transistor T12 is connected to the pull-up node Qn of the current stage. The first terminal of the thirteenth transistor T13 is connected to the drive output terminal of the current stage.

[0068] For example, j can be 3. When the control terminals of the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 receive the stage transmission signal of the (n+j)th stage, they will be turned on. The eleventh transistor T11 pulls down the drive control of the current stage to a low potential, the twelfth transistor T12 pulls down the pull-up node Qn of the current stage to a low potential, and the twelfth transistor T12 pulls down the drive output terminal of the current stage to a low potential, so as to ensure that the drive output terminal Gn of the current stage will no longer output the gate drive signal in the current frame scan signal. When the next frame scan signal arrives, the pull-up node Qn and the drive control node Qsn of the current stage can be charged again.

[0069] In some embodiments, a display panel is also provided, including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the aforementioned gate driving circuit. The output module 120 of the gate driving circuit is connected to at least one scan line.

[0070] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0071] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0072] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes N cascaded gate driving units, and the nth gate driving unit includes: The pull-up module, connected to the current stage's drive control node, is configured to charge the current stage's drive control node in response to the output signal of the ni-th stage's gate drive unit. The output module, connected to the drive control node and clock signal line of the current stage, is configured to output the stage transmission signal and the gate drive signal of the current stage under the action of the voltage on the drive control node and the clock signal of the current stage. The discharge module, connected to the drive control node of the (n+q)th stage and also connected to the stage transmission output terminal and / or drive output terminal of the output module, is configured to: pull down the stage transmission output terminal and / or drive output terminal of the current stage to a low potential under the voltage of the drive control node of the (n+q)th stage; where q represents the number of clock signal lines, and when there is voltage at the drive control node of the (n+q)th stage, the clock signal line of the current stage will receive a high-level signal; The discharge module includes: a first transistor; the control terminal of the first transistor is connected to the drive control node of the (n+q)th stage, the first terminal of the first transistor is connected to the stage transmission output terminal of the current stage and / or the drive output terminal of the current stage, and the second terminal of the first transistor is connected to a low-level terminal.

2. The gate driving circuit according to claim 1, characterized in that, The pull-up module includes: The precharge submodule, connected to the pull-up node of the current stage, is configured to charge the pull-up node of the current stage in response to the output signal of the gate drive unit of the nith stage. The switching submodule, which is connected to the drive control node of the ni-th stage, the clock signal line of the ni-th stage, the pull-up node of the current stage, and the drive control node of the current stage, is configured to control the pull-up node of the current stage to connect to the drive control node of the current stage under the action of the voltage of the drive control node of the ni-th stage and the clock signal of the ni-th stage.

3. The gate driving circuit according to claim 2, characterized in that, The switching submodule includes: a second transistor and a third transistor; The control terminal of the second transistor is connected to the clock signal line of the ni-th stage, the first terminal of the second transistor is connected to the drive control node of the ni-th stage, and the second terminal of the second transistor is connected to the control terminal of the third transistor. The first terminal of the third transistor is connected to the pull-up node of the current stage, and the second terminal of the third transistor is connected to the drive control node of the current stage.

4. The gate driving circuit according to claim 2, characterized in that, The pre-charge submodule includes: a fourth transistor; The control terminal of the fourth transistor is connected to the stage output terminal of the ni-th stage output module, the first terminal of the fourth transistor is connected to the drive output terminal of the ni-th stage output module, and the second terminal of the fourth transistor is connected to the pull-up node of the current stage.

5. The gate driving circuit according to claim 1, characterized in that, The output module includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a bootstrap capacitor; The control terminal of the fifth transistor, the control terminal of the sixth transistor, and the first terminal of the bootstrap capacitor are connected to the drive control node of the current stage. The first terminal of the fifth transistor is connected to the clock signal line of the current stage. The second terminal of the fifth transistor is connected to the control terminal of the seventh transistor, the first terminal of the seventh transistor, and the first terminal of the eighth transistor. The first terminal of the sixth transistor is connected to the clock signal line of the current stage, and the second terminal of the sixth transistor is connected to the second terminal of the bootstrap capacitor and serves as the drive output terminal of the current stage. The second terminal of the seventh transistor is connected to the control terminal of the eighth transistor; The second terminal of the eighth transistor serves as the stage output terminal of the current stage.

6. The gate driving circuit according to claim 1, characterized in that, The output module includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a bootstrap capacitor, a ninth transistor, and a tenth transistor; The control terminal of the fifth transistor, the control terminal of the sixth transistor, and the first terminal of the bootstrap capacitor are connected to the drive control node of the current stage. The first terminal of the fifth transistor is connected to the clock signal line of the current stage. The second terminal of the fifth transistor is connected to the control terminal of the seventh transistor, the second terminal of the seventh transistor, and the second terminal of the eighth transistor. The first terminal of the sixth transistor is connected to the clock signal line of the current stage, and the second terminal of the sixth transistor is connected to the second terminal of the bootstrap capacitor, the control terminal of the ninth transistor, the first terminal of the ninth transistor, and the first terminal of the tenth transistor. The second terminal of the seventh transistor is connected to the control terminal of the eighth transistor; The second terminal of the eighth transistor serves as the stage output terminal of the current stage; The second terminal of the ninth transistor is connected to the control terminal of the tenth transistor; The second terminal of the tenth transistor serves as the drive output terminal of the current stage.

7. The gate driving circuit according to claim 1, characterized in that, The output module includes: The first drive output submodule, connected to the clock signal line of the current stage, the drive control node of the current stage, and the output control node of the current stage, is configured to generate a voltage on the output control node of the current stage under the action of the voltage of the clock signal of the current stage and the voltage of the drive control node of the current stage. The second drive output submodule, connected to the output control node and the drive control node of the current stage, is configured to output the gate drive signal of the current stage under the action of the voltage of the output control node and the drive control node of the current stage. The discharge module is also connected to the output control node of the current stage and is configured to pull down the output control node of the current stage to a low potential under the voltage action of the drive control node of the (n+q)th stage.

8. The gate driving circuit according to claim 7, characterized in that, The first drive output submodule includes: a ninth transistor; The control terminal of the ninth transistor is connected to the drive control node of the current stage, the first terminal of the ninth transistor is connected to the clock signal line of the current stage, and the second terminal of the ninth transistor is connected to the output control node of the current stage.

9. The gate driving circuit according to claim 7, characterized in that, The second drive output submodule includes: a sixth transistor and a bootstrap capacitor; The control terminal of the sixth transistor is connected to the drive control node of the current stage and the first terminal of the bootstrap capacitor. The first terminal of the sixth transistor is connected to the output control node of the current stage. The second terminal of the sixth transistor is connected to the second terminal of the bootstrap capacitor and serves as the drive control node of the current stage.

10. A display panel comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-9, wherein the output module of the gate driving circuit is connected to at least one of the scan lines.

Images