A semiconductor device, a method for operating the semiconductor device, and a storage system

Abstract

This disclosure provides a semiconductor device, a method for operating the semiconductor device, and a storage system, applicable to the field of semiconductor technology. The semiconductor device includes a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array includes multiple memory banks, each including at least one memory block in a first type of programming state. The peripheral circuitry writes data from at least one first memory block to at least one second memory block, resulting in a second memory block in a second type of programming state. The first and second memory blocks are different memory blocks among the multiple memory blocks in the target memory bank, and the first memory block is the memory block in the first type of programming state. The process involves erasing the data from the first memory block until all memory blocks in the first type of programming state in the target memory bank have been erased once, thereby achieving wear leveling of the memory blocks in the memory bank.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method of operating the semiconductor device, and a storage system. Background Technology

[0002] Semiconductor devices, such as NAND semiconductor devices, contain multiple memory blocks. During their use, the memory blocks that are used more frequently are more prone to damage, which in turn affects the performance of the entire semiconductor device. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor device, a method for operating the semiconductor device, and a storage system.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, including: a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array includes multiple memory surfaces, each memory surface including multiple memory cells, and each memory cell including at least one memory block in a first type of programming state. The peripheral circuitry writes data from at least one first memory block to at least one second memory block, resulting in a second memory block in a second type of programming state. The first and second memory blocks are different memory blocks among multiple memory blocks in a target memory cell, and the first memory block is the memory block in the first type of programming state. The data in the first memory block is erased until all memory blocks in the target memory cell in the first type of programming state have been erased once.

[0005] In some possible implementations, the memory blocks in the first type of programmed state are those in the target memory that are in a programmed state between two adjacent data migration cycles. The memory blocks in the second type of programmed state are those that have undergone programming operations within one data migration cycle. One data migration cycle includes the duration for which all memory blocks in the first type of programmed state in the target memory are erased once.

[0006] In some possible implementations, the number of at least one first storage block is greater than the number of at least one second storage block. Alternatively, the number of at least one first storage block is equal to the number of at least one second storage block.

[0007] In some possible implementations, each memory bank includes a first type of memory block and a second type of memory block. The first type of memory blocks are in a programmed state, and the number of memory blocks in the target memory bank in the programmed state is equal to a first quantity. The programmed memory blocks include memory blocks in the first type of programmed state or memory blocks in the second type of programmed state. The second type of memory blocks are in an erased state, or are in an erased state after an erase operation. The number of memory blocks in the target memory bank in the erased state is equal to a second quantity.

[0008] In some possible implementations, the second type of storage block is also used to replace faulty storage blocks in the first type of storage block.

[0009] In some possible implementations, the peripheral circuitry is further configured to write data stored in the first memory bank into the second memory bank. The first memory bank is any one of a plurality of memory banks, and the number of faulty memory blocks in the first memory bank is greater than or equal to a first threshold. The second memory bank is any one of a plurality of memory banks, and the number of faulty memory blocks in the second memory bank is less than a second threshold.

[0010] In some possible implementations, each memory bank includes a first type of memory block and a second type of memory block, wherein the number of first type memory blocks is equal to a first quantity, and the number of second type memory blocks is equal to a second quantity. The first type of memory blocks are in a programmed state, and the second type of memory blocks are used to replace faulty memory blocks in the first type of memory blocks. A first threshold is greater than or equal to the second quantity, and a second threshold is less than the second quantity.

[0011] In some possible implementations, the peripheral circuitry is further configured to write data stored in the first memory bank into the second memory bank. The first memory bank is any one of a plurality of memory banks, and the number of erase cycles of the first memory bank is greater than a third threshold. The second memory bank is any one of a plurality of memory banks, and the number of erase cycles of the second memory bank is less than a fourth threshold. The number of erase cycles for a memory bank is the average number of erase cycles for the memory blocks within that memory bank, or the average number of erase cycles for the memory blocks in the erase state within that memory bank.

[0012] In some possible implementations, the peripheral circuitry is further configured to write data stored in the first memory bank into the third memory bank when the difference between the number of erases in the first memory bank and the number of erases in the second memory bank is greater than a fifth threshold. Here, the number of erases in a memory bank is the average number of erases of the memory blocks in the memory bank, or the average number of erases in a memory bank is the average number of erases of the memory blocks in the erase state. The first memory bank is any one of multiple memory banks with the highest number of erases, the second memory bank is any one of multiple memory banks with the lowest number of erases, and the third memory bank is any one of multiple memory banks and is different from the first memory bank.

[0013] In some possible implementations, the order in which storage blocks are written to data is positively correlated with the order in which storage blocks are erased between different data migration cycles. A data migration cycle includes the duration of erasing all storage blocks of the first type of programmed state in the target storage once.

[0014] In some possible implementations, each memory bank includes a first type of memory block and a second type of memory block. The first type of memory block is configured to perform a corresponding operation, and the second type of memory block is configured to replace a faulty memory block in the first type of memory block. The peripheral circuitry is also configured to control the first type of memory block in the target memory bank to perform the corresponding operation based on first address information. The first address information maps to the second type of memory block in the target memory bank.

[0015] In some possible implementations, the corresponding operation includes at least one of the following: data write operation, data read operation, data erase operation, or storage operation.

[0016] In some possible implementations, the first type of memory block is configured to perform memory operations. Specifically, the peripheral circuitry is configured to: receive a first operation instruction, which includes first address information and input data, wherein the first address information maps to a second type of memory block in the target memory; and, in response to the first operation instruction, obtain output data based on the first address information and the input data. The output data is the result of the operation between the input data and the data in the first type of memory block in the target memory.

[0017] In some possible implementations, the memory block in the target memory includes select lines, word lines, and memory strings. A memory string includes multiple transistors, with their drain and source lines alternately coupled, their gates coupled to the word lines, and the select line coupled to the gate line of a transistor at one end of the memory string. The first operation instruction also includes address information of the selected word line in the target memory block. The peripheral circuitry is specifically configured to: in response to the first operation instruction, based on the first address information, the address information of the selected word line, and the input data, input data to the select line in the target memory block, apply a read voltage to the selected word line, and apply an on-state voltage to the unselected word line to obtain output data. The output data is a current output from either the drain or source line. The on-state voltage is greater than the read voltage.

[0018] In some possible implementations, the peripheral circuitry is specifically configured to control a first type of memory block in the target memory to perform a corresponding operation based on first address information and second address information. The second address information maps to the starting memory block in the first type of memory block in the target memory.

[0019] In some possible implementations, the first type of memory block is configured to perform memory operations. The peripheral circuitry is specifically configured to: receive a second operation instruction, which includes first address information, second address information, and input data; and, in response to the second operation instruction, obtain output data based on the first address information, second address information, and input data. The output data is the result of the operation between the input data and the data in the first type of memory block in the target memory.

[0020] In some possible implementations, the memory block in the target memory includes select lines, word lines, and memory strings. A memory string includes multiple transistors, with the drain and source lines of the transistors alternately coupled, the gates of the transistors coupled to the word lines, and the select line coupled to the gate line of a transistor at one end of the memory string. The second operation instruction also includes address information of the selected word line in the target memory block. The peripheral circuitry is specifically configured to: respond to the second operation instruction, based on the first address information, the second address information, the address information of the selected word line, and the input data, input data to the select line in the target memory block, apply a read voltage to the selected word line, and apply a conduction voltage to the unselected word line to obtain output data. The output data is a current output from the drain or source line. The conduction voltage is greater than the read voltage.

[0021] Secondly, embodiments of this disclosure provide an operation method for a semiconductor device, comprising: writing data from at least one first memory block to at least one second memory block to obtain a second memory block in a second type of programming state. The first memory block and the second memory block are different memory blocks among a plurality of memory blocks in a target memory bank, and the first memory block is a memory block in a first type of programming state. The method further comprises: erasing the data in the first memory block until all memory blocks in the target memory bank in the first type of programming state have been erased once.

[0022] In some possible implementations, the method further includes writing data stored in a first storage bank into a second storage bank. The first storage bank is any one of a plurality of storage banks, and the number of faulty storage blocks in the first storage bank is greater than or equal to a first threshold. The second storage bank is any one of a plurality of storage banks, and the number of faulty storage blocks in the second storage bank is less than a second threshold.

[0023] In some possible implementations, the operation method further includes: writing data stored in a first storage bank into a second storage bank. The first storage bank is any one of a plurality of storage banks, and the number of erase cycles of the first storage bank is greater than a third threshold. The second storage bank is any one of a plurality of storage banks, and the number of erase cycles of the second storage bank is less than a fourth threshold. Wherein, the number of erase cycles of a storage bank is the average number of erase cycles of storage blocks within the storage bank, or the number of erase cycles of a storage bank is the average number of erase cycles of storage blocks in an erased state within the storage bank.

[0024] In some possible implementations, the operation method further includes: when the difference between the number of erases of the first memory bank and the number of erases of the second memory bank is greater than a fifth threshold, writing the data stored in the first memory bank into the third memory bank. Here, the number of erases of the memory bank is the average number of erases of the memory blocks in the memory bank, or the number of erases of the memory bank is the average number of erases of the memory blocks in the erase state in the memory bank. The first memory bank is any one of multiple memory banks and has the highest number of erases; the second memory bank is any one of multiple memory banks and has the lowest number of erases; the third memory bank is any one of multiple memory banks and is different from the first memory bank.

[0025] In some possible implementations, the operation method further includes: controlling a first type of storage block in the target memory to perform a corresponding operation based on the first address information. The first address information maps to a second type of storage block in the target memory.

[0026] In some possible implementations, based on the first address information, control a first type of storage block in the target memory to perform a corresponding operation. This includes: receiving a first operation instruction, the first operation instruction including the first address information and input data, the first address information mapping to a second type of storage block in the target memory; and, in response to the first operation instruction, obtaining output data based on the first address information and the input data. The output data is the result of the operation between the input data and the data in the first type of storage block in the target memory.

[0027] In some possible implementations, in response to a first operation instruction, output data is obtained based on first address information and input data, including: in response to the first operation instruction, inputting input data to a selection line in the target memory block, applying a read voltage to the selected word line, and applying an on-state voltage to an unselected word line, based on the first address information, the address information of the selected word line, and the input data, to obtain output data. The output data is a current output from the drain line or the source line. The on-state voltage is greater than the read voltage.

[0028] In some possible implementations, based on the first address information, the system controls a first type of storage block in the target memory to perform a corresponding operation. This includes controlling the first type of storage block in the target memory to perform a corresponding operation based on the first address information and the second address information. The second address information maps to a starting storage block within the first type of storage block in the target memory.

[0029] In some possible implementations, based on the first address information and the second address information, controlling a first type of storage block in the target memory to perform a corresponding operation includes: receiving a second operation instruction, the second operation instruction including the first address information, the second address information, and input data. In response to the second operation instruction, output data is obtained based on the first address information, the second address information, and the input data. The output data is the result of the operation between the input data and the data in the first type of storage block in the target memory.

[0030] In some possible implementations, in response to a second operation instruction, output data is obtained based on first address information, second address information, and input data. This includes: in response to the second operation instruction, inputting input data to a selection line in the target memory block, applying a read voltage to the selected word line, and applying an on-state voltage to an unselected word line, based on the first address information, second address information, address information of the selected word line, and input data, to obtain output data. The output data is a current output from the drain line or source line. The on-state voltage is greater than the read voltage.

[0031] Thirdly, embodiments of this disclosure provide a storage system including processing circuitry and any of the semiconductor devices described in the first aspect, wherein the processing circuitry and the semiconductor device are coupled together.

[0032] In some possible implementations, the processing circuit is configured to: send a third operation instruction, the third operation instruction including third address information and fourth address information, the third address information mapping to at least one first memory block, and the fourth address information mapping to at least one second memory block, wherein the first memory block is a memory block in a first type of programming state. The semiconductor device is configured to: write data from at least one first memory block to at least one second memory block, resulting in a second memory block in a second type of programming state. The first memory block and the second memory block are different memory blocks among a plurality of memory blocks in the target memory. And to erase the data in the first memory block until all memory blocks in the target memory in the first type of programming state have been erased once.

[0033] In some possible implementations, the processing circuitry is configured to: acquire management information of storage blocks in each of a plurality of memory banks, wherein a storage block in a memory bank comprises multiple pages, and one of the pages stores management information. The management information is used to indicate whether a storage block is a faulty storage block. Data stored in a first memory bank is written to a second memory bank. The first memory bank is any one of the plurality of memory banks, and the number of faulty storage blocks in the first memory bank is greater than or equal to a first threshold. The second memory bank is any one of the plurality of memory banks, and the number of faulty storage blocks in the second memory bank is less than a second threshold.

[0034] In some possible implementations, when the management information is 0xFF, it indicates that the current storage block is a faulty storage block.

[0035] Fourthly, embodiments of this disclosure provide an electronic device, the electronic device including a host and any of the storage systems described in the third aspect, the host and the storage system being coupled together.

[0036] Fifthly, embodiments of this disclosure provide an electronic device, the electronic device including a host and any of the semiconductor devices of the first aspect, the host and the semiconductor device being coupled together.

[0037] In a sixth aspect, embodiments of this disclosure provide a computer storage medium, the computer-readable storage medium including instructions. When the instructions are executed on a processor, they cause the processor to perform the operation method of any semiconductor device of the second aspect. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0039] Figure 1 This is a schematic diagram of the structure of an electronic device according to some embodiments. Figure 1 ;

[0040] Figure 2 This is a schematic diagram of the structure of an electronic device according to some embodiments. Figure 2 ;

[0041] Figure 3 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 1 ;

[0042] Figure 4 This is a schematic diagram of the structure of an electronic device according to some embodiments. Figure 3 ;

[0043] Figure 5 This is a schematic diagram of the structure of a memory card according to some embodiments;

[0044] Figure 6 This is a schematic diagram of the structure of a solid-state drive according to some embodiments;

[0045] Figure 7 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 2 ;

[0046] Figure 8This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 3 ;

[0047] Figure 9 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 4 ;

[0048] Figure 10 This is a schematic cross-sectional view of the structure of a memory string in a semiconductor device according to some embodiments;

[0049] Figure 11 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 5 ;

[0050] Figure 12 This is a schematic diagram of the structure of an electronic device according to some embodiments. Figure 4 ;

[0051] Figure 13 This is an illustration of a bad block management method according to some embodiments. Figure 1 ;

[0052] Figure 14 This is an illustration of a bad block management method according to some embodiments. Figure 2 ;

[0053] Figure 15 This is an illustration of a bad block management method according to some embodiments. Figure 3 ;

[0054] Figure 16 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 6 ;

[0055] Figure 17 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 7 ;

[0056] Figure 18 This is a schematic diagram of a threshold voltage distribution according to some embodiments;

[0057] Figure 19 This is an illustration of a bad block management method according to some embodiments. Figure 4 ;

[0058] Figure 20 This is an illustration of a bad block management method according to some embodiments. Figure 5 ;

[0059] Figure 21 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 8 ;

[0060] Figure 22 This is a flowchart illustrating an operation method according to some embodiments. Figure 1 ;

[0061] Figure 23 This is a schematic diagram of the structure of a memory computing device according to some embodiments. Figure 1 ;

[0062] Figure 24 This is a schematic diagram of the structure of a memory computing device according to some embodiments. Figure 2 ;

[0063] Figure 25 This is a schematic diagram of the structure of a memory computing device according to some embodiments. Figure 3 ;

[0064] Figure 26 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Figure 9 ;

[0065] Figure 27 This is a flowchart illustrating an operation method according to some embodiments. Figure 2 ;

[0066] Figure 28 This is a flowchart illustrating an operation method according to some embodiments. Figure 3 ;

[0067] Figure 29 This is a schematic diagram of the structure of a memory according to some embodiments. Figure 1 ;

[0068] Figure 30 This is a schematic diagram of the structure of a memory according to some embodiments. Figure 2 ;

[0069] Figure 31 This is a flowchart illustrating a data migration operation according to some embodiments. Figure 1 ;

[0070] Figure 32 This is a flowchart illustrating a data migration operation according to some embodiments. Figure 2 ;

[0071] Figure 33 This is a flowchart illustrating a data migration operation according to some embodiments. Figure 3 ;

[0072] Figure 34 This is a flowchart illustrating a data migration operation according to some embodiments. Figure 4 ;

[0073] Figure 35 This is a flowchart illustrating a data migration operation according to some embodiments. Figure 5 ;

[0074] Figure 36 This is a flowchart illustrating a data migration operation according to some embodiments. Figure 6 ;

[0075] Figure 37 This is a flowchart illustrating a data migration operation according to some embodiments. Figure 7 ;

[0076] Figure 38 This is a flowchart illustrating a data migration operation according to some embodiments. Figure 8 ;

[0077] Figure 39 This is a flowchart illustrating an operation method according to some embodiments. Figure 4 ;

[0078] Figure 40 This is a flowchart illustrating an operation method according to some embodiments. Figure 5 ;

[0079] Figure 41 This is a flowchart illustrating an operation method according to some embodiments. Figure 6 ;

[0080] Figure 42 This is a flowchart illustrating an operation method according to some embodiments. Figure 7 ;

[0081] Figure 43 This is a flowchart illustrating an operation method according to some embodiments. Figure 8 ;

[0082] Figure 44 This is a flowchart illustrating an operation method according to some embodiments. Figure 9 ;

[0083] Figure 45 This is a flowchart illustrating an operation method according to some embodiments. Figure 10 . Detailed Implementation

[0084] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0085] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0086] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0087] In describing some embodiments, the terms "coupled," "connected," and "linked," and their derivatives, may be used. For example, the term "linked" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0088] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0089] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0090] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0091] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0092] This disclosure is not limited to three-dimensional (3D) NAND semiconductor devices, although 3D NAND semiconductor devices may be used in some examples for illustration. For example, the techniques disclosed herein can be applied to planar NAND semiconductor devices and NOR semiconductor devices, etc.

[0093] Figure 1 A structural diagram of an electronic device 10 having semiconductor devices is shown according to some aspects. The electronic device 10 can be a mobile phone (e.g., a cell phone), desktop computer, tablet computer, laptop computer, server, in-vehicle device, game console, printer, positioning device, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, power bank, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0094] like Figure 1 As shown, the electronic device 10 includes a storage system 102 and a host 104. The storage system 102 includes one or more semiconductor devices 1022 and a processing circuit 1024, with the processing circuit 1024 coupled to the semiconductor devices 1022. The processing circuit 1024 can be a controller.

[0095] The host 104 can be a processor of the electronic device 10. For example, the processor can be a chip, specifically a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a micro controller unit (MCU), a programmable logic device (PLD), an application processor (AP), or other integrated chips.

[0096] In some possible implementations, such as Figure 2 A structural diagram of an electronic device 20 having semiconductor devices is shown according to some aspects, such as Figure 2As shown, the electronic device 20 includes a host 204 and a semiconductor device 202, which are coupled together.

[0097] like Figure 3 A schematic diagram of the structure of a semiconductor device is shown, such as... Figure 3 As shown, the semiconductor device 202 includes a processing circuit 2022 and a storage device 2024, which are coupled together.

[0098] The processing circuit 2022 includes a controller 20221, a converter 20222, and a processor 20223. The converter 20222 can be a digital-to-analog converter (DAC) or an analog-to-digital converter (ADC). The processor 20223 can be, but is not limited to, any of the following: a central processing unit (CPU), a graphics processing unit (GPU), and a neural network processing unit (NPU).

[0099] The storage device 2024 includes peripheral circuitry 20241 and a memory cell array 20242, which are coupled together.

[0100] In some possible implementations, such as Figure 4 A structural diagram of an electronic device 30 having semiconductor devices is shown according to some aspects, such as Figure 4 As shown, the electronic device 30 includes a host 304 and a semiconductor device 1022, which are coupled together. Figure 4 The host 304 shown integrates, for example Figure 1 The function of the processing circuit 1024 in the storage system 102 shown.

[0101] This embodiment uses, as follows Figure 1 The following explanation will be based on the electronic device 10 shown.

[0102] According to some embodiments, processing circuitry 1024 is coupled to semiconductor device 1022 and host 104 and is configured to control semiconductor device 1022. Processing circuitry 1024 can manage data stored in semiconductor device 1022 and communicate with host 104. In some embodiments, processing circuitry 1024 is designed to operate in a low duty cycle environment, such as secure digital (SD) cards, compact flash cards (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, processing circuitry 1024 is designed to operate in a high duty cycle environment, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which are used as data storage devices for mobile electronic devices such as smartphones, tablets, personal computers, etc., and for enterprise storage arrays.

[0103] The processing circuit 1024 can be configured to manage data stored in the semiconductor device 1022 and communicate with external devices (e.g., host 104). It controls the semiconductor device 1022 to perform corresponding operations, such as data reading, data erasing, and programming operations.

[0104] In some implementations, the processing circuitry 1024 is also configured to process error correction codes (ECCs) related to data read from or written to the semiconductor device 1022.

[0105] The processing circuit 1024 can also perform any other suitable functions, such as formatting the semiconductor device 1022. The processing circuit 1024 can communicate with external devices (e.g., host 104) according to a specific communication protocol. For example, the processing circuit 1024 can communicate with external devices through at least one of various interface protocols, such as USB, Multimedia Card (MMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0106] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0107] The processing circuitry 1024 and one or more semiconductor devices 1022 can be integrated into various types of storage systems 102, for example, included in the same package, such as an embedded multimedia card (eMMC), universal flash storage (UFS) package, embedded multi-chip package (eMCP) package, or UFS-based multi-chip package (uMCP) package. eMMC uses a unified MMC standard interface, encapsulating high-density NAND and the MMC controller in a ball grid array (BGA) package chip. UFS is an advanced version of eMMC, also an array-type storage module composed of multiple flash memory chips and a controller. UFS overcomes the limitation of eMMC, which only supports half-duplex operation (read and write operations must be performed separately), enabling full-duplex operation and thus doubling performance. eMCP is a package that incorporates volatile memory, such as static random-access memory (SRAM) or dynamic random-access memory (DRAM), on an eMMC.

[0108] In a practical implementation, the DRAM can be low-power double-data-rate synchronous dynamic random-access memory (LPDDR). uMCP is a packaged form of UFS with volatile memory (such as SRAM or DRAM) mounted on it, offering high performance and large capacity. In a practical implementation, the DRAM can be LPDDR. That is to say, the storage system 102 can be implemented and packaged into different types of end electronic devices.

[0109] In such Figure 5 In one example shown, processing circuitry 1024 and a single semiconductor device 1022 can be integrated into memory card 400. Memory card 400 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 400 may also include components for connecting memory card 400 to a host computer (e.g.,...). Figure 1 The memory card connector 410 is coupled to the host 104.

[0110] In such Figure 6In another example shown, processing circuitry 1024 and multiple semiconductor devices 1022 can be integrated into the SSD 500. The SSD 500 may also include a connection between the SSD 500 and a host (e.g.,...). Figure 1 The SSD connector 510 is coupled to the host 104. In some implementations, the storage capacity and / or operating speed of the SSD 500 is higher than that of the memory card 400.

[0111] Figure 7 A schematic circuit diagram of an exemplary semiconductor device 600, including peripheral circuitry 602, is shown according to some aspects of this disclosure. The semiconductor device 600 may be... Figure 1 An example of semiconductor device 1022 is shown. Semiconductor device 600 may include a memory cell array 601 and peripheral circuitry 602 coupled to the memory cell array 601. The memory cell array 601 may be a NAND flash memory cell array, wherein memory cells 606 are provided in the form of an array of NAND memory strings 608 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 608 includes a plurality of memory cells 606 coupled in series and stacked vertically. Each memory cell 606 is capable of holding a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 606. Each memory cell 606 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0112] In some implementations, each storage cell 606 is a single-level cell (SLC) with two possible storage states (levels) and thus capable of storing one bit of data. Specifically, each storage cell 606 can be configured to store 2... N One of the storage states (levels) stores N bits of data, where N is a natural number greater than 0. This 2 N The storage states include erase state and 2. N-1 non-erasable state. In some implementations, each memory cell 606 is a single-level cell (SLC) having two possible storage states (levels) and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a threshold voltage in a first range, and a second storage state "1" may correspond to a threshold voltage in a second range. In some implementations, each memory cell 606 is an xLC capable of storing more than one bit of data in four or more storage states (levels). For example, an xLC is capable of storing two bits per cell (multi-level cell, MLC), three bits per cell (triple-level cell, TLC), or four bits per cell (quad-level cell, QLC). Each xLC can be programmed to assume a range of possible nominal storage values. In one example, an MLC can be programmed from an erase state to assume one of three possible programming levels by writing one of three possible nominal storage values ​​(e.g., 01, 10, and 11) into memory cell 606. A fourth nominal storage value can be used for the erase state (e.g., 00).

[0113] like Figure 7 As shown, each NAND flash memory string 608 may further include a source select gate (SSG) transistor 610 at its source end and a drain select gate (DSG) transistor 612 at its drain end. The SSG transistor 610 and DSG transistor 612 can be configured to activate the selected NAND flash memory string 608 (column of the array) during read and program operations. In some embodiments, the sources of the NAND flash memory strings 608 in the same block 604 are coupled via the same source line (SL) 614 (e.g., common SL). In other words, according to some embodiments, all NAND flash memory strings 608 in the same block 604 have an array common source (ACS). According to some embodiments, the drain of each NAND flash memory string 608 is coupled to a corresponding bit line 616, enabling data to be read from or written to the corresponding bit line 616 via an output bus (not shown). In some implementations, each NAND memory string 608 is configured to be selected or deselected by applying a selection or deselection voltage to the gate of the corresponding DSG transistor 612 via one or more DSG lines 613 and / or by applying a selection or deselection voltage to the gate of the corresponding SSG transistor 610 via one or more SSG lines 615.

[0114] like Figure 7As shown, NAND memory strings 608 can be organized into multiple memory blocks 604, each of which may have a common source line 614, for example, coupled to the ACS. In some embodiments, each memory block 604 is the basic data unit for erase operations, i.e., all memory cells 606 on the same memory block 604 are erased simultaneously. To erase memory cells 606 in a selected memory block 604, the source lines 614 coupled to the selected memory block 604 and unselected memory blocks 604 in the same plane as the selected memory block 604 can be biased with an erase voltage (Vers), such as a high positive bias voltage (e.g., 20V or higher). Memory cells 606 of adjacent NAND memory strings 608 can be coupled via word lines (WL) 618, which selects which row of memory cells 606 is affected by read and program operations.

[0115] like Figure 7 As shown, the memory cell array 601 may include an array of memory cells 606 in multiple rows and columns within each memory block 604. According to some embodiments, one column of memory cells corresponds to one NAND memory string 608. Multiple rows of memory cells 606 may be coupled to word lines 618, and multiple columns of memory cells 606 may be coupled to bit lines 616.

[0116] like Figure 8 As shown, the memory cell array 601 may include a P memory plane (memory plane 0, memory plane 1, ..., memory plane P), where the memory plane is the smallest unit for integrating the memory cell array 601 in the manufacturing process. Each memory plane includes multiple memory blocks 604 (memory block 0, memory block 1, memory block 2, memory block 3, ..., memory block Q).

[0117] like Figure 9 This disclosure illustrates, according to some aspects, a three-dimensional (3D) semiconductor device 600 comprising multiple stacked layers. For example... Figure 9 As shown, the semiconductor device 600 includes multiple memory strings 608 and n layers of memory cells (including WL0, WL1, WL2, ..., WLn-1, WLn-2, ​​WLn-1). The multiple memory strings 608 included in the semiconductor device 600 are arranged in a direction parallel to the bearing surface of the substrate, and the multiple memory cells in each memory string 608 are arranged in a direction perpendicular to the bearing surface of the substrate. That is, the multiple memory cells included in the semiconductor device 600 are arranged in a three-dimensional array on the substrate, forming a memory cell array.

[0118] One end of the memory string 608 is connected to bit lines 616 (including BL0, BL2, ..., BLm-1), and the other end is connected to a common source line (CSL) or an array common source (ACS). The BSGs of the memory string 608 can be coupled to the same CSL or to different CSLs (e.g., ...). Figure 9 As shown, CSL0, ..., CSLm-1), there are no restrictions here.

[0119] The memory cells 606 in each memory string 608 are also connected to memory cells 606 in other memory strings via word lines 618. For example, if each memory string 608 may include 64 memory cells 606, then the 3D semiconductor device may include 64 word lines 618WL<63:0>, and each word line 618 is connected to a portion of the memory cells 606 located on the same layer (i.e., having the same height relative to the substrate). It should be noted that the 64 memory cells 606 are only a specific example, and the application is not limited to this.

[0120] In some embodiments, each memory string 608 may include more than 64 memory cells 606, such as 128, 196, etc. In the 3D semiconductor device 600, each memory cell 606 connected to the same word line 618 is called a memory page, and all memory strings 608 sharing a set of word lines 618 are called a memory block.

[0121] The memory string 608 also includes an upper select transistor connected to the drain of the first memory cell 606 and a lower select transistor connected to the source of the last memory cell 606. The upper select transistors are also called top select gates (TSGs) or DSG transistors, and include TSG0, TSG1, TSG2, and TSG3. The lower select transistors are also called bottom select gates (BSGs) or SSG transistors.

[0122] The gate of the TSG is connected to the drain select line (DSL), the source of the TSG is connected to the drain of the first memory cell 606, and the drain of the TSG is connected to the bit line 616.

[0123] The gate of the BSG is connected to the source select line (SSL), the drain of the BSG is connected to the source of the last memory cell 606, and the source of the BSG is connected to the source line.

[0124] Depend on Figure 9It is understood that the memory cells 606 in the memory string 608 share a set of word lines 618 with the memory cells 606 in other memory strings 608. Assuming each memory string 608 includes m+1 memory cells 606, the 3D semiconductor device can include m+1 word lines (WL): WL0 to WLm, where m is an integer greater than 1. Each WL is connected to each memory cell 606 located on the same layer (i.e., having the same height relative to the substrate's bearing surface). Alternatively, it can be understood that the control gates of each memory cell 606 located on the same layer, and the gate connection lines between each control gate, constitute a word line 618.

[0125] Figure 10 This is a schematic cross-sectional view of a memory string 608 according to an embodiment of this application. The memory string 608 includes a plurality of memory cells 606 disposed in the Z direction. Each memory cell 606 may have the same physical structure. Optionally, the memory cell 606 may be a charge-trapping memory cell. For example, the memory cell 606 may include a gate 606-G, a charge-blocking layer 310, a charge-trapping layer 320, a tunnel layer 330, and a channel layer 340 (such as a poly-Si channel). The tunnel layer 330 is located between the charge-trapping layer 320 and the channel layer 340.

[0126] In some embodiments, the charge trapping layer 320 may be made of, for example, silicon nitride. The tunneling layer 330 may be made of silicon oxide, silicon oxynitride, or any combination thereof. The charge blocking layer 310 may be made of silicon oxide, silicon oxynitride, a high dielectric constant dielectric, or any combination thereof.

[0127] In some implementations, word line 618 may be physically connected to the gate 606-G of memory cell 606 on memory string 608, and word line 618 may also be physically connected to the gate of memory cell 606 in other memory strings (not shown) at the same height (e.g., in the Z direction) or at approximately the same height.

[0128] When programming the memory cell 606, the charge trapping layer 320 can trap the charge H from the channel layer 340 and through the tunneling layer 330 under the voltage control of the gate 606-G according to the tunneling effect. Depending on the amount of charge H in the charge trapping layer 320 of the memory cell 606, the memory cell 606 can have different threshold voltages, and thus be in different programming states.

[0129] The charge H stored in the charge trapping layer 320 is isolated from other charge trapping layers 320 corresponding to different word lines 618, thus suppressing the longitudinal diffusion of charge H in the charge trapping layer 320 along the direction perpendicular to the substrate (not shown in the figure) (Z direction). Suppression of charge diffusion facilitates the formation of a uniform potential field at the charge trapping layer 320, thereby improving the storage reliability of the charge trapping layer 320 and consequently enhancing the retention characteristics of the semiconductor device 600.

[0130] The number of threshold voltage ranges that storage cell 606 can reach is related to the size of the data stored in storage cell 606. For example, storage cell 606 can be one of the following: SLC capable of reaching 2 threshold voltage ranges and storing 1 bit of data, MLC capable of reaching 4 threshold voltage ranges and storing 2 bits of data, TLC capable of reaching 8 threshold voltage ranges and storing 8 bits of data, or QLC capable of reaching 16 threshold voltage ranges and storing 16 bits of data. The peripheral circuit 602 uses the threshold voltage level of storage cell 606 to determine the data being read.

[0131] Return to reference Figure 7 The peripheral circuitry 602 can be coupled to the memory cell array 601 via bit line (BL) 616, word line 618, source line 614, SSG line 615, and DSG line 613. The peripheral circuitry 602 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 601 by applying and sensing voltage and / or current signals to and from each target memory cell 606 via bit line 616, word line 618, source line 614, SSG line 615, and DSG line 613. The peripheral circuitry 602 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0132] For example, Figure 11 Some exemplary peripheral circuitry is shown, including a page buffer / sensor amplifier 704, a column decoder / bit line driver 706, a row decoder / word line driver 708, a voltage generator 710, a control logic unit 712, a register 714, an interface (I / F) circuit 716, and a data bus 718. It should be understood that additional peripheral circuitry may be included. Figure 11 Additional peripheral circuitry not shown.

[0133] Page buffer / sensor amplifier 704 can be configured to read and program (write) data from and to memory cell array 601 according to control signals from control logic unit 712. In one example, page buffer / sensor amplifier 704 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 606 coupled to selected word line 618. In yet another example, page buffer / sensor amplifier 704 can also sense a low-power signal representing a data bit stored in memory cell 606 from bit line 616 during a read operation and amplify a small voltage swing to a recognizable logic level. As detailed below and consistent with the scope of this disclosure, during a programming operation, page buffer / sensor amplifier 704 may include a memory module (e.g., latch, cache, register, etc.) for temporarily storing a segment of N bits of data received from data bus 718 and using 2 N -2 N In each programming pass of the multi-pass programming operation, the N-bit data segment is provided to the corresponding target storage unit 606 via the corresponding bit line 616.

[0134] The column decoder / bit line driver 706 can be configured to be controlled by the control logic unit 712 and to select one or more NAND memory strings 608 by applying bit line voltages generated by the voltage generator 710. The row decoder / word line driver 708 can be configured to be controlled by the control logic unit 712 and to select / deselect memory blocks 604 of the memory cell array 601 and to select / deselect word lines 618 of the memory blocks 604. The row decoder / word line driver 708 can also be configured to drive word lines 618 using word line voltages generated by the voltage generator 710. In some embodiments, the row decoder / word line driver 708 can also select / deselect and drive SSG lines 615 and DSG lines 613. The voltage generator 710 can be configured to be controlled by the control logic unit 712 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, and verification voltage, etc.), bit line voltages, and source line voltages to be provided to the memory cell array 601.

[0135] Control logic unit 712 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 714 can be coupled to control logic unit 712 and includes a status register, a command register, and an address register for storing status information, command operation code (OP), and command address for controlling the operation of each peripheral circuit. Interface circuitry 716 can be coupled to control logic unit 712 and acts as a control buffer to buffer data from the host (e.g., ...). Figure 1The host 2000 receives control commands and forwards them to the control logic unit 712, and buffers the status information received from the control logic unit 712 and forwards it to the host. The interface circuit 716 can also be coupled to the column decoder / bit line driver 706 via the data bus 718, and acts as a data input / output (I / O) interface and data buffer to buffer and forward data to and from the memory cell array 601.

[0136] In practical applications, during the manufacturing and subsequent use of NAND semiconductor devices, in order to ensure their stable and reliable operation, the processing circuit 1024 can also be configured to manage various functions related to the data stored or to be stored in the semiconductor device 1022, including but not limited to bad block management, garbage collection (GC), logic-to-physical address translation, wear leveling, etc.

[0137] like Figure 12 As shown, a firmware system, a Flash Translation Layer (FTL) 10242, can be implemented in the processing circuit 1024. The performance, reliability, and durability of the storage system 102 (such as an SSD) depend on the implementation of the FTL 10242 algorithm. Currently, the FTL 10242 can include functional modules such as address mapping, garbage collection, wear leveling, bad block management, and power-loss recovery. The processing circuit 1024 also includes a host interface circuit 10244 and a semiconductor device interface circuit 10246. The host interface circuit 10244 is used to couple the host 104 and the FTL 10242. The semiconductor device interface circuit 10246 is used to couple the FTL 10242 and the semiconductor devices 1022. The semiconductor device interface circuit 10246 includes multiple semiconductor devices 1022 (such as semiconductor device 0, semiconductor device 1, semiconductor device 2, ..., semiconductor device N, etc.).

[0138] Due to the erase-before-write characteristic of semiconductor devices, such as NAND flash memory, data written to the same logical address cannot be modified based on the original physical address of the stored data. Instead, the updated data must be written to a new physical address. Therefore, the FTL 10242 needs to maintain a mapping table between logical addresses and physical addresses, continuously recording the mapping relationship between the logical addresses accessed by the host and the physical addresses in the NAND flash memory. For updated data, the data at the original physical address becomes invalid. This invalid data still occupies the storage space of the NAND flash memory. If this invalid data is not processed, the storage space of the NAND flash memory will be quickly exhausted. To address this, the FTL 10242 performs another important function: garbage collection.

[0139] Garbage data is randomly distributed across each storage block in a NAND semiconductor device, rather than concentrated in a few blocks. To improve garbage collection efficiency, blocks with less valid data or more invalid data can be selected for collection. Because there is less valid data, less data needs to be moved, thus freeing up storage blocks quickly and at a lower cost.

[0140] Specifically, for NAND semiconductor devices, the basic unit of erasure is a memory block. A memory block contains multiple physical addresses. Before garbage collection, the data in the addresses storing valid data in the selected memory block (such as the source block) needs to be moved to other free memory blocks (target blocks). Then, the source block is erased.

[0141] For example, a storage block that has been erased or is in a free state after an erase operation can be marked as a free block, which can then be used to perform corresponding operations, such as programming operations on the free block.

[0142] Furthermore, because the number of programmable / erase cycles a NAND flash memory block can withstand is limited, each block has a certain lifespan. If data write and erase operations are concentrated on certain blocks, these blocks will quickly become damaged, reducing the available space in the NAND. When the available space drops to a certain threshold, the NAND flash memory is considered damaged. To extend the lifespan of NAND flash memory, the FTL 10242 needs to evenly distribute data writes and erases across all memory blocks—a process known as wear leveling. Even with wear leveling algorithms, some memory blocks will eventually become damaged as they wear down. Damaged blocks can be replaced with good blocks from the over-provision (OP) space within the NAND flash memory, or damaged blocks can be skipped during data writes—this process is known as bad block management.

[0143] Bad block management includes managing factory bad blocks (FBB) and grown bad blocks (GBB).

[0144] Factory-marked bad blocks are those produced during the manufacturing process of NAND semiconductor devices due to limitations in the manufacturing process or accidental factors. These bad blocks are identified and marked during production. When using NAND semiconductor devices, the markings within the blocks are first scanned to identify the manufacturer-marked bad blocks, generating a bad block table (BBT). Subsequent use will not allow the selection of blocks from the bad block table to prevent data errors or loss at the user's end.

[0145] Growing bad blocks, unlike factory-installed bad blocks, gradually form during the normal use of NAND semiconductor devices. This is mainly due to the physical wear and tear on the memory cells caused by frequent erase and write operations, leading to data read / write / erase errors. The appearance of these bad blocks is an inherent characteristic of NAND semiconductor device technology and requires dynamic inspection and management through the BBT mechanism. When a memory block is detected to have become a bad block, it can no longer be selected for use, and the memory block is recorded in the BBT.

[0146] In some examples, as semiconductor devices are used and worn out, some good storage blocks may become faulty storage blocks during use. The main scenarios are as follows: (1) When performing a data erase operation, the erase operation fails. (2) When performing a data write operation, the data write operation fails. (3) When performing a data read operation, if there are too many data errors exceeding the ECC range, and various error checking and correction methods, such as read retry, low-density parity check (LDPC), or redundant array of independent disks (RAID), still fail to correct the errors. When any of the above three scenarios occur, the current storage block is considered a faulty storage block, recorded in the BBT, and will no longer be selected for corresponding operations.

[0147] Bad block management includes two strategies: skipping and replacing.

[0148] The skip strategy allows users to skip bad blocks registered in the table and write the next storage block when they encounter them during data write operations, based on the established BBT (Block Barrier).

[0149] Figure 13The diagram illustrates four semiconductor devices (semiconductor device 0, semiconductor device 1, semiconductor device 2, and semiconductor device 3) in the storage system 102. Data is sequentially written to each of these four devices. When selecting a parallel storage block, each semiconductor device selects the same block number. According to the user's bad block table, if storage block 0 of semiconductor device 0 is a bad block, it is not added to the parallel storage block strip. Instead, storage blocks 0 of semiconductor device 1, semiconductor device 2, and semiconductor device 3 are grouped into a parallel block strip.

[0150] The skip strategy skips bad blocks and does not use the semiconductor device where the bad block is located. Instead, it uses the semiconductor device where the remaining good memory blocks are located to build parallel blocks.

[0151] The advantage of the skip strategy is its simplicity in management; bad blocks can be skipped. Its disadvantage is performance instability. If N semiconductor devices operate concurrently, the system's parallelism will fluctuate between 1 and N, and performance cannot be guaranteed to remain stable with N concurrent chips.

[0152] Unlike the skip strategy, the replacement strategy divides the memory blocks in each die into a main block and an extra block. The extra block replaces a faulty block in the main block. When a bad block is found on a die, the replacement strategy replaces the faulty block in the main block with a good block from the extra block in that die. In other words, under the replacement strategy, upon encountering a faulty block, it searches for another available free block in the extra block of the current die and writes it to the replacement block, rather than skipping the die.

[0153] For example, Figure 14 The diagram illustrates four semiconductor devices (semiconductor device 0, semiconductor device 1, semiconductor device 2, and semiconductor device 3) in the storage system 102. Data is sequentially written to each of these four devices. If storage block 3 of semiconductor device 0 is faulty, it is replaced with storage block 0 (or storage block 1) from the redundant storage blocks in semiconductor device 0. Then, storage blocks 0 of semiconductor device 0, 3 of semiconductor device 1, 3 of semiconductor device 2, and 3 of semiconductor device 3 are arranged into parallel blocks.

[0154] For example Figure 15 As shown, the faulty storage block (black block) in the main storage block is replaced with a storage block from the redundant storage block (the block filled with diagonal stripes in the figure).

[0155] The replacement strategy demonstrates significant advantages in ensuring the simultaneous operation of N dies and improving performance stability. Furthermore, this strategy's supplementary operations for FBB / GBB are not constrained by physical addresses, allowing for flexible mapping of redundant memory blocks to any location in the logical address space to quickly replace damaged memory blocks.

[0156] However, while the replacement strategy is flexible, when the physical address of the faulty memory block is far from the physical address of the memory block used for replacement, the long power supply wiring path will introduce additional voltage drop due to the parasitic resistance of the semiconductor device, making the voltage drop more severe and significantly aggravating the voltage drop (IR Drop) problem, thus affecting the performance of the NAND semiconductor device.

[0157] Voltage drop, an unavoidable voltage loss phenomenon when current flows through resistance, is particularly critical in NAND semiconductor devices. Especially during large-scale data read, write, or erase operations, current demand surges and varies with the location of the memory cells in the array due to the changing parasitic resistance. For cells at the far ends of the array, this results in significant voltage drops in the internal metal wires, transistors, and other components due to the resistive effect. This voltage drop not only affects the voltage stability of different regions within the NAND semiconductor device but can also directly weaken the overall performance and functional reliability of the chip. For example, insufficient voltage during data read, write, or erase operations can lead to unsuccessful operations.

[0158] Furthermore, there is a close relationship between the specific location of memory blocks in NAND semiconductor devices and voltage drop. Due to differences in the physical layout of memory blocks at different locations, particularly variations in the length of additional wiring, current distribution and resistance effects occur, causing each memory block to be affected by voltage drops to varying degrees. This differential voltage drop effect can ultimately manifest as a decrease in memory block read / write performance and fluctuations in stability.

[0159] To solve one or more of the above problems, one can address issues such as... Figure 8 The structure of the storage cell array 601 shown is improved, such as... Figure 16 As shown, M storage blocks in the storage plane are configured into multiple storage banks. At the storage bank level, each storage bank includes a first number of first-type storage blocks and a second number of second-type storage blocks. The first-type storage blocks can be working storage blocks (or main storage blocks), and the second-type storage blocks can be redundant storage blocks. The second-type storage blocks can be used to replace faulty storage blocks in the first-type storage blocks.

[0160] For example, each storage bank includes m+n (e.g., n for a first number and m for a second number) storage blocks. Any n (i.e., the first number) of these m+n blocks are used as working blocks. When performing operations (e.g., write operations, read operations, erase operations, or storage operations) at the storage bank level, n blocks are selected from each storage bank to perform the corresponding operation. Any m (i.e., the second number) of these m+n blocks are used as redundant blocks to replace faulty blocks in the storage bank, ensuring that each storage bank has at least n normal blocks used as working blocks to perform the corresponding operation. If the number of normal blocks in a storage bank is less than n, the storage bank will be marked as faulty and will not be used for corresponding data operations.

[0161] like Figure 17 As shown, the memory cell array 601 contains P memory planes (memory plane 0, memory plane 1, memory plane 2, memory plane 3, ..., memory plane P). Each memory plane includes multiple memory banks (memory bank 0, memory bank 1, memory bank 2, ..., memory bank M). Each memory bank includes multiple TSGs (TSG0, TSG1, TSG2, TSG3, ..., TSGN). Each TSG is coupled to the gate line 1302 of the select transistor on the memory string 608. TSG slits 1304 are formed between the TSGs to cut off (or isolate) the TSGs. Gate line slits 1306 are formed adjacent to the TSGs to cut off (or isolate) the metal layer corresponding to the gate line of the select transistor on the memory string 608 in the memory cell array 601.

[0162] For example, the TSG can be a coarse TSG. Each memory bank can include 16KB of bit lines (BL).

[0163] To limit the relative physical address span between storage blocks within the same storage bank, the design ensures that the physical distance between any two storage blocks in the m+n storage blocks of each storage bank is less than a threshold. It also ensures that the difference between the physical address of any faulty storage block and the physical address of any normal storage block within the same storage bank is less than a threshold.

[0164] In the scheme disclosed in this application, it is not necessary to specify which m redundant memory blocks or n primary memory blocks are which m redundant memory blocks in each memory bank. During use, only n normal memory blocks are selected from the (n+m) memory blocks in each memory bank to perform the corresponding operations. By distributing redundant memory blocks across each memory bank, the relative physical address span between memory blocks within the same memory bank is smaller and relatively fixed, which reduces variations in current distribution and resistance effects, resulting in a more convergent threshold voltage (Vt) distribution.

[0165] like Figure 18 Any two programming states are shown, where the dashed line indicates the threshold voltage distribution before implementing this scheme, and the solid line indicates the threshold voltage distribution after implementing this scheme.

[0166] As can be seen, the solution disclosed in this application improves the read / write performance, stability, and reliability of memory blocks by reducing the impact of voltage drop on their read / write performance. Simultaneously, since the n working memory blocks are selected from the m+n memory blocks, the corresponding data operations are relatively evenly distributed across the n memory blocks within the m+n memory blocks, thereby achieving wear leveling and extending the lifespan of the semiconductor device.

[0167] For example Figure 16 In some scenarios, the probability of bad blocks being generated in the semiconductor device 600 may be relatively small, and the probability of bad blocks being generated in multiple memory banks is even smaller. If m redundant memory blocks are configured for each memory bank, it may lead to low utilization of the semiconductor device's storage space and high hardware material costs.

[0168] To improve storage space utilization efficiency and reduce hardware material costs, some possible implementations include... Figure 19 As shown, the storage cell array 601 can be configured such that at least two storage banks share m redundant storage blocks (m is greater than or equal to 1). Any redundant storage block among the m redundant storage blocks can only be used to replace a faulty storage block in one storage bank at a time.

[0169] In some examples, such as Figure 20 As shown, the storage cell array 601 can be configured with four storage banks sharing m redundant storage blocks. Each storage bank includes n primary storage blocks.

[0170] To accurately determine the relative physical location of redundant storage blocks (bank-level extra blocks) at the bank level, and to prevent the selection of redundant storage blocks across banks to replace faulty storage blocks, address decoding (X-Dec) employs a two-level decoding method at the bank-level and block-level.

[0171] like Figure 21 A schematic diagram of a semiconductor device is shown. In the semiconductor device 600, the peripheral circuit 602 includes a memory bank decoding circuit 6022, a memory block decoding circuit 6024, and a memory block enable circuit 6026, which are coupled sequentially. The memory cell array 601 can be, for example,... Figure 16 The storage cell array 601 is shown.

[0172] based on Figure 21 The semiconductor device 600 shown can realize, for example Figure 22 The operation method shown includes steps S110-S120:

[0173] S110. Send an operation instruction, which includes address information. The address information is used to determine the target memory bank among multiple memory banks and the first number of working memory blocks in the target memory bank.

[0174] In some possible examples, the operation instructions can be as follows: Figure 1 , Figure 5 and Figure 6 The processing circuit 1024 in the middle sends or such Figure 4 The host 304 sends, semiconductor devices (such as Figure 1 , Figure 4 , Figure 5 and Figure 6 (Showing a semiconductor device) receives operation commands.

[0175] In some examples, the address information may include A0-Am and Am+1-An. A0-Am is used to determine the location of the target memory bank, i.e., the address of the selected memory bank. The memory bank decoding circuit 6022 parses the address A0-Am of the selected memory bank. Am+1-An is used to determine the location of the working memory block in the target memory bank, i.e., the address of the selected memory block. The memory block decoding circuit 6024 parses the address Am+1-An of the selected memory block to ensure that the selected memory block is a memory block in the same memory bank, avoiding the selection of memory blocks across memory banks.

[0176] The memory bank decoding circuit 6022 receives address signals A0-Am and selects one or more memory banks for access based on these address signals. It also sends a selected memory bank enable signal to the memory block decoding circuit 6024. When the selected memory bank enable signal is activated, it allows corresponding operations to be performed on the data within the memory bank.

[0177] The memory block decoding circuit 6024 receives the address signal Am+1-An, selects a specific memory block within the selected memory bank according to the address signal, and activates the selected memory block by sending an enable signal to the selected memory block in the memory cell array 601 through the memory block enable circuit 6026. For example, if memory bank 0 is selected (e.g., ... Figure 16 The selected memory block is memory block 0 (or memory block Q), but memory bank M (as shown) will not be selected. Figure 16 Storage block 0 (or storage block Q) shown in the figure.

[0178] exist Figure 21 In this context, selecting a memory bank and a memory block indicates that, based on the control of the aforementioned memory bank decoding circuit 6022, memory block decoding circuit 6024, and memory block enable circuit 6026, as well as the enable signal, specific memory banks and memory blocks are selected. These selected memory banks and memory blocks can then perform corresponding data operations (such as data reading, data writing, data erasure, and storage operations). Not selecting a memory bank or memory block indicates that, without a corresponding enable signal, they will remain inactive and will not participate in the execution of corresponding data operations.

[0179] S120. In response to the operation command, perform the corresponding operation on the working storage block.

[0180] In some examples, the corresponding operations may include, but are not limited to, writing storage data to the target storage, reading storage data from the target storage, and erasing storage data in the target storage.

[0181] like Figure 16 , Figure 17 and Figure 21 The semiconductor devices in the corresponding embodiments, and such as Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 11 The semiconductor device in the corresponding implementation method is as follows Figure 16 , Figure 17 and Figure 21 The corresponding implementation method can be applied to in-memory computing devices.

[0182] Most current computing platforms are based on the von Neumann architecture. The von Neumann architecture is computation-centric, separating the computing and storage modules, which work together to perform data processing and access. However, because the computing module (such as the processor, which can be located in the processing circuit 1024 or the host 104, not shown in the diagram) is designed primarily to improve computing speed, while the storage module focuses more on capacity expansion and cost optimization, a performance mismatch between "storage" and "computing" leads to problems such as low memory access bandwidth, latency, and high power consumption—commonly known as the "memory wall" and "power wall." The more intensive the memory access, the more severe the "wall" problem becomes, and the more difficult it is to improve computing power. With the rapid rise of memory-intensive applications, such as convolutional neural networks (CNNs) and recurrent neural networks (RNNs), memory access latency and power consumption cannot be ignored, making a transformation of the computing architecture particularly urgent.

[0183] Compute-in-memory (CIM) architecture, as a new computing architecture, fully integrates storage and computation, effectively overcoming the bottlenecks of the von Neumann architecture and achieving orders-of-magnitude improvements in computing energy efficiency. In CIM, the distinction between storage and computation units is eliminated during chip design, truly achieving in-memory and computational convergence. Essentially, CIM utilizes the physical characteristics of different storage media to redesign storage circuits, enabling them to simultaneously possess computational and storage capabilities, directly eliminating the boundaries between "storage" and "computing," thus achieving orders-of-magnitude improvements in computing energy efficiency. Figure 23 A structural diagram of a memory computing device 800 is shown. The memory computing device 800 includes a memory computing array 801 and peripheral circuitry 802, which are coupled together. The memory computing array 801 is configured to store weight matrix data. The memory computing array includes memory computing units arranged in rows and columns. These units can perform various computational operations, such as matrix operations and vector operations, according to a preset algorithm.

[0184] Compared to the von Neumann architecture, in-memory computing has advantages such as faster computing speed, lower power consumption, and higher integration density. In-memory computing integrates computing functions into storage units, reducing the frequent data transfer between data storage modules and computing modules, and also reducing data transmission latency. In addition, in-memory computing integrates computing and storage functions on the same chip, reducing the need for external connections and wiring, resulting in higher chip integration and the ability to be applied to smaller and thinner electronic devices.

[0185] Artificial intelligence algorithms, exemplified by neural networks, involve various tensor and vector computations, with matrix-vector multiplication being the most representative operator. These operators typically feature large data volumes, high computational demands, and high parallelism requirements. In Von Neumann architecture-based computing platforms, processors executing AI algorithms suffer from significant power consumption and latency overhead due to the separation of storage and computation, resulting in data transfer power consumption far exceeding computational power consumption. This has become a bottleneck in the development of Von Neumann architecture accelerators. The core idea of ​​in-memory computing technology is to integrate memory and computation. By storing relatively fixed weight matrix data in memory and inputting feature vectors into an array, matrix-vector multiplication can be performed internally. This effectively avoids the large-scale transfer of weight data while achieving highly parallel data access and computation, thereby improving both computational speed and energy efficiency. Therefore, in-memory computing is highly suitable for accelerating matrix and vector operations in AI algorithms.

[0186] In some examples, the memory array 801 can be used to perform matrix-vector multiplication operations as shown in equation (1), where V IN0 V IN1 ,…,V INN This represents the computational data (or input vector) input to the computing array 801. Taking image recognition applications as an example, the computational data can be image feature information. 00 ,w 01 ,…,w 0M w 10 ,w 11 ,…,w 1M …, w N0 ,w N1 ,…,w NM Equations (2), (3), and (4) represent the weight matrix data stored in the memory array 801. The weight matrix data is composed of weight data (e.g., for flash memory, NAND or NOR can be characterized by the threshold voltage of the memory cell. For RRAM memory, it can be characterized by the conductance of the memory cell. This embodiment uses NAND as an example for explanation). Equations (2), (3), and (4) are used to represent the results of the operation of multiplying and accumulating the operation data with the weight matrix data.

[0187]

[0188] I D0 =V IN0 *w 00 +V IN1 *w 10 +…+V INN *w N0 Equation (2)

[0189] ID1 =V IN0 *w 01 +V IN1 *w 11 +…+V INN *wN1 Equation (3)

[0190] …

[0191] I DM =V IN0 *w 0M +V IN1 *w 1M +…+V INN *w NM Equation (4)

[0192] Figure 24 An example of matrix-vector operations performed when the semiconductor device 600 is used as a memory computing device 800 is shown, as in equations (5)-(9):

[0193]

[0194] I D0 =V IN0 *w 00 +V IN1 *w 10 +V IN2 *w 20 Equation (6)

[0195] I D1 =V IN1 *w 01 +V IN1 *w 10 +V IN1 *w 20 Equation (7)

[0196] I D2 =V IN0 *w 01 +V IN1 *w 11 +V IN2 *w 21 Equation (8)

[0197] I D2 =V IN0 *w 02 +V IN1 *w 12 +…+V IN2 *w 22 Equation (9)

[0198] Among them, the weight data w 00 ,w 01 ,w02 ;w 10 ,w 11 ,w 12 ;w 20 ,w 21 ,w 22 The process of writing to the semiconductor device 600 is completely consistent with the programming process of the memory cell array 601. The operation data (or input vector) V IN0 V IN1 V IN2 Input the gates of TSG0, TSG1, and TSG2 respectively, and process the data (output data or output vector) I. D0 I D1 I D2 Output from bit lines BL0, BL1, and BL2 respectively.

[0199] like Figure 25 This illustrates a basic principle of stored-data computation, such as... Figure 25 As shown, the storage cell array 601 shows seven word lines WL: WL0, WL1, WL2, WL3, WL4, WL5, and WL6, and eight storage strings (str): storage string 0 (str0), storage string 1 (str1), storage string 2 (str2), storage string 3 (str3), storage string 4 (str4), storage string 5 (str5), storage string 6 (str6), and storage string 7 (str7).

[0200] Storage cells can be configured as SLC, MLC, TLC, and QLC storage cells, but are not limited to. This example uses an SLC storage cell configured to store weighted array data. Each storage cell can have two states: erase state E or programmable state P. Erasure state E can indicate that the data stored in the current storage cell is 1, denoted as E(1). Programmable state P can indicate that the data stored in the current storage cell is 0, denoted as P(0).

[0201] Table 1 shows the relationship between the input computation data (Vin), the weight data in the memory cell (i.e., the threshold voltage Vth of the memory cell), and the output computation results (such as bit line current, BL current) of the memory cell array 601.

[0202] Table 1

[0203] 1 E(1) 1 1 P(0) 0 0 E(1) 0 0 P(0) 0

[0204] During in-memory computing operations, a read voltage Vrd is applied to the selected word line WL (programming word line, where the memory cells store weighted data) to activate the weighted data stored in the memory cells coupled to the selected word line WL. An on-state voltage Vpass is applied to the other WLs. An input voltage (operation data or input vector) is applied to the top selection gate TSG. The output current is collected at the BL or SL terminal. After collecting the output currents of all memory cells, addition is performed by accumulating the currents.

[0205] For example, such as Figure 25 As shown, taking the weighted data stored in the storage unit of word line WL3 as E(1), P(0), E(1), P(0), E(1), E(1), P(0), P(0) as an example. If... Figure 25 The word line WL3 of the memory array 801 shown is given a read voltage Vrd, and an input voltage V is given on the top select gate TSG. IN0 =1, V IN1＝1 V IN2 =0, V IN3＝0 V IN4 =1, V IN5 =1, V IN6 =1, V IN7 =1, then:

[0206] I D0 =1*E(1)+1*P(0)+1*E(1)+1*P(0)+1*E(1)+1*E(1)+1*P(0)+1*P(0)

[0207] Therefore, during vector matrix multiplication and addition operations in the in-memory computing device, the operation in the memory cell array 601 is equivalent to applying voltage and reading current. In the current I... D0 Storage strings 0, 4, and 5 contributed the current.

[0208] In in-memory computing devices, even minute voltage fluctuations can cause deviations in calculation results, especially in high-precision in-memory computing scenarios. Given the stringent accuracy requirements of in-memory computing on voltage drop (IR Drop), methods such as... Figure 16 , Figure 17 and Figure 21 The semiconductor device in the corresponding implementation is applied in a memory computing device to reduce the impact of voltage drop on the accuracy of in-memory computing.

[0209] like Figure 21In the schematic diagram of the semiconductor device shown, if the memory blocks in semiconductor device 600 are used for normal storage operations (such as data writing, data reading, or data erasure), only one memory block needs to be selected for operation at a time. However, if the memory blocks in semiconductor device 600 are used for in-memory computation operations, multiple memory blocks need to be selected each time (because the amount of computation data that a memory block can receive is limited). Therefore, the address of the selected memory block includes the addresses of multiple memory blocks, and the memory block decoding circuit 6024 needs to perform multiple decoding operations, outputting multiple high-level memory block enable signals to activate the selected memory block. Therefore, when the memory blocks in semiconductor device 600 are used for in-memory computation operations, the circuit requirements are complex, the operation is inconvenient, and the power consumption is high.

[0210] To reduce circuit complexity and power consumption and facilitate operation, this disclosure provides for the following: Figure 21 The circuit shown has been improved, such as Figure 26 As shown. Figure 26 In the semiconductor device 600 shown, an XOR logic circuit 6028 is added to reduce circuit complexity and power consumption. The inverse selection operation of the XOR logic circuit 6028 enables flexible selection of multiple memory blocks. Specifically, an in-memory computing enable signal controls whether the memory blocks perform normal storage operations or in-memory computing operations.

[0211] In some possible implementations, taking the address information including the address of the target memory and the addresses of a second number of redundant memory blocks as an example, such as... Figure 26 The semiconductor device 600 shown can realize, for example Figure 27 The method for operating a semiconductor device, as shown, includes the following steps S121-S124:

[0212] S121. The memory decoding circuit outputs the first enable signal according to the address of the target memory.

[0213] For example, the memory decoding circuit 6022 outputs a first enable signal (i.e., a selected memory address: A0-Am) based on the address of the target memory (i.e., the selected memory address: A0-Am).

[0214] S122. The memory block decoding circuit outputs a second enable signal based on the address of the second number of redundant memory blocks and the first enable signal.

[0215] S123, the XOR logic circuit receives the third enable signal and outputs the fourth enable signal based on the second and third enable signals.

[0216] In some examples, the fourth enable signal is the XOR result of the second and third enable signals. The third enable signal can be carried in the operation instruction and can be derived from, for example, Figure 1 , Figure 5 or Figure 6 The processing circuit 1024 shown or as... Figure 2 and Figure 3 The semiconductor device 202 shown or as Figure 4 The host 304, processing circuit 1024, semiconductor device 202, or host 304 shown can control the high and low levels of the third enable signal to control, for example... Figure 26 The semiconductor device 600 shown performs different operations (data writing, data reading, data erasure, or in-memory calculation).

[0217] In one example, if the third enable signal is low, the memory block performs normal storage operations. At this time, the memory block decoding circuit 6024 outputs a high-level enable signal to the selected memory block. After passing through the XOR logic circuit 6028, the XOR logic circuit 6028 outputs a high level, and the selected memory block is activated for normal storage operations (data writing, data reading, or data erasure).

[0218] For example, the operation instructions may include a sixth enable signal (an enable signal when the third enable signal is low). The sixth enable signal indicates that the target memory is configured to perform a data storage operation. The data storage operation may include, but is not limited to, writing stored data to the target memory, reading stored data from the target memory, and erasing stored data from the target memory.

[0219] In another example, if the third enable signal is high, the XOR logic circuit 6028 performs an inverse selection operation, and the memory block performs storage and computation operations. At this time, the memory block decoding circuit 6024 outputs a high-level enable signal to the selected memory block. After passing through the XOR logic circuit 6028, the XOR logic circuit 6028 outputs a low level, the selected memory block is in an inactive state, and the unselected memory blocks are in an active state for storage and computation operations.

[0220] For example, the operation instructions also include a seventh enable signal (an enable signal when the third enable signal is high). The seventh enable signal is used to indicate that the target memory is configured to perform in-memory computation. Figure 23 , Figure 24 and Figure 25 In the illustrated implementation, the peripheral circuit 802 responds to an operation command by inputting computation data into a first number of working memory blocks to obtain a computation result. The computation result is the result of the computation data and the data stored in the working memory blocks.

[0221] In the above embodiment, both the second and third enable signals are high. After passing through the XOR logic circuit 6028, the fourth enable signal output by the XOR logic circuit 6028 is low. The selected second number of redundant memory blocks (which may include faulty memory blocks) are in an inactive state, while the unselected first number of working memory blocks are in an active state to perform corresponding operations. The number of the second number of redundant memory blocks is less than the number of the first number of working memory blocks. This is simplified by the inverse selection operation of the XOR logic circuit 6028. Figure 26 The control logic of the semiconductor device 600 shown.

[0222] S124. The memory block enable circuit outputs a fifth enable signal to the first number of working memory blocks according to the fourth enable signal. The fifth enable signal is used to select the first number of working memory blocks.

[0223] For example, such as Figure 24 and Figure 25 As shown, the working memory block includes a select line (such as TSG) and a memory string. The memory string includes multiple transistors, with their drain and source lines alternately coupled. The select line is coupled to the gate line of a transistor at one end of the memory string. External circuitry responds to operation commands by inputting computational data (such as V) to the select line in the working memory block. IN0 =1, V IN1＝1 V IN2 =0, V IN3＝0 V IN4 =1, V IN5 =1, V IN6 =1, V IN7 =1), to obtain the calculation result, such as:

[0224] I D0 =1*E(1)+1*P(0)+1*E(1)+1*P(0)+1*E(1)+1*E(1)+1*P(0)+1*P(0).

[0225] In the above embodiments, such as Figure 26 The semiconductor device 600 shown can simplify its circuit structure and control logic, reduce power consumption, and enable flexible selection of multiple memory banks through the inverse selection operation of the XOR logic circuit 6028.

[0226] Although Figure 23 , Figure 24 or Figure 25The in-memory computing device shown can distribute redundant memory blocks into each memory bank. The relative physical address span between memory blocks in the same memory bank is small and relatively fixed, which can reduce the variation of current distribution and resistance effect, and make the threshold voltage (Vt) distribution more convergent, thereby improving the read and write performance, stability and reliability of memory blocks.

[0227] However, when the memory cell 606 in the semiconductor device 600 is not accessed for a long time, such as Figure 10 As shown, the charge on its charge trapping layer 320 may gradually decrease due to leakage. Due to the influence of charge leakage and other physical factors, the data retention capability of the semiconductor device 600 will gradually decrease, causing the threshold voltage of the storage cell 606 to change, thereby affecting the accuracy, stability and reliability of the data.

[0228] To maintain data stability and reliability, the data in the storage unit needs to be updated or refreshed periodically to recharge and restore its original threshold voltage.

[0229] Due to the erase-before-write characteristic of semiconductor devices, such as NAND semiconductor devices, when writing data to the same logical address, the original physical address of the stored data cannot be modified; instead, a new physical address must be found to write the updated data.

[0230] For updated data, the data at the original physical address becomes invalid. If this invalid data is not processed, the NAND semiconductor device's storage space will be quickly exhausted. To address this, the FTL 10242 performs garbage collection to free up storage space.

[0231] Therefore, when updating data in the storage bank, the data to be updated needs to be migrated or moved to a new physical address first, and then garbage collection is performed to erase the data at the original physical address.

[0232] However, for such Figure 23 , Figure 24 or Figure 25 The in-memory computing device shown performs computational operations at the bank level during in-memory computing operations and erases data at the block level during garbage collection operations. Because the granularity of computational operations and garbage collection operations are mismatched, uneven wear of the blocks within the bank may occur.

[0233] In order to solve the problem in such Figure 23 , Figure 24 or Figure 25The in-memory computing device shown may suffer from uneven wear of storage blocks within the storage bank due to a mismatch between the granularity of computation operations and the granularity of garbage collection operations. This disclosure provides an operating method that avoids uneven wear of different storage blocks during garbage collection by rotating and migrating the data stored in multiple storage blocks within the storage bank. Figure 28 As shown, the operation method specifically includes steps S210-S230:

[0234] S210, Send the third operation command.

[0235] S220, in response to the third operation instruction, write data from at least one first storage block to at least one second storage block, thereby obtaining a second storage block in a second type of programming state, while the first storage block is in a first type of programming state.

[0236] S230. Erase the data in the first storage block until all storage blocks in the target storage that are in the first type of programming state have been erased once.

[0237] In some possible implementations, the third operation instruction can be derived from, for example... Figure 1 , Figure 5 or Figure 6 The processing circuit 1024 shown or as... Figure 4 The host 304 shown, or as... Figure 2 and Figure 3 The processing circuit 2022 in the semiconductor device 202 shown transmits.

[0238] Can be like Figure 1 , Figure 4 , Figure 5 , Figure 6 The semiconductor device 1022 shown, or as Figure 7 , Figure 8 , Figure 9 , Figure 11 , Figure 12 , Figure 16 , Figure 17 , Figure 21 , Figure 26 The semiconductor device 600 shown, or as... Figure 2 and Figure 3 The memory device 2024 in the semiconductor device 202 shown, or as Figure 23 The in-memory computing device 800 shown sends a third operation command.

[0239] Taking semiconductor device 600 as an example, such as Figure 16As shown, the semiconductor device 600 includes multiple memory surfaces, each memory surface includes multiple memory cells, and each memory cell includes multiple memory blocks. Each memory block includes a first number of first-type memory blocks and a second number of second-type memory blocks. The first-type memory blocks are in a programming state, and the second-type memory blocks are in an erase state, or, after an erase operation, are in an erase state.

[0240] In some examples, the first type of storage block is in a programmed state, and the programmed state storage block includes storage blocks in the first type of programmed state or storage blocks in the second type of programmed state.

[0241] For example, a storage block in the first type of programmed state is a storage block in the target memory that is in a programmed state between two adjacent data migration cycles. A storage block in the second type of programmed state is a storage block that has undergone programming operations within a data migration cycle. A data migration cycle includes the duration of erasing all storage blocks in the first type of programmed state in the target memory once. The target memory can be any one of a plurality of memory banks.

[0242] The third operation instruction includes third address information and fourth address information. The third address information maps to at least one first storage block, and the fourth address information maps to at least one second storage block. The first storage block is a storage block in a first type of programming state, and the first storage block and the second storage block are different storage blocks among multiple storage blocks of the target storage body.

[0243] In some possible implementations, the first quantity is greater than the second quantity. The second quantity can be one (e.g., ...). Figure 29 (as shown) or multiple (such as) Figure 30 As shown, taking the second quantity as two as an example.

[0244] In some examples, within a storage bank where data migration operations need to be performed, the first number of storage blocks in the programmed state is greater than the second number of storage blocks in the erased state. For example... Figure 29 As shown, the first number of first-type storage blocks in the storage bank include storage block 0, storage block 1, storage block 2, storage block 3, storage block 4, storage block 5, storage block 6, and storage block 7, and the second number of second-type storage blocks include storage block 8. Storage blocks 0, 1, 2, 3, 4, 5, 6, and 7 are in the first-type programmed state, while storage block 8 is in the erased state.

[0245] In other examples, Figure 30 A type of storage is shown, such as Figure 30 As shown, the first number of first-type storage blocks in the storage bank include storage block 0, storage block 1, storage block 2, storage block 3, storage block 4, storage block 5, storage block 6, and storage block 7. The second number of second-type storage blocks include storage block 8 and storage block 9. Among them, storage blocks 0, 1, 2, 3, 4, 5, 6, and 7 are in the first-type programmed state, while storage blocks 8 and 9 are in the erased state.

[0246] In one example, with Figure 29 Taking the storage bank shown as an example, for example... Figure 29 The data stored in the storage blocks within the storage bank shown is rotated and migrated. The third address information can map to any one of the storage blocks 0, 1, 2, 3, 4, 5, 6, and 7, and the fourth address information can map to storage block 8. When updating the data in storage blocks 0, 1, 2, 3, 4, 5, 6, and 7, in order to achieve wear leveling between different storage blocks, the data in each of these blocks can be migrated once.

[0247] In some possible implementations, the relationship between the number of at least one first storage block and the number of at least one second storage block includes at least two size relationships: one is that the number of at least one first storage block is equal to the number of at least one second storage block; the other is that the number of at least one first storage block is equal to the number of at least one second storage block.

[0248] In some examples, the number of at least one first storage block is equal to the number of at least one second storage block, that is, the number of storage blocks mapped by the third address information is greater than the number of storage blocks mapped by the fourth address information. For example, in a data migration cycle, the storage bank can perform garbage collection. When performing garbage collection, the storage space occupied by the valid data in the storage block is less than the storage space of the storage block. In this scenario, the valid data in multiple storage blocks can be migrated to a storage block in the erase state (or a storage block with free storage space).

[0249] In other examples, the number of at least one first storage block is equal to the number of at least one second storage block, that is, the number of storage blocks mapped by the third address information is equal to the number of storage blocks mapped by the fourth address information. Similarly, the storage space occupied by valid data in a storage block is equal to the total storage space of the storage block.

[0250] In some examples, taking the addition of storage block 8 and the release of storage block 7 in the first data migration cycle as an example, data rotation migration is performed, such as... Figure 31 As shown:

[0251] Step 1: Migrate the data in storage block 0 to storage block 8, and then erase the data in storage block 0.

[0252] Step 2: Migrate the data in storage block 1 to storage block 0, and then erase the data in storage block 1.

[0253] Step 3: Migrate the data in storage block 2 to storage block 1, and then erase the data in storage block 2.

[0254] Step 4: Migrate the data in storage block 3 to storage block 2, and then erase the data in storage block 3.

[0255] Step 5: Migrate the data in storage block 4 to storage block 3, and then erase the data in storage block 4.

[0256] Step 6: Migrate the data in storage block 5 to storage block 4, and then erase the data in storage block 5.

[0257] Step 7: Migrate the data in storage block 6 to storage block 5, and then erase the data in storage block 6.

[0258] Step 8: Migrate the data in storage block 7 to storage block 6, and then erase the data in storage block 7.

[0259] After the first data migration cycle ends, storage blocks 0, 1, 2, 3, 4, 5, 6, and 8 are in the programming state, while storage block 7 is in the erasure state, meaning that the space of storage block 7 is released.

[0260] In some possible embodiments, such as Figure 31 The storage bank shown is in the first type of programming state when the second data migration cycle is executed after the first data migration cycle is completed, while storage block 0, storage block 1, storage block 2, storage block 3, storage block 4, storage block 5, storage block 6 and storage block 8 are in the erase state.

[0261] In the second data migration cycle, a first-in, first-out (FIFO) strategy can be followed. This means that the order in which data is written to storage blocks and the order in which data is erased are positively correlated between different data migration cycles. For example, if data is written to (or migrated into) storage block 8 first in the first data migration cycle, then the data in storage block 8 will be updated (or migrated out) first in the next adjacent second data migration cycle. Specifically... Figure 32 As shown:

[0262] Step 1: Migrate the data in storage block 8 to storage block 7, and then erase the data in storage block 8.

[0263] Step 2: Migrate the data in storage block 0 to storage block 8, and then erase the data in storage block 0.

[0264] Step 3: Migrate the data in storage block 1 to storage block 0, and then erase the data in storage block 1.

[0265] Step 4: Migrate the data in storage block 2 to storage block 1, and then erase the data in storage block 2.

[0266] Step 5: Migrate the data in storage block 3 to storage block 2, and then erase the data in storage block 3.

[0267] Step 6: Migrate the data in storage block 4 to storage block 3, and then erase the data in storage block 4.

[0268] Step 7: Migrate the data in storage block 5 to storage block 4, and then erase the data in storage block 5.

[0269] Step 8: Migrate the data in storage block 6 to storage block 5, and then erase the data in storage block 6.

[0270] After the second data migration cycle ends, the space of storage block 6 is released.

[0271] In some possible implementations, data migration is performed on the data stored in the storage blocks within the storage bank during multiple data migration cycles, with the result as follows: Figure 33 As shown.

[0272] like Figure 31 , Figure 32 as well as Figure 33As shown, the data stored in the storage blocks within the storage bank is rotated and migrated. This means that each storage block has an equal chance to be selected for read and write operations, which helps maintain the stability and reliability of the system and ensures that all storage blocks are processed in a balanced manner, thereby achieving wear leveling of the storage blocks within the storage bank.

[0273] It should be noted that, as Figure 31 , Figure 32 as well as Figure 33 The process shown illustrates the rotation and migration of data stored in storage blocks within a storage bank, following a first-in, first-out (FIFO) strategy between different rotation cycles.

[0274] The FIFO (First-In, First-Out) strategy is relatively simple to implement, requiring no complex algorithms or data structures. This simplification helps reduce management costs and improve management efficiency. Furthermore, under the FIFO strategy, the block rotation order is predictable. This helps the system better plan and allocate resources. For example, the system can prepare data in advance based on the block rotation order, thereby improving data access speed. In addition, the FIFO strategy can avoid resource idleness and waste, ensuring that resources within the bank are fully utilized.

[0275] Using a FIFO (First-In, First-Out) strategy to rotate and migrate data stored in blocks within a storage bank is a preferred approach. However, achieving wear leveling is not limited to the FIFO strategy; it only requires that all blocks within the storage bank be rotated within a single rotation cycle. For example, such as... Figure 34 As shown:

[0276] Step 1: Migrate the data in storage block 0 to storage block 7, and then erase the data in storage block 0.

[0277] Step 2: Migrate the data in storage block 8 to storage block 0, and then erase the data in storage block 8.

[0278] Step 3: Migrate the data in storage block 1 to storage block 8, and then erase the data in storage block 1.

[0279] Step 4: Migrate the data in storage block 2 to storage block 1, and then erase the data in storage block 2.

[0280] Step 5: Migrate the data in storage block 3 to storage block 2, and then erase the data in storage block 3.

[0281] Step 6: Migrate the data in storage block 4 to storage block 3, and then erase the data in storage block 4.

[0282] Step 7: Migrate the data in storage block 5 to storage block 4, and then erase the data in storage block 5.

[0283] Step 8: Migrate the data in storage block 6 to storage block 5, and then erase the data in storage block 6.

[0284] In some possible implementations, during the round-robin migration of data in the storage blocks within the storage bank, the mapping relationship between the input data (or input vector) and the weight data storage location may change due to the change in data storage location.

[0285] In some examples, when performing such Figure 25 The in-memory computing operation shown may involve at least one of the following address information: Plane_add, Bank_add, WL_Add, Head_Add, Unsel_blk.

[0286] Where Plane_add: represents the address of the storage plane.

[0287] Bank_add: Represents the address of the storage bank, Bank.

[0288] WL_Add: Indicates the selected WL during in-memory computation.

[0289] Head_Add: Represents the address of the starting storage block in the programming state (a storage block used to input "input data / input vector" or store "weight data / weight vector").

[0290] Unsel_blk: Represents the address of a storage block that is in the erase state (a storage block where "input data / input vector" is not selected or "weight data / weight vector" is not stored).

[0291] In one example, such as Figure 35 As shown, after the data transfer of WL0 in storage block 0 is completed, the input data corresponding to WL0 in storage block 0 needs to be mapped to WL0 in storage block 8. Therefore, the input data that was originally mapped to the data of WL0 in storage block 0 needs to be adjusted to be mapped to the data of WL0 in storage block 8.

[0292] In another example, such as Figure 36As shown, after the data transfer of WL0 to WL3 in storage block 0 is completed, the input data corresponding to WL0 to WL3 in storage block 0 needs to be mapped to WL0 to WL3 in storage block 8. Therefore, the input data that was originally mapped to the data of WL0 to WL3 in storage block 0 needs to be adjusted to be mapped to the data of WL0 to WL3 in storage block 8.

[0293] In yet another example, when adjusting the mapping relationship during data rotation migration, it is not limited to... Figure 35 or Figure 36 Alternatively, the mapping relationship could be adjusted after all data in storage block 0 has been migrated to storage block 8.

[0294] For example, such as Figure 37 As shown, the addresses of the storage plane and the storage bank do not change, and WL does not change the weight data. Head_Add and Unsel_Add change, such as Head_Add changing from storage block 0 to storage block 8, and Unsel_blk changing from storage block 8 to storage block 7.

[0295] like Figure 28 Steps S210-S230, as shown, involve data migration operations completed within the same storage bank. However, in some scenarios, it may be necessary to migrate data from one storage bank to another, such as:

[0296] In the first scenario, if the number of faulty storage blocks in a storage bank exceeds a threshold, the storage bank is marked as a faulty storage bank and will not be used to perform corresponding operations. In this scenario, data migration between storage banks is triggered.

[0297] In some examples, such as Figure 29 Taking the memory bank shown as an example, such as Figure 38 As shown, when storage block 8 in storage bank A is a faulty storage block, since all redundant storage blocks in storage bank become faulty storage blocks, data migration between storage banks is triggered, and the data in storage bank A is migrated to storage bank B.

[0298] In the second scenario, when different storage banks are erased at different numbers and the difference in the number of erasures is greater than a threshold, in order to achieve wear leveling between different storage banks, data in storage banks with more erasures can be migrated to storage banks with fewer erasures.

[0299] In some examples, such as when data migration between storage banks is triggered if |ec_max – ec_min| >= ec_wl_limit (balance threshold), data migration between storage banks is triggered. The erase count (EC) of a storage bank is taken as the average EC of all blocks within the storage bank, or as the EC corresponding to a free-block that is currently being erased. ec_max represents the erase count of the storage bank with the maximum erase count, and ec_min represents the erase count of the storage bank with the minimum erase count.

[0300] In some possible implementations, when the first scenario is met, data migration between different storage banks is triggered, such as... Figure 39 As shown, the specific steps include S310-S320:

[0301] S310. Obtain the management information of the storage blocks in each of the multiple storage banks.

[0302] In some examples, a storage block within a memory bank comprises multiple pages, one of which contains management information. This management information indicates whether the storage block is a faulty block.

[0303] In some examples, a management information of 0xFF indicates that the current storage block is a faulty storage block.

[0304] S320. When the management information meets the first preset condition, the data stored in the first storage is written into the second storage.

[0305] In some examples, the first storage bank and the second storage bank are either any of a plurality of storage banks and the first storage bank and the second storage bank are different. The first preset condition can be that the number of faulty storage blocks in the first storage bank is greater than or equal to a first threshold and the number of faulty storage blocks in the second storage bank is less than a second threshold.

[0306] In some examples, each memory bank includes a first number of first-type memory blocks and a second number of second-type memory blocks. The first number of first-type memory blocks are in a programmed state, and the second number of second-type memory blocks are used to replace faulty memory blocks in the first number of first-type memory blocks. For instance, a first threshold is greater than or equal to the second number, and a second threshold is less than the second number, thus satisfying the conditions in the first scenario. The first and second thresholds can be the same or different, and their specific values ​​can be determined according to actual needs; no limitation is made here.

[0307] In some possible implementations, when the second scenario is met, data migration between different storage banks is triggered, such as... Figure 40 As shown, the specific steps include S410-S430:

[0308] S410. Obtain the erase information of the storage blocks in each of the multiple storage banks.

[0309] In some examples, the erase information may include the number of erases of the memory bank, wherein the number of erases of the memory bank is the average number of erases of the memory blocks in the memory bank, or the number of erases of the memory bank is the average number of erases of the memory blocks in the memory bank that are in the erase state.

[0310] S420. When the erase information meets the second preset condition, the data stored in the first storage is written into the second storage.

[0311] In some examples, the first and second memory banks are either any of a plurality of memory banks, and the first and second memory banks are different. The second preset condition can be that the number of erases of the first memory bank is greater than the third threshold and the number of erases of the second memory bank is less than the fourth threshold. The third and fourth thresholds can be the same or different, and their specific values ​​can be determined according to actual needs, without limitation here.

[0312] S430. When the erase information meets the third preset condition, the data stored in the first storage is written into the third storage.

[0313] In some examples, the third preset condition can be that the difference between the number of erases of the first memory bank and the number of erases of the second memory bank is greater than the fifth threshold. The first memory bank has the most erases (ec_max), and the second memory bank has the fewest erases (ec_min). The third memory bank can be any memory bank among multiple memory banks and is different from the first memory bank. The specific value of the fifth threshold can be determined according to actual needs and is not limited here.

[0314] For example Figure 23 , Figure 24 or Figure 25 The in-memory computing device shown is configured to perform corresponding operations after performing data rotation migration within a storage bank or data migration between storage banks. The corresponding operations include at least one of the following: data write operation, data read operation, data erase operation, or in-memory computing operation.

[0315] Taking the storage bank configured to perform stored-value operations as an example, such as Figure 41 As shown, this embodiment provides a storage and computation operation method, specifically including steps S510-S520:

[0316] S510, Send operation command.

[0317] In some possible implementations, the operation instructions can be provided by, for example Figure 1 , Figure 5 or Figure 6 The processing circuit 1024 shown or as... Figure 4 The host 304 shown, or as... Figure 2 and Figure 3 The processing circuit 2022 in the semiconductor device 202 shown transmits.

[0318] Can be like Figure 1 , Figure 4 , Figure 5 , Figure 6 The semiconductor device 1022 shown, or as Figure 7 , Figure 8 , Figure 9 , Figure 11 , Figure 12 , Figure 16 , Figure 17 , Figure 21 , Figure 26 The semiconductor device 600 shown, or as... Figure 2 and Figure 3 The memory device 2024 in the semiconductor device 202 shown, or as Figure 23 The in-memory computing device 800 shown sends operation commands.

[0319] In some examples, the operation instruction can be either a first operation instruction or a second operation instruction.

[0320] In one example, the first operation instruction includes first address information and input data, whereby the first address information maps to a second type of storage block in the target memory. For example, the first address information could be Unsel_blk, representing the address of a storage block in an erased state (a storage block where "input data / input vector" is not selected or "weight data / weight vector" is not stored).

[0321] In one example, the second operation instruction includes first address information, second address information, and input data. The second address information maps to the starting storage block in the first type of storage block in the target memory. For example, the second address information can be Head_Add, representing the address of the starting storage block in the programming state (the storage block used to input "input data / input vector" or store "weight data / weight vector").

[0322] In another example, the memory block in the target memory includes a select line, a word line, and a memory string. The memory string includes multiple transistors, with their drain and source lines alternately coupled. The gates of the transistors are coupled to the word lines, and the select line is coupled to the gate line of a transistor at one end of the memory string. The first or second operation instruction also includes address information for the selected word line in the target memory block, such as WL_Add, indicating the selected word line WL during in-memory computation.

[0323] S520: Responds to the operation command and obtains the output data.

[0324] In some examples, when the operation instruction is a first operation instruction, and the first operation instruction includes first address information and input data, such as... Figure 42 As shown, step S520 specifically includes step S522:

[0325] S522. In response to the first operation instruction, output data is obtained based on the first address information and input data. The output data is the result of the operation between the input data and the data in the first type of storage block in the target storage. The specific operation principle can be referenced, but is not limited to, as follows: Figure 25 The implementation method shown.

[0326] In some examples, when the operation instruction is a first operation instruction, and the first operation instruction includes first address information, input data, and the address information of the selected word line, such as... Figure 43 As shown, step S520 specifically includes step S524:

[0327] S524. In response to the first operation instruction, based on the first address information, the address information of the selected word line, and the input data, input data is input to the selection line in the target memory block, a read voltage is applied to the selected word line, and a conduction voltage is applied to the unselected word line to obtain output data.

[0328] The output data is the current flowing from the drain or source line, and the on-state voltage is greater than the read voltage. The specific operational principle can be referenced, but is not limited to, [reference needed]. Figure 25 The implementation method shown.

[0329] In some examples, when the operation instruction is a second operation instruction, and the second operation instruction includes first address information, second address information, and input data, such as... Figure 44 As shown, step S520 specifically includes step S526:

[0330] S526. In response to the second operation instruction, the output data is obtained based on the first address information, the second address information, and the input data.

[0331] The output data is the result of the operation between the input data and the data in the first type of storage block in the target storage. The specific operation principle can be referenced, but is not limited to, as shown in [reference needed]. Figure 25 The implementation method shown.

[0332] In some examples, when the operation instruction is a second operation instruction, and the second operation instruction includes first address information, second address information, input data, and address information of the selected word line, such as... Figure 45 As shown, step S520 specifically includes step S528:

[0333] S528. In response to the second operation instruction, based on the first address information, the second address information, the address information of the selected word line, and the input data, input data is input to the selection line in the target memory block, a read voltage is applied to the selected word line, and a conduction voltage is applied to the unselected word line to obtain output data.

[0334] The output data is the current flowing from the drain or source line, and the on-state voltage is greater than the read voltage. The specific operational principle can be referenced, but is not limited to, [reference needed]. Figure 25 The implementation method shown.

[0335] This application also provides a computer-readable storage medium including instructions. When the instructions are executed on the electronic device or storage system described in the above embodiments, the electronic device or storage system performs the operation methods described in the above embodiments.

[0336] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device includes: A storage cell array includes multiple storage surfaces, each storage surface includes multiple storage cells, and each storage cell includes at least one storage block in a first type of programming state; And peripheral circuitry, coupled to the memory cell array, is configured as follows: At least one first storage block is written into at least one second storage block to obtain a second storage block in a second type of programming state; the first storage block and the second storage block are different storage blocks among multiple storage blocks of the target storage body, and the first storage block is a storage block in the first type of programming state; and Erase the data in the first storage block until all storage blocks in the target storage that are in the first type of programming state have been erased once.

2. The semiconductor device according to claim 1, wherein The storage blocks in the first type of programmed state are the storage blocks in the target storage that are in the programmed state between two adjacent data migration cycles; the storage blocks in the second type of programmed state are the storage blocks that are programmed within one data migration cycle; one data migration cycle includes the duration of erasing all the storage blocks in the first type of programmed state in the target storage once.

3. The semiconductor device according to claim 1 or 2, wherein The number of at least one first storage block is greater than the number of at least one second storage block; or, The number of the at least one first storage block is equal to the number of the at least one second storage block.

4. The semiconductor device according to claim 1 or 2, wherein Each of the aforementioned storage blocks includes a first type of storage block and a second type of storage block; The first type of storage block is in a programmed state, and the number of storage blocks in the target storage body that are in a programmed state is equal to the first number; the programmed storage blocks include storage blocks in the first type of programmed state or storage blocks in the second type of programmed state; The second type of storage block is in the erase state, or is in the erase state after an erase operation is performed; the number of storage blocks in the target storage that are in the erase state is equal to the second quantity.

5. The semiconductor device of claim 4, wherein, The second type of storage block is also used to replace faulty storage blocks in the first type of storage block.

6. The semiconductor device according to claim 1 or 2, wherein The peripheral circuit is also configured to: The data stored in the first storage bank is written into the second storage bank; the first storage bank is any one of the plurality of storage banks and the number of faulty storage blocks in the first storage bank is greater than or equal to a first threshold. The second storage unit is any one of the plurality of storage units, and the number of faulty storage blocks in the second storage unit is less than the second threshold.

7. The semiconductor device of claim 6, wherein, Each of the memory blocks includes a first type of memory blocks and a second type of memory blocks, wherein the number of the first type of memory blocks is equal to a first quantity and the number of the second type of memory blocks is equal to a second quantity; The first type of storage block is in a programmed state, and the second type of storage block is used to replace the faulty storage block in the first type of storage block; The first threshold is greater than or equal to the second quantity, and the second threshold is less than the second quantity.

8. The semiconductor device according to claim 1 or 2, wherein The peripheral circuit is also configured to: The data stored in the first storage bank is written into the second storage bank; the first storage bank is any one of the plurality of storage banks and the number of times the first storage bank is erased is greater than a third threshold; the second storage bank is any one of the plurality of storage banks and the number of times the second storage bank is erased is less than a fourth threshold; The number of erases in the memory bank is the average number of erases of the memory blocks in the memory bank, or the number of erases in the memory bank is the average number of erases of the memory blocks in the erase state in the memory bank.

9. The semiconductor device according to claim 1 or 2, wherein The peripheral circuit is also configured to: When the difference between the number of erases in the first storage and the number of erases in the second storage is greater than the fifth threshold, the data stored in the first storage is written into the third storage. Wherein, the number of erases of the storage bank is the average number of erases of the storage blocks in the storage bank, or the number of erases of the storage bank is the average number of erases of the storage blocks in the storage bank that are in the erase state; the first storage bank is any one of the plurality of storage banks and the first storage bank has the most erases, the second storage bank is any one of the plurality of storage banks and the second storage bank has the fewest erases, and the third storage bank is any one of the plurality of storage banks and is different from the first storage bank.

10. The semiconductor device according to claim 1 or 2, wherein Between different data migration cycles, the order in which data is written to the storage blocks is positively correlated with the order in which data is erased from the storage blocks. One data migration cycle includes the duration of erasing all storage blocks of the first type of programmed state in the target storage once.

11. The semiconductor device according to claim 1 or 2, wherein Each of the memory banks includes a first type of memory block and a second type of memory block; the first type of memory block is configured to perform a corresponding operation, and the second type of memory block is configured to replace a faulty memory block in the first type of memory block; the peripheral circuitry is further configured to: Based on the first address information, the first type of storage block in the target storage is controlled to perform corresponding operations; the first address information maps to the second type of storage block in the target storage.

12. The semiconductor device according to claim 11, characterized in that, The corresponding operation includes at least one of the following: data write operation, data read operation, data erase operation, or storage operation.

13. The semiconductor device according to claim 12, characterized in that, The first type of storage block is configured to perform in-memory computation operations, and the peripheral circuitry is specifically configured as follows: Receive a first operation instruction, the first operation instruction including first address information and input data, the first address information mapping to the second type of storage block in the target storage; In response to the first operation instruction, output data is obtained based on the first address information and the input data; the output data is the result of the operation between the input data and the data in the first type of storage block in the target storage.

14. The semiconductor device according to claim 13, characterized in that, The target memory bank includes a memory block comprising a select line, a word line, and a memory string; the memory string comprises multiple transistors, the drain and source lines of which are alternately coupled, the gate of which is coupled to the word line, and the select line is coupled to the gate line of a transistor at one end of the memory string; the first operation instruction further includes address information of the selected word line in the target memory block; the peripheral circuitry is specifically configured as follows: In response to the first operation instruction, based on the first address information, the address information of the selected word line, and the input data, the input data is input to the selection line in the target memory block, a read voltage is applied to the selected word line, and a conduction voltage is applied to the unselected word line to obtain output data; the output data is the current output from the drain line or the source line. The on-state voltage is greater than the read-state voltage.

15. The semiconductor device of claim 11, wherein, The peripheral circuit is specifically configured as follows: Based on the first address information and the second address information, the first type of storage block in the target storage is controlled to perform corresponding operations; the second address information maps to the starting storage block in the first type of storage block in the target storage.

16. The semiconductor device of claim 15, wherein, The first type of storage block is configured to perform in-memory computation operations; the peripheral circuitry is specifically configured as follows: Receive a second operation instruction, the second operation instruction including the first address information, the second address information, and input data; In response to the second operation instruction, output data is obtained based on the first address information, the second address information, and the input data; the output data is the result of the operation between the input data and the data in the first type of storage block in the target storage.

17. The semiconductor device of claim 16, wherein, The target memory bank includes a memory block comprising a select line, a word line, and a memory string; the memory string comprises multiple transistors, the drain and source lines of which are alternately coupled, the gate of which is coupled to the word line, and the select line is coupled to the gate line of a transistor at one end of the memory string; the second operation instruction further includes the address information of the selected word line in the target memory block; the peripheral circuitry is specifically configured as follows: In response to the second operation instruction, based on the first address information, the second address information, the address information of the selected word line, and the input data, the input data is input to the selection line in the target memory block, a read voltage is applied to the selected word line, and a conduction voltage is applied to the unselected word line to obtain output data; the output data is the current output from the drain line or the source line. The on-state voltage is greater than the read-state voltage.

18. A method of operating a semiconductor device, characterized by, include: At least one first storage block is written into at least one second storage block to obtain a second storage block in a second type of programming state; the first storage block and the second storage block are different storage blocks among multiple storage blocks of the target memory, and the first storage block is a storage block in a first type of programming state; and Erase the data in the first storage block until all storage blocks in the target storage that are in the first type of programming state have been erased once.

19. The method of operation of claim 18, wherein, The operation method further includes: The data stored in the first storage bank is written into the second storage bank; the first storage bank is any one of the plurality of storage banks and the number of faulty storage blocks in the first storage bank is greater than or equal to a first threshold; the second storage bank is any one of the plurality of storage banks and the number of faulty storage blocks in the second storage bank is less than a second threshold.

20. The method of claim 18, wherein, The operation method further includes: The data stored in the first storage bank is written into the second storage bank; the first storage bank is any one of the plurality of storage banks and the number of times the first storage bank is erased is greater than a third threshold; the second storage bank is any one of the plurality of storage banks and the number of times the second storage bank is erased is less than a fourth threshold; The number of erases in the memory bank is the average number of erases of the memory blocks in the memory bank, or the number of erases in the memory bank is the average number of erases of the memory blocks in the erase state in the memory bank.

21. The method of claim 18, wherein, The operation method further includes: When the difference between the number of erases in the first storage and the number of erases in the second storage is greater than the fifth threshold, the data stored in the first storage is written into the third storage. Wherein, the number of erases of the storage bank is the average number of erases of the storage blocks in the storage bank, or the number of erases of the storage bank is the average number of erases of the storage blocks in the storage bank that are in the erase state; the first storage bank is any one of the plurality of storage banks and the first storage bank has the most erases, the second storage bank is any one of the plurality of storage banks and the second storage bank has the fewest erases, and the third storage bank is any one of the plurality of storage banks and is different from the first storage bank.

22. The method of claim 18, wherein, The operation method further includes: Based on the first address information, the first type of storage block in the target storage is controlled to perform corresponding operations; the first address information maps to the second type of storage block in the target storage.

23. The method of operation of claim 22, wherein, The step of controlling the first type of storage block in the target storage to perform corresponding operations based on the first address information includes: Receive a first operation instruction, the first operation instruction including first address information and input data, the first address information mapping to the second type of storage block in the target storage; In response to the first operation instruction, output data is obtained based on the first address information and the input data; the output data is the result of the operation between the input data and the data in the first type of storage block in the target storage.

24. The method of operation of claim 23, wherein, The step of responding to the first operation instruction and obtaining output data based on the first address information and the input data includes: In response to the first operation instruction, based on the first address information, the address information of the selected word line, and the input data, the input data is input to the selection line in the target memory block, a read voltage is applied to the selected word line, and a conduction voltage is applied to the unselected word line to obtain output data; the output data is the current output from the drain line or the source line; the conduction voltage is greater than the read voltage.

25. The operating method according to claim 22, characterized in that, The step of controlling the first type of storage block in the target storage to perform corresponding operations based on the first address information includes: Based on the first address information and the second address information, the first type of storage block in the target storage is controlled to perform corresponding operations; the second address information maps to the starting storage block in the first type of storage block in the target storage.

26. The method of operating according to claim 25, wherein, The step of controlling the first type of storage block in the target storage to perform corresponding operations based on the first address information and the second address information includes: Receive a second operation instruction, the second operation instruction including the first address information, the second address information, and input data; In response to the second operation instruction, output data is obtained based on the first address information, the second address information, and the input data; the output data is the result of the operation between the input data and the data in the first type of storage block in the target storage.

27. The method of operating according to claim 26, wherein, In response to the second operation instruction, the output data is obtained based on the first address information, the second address information, and the input data, including: In response to the second operation instruction, based on the first address information, the second address information, the address information of the selected word line, and the input data, the input data is input to the selection line in the target memory block, a read voltage is applied to the selected word line, and a conduction voltage is applied to the unselected word line to obtain output data; the output data is the current output from the drain line or the source line; the conduction voltage is greater than the read voltage.

28. A storage system, comprising: It includes a processing circuit and a semiconductor device as described in any one of claims 1-17, wherein the processing circuit and the semiconductor device are coupled.

29. The storage system of claim 28, wherein, The processing circuit is configured as follows: Send a third operation instruction, the third operation instruction including third address information and fourth address information, the third address information mapping at least one first storage block, the fourth address information mapping at least one second storage block, and the first storage block being a storage block in a first type of programming state; The semiconductor device is configured to: write data from at least one first memory block to at least one second memory block to obtain a second memory block in a second type of programming state; the first memory block and the second memory block are different memory blocks among a plurality of memory blocks of the target memory; as well as Erase the data in the first storage block until all storage blocks in the target storage that are in the first type of programming state have been erased once.

30. The storage system of claim 28, wherein, The processing circuit is configured as follows: The system obtains management information for storage blocks in each of multiple storage banks, wherein each storage block comprises multiple pages, and one of the pages contains management information; the management information is used to indicate whether the storage block is a faulty storage block. Write the data stored in the first storage bank into the second storage bank; The first storage unit is any one of the plurality of storage units, and the number of faulty storage blocks in the first storage unit is greater than or equal to a first threshold. The second storage unit is any one of the plurality of storage units, and the number of faulty storage blocks in the second storage unit is less than the second threshold.

31. The storage system of claim 30, wherein, When the management information is 0xFF, it indicates that the current storage block is a faulty storage block.

32. A computer storage medium, comprising, The computer-readable storage medium includes instructions that, when executed on a processor, cause the processor to perform a method of operating the semiconductor device as described in any one of claims 18-27.

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