Memory device, test system therefor, and calibration method

Abstract

This application discloses a storage device, its testing system, and a calibration method. The storage device includes a storage unit and multiple calibration compensation circuits. Each storage unit includes multiple storage chips, and each storage chip contains a calibration network. The calibration compensation circuits are connected to their respective storage chips to activate the calibration network for calibration matching. This structure helps improve the stability of the storage chip's output signal, reduces storage chip calibration mismatch that could lead to incomplete product functionality or problems, and improves the stability and reliability of the storage device.

Description

Technical Field

[0001] This application relates to the technical field of signal calibration for storage products, and in particular to storage devices, their testing systems, and calibration methods. Background Technology

[0002] Memory chips are widely used in smart electronic products due to their low power consumption and small size. The primary function of memory products is to store data.

[0003] Generally, storage products are manufactured by cutting wafers into dies, i.e., storage chips, which are then packaged and tested to become qualified products.

[0004] However, due to the uneven quality of chip resources or resource defects inherent in the manufacturing process, storage products packaged with defective chips may experience calibration mismatches when applied to mainstream platforms, resulting in incomplete product functionality or problems. Summary of the Invention

[0005] This application provides a storage device, a testing system thereof, and a calibration method to address the problem of calibration mismatch in storage chips.

[0006] To address the aforementioned technical problems, this application provides a storage device, comprising: a storage unit and multiple calibration compensation circuits. The storage unit includes multiple storage chips, each storage chip having a calibration network disposed therein. The calibration compensation circuits are connected to the corresponding storage chips one by one to activate the calibration network for calibration matching.

[0007] The calibration compensation circuit includes a calibration resistor; one end of the calibration resistor is connected to the corresponding memory chip, and the other end of the calibration resistor is connected to the power supply or ground.

[0008] The memory chip has multiple pads, including internal signal pads, functional pads, and external signal pads; one end of the calibration resistor is connected to the corresponding internal signal pad of the memory chip.

[0009] The storage unit includes a circuit board, multiple storage chips, and a molding compound. The multiple storage chips and calibration compensation circuit are fixed on the first side of the circuit board. The molding compound encapsulates the first side of the circuit board and wraps each storage chip and calibration compensation circuit for molding. The internal signal pads, functional pads, and external signal pads of the storage chips are connected to the corresponding pads on the first side of the circuit board.

[0010] The storage unit also includes multiple connectors, which are disposed within the molding compound. One end of each connector is connected to the pad of the storage chip, and the other end of each connector is connected to the corresponding pad on the first side of the circuit board. The connectors include one or more of the following: connecting wires, electroplated connectors, or stamped connectors.

[0011] The circuit board is equipped with a connecting mechanism, and multiple solder balls are fixedly arranged on the second side of the circuit board; the connecting mechanism connects the pads on the first side of the circuit board and the corresponding solder balls respectively.

[0012] The calibration compensation circuit includes wire bonding pads, a first trace, a first resistor pad, a calibration resistor, a second resistor pad, and a second trace connected in sequence. The wire bonding pads are also connected to the internal signal pads on the corresponding memory chips, and the second trace is grounded or connected to the power supply. The calibration resistor is soldered to the first side of the circuit board through the first and second resistor pads. The first and second traces are built into the circuit board.

[0013] Multiple memory chips are arranged on the first side of the circuit board by vertical stacking, side-by-side placement, and / or stepped stacking; the memory chips are stacked and fixed together by adhesive.

[0014] To address the aforementioned technical problems, this application also provides a testing system for a storage device, comprising: a storage device, a test board, and a tester connected in sequence; the storage device includes any of the storage devices described above; wherein, the test board is provided with other calibration compensation circuits, which are connected one by one to other storage chips in the storage device that are not connected to the calibration compensation circuits, so as to activate the calibration network of the other storage chips for calibration matching.

[0015] To address the aforementioned technical problems, this application also provides a calibration method for a storage device applied to any of the storage devices described above or a testing system for the storage device described above, comprising: in response to a calibration mismatch detected by a tester, connecting a calibration compensation circuit of the storage device to a power supply and the corresponding storage chip respectively, thereby activating a calibration network within the storage chip for calibration matching until the impedance of the storage chip matches the impedance of the calibration compensation circuit; and in response to a calibration match detected by the tester, adjusting one end of the calibration compensation circuit connected to the power supply to ground.

[0016] The beneficial effects of this application are as follows: Unlike existing technologies, the storage device of this application includes a storage unit and multiple calibration and compensation circuits. The storage unit includes multiple storage chips, each with a calibration network. The calibration and compensation circuits are connected one-to-one with each storage chip to activate the calibration network for calibration matching. This allows the storage chip to adjust its impedance through the calibration network to match the connected calibration and compensation circuits. Matching improves the stability of the storage chip's output signal, reduces calibration mismatch that could lead to incomplete product functionality or problems, and enhances the stability and reliability of the storage device. This calibration can resolve calibration mismatch issues during the die packaging stage, ensuring proper calibration of the storage device and making it suitable for various mainstream platforms. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of the first embodiment of the storage device provided in this application;

[0018] Figure 2 This is a schematic diagram of one implementation of the calibration network;

[0019] Figure 3 This is a schematic structural block diagram of the first embodiment of the storage device provided in this application;

[0020] Figure 4 This is a cross-sectional schematic diagram of the first embodiment of the storage device provided in this application;

[0021] Figure 5 This is a schematic diagram of the amplified structure of the calibration compensation circuit;

[0022] Figure 6 This is a cross-sectional schematic diagram of the second embodiment of the storage device provided in this application;

[0023] Figure 7 This is a cross-sectional schematic diagram of the third embodiment of the storage device provided in this application;

[0024] Figure 8 This is a cross-sectional schematic diagram of the fourth embodiment of the storage device provided in this application;

[0025] Figure 9 This is a cross-sectional schematic diagram of the fifth embodiment of the storage device provided in this application;

[0026] Figure 10 This is a cross-sectional schematic diagram of the sixth embodiment of the storage device provided in this application;

[0027] Figure 11 This is a cross-sectional schematic diagram of the seventh embodiment of the storage device provided in this application;

[0028] Figure 12This is a cross-sectional schematic diagram of the eighth embodiment of the storage device provided in this application;

[0029] Figure 13 This is a cross-sectional schematic diagram of the ninth embodiment of the storage device provided in this application;

[0030] Figure 14 This is a schematic diagram of the structure of an embodiment of the test system for the storage device provided in this application;

[0031] Figure 15 This is a schematic flowchart of an embodiment of the calibration method for the storage device provided in this application. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0034] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0035] Please refer to this together. Figure 1-2 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the storage device provided in this application. Figure 2 This is a schematic diagram of one implementation of the calibration network.

[0036] Storage device 100 includes a storage cell 110 and multiple calibration compensation circuits 120. The storage cell 110 implements the storage function of storage device 100. The storage cell 110 includes multiple memory chips 111 (DIEs), where a memory chip 111 (DIE) is a small piece of semiconductor material on which given functional circuitry is fabricated to achieve data storage. Please refer to further details. Figure 2 Each memory chip 111 is equipped with a calibration network 400. The impedance within the memory chip 111 may be inaccurate. By setting the calibration network 400 to anchor an external standard resistor, the impedance within the memory chip 111 can be adjusted to achieve impedance matching and improve the accuracy of the impedance within the memory chip 111.

[0037] Specifically, the calibration network 400 may include a control circuit 401 and a calibration adjustment circuit 402. The calibration adjustment circuit 402 is connected to both the control circuit 401 and the calibration compensation circuit 120, and the control circuit 401 is also connected to the calibration compensation circuit 120. The control circuit 401 includes an RCV circuit (receiver) or other control circuits. The calibration adjustment circuit 402 is composed of multiple MOSFETs arranged in combination, and its impedance may have deviations. Therefore, it needs to be controlled by the control circuit 401 for impedance matching. Specifically, the control circuit 401 is used to calibrate the resistance of the control circuit 401 based on the resistance value of the calibration compensation circuit 120 to obtain the matched impedance after calibration, so as to enable the memory chip 111 to function normally.

[0038] The calibration compensation circuit 120 is connected to the corresponding memory chip 111 one by one to activate the calibration network 400 in the memory chip 111 for calibration matching. Specifically, after activating the calibration network 400, the memory chip 111 will adjust its own impedance through the calibration network 400 to match it with the connected calibration compensation circuit 120. After matching, it is beneficial to improve the stability of the output signal of the memory chip 111.

[0039] The specific number of calibration compensation circuit 120 and memory chip 111 is set based on actual needs and is not limited.

[0040] The storage device 100 in this embodiment includes, but is not limited to, various types of DDR (Double Data Rate DRAM) and various types of LPDDR (Low Power Double Data Rate DRAM), such as LPDDR1, LPDDR2, LPDDR3, LPDDR4 / 4X, LPDDR5 / 5X, DDR3, DDR4 or DDR5, etc., and is not limited here.

[0041] Through the above steps, the storage device of this embodiment includes a storage unit and multiple calibration compensation circuits. The storage unit includes multiple storage chips, each with a calibration network. The calibration compensation circuits are connected one-to-one with each storage chip to activate the calibration network for calibration matching. This allows the storage chip to adjust its impedance through the calibration network to match the connected calibration compensation circuit. Matching improves the stability of the storage chip's output signal, reduces calibration mismatch that could lead to incomplete product functionality or problems, and enhances the stability and reliability of the storage device. This calibration can resolve calibration mismatch issues during the die packaging stage, ensuring proper calibration of the storage device and making it suitable for various mainstream platforms.

[0042] Please refer to further information. Figure 3-4 , Figure 3 This is a structural block diagram of the first embodiment of the storage device provided in this application. Figure 4 This is a cross-sectional schematic diagram of the first embodiment of the storage device provided in this application. The above schematic diagram shows two storage chips and a calibration compensation circuit, which is for illustration only and not intended to be limiting. The number of storage chips and calibration compensation circuit in the storage device can be other than the stated number.

[0043] In some embodiments, the calibration compensation circuit 120 includes a calibration resistor 121; one end of the calibration resistor 121 is connected to the corresponding memory chip 111, and the other end of the calibration resistor 121 is connected to the power supply or ground.

[0044] When the calibration resistor 121 is connected to the power supply or grounded, the calibration compensation circuit 120 is activated to activate the verification network in the memory chip 111. The choice of whether the calibration resistor 121 is connected to the power supply or grounded to activate the calibration compensation circuit 120 is set according to different types of memory 100 to meet the requirements of wide applicability.

[0045] The calibration resistor 121 is a fixed resistor, and its specific resistance value can be set according to different types of storage devices 100 in order to activate the corresponding verification network. In different types of storage devices 100, the resistance value of the calibration resistor 121 can be, but is not limited to, 15 ohms, 50 ohms, 100 ohms, 180 ohms, 200 ohms, 220 ohms, 240 ohms or 300 ohms, etc.

[0046] The aforementioned calibration compensation circuit 120 is low in cost and has a simple and ingenious design that does not affect the packaging process.

[0047] In some embodiments, the memory chip 111 is provided with multiple pads, including internal signal pads 112, functional pads 113, and external signal pads 114. Pads 114 are used for data transmission or exchange. The signal types of the external signal pads 114 include DQ signals (data signals), CA signals (address signals), CS (Chip Select), and CKE (Clock Enable), etc., for external transmission. Functional pads 113 are used for power supply or grounding, including power pads and ground pads. Internal signal pads 112 refer to special enable signals, such as ZQRX, ZQTX (ZQ Receiver or Transfer, internal chip communication signals), and ODT (On-Die Termination, on-chip terminating resistor), etc., transmitted internally within the memory device 100. The specific number of internal signal pads 112, functional pads 113, and external signal pads 114 can be multiple, depending on the connection requirements of the memory chip 111, and is not limited here.

[0048] One end of the calibration resistor 121 is connected to the internal signal pad 112 of the corresponding memory chip 111, and the other end of the calibration resistor 121 is grounded or connected to a power supply. By connecting the calibration resistor 121 to the internal signal pad 112, the calibration network within the memory chip 111 is internally activated.

[0049] In some embodiments, the storage unit 110 includes a circuit board 150, a plurality of storage chips 111, and a molding compound 140.

[0050] Multiple memory chips 111 and calibration compensation circuit 120 are fixed on the first side 151 of circuit board 150. A molding layer 140 molds the first side 151 of circuit board 150 and wraps each memory chip 111 and calibration compensation circuit 120 to fix the relative position between circuit board 150, memory chips 111 and calibration compensation circuit 120, thereby improving the stability of storage device 100.

[0051] Circuit board 150 is a pre-fabricated PCB (Printed Circuit Board), in which the circuitry is patterned. Circuit board 150 can be a multilayer board with only through-hole interconnects, or an HDI (High Density Interconnect) board with blind via interconnects. The specific structure of circuit board 150 is set according to actual requirements.

[0052] The molding layer 140 includes, but is not limited to, one or more insulating materials such as epoxy resin, polyester resin (PET), polyimide, polyimide, polycarbonate (PC), bismaleimide triazine (BT), Ajinomoto build film (ABF), and FR4 resin.

[0053] The internal signal pads 112, functional pads 113, and external signal pads 114 of the memory chip 111 are respectively connected to corresponding pads 134 on the first side 151 of the circuit board 150. In a specific application scenario, the pads 134 on the circuit board 150 may include a first pad 131, a second pad 132, and a third pad 133. The first pad 131 is connected to the internal signal pad 112, the second pad 132 is connected to the functional pad 113, and the third pad 133 is connected to the external signal pad 114, so as to interconnect the various signals of the memory chip 111 with the circuit board 150 and realize signal interaction.

[0054] In some embodiments, the storage unit 110 further includes a plurality of connectors 160 disposed within the molding compound 140. One end of each connector 160 is connected to the pad of the storage chip 111, and the other end of the connector 160 is connected to the corresponding pad 134 on the first side 151 of the circuit board 150, so as to realize the connection between the circuit board 150 and the storage chip 111.

[0055] The connector 160 includes one or more of the following: a connecting wire, an electroplated connector, or a stamped connector, which are not limited here.

[0056] Please refer to further information. Figure 5 , Figure 5 This is a schematic diagram of the magnified structure of the calibration compensation circuit.

[0057] The calibration compensation circuit 120 includes wire bonding pads 122, first traces 123, first resistor pads 124, calibration resistors 121, second resistor pads 125, and second traces 126 connected in sequence.

[0058] The wire bonding pad 122 is also connected to the internal signal pad 112 on the corresponding memory chip 111. Specifically, the wire bonding pad 122 and the internal signal pad 112 can be connected through the connector 160.

[0059] The end of the second trace 126 away from the second resistor pad 125 is grounded or connected to the power supply 170.

[0060] The calibration resistor 121 is soldered to the first side 151 of the circuit board 150 via the first resistor pad 124 and the second resistor pad 125; the first trace 123 and the second trace 126 are built into the circuit board 150, thereby fixing the calibration resistor 121 and its connection mechanism to the first side 151 of the circuit board 150.

[0061] Please read back Figure 4 The circuit board 150 is provided with a connection mechanism 180, and a plurality of solder balls 153 are fixedly provided on the second side 152 of the circuit board 150. The connection mechanism 180 connects the pads 134 of each memory chip 111 and the corresponding solder balls 153 respectively, so as to connect the signal of the memory chip 111 to the outside through the solder balls 153.

[0062] In a specific application scenario, the connection mechanism 180 may include metallized holes and conductive lines. The specific positions and shapes of the metallized holes and conductive lines are varied and can be set according to the electrical connection requirements of the circuit board 150. No limitation is made here.

[0063] In a specific application scenario, multiple memory chips 111 are arranged on the first side 151 of the circuit board 150 by vertical stacking, side-by-side placement and / or stair stacking.

[0064] The memory chips 111 are stacked and fixed together by adhesive 119. Figure 4 The image shows a diagram of items placed side by side.

[0065] Please see Figure 6 , Figure 6 This is a cross-sectional schematic diagram of the second embodiment of the storage device provided in this application.

[0066] This embodiment uses four memory chips as an example for illustration. The first memory chip 211 and the second memory chip 212 are offset stacked, that is, there is a certain offset between the positions of the two chips in the vertical direction; the third memory chip 213 and the fourth memory chip 214 are stacked vertically, that is, the positions of the two chips coincide in the vertical direction.

[0067] Within a storage device, vertical stacking, side-by-side placement, and stepped stacking can be configured individually or in combination based on actual needs and the number of storage chips required; no specific choice is specified here.

[0068] In a specific application scenario, the first memory chip 211 is connected to the first calibration compensation circuit 222 to activate its internal calibration network. The third memory chip 213 is connected to the second calibration compensation circuit 221 to activate its internal calibration network. The second memory chip 212 and the fourth memory chip 214 may not be connected to their corresponding calibration compensation circuits within the memory device. However, during testing, they can be connected one-to-one with their corresponding calibration compensation circuits on a test board. This means that during testing, multiple memory chips can be fully connected to their corresponding calibration compensation circuits using the test board. Having some corresponding calibration compensation circuits on the memory device saves internal space, promotes miniaturization and portability, and increases the flexibility of wiring within the device.

[0069] In a specific application scenario, if there are N memory chips in the storage device, where N is a positive integer, then N calibration compensation circuits can also be set on the first side of the circuit board to connect one-to-one with the memory chips, thereby setting a corresponding calibration compensation circuit for each memory chip and improving test stability.

[0070] Please read back Figure 1 , Figure 1 The illustration shows an example where a corresponding calibration compensation circuit is provided for each memory chip; please refer back to [link / reference]. Figure 3 , 4 5. The above schematic diagram is an embodiment of setting corresponding calibration compensation circuits for some memory chips; wherein, in the storage device, corresponding calibration compensation circuits are set for at least some memory chips, and the calibration compensation circuits for other memory chips can be supplemented by the test board.

[0071] Please see Figure 7 , Figure 7 This is a cross-sectional schematic diagram of the third embodiment of the storage device provided in this application.

[0072] This embodiment shows a first memory chip 61 and a second memory chip 62 stacked off-center, with the first memory chip 61 connected to a calibration compensation circuit 63. The stacked chips are not connected to each other, but are directly connected to pads on the circuit board.

[0073] Please see Figure 8 , Figure 8 This is a cross-sectional schematic diagram of the fourth embodiment of the storage device provided in this application.

[0074] This embodiment shows a first memory chip 71 and a second memory chip 72 stacked vertically, and a third memory chip 73 and a fourth memory chip 74 stacked vertically. The first memory chip 71 is connected to the calibration compensation circuit 75. The stacked chips are not connected to each other, but are directly connected to pads on the circuit board.

[0075] Please see Figure 9 , Figure 9 This is a cross-sectional schematic diagram of the fifth embodiment of the storage device provided in this application.

[0076] This embodiment shows a first memory chip 81 and a second memory chip 82 stacked at an offset, and a third memory chip 83 and a fourth memory chip 84 stacked at an offset, with the first memory chip 81 connected to a calibration compensation circuit 85. The stacked chips are not connected to each other, but are directly connected to pads on the circuit board.

[0077] Please see Figure 10 , Figure 10 This is a cross-sectional schematic diagram of the sixth embodiment of the storage device provided in this application.

[0078] This embodiment shows a first memory chip 91 and a second memory chip 92 stacked with offset orientation, and a third memory chip 93 and a fourth memory chip 94 stacked with offset orientation. The first memory chip 91 is connected to a calibration compensation circuit 95. The stacked chips are connected as follows: the first memory chip 91 is connected to the circuit board pads via the pads connecting the second memory chip 92; the third memory chip 93 is connected to the circuit board pads via the pads connecting the fourth memory chip 94; and the second memory chip 92 and the fourth memory chip 94 are directly connected to the circuit board pads.

[0079] The interconnections between the stacked chips can be configured according to actual needs and are not limited here. Figure 7-10 These are various embodiments under a single calibration compensation circuit, i.e., when the storage device contains 4m or 2m storage chips and m calibration compensation circuits, the configuration structure can be found in [reference needed]. Figure 7-10 m is a positive integer.

[0080] Please see Figure 11 , Figure 11 This is a cross-sectional schematic diagram of the seventh embodiment of the storage device provided in this application.

[0081] This embodiment shows a first memory chip 1001 and a second memory chip 1002 vertically stacked. The first memory chip 1001 is connected to a first calibration compensation circuit 1003, and the second memory chip 1002 is connected to a second calibration compensation circuit 1004. The stacked chips are not connected to each other, but are directly connected to pads on the circuit board.

[0082] Please see Figure 12 , Figure 12 This is a cross-sectional schematic diagram of the eighth embodiment of the storage device provided in this application.

[0083] This embodiment shows a first memory chip 1101 and a second memory chip 1102 stacked with offset orientation, and a third memory chip 1103 and a fourth memory chip 1104 stacked with offset orientation. The second memory chip 1102 is connected to a first calibration compensation circuit 1005, and the third memory chip 1103 is connected to a second calibration compensation circuit 1006. The stacked chips are connected as follows: the first memory chip 1101 is connected to the circuit board pads via the pads connecting the second memory chip 1102; the third memory chip 1103 is connected to the circuit board pads via the pads connecting the fourth memory chip 1104; the second memory chip 1102 and the fourth memory chip 1104 are directly connected to the circuit board pads. Figure 11-12 These are various embodiments with two calibration compensation circuits, i.e., when the storage device contains 4m or 2m storage chips and 2m calibration compensation circuits, the configuration can be found in [reference needed]. Figure 11-12 .

[0084] Please see Figure 13 , Figure 13 This is a cross-sectional schematic diagram of the ninth embodiment of the storage device provided in this application.

[0085] This embodiment shows a first memory chip 1201 and a second memory chip 1202 vertically stacked, and a third memory chip 1203 and a fourth memory chip 1204 vertically stacked. The first memory chip 1201 is connected to a first calibration compensation circuit 1205, the second memory chip 1102 is connected to a second calibration compensation circuit 1206, the third memory chip 1103 is connected to a third calibration compensation circuit 1208, and the fourth memory chip 1204 is connected to a fourth calibration compensation circuit 1207. Each memory chip is directly connected to pads on the circuit board.

[0086] In this embodiment, the four memory chips are connected one-to-one with the four calibration and compensation circuits, and this is applied to an embodiment where the memory chips and calibration and compensation circuits are fully connected.

[0087] The embodiments described above regarding connections and settings are merely some embodiments of this application, and not all embodiments. Equivalent structures based on the above embodiments are all within the protection scope of this application.

[0088] With the above structure, the storage device of this embodiment includes a storage unit and multiple calibration compensation circuits. The storage unit includes multiple storage chips, and each storage chip is provided with a calibration network. The calibration compensation circuit is connected to the storage chip in a one-to-one correspondence to activate the calibration network for calibration matching. This allows the storage chip to adjust its own impedance through the calibration network to match the connected calibration compensation circuit. After matching, it is beneficial to improve the stability of the output signal of the storage chip, reduce the occurrence of storage chip calibration mismatch, and thus improve the stability and reliability of the storage device.

[0089] Based on the same concept, this application also provides a testing system for a storage device; please refer to [link to relevant documentation]. Figure 14 , Figure 14 This is a schematic diagram of an embodiment of the test system for the storage device provided in this application.

[0090] The storage device testing system 300 of this embodiment includes a storage device 310, a test board 320, and a tester 330 connected in sequence. The tester 330 is connected to the storage device 310 through the test board 320 to perform relevant tests on it.

[0091] The storage device 310 includes the storage device 100 of any of the above embodiments. Therefore, during testing, the calibration compensation circuit within the storage device 310 activates the calibration network within the storage chip to perform calibration matching. This causes the storage chip to adjust its impedance through the calibration network to match the connected calibration compensation circuit. After matching, it helps improve the stability of the storage chip's output signal, reduces the occurrence of storage chip calibration mismatch, and prevents incomplete product functionality or problems, thereby improving the stability and reliability of the storage device.

[0092] In some embodiments, the test board 320 may be provided with other calibration compensation circuits, which are connected one by one to other memory chips in the storage device 310 that are not connected to the calibration compensation circuits, so as to activate the calibration network of other memory chips for calibration matching.

[0093] That is, when the storage device 310 only has corresponding calibration compensation circuits for some of the storage chips, the test board 320 has corresponding calibration compensation circuits for the remaining storage chips, so that each storage chip has a corresponding calibration compensation circuit to connect to during testing.

[0094] The testing system 300 for the storage device in this embodiment can be applied to scenarios such as pre-shipment testing and post-shipment maintenance of the storage device 310.

[0095] Based on the same concept, this application also provides a calibration method for a storage device; please refer to [link to relevant documentation]. Figure 15 , Figure 15 This is a schematic flowchart of an embodiment of the calibration method for a storage device provided in this application. The calibration method for the storage device is applied to the storage device or the testing system for the storage device in any of the above embodiments.

[0096] Step S11: In response to the detection of calibration mismatch in the memory chip of the storage device by the tester, the calibration compensation circuit of the storage device is connected to the power supply and the corresponding memory chip respectively to activate the calibration network in the memory chip for calibration matching until the impedance of the memory chip matches the impedance of the calibration compensation circuit.

[0097] When the tester detects a calibration mismatch in the memory chip, i.e., unstable signal output, the calibration compensation circuit of the memory device is connected to the power supply and the corresponding memory chip respectively, thereby activating the calibration compensation circuit and activating the calibration network to perform calibration matching until the impedance of the memory chip matches the impedance of the calibration compensation circuit.

[0098] After impedance matching, it is confirmed that the signal output of the memory chip has stabilized.

[0099] Step S12: In response to the detection of calibration matching of the memory chip by the tester, adjust the end of the calibration compensation circuit of the memory device connected to the power supply to ground.

[0100] Once the tester detects that the memory chip is calibrated and matched, the end of the calibration compensation circuit connected to the power supply of the memory device is adjusted to ground, so that the calibration compensation circuit is powered off and silenced, thus not affecting the normal operation of the memory chip.

[0101] Through the above steps, the calibration compensation circuit of the calibration method of the storage device in this embodiment will activate the calibration network in the storage chip for calibration matching during testing. This will cause the storage chip to adjust its own impedance through the calibration network to match the connected calibration compensation circuit. After matching, it will help improve the stability of the output signal of the storage chip, reduce the occurrence of storage chip calibration mismatch, which may lead to incomplete product function or problems, and improve the stability and reliability of the storage device.

[0102] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A storage device, characterized in that, The storage device includes: A storage unit, the storage unit comprising multiple storage chips, each of the storage chips having a calibration network disposed therein; Multiple calibration compensation circuits are provided, each connected to a corresponding memory chip, to activate the calibration network for calibration matching.

2. The storage device according to claim 1, characterized in that, The calibration compensation circuit includes a calibration resistor; One end of the calibration resistor is connected to the corresponding memory chip, and the other end of the calibration resistor is connected to the power supply or ground.

3. The storage device according to claim 2, characterized in that, The memory chip is provided with multiple pads, including internal signal pads, functional pads, and external signal pads. One end of the calibration resistor is connected to the internal signal pad of the corresponding memory chip.

4. The storage device according to claim 3, characterized in that, The storage unit includes a circuit board, multiple storage chips, and a molding layer; Multiple memory chips and the calibration compensation circuit are fixed to the first side of the circuit board. The molding layer encapsulates the first side of the circuit board and wraps each memory chip and the calibration compensation circuit for molding. The internal signal pads, functional pads, and external signal pads of the memory chip are connected to corresponding pads on the first side of the circuit board.

5. The storage device according to claim 4, characterized in that, The storage unit also includes a plurality of connectors disposed within the molding compound. One end of each connector is connected to the pad of the storage chip, and the other end of each connector is connected to a corresponding pad on the first side of the circuit board. The connector includes one or more of the following: a connecting wire, an electroplated connector, or a stamped connector.

6. The storage device according to claim 4, characterized in that, The circuit board is provided with a connecting mechanism, and a plurality of solder balls are fixedly provided on the second side of the circuit board; the connecting mechanism connects the pads on the first side of the circuit board and the corresponding solder balls respectively.

7. The storage device according to claim 4, characterized in that, The calibration compensation circuit includes wire bonding pads, a first trace, a first resistor pad, the calibration resistor, a second resistor pad, and a second trace connected in sequence. The wire bonding pad is also connected to the internal signal pad on the corresponding memory chip, and the end of the second trace away from the second resistor pad is grounded or connected to the power supply. The calibration resistor is soldered to the first side of the circuit board via the first resistor pad and the second resistor pad; the first trace and the second trace are embedded within the circuit board.

8. The storage device according to claim 4, characterized in that, Multiple memory chips are arranged on the first side of the circuit board by means of vertical stacking, side-by-side placement and / or stepped stacking; The memory chips are stacked and fixed together using adhesive.

9. A testing system for a storage device, characterized in that, The testing system for the storage device includes a storage device, a test board, and a tester connected in sequence; the storage device includes the storage device as described in any one of claims 1-8; The test board is equipped with other calibration compensation circuits, which are connected to other memory chips in the storage device that are not connected to the calibration compensation circuits, so as to activate the calibration network of the other memory chips for calibration matching.

10. A calibration method for a storage device, characterized in that, The calibration method for the storage device is applied to the testing system for the storage device as described in any one of claims 1-8 or as described in claim 9, and includes: In response to the detection of calibration mismatch in the memory chip of the storage device by the tester, the calibration compensation circuit of the storage device is connected to the power supply and the corresponding memory chip respectively to activate the calibration network in the memory chip for calibration matching until the impedance of the memory chip matches the impedance of the calibration compensation circuit. In response to the detection of calibration matching of the memory chip by the tester, the end of the calibration compensation circuit connected to the power supply is adjusted to ground.

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