A data read method for a three-dimensional flash memory array and related products

Abstract

This application discloses a data reading method and related products for a 3D flash memory array, applicable to the semiconductor technology field. The method includes: determining a preset reading order for the target 3D flash memory array; applying an on-state voltage to the word lines of all memory blocks to be read in the target 3D flash memory array before the read operation; grounding the source line of the current memory block before reading it, and performing a discharge operation on the source line of the next memory block to be read during the read operation; adjusting the selected word line in the current memory block from the on-state voltage to the read voltage, and controlling the selection gate to be on to perform data reading. Thus, by applying an on-state voltage to the word lines of all memory blocks before the read operation and performing a discharge operation on the source line of the next memory block to be read before the read operation of the current memory block is completed, the voltage settling time during memory block switching is reduced, effectively improving the data reading speed of the 3D flash memory array.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a data reading method and related products for a three-dimensional flash memory array. Background Technology

[0002] 3D NAND flash memory arrays, also known as 3D NAND flash memory arrays, change the traditional planar two-dimensional arrangement of massive flash memory storage cells to a high-density storage array formed by vertical three-dimensional stacking. It is the core storage structure of modern solid-state drives.

[0003] 3D flash memory arrays typically contain multiple memory blocks. During reading, an on-state voltage needs to be applied to the unselected word lines in the selected memory block, while a read voltage is applied to the selected word lines. The word lines in the unselected memory blocks are given zero voltage. Therefore, when switching memory blocks for data reading, an on-state voltage needs to be applied to the unselected word lines in the newly selected memory block. As the number of word lines increases, the total capacitance on the unselected word lines becomes very large. Switching memory blocks requires a long waiting period to establish the on-state voltage on the unselected word lines, resulting in slow data read speeds when reading data from a 3D flash memory array.

[0004] Therefore, how to improve the data read speed of a 3D flash memory array is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned issues, this application provides a data reading method and related products for a 3D flash memory array. By applying a conduction voltage to the word lines of all memory blocks before the read operation and performing a discharge operation on the source line of the next memory block to be read before the read operation of the current memory block is completed, the voltage setup time during memory block switching is reduced, effectively improving the data reading speed of the 3D flash memory array.

[0006] In a first aspect, embodiments of this application provide a data reading method for a three-dimensional flash memory array, including: Determine the preset reading order for each memory block to be read in the target 3D flash memory array; Before the read operation, an on-state voltage is applied to the word lines of all memory blocks to be read in the target 3D flash memory array; Before reading the Mth memory block to be read, the source lines in the Mth memory block to be read are set to 0 voltage, and when reading the Mth memory block to be read, the source lines in the (M+1)th memory block to be read in the preset reading order are set to 0 voltage; M is an integer greater than or equal to 1; The selected word line in the Mth memory block to be read is adjusted from the on-state voltage to the read-state voltage, and the top and bottom selection gates corresponding to the Mth memory block to be read are turned on to perform data reading.

[0007] Optionally, the data reading method further includes: Before the read operation, a fixed voltage is applied to the source lines of all memory blocks to be read in the target 3D flash memory array; the fixed voltage is less than the on-state voltage.

[0008] Optionally, the data reading method further includes: Before the read operation, apply a zero voltage to the top selected gate line and an on voltage to the bottom selected gate line in all the memory blocks to be read in the target 3D flash array.

[0009] Optionally, setting the source line in the Mth memory block to be read to 0 voltage includes: The source line in the Mth memory block to be read is discharged from the fixed voltage to 0 voltage.

[0010] Optionally, setting the source line of the (M+1)th memory block to be read in the preset read order to 0 voltage includes: The source line in the (M+1)th memory block to be read, which is located after the Mth memory block to be read in the preset reading order, is discharged to 0 voltage by the fixed voltage.

[0011] Secondly, embodiments of this application provide a data reading device for a three-dimensional flash memory array, comprising: The determination module is used to determine the preset reading order corresponding to each storage block to be read in the target 3D flash memory array; The first voltage preset module is used to apply a conduction voltage to the word lines of all the memory blocks to be read in the target three-dimensional flash memory array before the read operation; The first voltage regulation module is used to set the source line of the Mth memory block to 0 voltage before reading the Mth memory block to be read, and to set the source line of the (M+1)th memory block to be read after the Mth memory block to be read in the preset reading order to 0 voltage when reading the Mth memory block to be read; M is an integer greater than or equal to 1; The second voltage adjustment module is used to adjust the selected word line in the Mth memory block to be read from the conduction voltage to the read voltage, and control the top selection gate and bottom selection gate corresponding to the Mth memory block to be read to be turned on, so as to perform data reading.

[0012] Optionally, the data reading device further includes: a second voltage preset module; The second voltage preset module is used to apply a fixed voltage to the source lines of all memory blocks to be read in the target 3D flash memory array before the read operation; the fixed voltage is less than the turn-on voltage.

[0013] Optionally, the data reading device further includes: a third voltage preset module; The third voltage preset module is used to apply 0 voltage to the top selected gate line and apply on voltage to the bottom selected gate line of all the storage blocks to be read in the target three-dimensional flash memory array before the read operation.

[0014] Thirdly, embodiments of this application provide a data reading device for a three-dimensional flash memory array, comprising: Memory, used to store computer programs; A processor, used to execute the computer program to implement the steps of the data reading method for a three-dimensional flash memory array as described above.

[0015] Fourthly, embodiments of this application provide a readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the data reading method for a three-dimensional flash memory array as described above.

[0016] As can be seen from the above technical solutions, compared with the prior art, this application has the following advantages: This application provides a data reading method for a 3D flash memory array. First, it determines the preset read order of each memory block to be read in the target 3D flash memory array and applies an on-state voltage to the word lines of all memory blocks to be read before the read operation. Before reading the Mth memory block, the source line of the Mth memory block is set to 0 voltage. Then, when reading the Mth memory block, the selected word line of the Mth memory block is adjusted from the on-state voltage to the read voltage, and the top and bottom select gates corresponding to the Mth memory block are turned on to perform data reading. In addition, when reading the Mth memory block, the source line of the (M+1)th memory block following the Mth memory block in the preset read order is also set to 0 voltage. M is an integer greater than or equal to 1. Thus, by applying a conduction voltage to the word lines of all memory blocks before the read operation and performing a discharge operation on the source line of the next memory block to be read before the read operation of the current memory block is completed, the voltage settling time during memory block switching is reduced, effectively improving the data read speed of the 3D flash memory array. Attached Figure Description

[0017] Figure 1 A flowchart illustrating a data reading method for a three-dimensional flash memory array provided in this application embodiment; Figure 2 A schematic diagram of a storage block to be read in a target three-dimensional flash memory array provided in an embodiment of this application; Figure 3 This is a schematic diagram of a data reading device for a three-dimensional flash memory array provided in an embodiment of this application. Detailed Implementation

[0018] As mentioned earlier, existing methods for reading data from 3D flash memory arrays suffer from slow data read speeds. Specifically, during reading, these methods require applying a conduction voltage to the unselected word lines within the selected memory block and a read voltage to the selected word lines. Meanwhile, word lines in unselected memory blocks are given zero voltage. Thus, when switching memory blocks for data reading, conduction voltages must be applied to the unselected word lines in the newly selected block. As the number of word lines increases, the total capacitance on the unselected word lines becomes very large. Switching memory blocks requires a long waiting period to establish the conduction voltage on the unselected word lines, resulting in slow data read speeds when reading data from 3D flash memory arrays.

[0019] To address the aforementioned problems, this application provides a data reading method for a 3D flash memory array, comprising: firstly, determining the preset reading order corresponding to each memory block to be read in the target 3D flash memory array, and applying a conduction voltage to the word lines of all memory blocks to be read in the target 3D flash memory array before the read operation. Before reading the Mth memory block to be read, the source line of the Mth memory block to be read needs to be set to 0 voltage. Then, when reading the Mth memory block to be read, the selected word line of the Mth memory block to be read is adjusted from the conduction voltage to the read voltage, and the top selection gate and bottom selection gate corresponding to the Mth memory block to be read are controlled to be turned on to perform data reading. In addition, when reading the Mth memory block to be read, the source line of the (M+1)th memory block to be read after the Mth memory block in the preset reading order needs to be set to 0 voltage. M is an integer greater than or equal to 1.

[0020] Thus, by applying a conduction voltage to the word lines of all memory blocks before the read operation and performing a discharge operation on the source line of the next memory block to be read before the read operation of the current memory block is completed, the voltage settling time during memory block switching is reduced, effectively improving the data read speed of the 3D flash memory array.

[0021] It should be noted that the data reading method and related products for a 3D flash memory array provided in this application can be applied to the field of semiconductor technology. The above are merely examples and do not limit the application field of the data reading method and related products for a 3D flash memory array provided in this application.

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] Figure 1 This is a flowchart illustrating a data reading method for a three-dimensional flash memory array, provided as an embodiment of this application. (In conjunction with...) Figure 1 As shown in the embodiments of this application, a data reading method for a three-dimensional flash memory array may include: S101: Determine the preset read order corresponding to each storage block to be read in the target 3D flash memory array.

[0024] In practical applications, the target 3D flash memory array to be read may contain multiple memory blocks to be read. Therefore, it is necessary to first determine the preset reading order corresponding to each memory block to be read. Typically, the memory blocks to be read inside the target 3D flash memory array are assigned fixed physical numbers at the factory, and the preset reading order is by default the order of the fixed physical numbers from smallest to largest. Figure 2 This is a schematic diagram of a target 3D flash memory array containing a storage block to be read, provided as an embodiment of this application. (In conjunction with...) Figure 2 As shown, the target 3D flash memory array can contain three memory blocks to be read: memory block a, memory block b, and memory block c. Correspondingly, the preset reading order of this target 3D flash memory array can be to read memory block a first, then memory block b, and finally memory block c. For each memory block to be read, it includes N word lines (WL<0:N>), one layer of TSG lines (TSG<0:1>), one layer of bottom select gate (BSG<0:1>), and source lines (SL). Specifically, memory block a corresponds to TSGa, WLa, BSGa, and Sla; memory block b corresponds to TSGb, WLb, BSGb, and Slb; and memory block c corresponds to TSGc, WLc, BSGc, and Slc.

[0025] S102: Apply a conduction voltage to the word lines of all memory blocks to be read in the target 3D flash memory array before the read operation.

[0026] In practical applications, the word line setup time caused by memory block switching can be reduced by activating the next selected memory block in advance, thereby improving data read speed. Specifically, continuing with the example of the target 3D flash memory array including memory blocks a, b, and c to be read, assuming that blocks a, b, and c are all selected for data reading, a pass voltage (Vpass) needs to be applied to the word lines of all memory blocks to be read (i.e., blocks a, b, and c) in the target 3D flash memory array after chip power-on and before the read operation. In this way, by pre-establishing the pass voltage of the word lines in all memory blocks to be read, the long voltage setup time caused by switching between blocks is avoided, making the data read process smoother and effectively improving the data read speed of the 3D flash memory array.

[0027] Furthermore, since the voltage configuration before the read operation is not entirely the same, the embodiments of this application can describe one possible voltage configuration.

[0028] In one instance, the data reading method further includes: Before the read operation, a fixed voltage is applied to the source lines of all memory blocks to be read in the target 3D flash memory array; the fixed voltage is less than the on-state voltage.

[0029] In addition, before the read operation, a zero voltage is applied to the top selection gate line and an on voltage is applied to the bottom selection gate line in all the memory blocks to be read in the target 3D flash array.

[0030] In practical applications, the voltage setup process before a read operation can apply a conduction voltage to all word lines in all blocks of memory to be read in the target 3D flash memory array. Alternatively, a fixed voltage can be applied to the source lines of all blocks of memory to be read in the target 3D flash memory array, zero voltage can be applied to the top select gate line, and a conduction voltage can be applied to the bottom select gate line. Continuing with the example of a target 3D flash memory array including blocks a, b, and c, assuming that blocks a, b, and c are all selected for data reading, after the chip is powered on and before the read operation, a fixed voltage (VS) can be applied to the source lines of blocks a, b, and c, a conduction voltage can be applied to the bottom select gate line of blocks a, b, and c, and zero voltage can be applied to the top select gate line of blocks a, b, and c. Because the capacitance from the word line to the channel (the channel is electrically connected to the source line) is very large, applying a turn-on voltage to all word lines and a fixed voltage to all source lines helps stabilize the turn-on voltage. This also eliminates the need for additional decoupling capacitors for the turn-on voltage, thereby reducing the impact of turn-on voltage noise during read operations and reducing chip area. Furthermore, Vpass is greater than VS, and the voltage difference between Vpass and VS is made as large as possible during voltage construction, thus eliminating read disturb.

[0031] S103: Before reading the Mth memory block to be read, the source line in the Mth memory block to be read is set to 0 voltage, and when reading the Mth memory block to be read, the source line in the (M+1)th memory block to be read in the preset reading order is set to 0 voltage; M is an integer greater than or equal to 1.

[0032] Furthermore, setting the source line in the Mth memory block to be read to 0 voltage includes: The source line in the Mth memory block to be read is discharged from the fixed voltage to 0 voltage.

[0033] Setting the source line of the (M+1)th memory block to be read in the preset reading order to 0 voltage includes: The source line in the (M+1)th memory block to be read, which is located after the Mth memory block to be read in the preset reading order, is discharged to 0 voltage by the fixed voltage.

[0034] In practical applications, each selected memory block in the target 3D flash memory array needs to be read sequentially according to a preset reading order. When it is determined that the next memory block to be read is the Mth memory block, that is, before reading the Mth memory block, the voltage of the Mth memory block needs to be established, including setting the source line of the Mth memory block to 0 voltage. Continuing with the example of the target 3D flash memory array including memory blocks a, b, and c, and all three blocks are selected for data reading, if the preset reading order is known to be "Block a→Block b→Block c" and the Mth memory block is Block a, then when it is determined that Block a will be read, the source line of Block a is set to 0 voltage (grounded), that is, the source line is discharged from a fixed voltage to 0 voltage (GND), and when reading Block a (at the last word line Wla of Block a)... <n>Before the read operation is completed, the source lines in Block b are set to 0 voltage, that is, the source lines are discharged from a fixed voltage to 0 voltage. Similarly, when the Mth memory block to be read is Block b, when it is determined that Block b will be read (during the reading of Block a), the source lines in Block b are discharged from a fixed voltage to 0 voltage (GND), and when reading Block b, the source lines in Block c are discharged from a fixed voltage to 0 voltage. In this way, by discharging the source lines in the memory blocks to be read in advance, read interference is avoided.

[0035] S104: Adjust the selected word line in the Mth memory block to be read from the on-state voltage to the read-state voltage, and control the top selection gate and bottom selection gate corresponding to the Mth memory block to be read to be turned on, so as to perform data reading.

[0036] In practical applications, for each memory block to be read, during a read operation, the top and bottom selection gates of the current memory block to be read need to be turned on according to the given address, and the word lines in the memory block to be read are selected sequentially according to the layer order. Then, the selected word lines are adjusted from the on voltage to the read voltage to realize the data reading of the memory block to be read. In this way, combined with the voltage control method in the above-mentioned read operation process, each memory block to be read in the target 3D flash memory array is traversed according to the preset read order, thereby realizing the data reading of the target 3D flash memory array. Continuing with the example of the target 3D flash memory array including memory blocks a, b, and c to be read, and all three blocks are selected for data reading, when the Mth memory block to be read is Block a, then when reading Block a, it is necessary to follow the layer order (WLa)... <0> To WLa <n>First, select one word line in Block a, adjust its on-state voltage to the read voltage, and read the data on the current word line (the remaining unselected word lines need to maintain their on-state voltage). During the reading process, read the data sequentially (TSGa... <0> To TSGa <1> The voltage of each selected top selection gate line is adjusted from 0 to the on-state voltage (the voltage of the remaining unselected top selection gate lines needs to be kept at 0), thereby sequentially reading the data on the word lines corresponding to each top selection gate line. After all the data (on all word lines corresponding to the top selection gate lines) has been read, the word line is switched, and the top selection word lines are selected sequentially again to read the data on the selected word lines. This process is repeated until all the data on all word lines in Block a has been read. Then, the process switches to Block b for data reading. After all the data on all word lines in Block b has been read, the process switches to Block c for data reading. It is understood that the data reading process in Block b and Block c is the same as in Block a, and will not be elaborated here. The data reading process for the target 3D flash memory array is considered complete after all selected memory blocks have been read. At this point, the source lines of all memory blocks to be read are recharged to a fixed voltage.

[0037] In summary, this application first needs to determine the preset read order corresponding to each memory block to be read in the target 3D flash memory array, and apply a conduction voltage to the word lines of all memory blocks to be read in the target 3D flash memory array before the read operation. Before reading the Mth memory block to be read, the source line of the Mth memory block to be read needs to be set to 0 voltage. Then, when reading the Mth memory block to be read, the selected word line of the Mth memory block to be read is adjusted from the conduction voltage to the read voltage, and the top selection gate and bottom selection gate corresponding to the Mth memory block to be read are controlled to be turned on to perform data reading. In addition, when reading the Mth memory block to be read, the source line of the (M+1)th memory block to be read after the Mth memory block in the preset read order needs to be set to 0 voltage. M is an integer greater than or equal to 1. Thus, by applying a conduction voltage to the word lines of all memory blocks before the read operation and performing a discharge operation on the source line of the next memory block to be read before the read operation of the current memory block is completed, the voltage settling time during memory block switching is reduced, effectively improving the data read speed of the 3D flash memory array.

[0038] Figure 3 This is a schematic diagram of a data reading device for a three-dimensional flash memory array, provided as an embodiment of this application. (Combined with...) Figure 3 As shown, the data reading device 300 includes: The determining module 301 is used to determine the preset reading order corresponding to each storage block to be read in the target three-dimensional flash memory array; The first voltage preset module 302 is used to apply a conduction voltage to the word lines of all the memory blocks to be read in the target three-dimensional flash memory array before the read operation. The first voltage adjustment module 303 is used to set the source line of the Mth memory block to 0 voltage before reading the Mth memory block to be read, and to set the source line of the (M+1)th memory block to be read after the Mth memory block to be read in the preset reading order to 0 voltage when reading the Mth memory block to be read; M is an integer greater than or equal to 1; The second voltage adjustment module 304 is used to adjust the selected word line in the Mth memory block to be read from the conduction voltage to the read voltage, and control the top selection gate and bottom selection gate corresponding to the Mth memory block to be read to be turned on, so as to perform data reading.

[0039] As one implementation, regarding how to construct the voltage, the data reading device 300 further includes: a second voltage preset module; the second voltage preset module is used for: Before the read operation, a fixed voltage is applied to the source lines of all memory blocks to be read in the target 3D flash memory array; the fixed voltage is less than the on-state voltage.

[0040] As one implementation, regarding how to construct the voltage, the data reading device 300 further includes: a third voltage preset module; the third voltage preset module is used for: Before the read operation, apply a zero voltage to the top selected gate line and an on voltage to the bottom selected gate line in all the memory blocks to be read in the target 3D flash array.

[0041] As one implementation method, regarding how to set the source line in the Mth memory block to be read to 0 voltage, the first voltage adjustment module 303 is specifically used for: The source line in the Mth memory block to be read is discharged from the fixed voltage to 0 voltage.

[0042] As one implementation method, regarding how to set the source line in the Mth memory block to be read to 0 voltage, the aforementioned first voltage adjustment module 303 is further used for: The source line in the (M+1)th memory block to be read, which is located after the Mth memory block to be read in the preset reading order, is discharged to 0 voltage by the fixed voltage.

[0043] In summary, this application first needs to determine the preset read order corresponding to each memory block to be read in the target 3D flash memory array, and apply a conduction voltage to the word lines of all memory blocks to be read in the target 3D flash memory array before the read operation. Before reading the Mth memory block to be read, the source line of the Mth memory block to be read needs to be set to 0 voltage. Then, when reading the Mth memory block to be read, the selected word line of the Mth memory block to be read is adjusted from the conduction voltage to the read voltage, and the top selection gate and bottom selection gate corresponding to the Mth memory block to be read are controlled to be turned on to perform data reading. In addition, when reading the Mth memory block to be read, the source line of the (M+1)th memory block to be read after the Mth memory block in the preset read order needs to be set to 0 voltage. M is an integer greater than or equal to 1. Thus, by applying a conduction voltage to the word lines of all memory blocks before the read operation and performing a discharge operation on the source line of the next memory block to be read before the read operation of the current memory block is completed, the voltage settling time during memory block switching is reduced, effectively improving the data read speed of the 3D flash memory array.

[0044] In addition, this application also provides a data reading device for a three-dimensional flash memory array, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the data reading method for a three-dimensional flash memory array as described above.

[0045] In addition, this application also provides a readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the data reading method for a three-dimensional flash memory array as described above.

[0046] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.< / n> < / n>

Claims

1. A data reading method for a three-dimensional flash memory array, characterized in that, The data reading method includes: Determine the preset reading order for each memory block to be read in the target 3D flash memory array; Before the read operation, an on-state voltage is applied to the word lines of all memory blocks to be read in the target 3D flash memory array; Before reading the Mth memory block to be read, the source lines in the Mth memory block to be read are set to 0 voltage, and when reading the Mth memory block to be read, the source lines in the (M+1)th memory block to be read in the preset reading order are set to 0 voltage; M is an integer greater than or equal to 1; The selected word line in the Mth memory block to be read is adjusted from the on-state voltage to the read-state voltage, and the top and bottom selection gates corresponding to the Mth memory block to be read are turned on to perform data reading.

2. The data reading method according to claim 1, characterized in that, The data reading method further includes: Before the read operation, a fixed voltage is applied to the source lines of all memory blocks to be read in the target 3D flash memory array; the fixed voltage is less than the on-state voltage.

3. The data reading method according to claim 1, characterized in that, The data reading method further includes: Before the read operation, apply a zero voltage to the top selected gate line and an on voltage to the bottom selected gate line in all the memory blocks to be read in the target 3D flash array.

4. The data reading method according to claim 2, characterized in that, Setting the source line in the Mth memory block to be read to 0 voltage includes: The source line in the Mth memory block to be read is discharged from the fixed voltage to 0 voltage.

5. The data reading method according to claim 2, characterized in that, Setting the source line of the (M+1)th memory block to be read in the preset reading order to 0 voltage includes: The source line in the (M+1)th memory block to be read, which is located after the Mth memory block to be read in the preset reading order, is discharged to 0 voltage by the fixed voltage.

6. A data reading device for a three-dimensional flash memory array, characterized in that, include: The determination module is used to determine the preset reading order corresponding to each storage block to be read in the target 3D flash memory array; The first voltage preset module is used to apply a conduction voltage to the word lines of all the memory blocks to be read in the target three-dimensional flash memory array before the read operation; The first voltage regulation module is used to set the source line of the Mth memory block to 0 voltage before reading the Mth memory block to be read, and to set the source line of the (M+1)th memory block to be read after the Mth memory block to be read in the preset reading order to 0 voltage when reading the Mth memory block to be read; M is an integer greater than or equal to 1; The second voltage adjustment module is used to adjust the selected word line in the Mth memory block to be read from the conduction voltage to the read voltage, and control the top selection gate and bottom selection gate corresponding to the Mth memory block to be read to be turned on, so as to perform data reading.

7. The data reading device according to claim 6, characterized in that, The data reading device further includes: a second voltage preset module; The second voltage preset module is used to apply a fixed voltage to the source lines of all memory blocks to be read in the target 3D flash memory array before the read operation; the fixed voltage is less than the turn-on voltage.

8. The data reading device according to claim 6, characterized in that, The data reading device further includes: a third voltage preset module; The third voltage preset module is used to apply 0 voltage to the top selected gate line and apply on voltage to the bottom selected gate line of all the storage blocks to be read in the target three-dimensional flash memory array before the read operation.

9. A data reading device for a three-dimensional flash memory array, characterized in that, include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the data reading method for a three-dimensional flash memory array as described in any one of claims 1 to 5.

10. A readable storage medium, characterized in that, The readable storage medium stores a computer program that, when executed by a processor, implements the steps of the data reading method for a three-dimensional flash memory array as described in any one of claims 1 to 5.

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