Ferroelectric memory circuit

Abstract

This disclosure relates to a ferroelectric memory circuit, comprising: a memory array including multiple memory blocks, each memory block including multiple sub-blocks, each sub-block including multiple rows and columns of memory cells; a multi-level bit line structure including: sub-block level bit lines, each sub-block being configured with N pairs of complementary sub-block bit lines, each pair of sub-block bit lines connecting to memory cells in the same column within the sub-block; block level bit lines, each memory block being configured with N pairs of complementary block level bit lines, the N pairs of sub-block bit lines of all sub-blocks within the memory block converging to the N pairs of block level bit lines via corresponding sub-block transmission gates within the memory block; global bit lines, configured with N pairs of complementary global bit lines, the N pairs of block level bit lines of all memory blocks converging to the N pairs of global bit lines via corresponding block transmission gates; and N sensitive amplifiers, each connected to the N pairs of global bit lines, for amplifying differential signals read from selected sub-blocks electrically connected to the N pairs of global bit lines. This reduces the chip core area and static power consumption.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and in particular to a ferroelectric memory circuit. Background Technology

[0002] In traditional ferroelectric memory arrays, the number of sensitive amplifiers increases linearly with the number of columns in the memory array. Each column bit line requires an independent sensitive amplifier to detect its minute voltage difference in order to complete data reading. As memory capacity increases from the Kb level to the Mb level and even higher, the number of columns in the memory array increases dramatically, leading to a proportional increase in the number of sensitive amplifiers.

[0003] However, the sensitive amplifier and its associated circuitry occupy a large proportion of the chip's core area, and the static power consumption accumulated by the sensitive amplifier and its associated circuitry, including DC power consumption and leakage power consumption, increases. Therefore, how to reduce the chip's core area and static power consumption is one of the problems that needs to be solved. Summary of the Invention

[0004] In view of this, this disclosure proposes a ferroelectric memory circuit that can reduce chip core area and static power consumption.

[0005] According to a first aspect of this disclosure, a ferroelectric memory circuit is provided, comprising: a memory array including multiple memory blocks, each memory block including multiple sub-blocks, each sub-block including multiple rows and columns of memory cells; a multi-level bit line structure including: sub-block level bit lines, each sub-block being configured with N pairs of complementary sub-block bit lines, where N is the total read / write bit width, and each pair of sub-block bit lines connecting memory cells in the same column within the sub-block; block level bit lines, each memory block being configured with N pairs of complementary block level bit lines, where the N pairs of sub-block bit lines of all sub-blocks within the memory block are converged to the N pairs of block level bit lines via corresponding sub-block transmission gates within the memory block; global bit lines, configured with N pairs of complementary global bit lines, where the N pairs of block level bit lines of all memory blocks are converged to the N pairs of global bit lines via corresponding block transmission gates; and N sensitive amplifiers, respectively connected to the N pairs of global bit lines, for amplifying differential signals read from selected sub-blocks that are electrically connected to the N pairs of global bit lines. The multi-level bit line structure is used to converge the bit line signals of the selected sub-blocks to the global bit line in a hierarchical manner according to the sub-block level bit line, the block level bit line, and the global bit line, so that multiple sub-blocks can share the N sensitive amplifiers.

[0006] In one possible implementation, the block transfer gate corresponding to each memory block is located between the memory block and the global bit line, outside the memory block, and unselected memory blocks are electrically isolated from the global bit line through the block transfer gate.

[0007] In one possible implementation, the ferroelectric memory circuit further includes: a word line hierarchical driving module, used to generate a global word line enable signal, and to perform a logical AND operation between the global word line enable signal and a block enable signal, a sub-block enable signal, and a row enable signal, respectively, to generate a driving signal for word lines that activate only the target row of the target sub-block in the target memory block.

[0008] In one possible implementation, the ferroelectric memory circuit further includes: a global board line; multiple sector-level board lines, each sector containing multiple rows of memory cells; and an array of board line transmission modules, each board line transmission module being connected between the global board line and a sector-level board line and controlled by a sector strobe signal. The corresponding board line transmission module is activated only when the sector strobe signal is valid, transmitting the global board line enable signal to the sector-level board line connected to the activated board line transmission module.

[0009] In one possible implementation, the board line transmission module includes: a transmission gate controlled by the sector gating signal; and a first transistor for discharging residual charge on the sector-level board line when the sector gating signal is invalid.

[0010] In one possible implementation, each sensitive amplifier includes: a first PMOS transistor whose gate is connected to a global bit line and whose source is connected to a first intermediate node; a second PMOS transistor whose gate is connected to a complementary global bit line and whose source is connected to the first intermediate node; a fifth PMOS transistor whose gate, source, and drain are respectively connected to a precharge signal, a power supply, and the first intermediate node; a third PMOS transistor whose source is connected to the drain of the first PMOS transistor and whose drain is connected to a first output node; a first NMOS transistor whose gate is connected to the gate of the third PMOS transistor, whose drain is connected to the drain of the third PMOS transistor, and whose source is connected to ground; a fourth PMOS transistor whose source is connected to the drain of the second PMOS transistor and whose drain is connected to a second output node; a second NMOS transistor whose source is connected to ground and whose drain is connected to the drain of the fourth PMOS transistor, and the common connection point of the gate of the second PMOS transistor and the gate of the third PMOS transistor is connected to the common connection point of the gate of the first NMOS transistor and the gate of the third PMOS transistor.

[0011] In one possible implementation, the ferroelectric memory circuit further includes a bit line driving circuit comprising: a sixth PMOS transistor whose gate receives a first control signal, whose source is connected to a low power supply voltage, and whose drain is connected to a global bit line; a third NMOS transistor whose gate receives a second control signal, whose source is connected to the ground terminal, and whose drain is connected to a global bit line; a fourth NMOS transistor whose gate receives a pre-charge signal, whose source is connected to the ground terminal, and whose drain is connected to a global bit line; a seventh PMOS transistor whose gate receives a third control signal, whose source is connected to the low power supply voltage, and whose drain is connected to a complementary global bit line; a fifth NMOS transistor whose gate receives a fourth control signal, whose source is connected to the ground terminal, and whose drain is connected to a complementary global bit line; and a sixth NMOS transistor whose gate receives the pre-charge signal, whose source is connected to the ground terminal, and whose drain is connected to a complementary global bit line.

[0012] In one possible implementation, the sub-block transmission gate includes NMOS transistors and PMOS transistors connected in parallel, and is turned on or off under the control of a sub-block enable signal; and / or the block transmission gate includes NMOS transistors and PMOS transistors connected in parallel, and is turned on or off under the control of a block enable signal.

[0013] In one possible implementation, the ferroelectric memory circuit further includes: an address decoding module, used to generate block strobe signals and sub-block strobe signals according to the received address signals, so as to control the opening or closing of the block transmission gate and the sub-block transmission gate, so that the N pairs of global bit lines are electrically connected to the N pairs of sub-block bit lines of the selected sub-block.

[0014] In one possible implementation, the storage cell includes two ferroelectric capacitors and two gating transistors.

[0015] Through this disclosure, in the ferroelectric memory circuit, the memory array adopts a three-level memory architecture, and the bit line adopts a three-level bit line structure. In this way, the bit lines of all sub-blocks can be converged to the global bit line through selectively conducting transmission gates. Therefore, only N sensitive amplifiers are needed to read and amplify the N bits of data of the selected sub-block, thereby realizing the multiplexing of sensitive amplifiers among multiple sub-blocks, significantly reducing the number of sensitive amplifiers used, thereby reducing the chip core area and static power consumption, and thus realizing high-density and low-cost embedded ferroelectric memory.

[0016] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0017] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0018] Figures 1-2 A schematic diagram of a ferroelectric memory circuit according to an embodiment of the present disclosure is shown.

[0019] Figures 3-5 A schematic diagram illustrating the analysis of a load bitline based on a bitline hierarchical architecture according to an embodiment of the present disclosure is shown.

[0020] Figure 6 A schematic diagram of a word line hierarchical driving structure according to an embodiment of the present disclosure is shown.

[0021] Figure 7 A schematic diagram of a board line hierarchical driving structure according to an embodiment of the present disclosure is shown.

[0022] Figure 8 A circuit diagram of a board-line transmission module according to an embodiment of the present disclosure is shown.

[0023] Figure 9 A schematic diagram of a sensitive amplifier according to an embodiment of the present disclosure is shown.

[0024] Figure 10 A schematic diagram of a bit line driving circuit according to an embodiment of the present disclosure is shown.

[0025] Figure 11 An overall block diagram of a ferroelectric memory circuit according to an embodiment of the present disclosure is shown. Detailed Implementation

[0026] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0027] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0028] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0029] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0030] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0031] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0032] Figures 1-2 A schematic diagram of a ferroelectric memory circuit according to an embodiment of the present disclosure is shown. Figures 1-2 As shown, the ferroelectric memory circuit may include a memory array, a multi-level bit line structure, and N sensitive amplifiers, where N is the total read / write bit width, including data bits and ECC check bits. The memory array may include multiple memory blocks, each memory block may include multiple sub-blocks, and each sub-block may include multiple rows and columns of memory cells. The N sensitive amplifiers are respectively connected to the N pairs of global bit lines to amplify the differential signals read from the selected sub-blocks that are electrically connected to the N pairs of global bit lines.

[0033] A multi-level bitline structure can include sub-block level bitlines, block level bitlines, and global bitlines, hence it is also called a three-level bitline structure. Each sub-block is configured with N pairs of complementary sub-block bitlines, and each pair of sub-block bitlines connects to the memory cells in the same column within the sub-block. Each memory block is configured with N pairs of complementary block level bitlines, and the N pairs of sub-block bitlines from all sub-blocks within the memory block are converged to the N pairs of block level bitlines via the corresponding sub-block transmission gates within the memory block. It also has N pairs of complementary global bitlines, and the N pairs of block level bitlines from all memory blocks are converged to the N pairs of global bitlines via the corresponding block transmission gates. Therefore, the multi-level bitline structure is hierarchically divided into sub-block level bitlines, block level bitlines, and global bitlines, achieving precise connection between memory cells and sensitive amplifiers through a hierarchical convergence architecture. During read operations, only selected sub-blocks establish a conduction path with the global bitlines through the corresponding sub-block transmission gates and block transmission gates; unselected sub-blocks and memory blocks are isolated from the global bitlines.

[0034] In this embodiment, the storage array adopts a multi-level modular design, including multiple independent storage blocks (BLOCK), each storage block can be further divided into multiple sub-blocks (SUB_BLOCK), and each sub-block consists of multiple rows and columns of storage units, forming a three-level storage architecture of storage block-sub-block-storage unit.

[0035] As the basic building block of a storage array, a storage block can independently perform data storage and read / write operations. Multiple storage blocks are arranged in parallel to form a large-capacity storage space, supporting independent addressing and control of different storage areas.

[0036] A sub-block is a smaller unit within a storage block, and the number of storage units contained in each sub-block can be designed according to storage density requirements. Sub-blocking helps to achieve local control and signal isolation within storage units, reducing interference between storage units.

[0037] In some embodiments, each storage cell consists of two ferroelectric capacitors and two gating transistors. The residual polarization characteristics of the ferroelectric capacitors are used to achieve non-volatile data storage. The two gating transistors are used to control the data read and write paths, respectively, to ensure the accuracy and reliability of data reading and writing.

[0038] For example, such as Figures 1-2 and Figure 11 As shown, the ferroelectric memory circuit uses a 14-bit wide address bus ADDR[13:0] and a 39-bit wide data bus. Therefore, in this embodiment, N can be 39, with 32 bits used for data and 7 bits used for Error Correction Code (ECC) verification. ECC verification can effectively improve the data storage reliability of the ferroelectric memory and reduce the probability of errors during data transmission and storage.

[0039] like Figures 1-2 and Figure 11 As shown, the storage array is divided into eight storage blocks, namely BLOCK0 to BLOCK7, with a storage capacity of 2K×39bit per block. Each storage block is further subdivided into eight sub-blocks, namely SUB_BLOCK0 to SUB_BLOCK7, with each sub-block containing 256 rows × 39bit storage units.

[0040] The multi-level partitioning architecture described above not only integrates large-capacity storage space, but also enhances the flexibility of storage management through the subdivision of sub-blocks, facilitating independent addressing, read / write control, and fault isolation for different storage areas.

[0041] It should be understood that this embodiment does not impose specific restrictions on the capacity and size of storage blocks, sub-blocks, and individual storage units in the storage array. The capacity and performance requirements of the actual application scenario can be flexibly adjusted to any suitable parameter configuration.

[0042] In this embodiment, each sub-block is configured with N pairs of complementary sub-block bit lines. Each pair of sub-block bit lines connects to all memory cells in the same column within the sub-block, forming a one-to-one column-level signal acquisition path. This allows for direct acquisition of differential read signals from memory cells within the sub-block. Simultaneously, the differential structure of the complementary bit lines effectively cancels common-mode interference, improving the signal-to-noise ratio of the read signal. The load on the sub-block-level bit lines is only the capacitance of a single memory cell within the sub-block, resulting in low signal transmission delay and ensuring rapid response of read and write signals.

[0043] Continuing with the example above, such as Figures 1-2 As shown, the eight sub-blocks SUB_BLOCK0 to SUB_BLOCK7 are each connected to the sub-block bit line SUB_BL[38:0] and the complementary sub-block bit line SUB_BLN[38:0], thus each sub-block is configured with 39 pairs of SUB_BL[38:0] / SUB_BLN[38:0]. Within each sub-block, each sub-block level bit line is isolated by a sub-block transmission gate, therefore each sub-block contains a total of 39 pairs of sub-block transmission gates. These sub-block transmission gates are enabled by the sub-block enable signal SUB_BLOCK_EN, for example... Figures 6-7 The SUB_BLOCK_EN[0]~SUB_BLOCK_EN[7] are enabled or disabled under the control of the SUB_BLOCK_EN[0]~SUB_BLOCK_EN[7]. Each memory block is configured with N pairs of complementary block-level bit lines to aggregate the sub-block-level bit line signals of all sub-blocks in the memory block. Specifically, the N pairs of sub-block bit lines of each sub-block in the memory block are connected to the block-level bit lines through the corresponding sub-block transmission gate. The sub-block transmission gate is controlled by the sub-block enable signal. When the target sub-block is selected, it is turned on to realize the electrical connection between the sub-block-level bit lines and the block-level bit lines; when no sub-block is selected, the sub-block transmission gate is turned off to avoid the bit lines of the unselected sub-blocks from causing load interference to the block-level bit lines. The load of the block-level bit lines is the sum of the bit line capacitances of all sub-blocks in a single memory block. By controlling the switching of the sub-block transmission gate, the signal can be locally aggregated, reducing the signal transmission load during a single read / write operation.

[0044] Continuing with the example above, such as Figures 1-2As shown, each of the eight sub-blocks within a memory block has one set of SUB_BL[38:0] / SUB_BLN[38:0], resulting in eight sets of SUB_BL[38:0] / SUB_BLN[38:0] within each memory block. These eight sets of SUB_BL[38:0] / SUB_BLN[38:0] are merged after passing through their respective sub-block transmission gates to form the block-level bit lines BLOCK_BL[38:0] / BLOCK_BLN[38:0] of that memory block. Within each memory block, each block-level bit line is isolated by a block transmission gate, resulting in a total of 78 block transmission gates within each memory block. These block transmission gates are activated by the block enable signal BLOCK_EN, for example... Figures 6-7 It can be turned on or off under the control of BLOCK_EN[0]~BLOCK_EN[7].

[0045] N pairs of complementary global bit lines are configured as the signal bus for the entire memory array, used to aggregate the block-level bit line signals of all memory blocks. Each memory block's N pairs of block-level bit lines are connected to the global bit lines through a corresponding block transmission gate. The block transmission gate is controlled by the block enable signal BLOCK_EN, which turns on when a target memory block is selected, achieving electrical connection between the block-level bit lines and the global bit lines; when no memory block is selected, the block transmission gate is off to prevent unselected memory blocks from causing load interference to the global bit lines.

[0046] Continuing with the example above, such as Figures 1-2 As shown, each storage block is configured with one set of BLOCK_BL / BLOCK_BLN[38:0]. Thus, the eight storage blocks are configured with eight sets of BLOCK_BL / BLOCK_BLN[38:0]. These eight sets of BLOCK_BL / BLOCK_BLN[38:0] are merged after passing through their respective block transfer gates to form the global bit line TOP_BL[38:0] / TOP_BLN[38:0].

[0047] The global bit line is directly connected to N sensitive amplifiers, which transmit the differential read signal of the memory cell to the sensitive amplifier for amplification. Its load is the sum of the block-level bit line capacitance of all memory blocks. By controlling the switching of the block transmission gate, global convergence of signals can be achieved, while avoiding the load of unselected memory blocks from affecting the signal transmission efficiency.

[0048] In some embodiments, such as Figure 11 As shown, the ferroelectric memory circuit may further include: an address decoding module 1110, used to generate a block strobe signal and a sub-block strobe signal according to the received address signal, so as to control the opening or closing of the block transmission gate and the sub-block transmission gate, so that the N pairs of global bit lines are electrically connected to the N pairs of sub-block bit lines of the selected sub-block.

[0049] With the help of the address decoding module 1110, precise addressing of memory cells can be achieved. In some embodiments, the address decoding module 1110 may include a block decoder 1111, a sub-block decoder 1112, and a row decoder 1113. The block decoder 1111 generates a block strobe signal based on the high-order address segment of the address signal to select a target memory block from multiple memory blocks and control the block transfer gate of the target memory block to be turned on. The sub-block decoder 1112 generates a sub-block strobe signal based on the middle-order address segment of the address signal to select a target sub-block from the target memory block and control the sub-block transfer gate of the target sub-block to be turned on. The row decoder 1113 generates a row strobe signal based on the low-order address segment of the address signal to select a target row from the target sub-block. Thus, electrical connection between N pairs of global bit lines and N pairs of sub-block bit lines of the selected sub-block can be achieved, establishing a precise signal path for subsequent read and write operations.

[0050] In some embodiments, such as Figure 11 As shown, the ferroelectric memory circuit may also include an address latch 1120, which is used to receive the externally input 14-bit address signal ADDR[13:0], split it and send it to the block decoder 1111, the sub-block decoder 1112 and the row decoder 1113 respectively, so as to provide a precise address for the location of the memory cell.

[0051] Continuing with the example above, such as Figure 11 As shown, after the externally input address signal ADDR[13:0] is latched by the address latch 1120, the block decoder 1111 selects one of the eight memory blocks according to the high-order address segment ADDR[13:11] of the address signal ADDR[13:0], and opens the 78 block transmission gates of the selected memory block, so that the global bit line TOP_BL[38:0] / TOP_BLN[38:0] is electrically connected to the block-level bit line BLOCK_BL / BLOCK_BLN[38:0] of the selected memory block, thus completing the signal path construction at the memory block level.

[0052] Then, the sub-block decoder 1112 selects one of the eight sub-blocks within the selected memory block according to the middle address segment ADDR[10:8] of the address signal ADDR[13:0], and opens the 39 pairs of sub-block transmission gates of the selected sub-block, so that the sub-block bit lines SUB_BL[38:0] / SUB_BLN[38:0] of the selected sub-block are connected to the block-level bit lines BLOCK_BL / BLOCK_BLN[38:0] of the selected memory block. Thus, the global bit lines TOP_BL[38:0] / TOP_BLN[38:0] are electrically connected to the sub-block bit lines SUB_BL[38:0] / SUB_BLN[38:0] of the selected sub-block, completing the signal path construction at the sub-block level.

[0053] The row decoder 1113 selects a row within the selected sub-block based on the low address segment ADDR[7:0] of the address signal ADDR[13:0]. The 39 bits of data of the selected row are used as the smallest read / write unit, and read / write operations can be performed on the selected row.

[0054] In some embodiments, such as Figure 11 As shown, the ferroelectric memory circuit may further include: a data latch 1130, used to receive 39 pairs of data DIN[38:0] from external input, temporarily store the data, and then send it to the sensitive amplifier and BL control module 1140; the sensitive amplifier and BL control module 1140, used to amplify the weak signal read from the memory cell, and at the same time control the working state of the bit line (BL) to ensure the accuracy of data reading and writing; and a control logic and timing generation module 1150, used to receive control signals such as CS (chip select), OE (output enable), WE (write enable), S1, SO, etc., and generate unified timing signals such as word line enable signal WL_EN and board line enable signal PL to coordinate the working timing of each module and ensure that the storage operation is carried out in an orderly manner.

[0055] During the write operation, the sensitive amplifier and BL control module 1140 drive the global bit lines TOP_BL[38:0] / TOP_BLN[38:0] according to the 39 pairs of data DIN[38:0] input from the outside, and transmit them to the sub-block bit lines SUB_BL[38:0] / SUB_BLN[38:0] of the target sub-block through two levels of transmission gates: block-level transmission gate and sub-block-level transmission gate. After the voltage on the sub-block bit lines SUB_BL[38:0] / SUB_BLN[38:0] stabilizes, the write operation is performed on the selected row memory cell of the target sub-block according to the preset ferroelectric memory write timing, and non-volatile storage is achieved by utilizing the residual polarization characteristics of the ferroelectric capacitor.

[0056] During the read operation, the data stored in the target row of the target sub-block of the target memory block forms 39 pairs of voltage differences on the sub-block bit lines SUB_BL[38:0] / SUB_BLN[38:0]. 39 pairs of voltage differences The data is directly transmitted to the global bit line TOP_BL[38:0] / TOP_BLN[38:0] through the above two-stage transmission gates. The 39 sensitive amplifiers connected to the global bit line TOP_BL[38:0] / TOP_BLN[38:0] then transmit the data to 39 pairs of voltage difference pairs. The data is amplified and output as 39-bit data DOUT[38:0]. Simultaneously, after receiving the output data from the sensitive amplifier, the sensitive amplifier and BL control module 1140 re-drive the global bit lines TOP_BL[38:0] / TOP_BLN[38:0] and the sub-block bit lines SUB_BL[38:0] / SUB_BLN[38:0], writing the data back to the corresponding rows. This avoids damage to the stored data during read operations.

[0057] According to this embodiment, in the ferroelectric memory circuit, the memory array adopts a three-level memory architecture, and the bit line adopts a three-level bit line structure. In this way, the bit lines of all sub-blocks can be converged to the global bit line through selectively conducting transmission gates. Therefore, only N sensitive amplifiers are needed to read and amplify the N bits of data of the selected sub-block, thereby realizing the multiplexing of sensitive amplifiers among multiple sub-blocks, significantly reducing the number of sensitive amplifiers used, thereby reducing the chip core area and static power consumption, and thus realizing a high-density and low-cost embedded ferroelectric memory.

[0058] In addition, within each storage block, each block-level bit line is isolated by a block transmission gate, and within each sub-block, each sub-block bit line is isolated by a sub-block transmission gate. Therefore, the range of signal interference can be limited to a single sub-block or storage block, thereby avoiding signal crosstalk problems caused by large-scale bit line interconnection. At the same time, ECC verification can further ensure the accuracy of data reading and writing.

[0059] In some embodiments, the sub-block transmission gate includes NMOS transistors and PMOS transistors connected in parallel, and is turned on or off under the control of a sub-block enable signal; and / or the block transmission gate includes NMOS transistors and PMOS transistors connected in parallel, and is turned on or off under the control of a block enable signal.

[0060] The sub-block transmission gate can be a CMOS complementary transmission gate, consisting of an NMOS transistor and a PMOS transistor connected in parallel. In practical design, the sizes of the NMOS and PMOS transistors can be appropriately set according to the manufacturing process. The on / off state of this CMOS complementary transmission gate is controlled by the sub-block enable signal. The gates of the NMOS and PMOS transistors are connected to the sub-block enable signal and its inverted signal, respectively. The source and drain are connected in parallel and then connected to the sub-block bit line and the block-level bit line. When the sub-block enable signal is high, the NMOS transistor is turned on, and the PMOS transistor is turned on under the control of the inverted sub-block enable signal, thus forming a low-impedance transmission path. When the sub-block enable signal is low, both the NMOS and PMOS transistors are turned off, thus forming high-impedance isolation.

[0061] By using CMOS complementary transmission gates as sub-block transmission gates, a low-impedance path can be achieved when the sub-block is selected, and a high-impedance isolation can be formed when it is not selected, effectively reducing the load interference of the unselected sub-block on the block-level bit line.

[0062] Similarly, the block transmission gate can be a CMOS complementary transmission gate, consisting of an NMOS transistor and a PMOS transistor connected in parallel. In actual design, the sizes of the NMOS and PMOS transistors can be appropriately set according to the manufacturing process. The conduction and cutoff of this CMOS complementary transmission gate are controlled by the block enable signal. The gates of the NMOS and PMOS transistors are connected to the block enable signal and its inverted signal, respectively. The source and drain are connected in parallel and then connected to the block-level bit line and the global bit line. When the block enable signal is high, the NMOS transistor is turned on, and the PMOS transistor is turned on under the control of the inverted block enable signal, thus forming a low-impedance transmission path. When the block enable signal is low, both the PMOS and NMOS transistors are turned off, thus forming high-impedance isolation.

[0063] By using CMOS complementary transmission gates as block transmission gates, a low-impedance path can be achieved when the block is selected, and a high-impedance isolation can be formed when it is not selected, effectively reducing the load interference of the unselected block on the global bit line.

[0064] Continuing with the example above, such as Figure 3 As shown, assuming the high-order address segment ADDR[13:11] of the address signal ADDR[13:0] is 001 and the middle-order address segment ADDR[10:8] is 101, then the address decoding module 1110 determines whether to enable based on these address segments. Figure 3 The SUB_BLOCK5 block within BLOCK1. If a row in SUB_BLOCK5 is selected for a read operation, the bit line connects to 14 transmission gates: 7 sub-block transmission gates within BLOCK1 and 7 block transmission gates outside BLOCK1. Additionally, the bit line connects to the drain equivalent capacitance of the gate transistors for the remaining 255 memory cells in SUB_BLOCK5. Therefore, the size of the transistors included in the transmission gates can be appropriately set to avoid excessively large transistor sizes leading to excessively large total capacitance of the bit line, which would reduce the differential voltage difference during reading and affect the detection accuracy of the sensitive amplifier.

[0065] For example, in practical design, by reasonably setting the channel width, length and other dimensional parameters of the NMOS and PMOS transistors in the CMOS transmission gate, the parasitic capacitance of the transmission gate can be controlled while ensuring signal transmission capability, so as to avoid its excessive impact on the bit line capacitance.

[0066] In some embodiments, the block transfer gate corresponding to each memory block is located between the memory block and the global bit line, outside the memory block.

[0067] For example, such as Figures 3-5 As shown, a corresponding block transfer gate is set outside each storage block to isolate the load of the global bit line from the block-level bit line.

[0068] This avoids the bit line capacitors of unselected memory blocks from creating an additional load on the gating signal path, thereby reducing the effective load on the bit lines, ensuring the stability of the voltage difference during reading, and preventing the reading signal from failing to start normally due to excessive load.

[0069] In some embodiments, a total bit line capacitance model can be established, which quantizes and superimposes the parasitic capacitance of the transmission gate, the equivalent capacitance of the memory cell gating transistor, and the parasitic capacitance of the bit line itself, thereby estimating the total load of the bit line. Based on this total load, the transistor size of the transmission gate is adjusted and the memory cell layout is optimized to ensure that the bit line load is within a reasonable range and to ensure the reliability of read and write operations.

[0070] In some embodiments, such as Figure 6 As shown, the ferroelectric memory circuit further includes a word line hierarchical driving module, used to generate a global word line enable signal. This global word line enable signal is then logically ANDed with a block enable signal, a sub-block enable signal, and a row enable signal to generate a driving signal for the word line of the target row in the target sub-block of the target memory block. Therefore, the word line hierarchical driving module uses the global word line enable signal as a reference input and generates precise word line driving signals through three levels of logical AND operations.

[0071] Specifically, the word line hierarchical driver module performs a logical AND operation between the global word line enable signal WL_EN and the block enable signal BLOCK_EN to generate the block-level word line enable signal BWL (Block WL). The block-level word line enable signal is only effective when the global word line enable signal WL_EN is valid and the target memory block is selected, thereby achieving initial selection of the memory block.

[0072] Optionally, the global word line enable signal WL_EN can be used as the highest priority control signal to enable the word line driving function of the ferroelectric memory, avoiding power waste in the inactive state. Through a logical AND operation with the block enable signal BLOCK_EN, it can be ensured that only the word lines of the target memory block are selected, while the word lines of unselected memory blocks remain off. This effectively isolates the capacitive load between different memory blocks and reduces signal interference.

[0073] Then, the generated block-level word line enable signal BWL is logically ANDed with the sub-block enable signal SUB_BLOCK_EN to generate the sub-block level word line enable signal SWL (Sub Block WL). The sub-block level word line enable signal is only effective when both the target memory block and the target sub-block are selected simultaneously, thereby further narrowing the selection range. In this way, combined with the sub-block enable signal SUB_BLOCK_EN, the selection range is further refined, activating only the word lines within the target sub-block, which can prevent the load of unselected sub-blocks within the same memory block from affecting the transmission of the target signal.

[0074] Next, the generated sub-block level word line enable signal SWL is logically ANDed with the exercise enable signal LINE_EN to generate the target row word line drive signal LWL. The target row word line drive signal is only effective when the target row within the target sub-block is selected, thus precisely activating the word line of the target memory cell. In this way, by performing a logical AND operation with the exercise enable signal LINE_EN, the word line of the target row is precisely activated, ensuring that read and write operations are performed only on the target memory cell, thereby guaranteeing the accuracy of data operations.

[0075] For example, such as Figure 6 As shown, assuming that the high address segment ADDR[13:11] of the address signal ADDR[13:0] is 001 and the middle address segment ADDR[10:8] is 101, then during the word line activation selection process, the global word line enable signal WL_EN can be generated by the control logic and timing generation module 1150. The word line hierarchical driving module receives the global word line enable signal WL_EN, and performs a logical AND operation with the block enable signal BLOCK_EN[1] of BLOCK1, the sub-block enable signal SUB_BLOCK_EN[5] of SUB_BLOCK5 and the line enable signal LINE_EN of the target row. Finally, a word line driving signal is generated that only activates the target row in SUB_BLOCK5 of BLOCK1. The word line driving signal is output to the target row, and the word lines of all 39 2T2C array units of the target row are pulled high, and 39 bits of data are read out at the same time.

[0076] According to this embodiment, word line drive signals are generated by performing a logical AND operation on the global enable signal, block enable signal, sub-block enable signal, and execution enable signal. This ensures that only the word line of the target row containing the target sub-block of the target memory block is activated each time, thereby reducing the word line load that needs to be driven once, which helps to reduce word line drive load and improve access timing performance.

[0077] In some embodiments, such as Figure 7As shown, the ferroelectric memory circuit further includes: a global board line; multiple sector-level board lines, each sector containing multiple rows of memory cells; and a board line transmission module array, each board line transmission module being connected between the global board line and a sector-level board line and controlled by a sector strobe signal. The corresponding board line transmission module is activated only when the sector strobe signal is valid, transmitting the global board line enable signal to the sector-level board line connected to the activated board line transmission module.

[0078] Similar to word lines, board lines also employ a hierarchical driving architecture. Global board lines serve as the global control bus for the ferroelectric memory, running throughout the entire memory array and responsible for transmitting a unified global board line enable signal. Each sub-block can be divided into multiple sectors, each sector containing multiple rows of memory cells, and each sector corresponds to an independent sector-level board line to transmit the global board line enable signal to the memory cells within the corresponding sector.

[0079] For example, such as Figure 7 As shown, the board line signal (PL signal) is also processed in the same way. Figure 6 Similar hierarchical processing. The difference lies in that when the Global Board Line Enable (GPL) signal enters the sub-block, it drives a heavily loaded board line to provide board line signals for the entire sub-block. Each sub-block is divided into 64 sectors, each containing 4 rows × 39 bits of storage. The Global Board Line Enable (GPL) signal is connected to 64 board line transfer modules (PL_TRANS), and each board line transfer module is connected to one sector.

[0080] Therefore, according to this embodiment, both word lines and board lines are driven in a hierarchical manner, which can reduce the load on signal lines, speed up signal transmission and switching speed, thereby shortening the read / write cycle, improving read / write speed, and thus improving the overall performance of the ferroelectric memory.

[0081] In some embodiments, such as Figure 8 As shown, the board line transmission module includes: a transmission gate Q1, controlled by the sector gating signal SECTOR_EN; and a first transistor Q2, used to discharge residual charge of the sector-level board line when the sector gating signal SECTOR_EN is invalid.

[0082] In some embodiments, the memory cell includes two ferroelectric capacitors and two gate transistors.

[0083] If the Global Board Line Enable (GPL) signal is directly connected to the lower plate of the ferroelectric capacitors of all memory cells in the entire sub-block, it will increase the parasitic capacitance and total load, interfering with the polarization state of unselected ferroelectric capacitors and thus affecting the reliability of data storage. Therefore, this embodiment divides a sub-block into 64 sectors and sets up a corresponding board line transmission module for each sector. Only one sector's sector select signal (SECTOR_EN) is active at a time. The board line transmission module will only be activated when the corresponding sector's sector select signal (SECTOR_EN) is active, and at this time, the Global Board Line Enable (GPL) signal only connects to the memory cells within that sector.

[0084] Taking a 2T2C memory cell with 4 rows × 39 bits in a single sector as an example, each memory cell contains 2 ferroelectric capacitors. Therefore, during a single selection, the global board line enable signal GPL only needs to drive 4 × 39 × 2, a total of 312 ferroelectric capacitors, which greatly reduces the load scale, effectively ensures the transmission quality of board line signals, and avoids polarization interference to unselected memory cells.

[0085] In addition, the board line transmission module in the unselected sector is in the off state, forming high impedance isolation, which avoids the capacitive load of the unselected sector from consuming the global board line enable signal GPL, thereby reducing static power consumption.

[0086] It should be understood that this embodiment does not limit the number of sectors or the size of a single sector storage unit, and the number of sectors and the size of a single sector storage unit can be flexibly adjusted according to the capacity requirements of the ferroelectric memory.

[0087] Therefore, this embodiment designs a board line transmission module and constructs a hierarchical driving architecture for global board lines and local board lines. The global board line is connected to the input of multiple board line transmission modules. Each board line transmission module is responsible for driving the corresponding small range of local board lines. The local board line is only connected to the memory unit within a sector. Only when the sector is selected can the global board line enable signal be transmitted to the local board line with a small voltage loss.

[0088] This significantly reduces the effective load capacitance of the board lines during a single read / write operation, resulting in steeper signal edges and improved read / write speeds. Furthermore, it reduces the interference range of the board line signals from the entire sub-block to a smaller sector, thereby reducing disturbances to unselected memory cells and improving the data retention and reliability of ferroelectric memory.

[0089] In this embodiment, a parallel word line and board line architecture is adopted. The corresponding word line is activated only when the target row is selected, avoiding signal crosstalk in non-selected areas and reducing unnecessary capacitor charging and discharging losses, effectively reducing overall power consumption and improving the signal-to-noise ratio of data reading and writing. In addition, the parallel word line and board line architecture can flexibly adapt to different sizes of memory array designs. By increasing the number of rows or memory cells in the sub-block, the storage capacity of the ferroelectric memory can be expanded without significantly increasing the signal transmission load due to the expansion of the memory array size. Therefore, it is suitable for large-capacity ferroelectric memories.

[0090] Therefore, while ensuring data read and write efficiency, it also takes into account low power consumption, low interference and high scalability, making it suitable for ferroelectric memories with high requirements for storage density and energy efficiency.

[0091] In some embodiments, such as Figure 9 As shown, each sensitive amplifier may include: a first PMOS transistor P1, whose gate is connected to the global bit line TOP_BL and whose source is connected to the first intermediate node; a second PMOS transistor P2, whose gate is connected to the complementary global bit line TOP_BLN and whose source is connected to the first intermediate node; a fifth PMOS transistor P5, whose gate, source, and drain are respectively connected to the precharge signal, the power supply VDD, and the sources of the first PMOS transistor P1 and the second PMOS transistor P2; a third PMOS transistor P3, whose source is connected to the drain of the first PMOS transistor P1 and whose drain is connected to the first output node OUTN; and a first N MOS transistor N1 has its gate connected to the gate of the third PMOS transistor P3, its drain connected to the drain of the third PMOS transistor P3, and its source connected to ground VSS; fourth PMOS transistor P4 has its source connected to the drain of the second PMOS transistor P2, and its drain connected to the second output node OUT; second NMOS transistor N2 has its source connected to ground VSS, its drain connected to the drain of the fourth PMOS transistor P4, and the common connection point of its gate and the gate of the fourth PMOS transistor P4 is connected to the common connection point of the gate of the first NMOS transistor N1 and the gate of the third PMOS transistor P3.

[0092] In the initial state, the sensitive amplifier enters a pre-charge mode, pre-charging the voltages of both output nodes OUTN and OUT to 0, providing a uniform initial state for subsequent read operations. When a read operation is performed and the read data is 1, the voltage value of the bit line BL connected to the sensitive amplifier is greater than the voltage value of the complementary bit line BLN. At this time, the sensitive amplifier is turned on, and the fifth PMOS transistor P5 is turned on. Since the voltage value of bit line BL is greater, the charging current flowing through the second PMOS transistor P2 is greater than the charging current flowing through the first PMOS transistor P1, causing the voltage of the OUT node to rise faster than the voltage of the OUTN node.

[0093] When the voltage of the OUT node reaches the threshold voltage of the first NMOS transistor N1, the first NMOS transistor N1 turns on and begins to discharge the OUTN node. As the voltage of the OUT node continues to rise, the charging rate of the OUTN node is less than the discharging rate, and the voltage of the OUTN node begins to drop. Finally, the voltage of the OUT node is quickly pulled up to the power supply voltage VDD through the latch structure, and the voltage of the OUTN node stabilizes at 0, outputting logic 1.

[0094] Because the input of the sensitive amplifier is directly connected to the gate of the transistor, it can effectively isolate the input signal from the amplification circuit, thereby achieving high input impedance, reducing the load effect of the signal source, and avoiding signal distortion. Furthermore, the sensitive amplifier has no continuous DC current path in steady state, thus avoiding quiescent current consumption and significantly reducing quiescent power consumption, making it suitable for low-power applications.

[0095] Therefore, the sensitive amplifier according to this embodiment can not only ensure signal integrity, but also reduce static power consumption.

[0096] In some embodiments, the ferroelectric memory circuit further includes a bit line driving circuit, such as... Figure 10 As shown, it includes: a sixth PMOS transistor P6, whose gate receives a first control signal A, whose source is connected to a low power supply voltage VDDL, and whose drain is connected to the global bit line TOP_BL; a third NMOS transistor N3, whose gate receives a second control signal B, whose source is connected to the ground terminal VSS, and whose drain is connected to the global bit line TOP_BL; a fourth NMOS transistor N4, whose gate receives a precharge signal PRE, whose source is connected to the ground terminal VSS, and whose drain is connected to the global bit line TOP_BL; a seventh PMOS transistor P7, whose gate receives a third control signal C, whose source is connected to the low power supply voltage VDDL, and whose drain is connected to the complementary global bit line TOP_BLN; a fifth NMOS transistor N5, whose gate receives a fourth control signal D, whose source is connected to the ground terminal VSS, and whose drain is connected to the complementary global bit line TOP_BLN; and a sixth NMOS transistor N6, whose gate receives the precharge signal PRE, whose source is connected to the ground terminal VSS, and whose drain is connected to the complementary global bit line TOP_BLN.

[0097] This bit line driving circuit can precisely control the working state of the global bit line TOP_BL and the complementary global bit line TOP_BLN according to the different working modes of the ferroelectric memory, adapting to the needs of all scenarios such as read, write, read-write-back and standby pre-charging.

[0098] During write operations in a ferroelectric memory, the global bit line TOP_BL and the complementary global bit line TOP_BLN are driven by externally input data. During read operations, the global bit line TOP_BL and the complementary global bit line TOP_BLN need to be kept in a high-impedance state to receive the voltage difference caused by the ferroelectric polarization switching. During read-write-back operations in a ferroelectric memory, the global bit line TOP_BL and the complementary global bit line TOP_BLN need to be driven according to the read data from the sensitive amplifier.

[0099] When the ferroelectric memory is in standby or precharge state, the precharge signal PRE is active, for example, at a high level. The fourth NMOS transistor N4 and the sixth NMOS transistor N6 are turned on to precharge the global bit line TOP_BL and the complementary global bit line TOP_BLN. At the same time, the first control signal A and the third control signal C are at a high level, the second control signal B and the fourth control signal D are at a low level, and the sixth PMOS transistor P6, the seventh PMOS transistor P7, the third NMOS transistor N3, and the fifth NMOS transistor N5 are all turned off. This avoids additional current loss and provides a stable initial level for subsequent read and write operations.

[0100] When the ferroelectric memory is in read mode, the global bit line TOP_BL and the complementary global bit line TOP_BLN are in a high-impedance state. The first control signal A and the third control signal C are at a high level, and the second control signal B and the fourth control signal D are at a low level. The sixth PMOS transistor P6, the seventh PMOS transistor P7, and the third NMOS transistor N3 to the sixth NMOS transistor N6 are all turned off. The global bit line TOP_BL and the complementary global bit line TOP_BLN are basically isolated from the power supply and ground, and form a loop only through the memory cell and the sensitive amplifier, thereby ensuring the accuracy of the read signal.

[0101] When the ferroelectric memory is in write mode or read-write-back mode, it is necessary to drive the global bit line TOP_BL and the complementary global bit line TOP_BLN according to the input data, such as data from the data latch or data obtained from the sensitive amplifier.

[0102] When data 1 is written, the global bit line TOP_BL is driven by VDD, the complementary global bit line TOP_BLN is driven by 0, the first control signal A and the second control signal B are low, the third control signal C and the fourth control signal D are high, the sixth PMOS transistor P6 and the fifth NMOS transistor N5 are turned on, thereby pulling the global bit line TOP_BL high and pulling the complementary global bit line TOP_BLN low.

[0103] When data 0 is written, the global bit line TOP_BL is driven by 0, the complementary global bit line TOP_BLN is driven by VDD, the first control signal A and the second control signal B are high, the third control signal C and the fourth control signal D are low, the seventh PMOS transistor P7 and the third NMOS transistor N3 are turned on, thereby pulling the global bit line TOP_BL low and pulling the complementary global bit line TOP_BLN high.

[0104] Therefore, the bit line driving circuit according to this embodiment achieves precise level control in different operating modes through flexible transistor on / off combinations. This not only ensures the signal integrity of read and write operations, but also improves the overall energy efficiency ratio of ferroelectric memory through low-power standby / pre-charge design. Thus, it can be adapted to large-scale ferroelectric memory and improves the design flexibility and robustness of ferroelectric memory.

[0105] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A ferroelectric memory circuit, characterized by comprising: include: A storage array comprises multiple storage blocks, each storage block comprises multiple sub-blocks, and each sub-block comprises multiple rows and columns of storage cells; Multi-level bitline structures include: Sub-block level bit lines, each sub-block is configured with N pairs of complementary sub-block bit lines, where N is the total read and write bit width, and each pair of sub-block bit lines connects to the storage cells in the same column within the sub-block; Block-level bit lines: Each storage block is configured with N pairs of complementary block-level bit lines. The N pairs of sub-block bit lines of all sub-blocks in the storage block are converged to the N pairs of block-level bit lines through the corresponding sub-block transmission gates in the storage block. Global bit lines are configured with N pairs of complementary global bit lines. The N pairs of block-level bit lines of all memory blocks are converged to the N pairs of global bit lines through the corresponding block transfer gates. N sensitive amplifiers, each connected to the N pairs of global bit lines, are used to amplify differential signals read from selected sub-blocks that are electrically connected to the N pairs of global bit lines.

2. The ferroelectric memory circuit according to claim 1, characterized in that, The block transfer gate corresponding to each memory block is located between the memory block and the global bit line, outside the memory block. Unselected memory blocks are electrically isolated from the global bit line through the block transfer gate.

3. The ferroelectric memory circuit of claim 1, wherein, Also includes: The word line hierarchical driving module is used to generate a global word line enable signal, and to perform a logical AND operation between the global word line enable signal and the block enable signal, the sub-block enable signal, and the row enable signal to generate a driving signal for word lines that only activate the target row of the target sub-block in the target memory block.

4. The ferroelectric memory circuit of claim 1, wherein, Also includes: Global board line; Multiple sector-level board lines, each sector containing multiple rows of storage units; The board line transmission module array, where each board line transmission module is connected between the global board line and a sector-level board line, is controlled by a sector selection signal. Specifically, the corresponding board line transmission module is activated only when the sector selection signal is valid, and the global board line enable signal is transmitted to the sector-level board line connected to the activated board line transmission module.

5. The ferroelectric memory circuit of claim 4, wherein, The board wire transmission module includes: The transmission gate is controlled by the sector gating signal; The first transistor is used to discharge residual charge on the sector-level board line when the sector strobe signal is invalid.

6. The ferroelectric memory circuit of any one of claims 1-5, wherein, Each sensitive amplifier includes: The first PMOS transistor has its gate connected to the global bit line and its source connected to the first intermediate node. The second PMOS transistor has its gate connected to the complementary global bit line and its source connected to the first intermediate node. The fifth PMOS transistor has its gate, source, and drain connected to the precharge signal, the power supply, and the first intermediate node, respectively. The source of the third PMOS transistor is connected to the drain of the first PMOS transistor, and the drain is connected to the first output node. The first NMOS transistor has its gate connected to the gate of the third PMOS transistor, its drain connected to the drain of the third PMOS transistor, and its source connected to the ground terminal. The source of the fourth PMOS transistor is connected to the drain of the second PMOS transistor, and the drain is connected to the second output node. The second NMOS transistor has its source connected to ground, its drain connected to the drain of the fourth PMOS transistor, and its gate connected to the common connection point of the gate of the fourth PMOS transistor, which is connected to the common connection point of the gate of the first NMOS transistor and the gate of the third PMOS transistor.

7. The ferroelectric memory circuit according to any one of claims 1-5, characterized in that, It also includes a bit line driving circuit, which includes: The sixth PMOS transistor receives the first control signal at its gate, connects its source to a low power supply voltage, and connects its drain to the global bit line. The third NMOS transistor receives the second control signal at its gate, connects its source to ground, and connects its drain to the global bit line. The fourth NMOS transistor receives the precharge signal at its gate, is connected to the ground terminal at its source, and is connected to the global bit line at its drain. The seventh PMOS transistor receives the third control signal at its gate, is connected to the low power supply voltage at its source, and is connected to the complementary global bit line at its drain. The fifth NMOS transistor receives the fourth control signal at its gate, its source is connected to the ground terminal, and its drain is connected to the complementary global bit line. The sixth NMOS transistor receives the precharge signal at its gate, is connected to the ground terminal at its source, and is connected to the complementary global bit line at its drain.

8. The ferroelectric memory circuit according to any one of claims 1-5, characterized in that, The sub-block transmission gate comprises NMOS and PMOS transistors connected in parallel, and is turned on or off under the control of the sub-block enable signal; and / or The block transmission gate consists of NMOS and PMOS transistors connected in parallel, and is turned on or off under the control of the block enable signal.

9. The ferroelectric memory circuit according to any one of claims 1-5, characterized in that, Also includes: The address decoding module is used to generate block strobe signals and sub-block strobe signals based on the received address signals, so as to control the opening or closing of the block transmission gate and the sub-block transmission gate, and establish an electrical connection between the N pairs of global bit lines and the N pairs of sub-block bit lines of the selected sub-block.

10. The ferroelectric memory circuit according to any one of claims 1-5, characterized in that, The storage unit includes two ferroelectric capacitors and two gate transistors.

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