A method for suppressing ferroelectric transistor write fluctuations based on capacitive voltage division negative feedback
By forming a voltage divider path between the gate terminal of the FeFET and the dielectric capacitor, and utilizing the negative feedback of the capacitor voltage divider to adjust the gate voltage of the FeFET, the write fluctuation problem of the FeFET is solved, the accuracy and consistency of in-memory calculation are improved, and the low power consumption advantage is maintained.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2026-05-20
- Publication Date
- 2026-07-31
AI Technical Summary
FeFETs suffer from significant write fluctuations in in-memory computations, which affect computational accuracy. Existing methods either incur additional overhead or sacrifice performance.
By forming a voltage divider path between the gate terminal of the FeFET and the dielectric capacitor, the gate voltage of the FeFET is adjusted using the negative feedback of the capacitor voltage divider, thereby adaptively adjusting the polarization switching rate and reducing write fluctuations.
Improve the consistency of weighted devices in FeFETs, enhance the accuracy of in-memory calculations, without increasing additional overhead or complexity, and maintain the low power consumption advantage of FeFETs.
Smart Images
Figure CN122493904A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of novel storage and in-memory computing, specifically to a method for suppressing write fluctuations in ferroelectric transistors based on capacitive voltage division negative feedback. Background Technology
[0002] The deployment of AI applications such as large language models and embodied intelligence on edge devices is becoming a mainstream trend due to its faster response times, better privacy, and lower operating costs, requiring highly reliable and energy-efficient computing equipment as hardware support. To overcome the energy efficiency and latency bottlenecks of traditional von Neumann architectures in data movement, in-memory computing (CIM) technology performs generalized matrix-vector multiplication (GEMV) operations directly within memory cells, significantly reducing the frequent movement of data between the processor and memory. Among various CIM paradigms, FeFET-based CIM has received widespread attention in recent years. FeFETs are made by integrating ferroelectric materials into MOSFET gate stacks. Compared to traditional volatile static random access memory (SRAM), they have smaller cell areas, multi-value storage capabilities, and help reduce the hardware overhead of computing systems. Furthermore, they avoid the static power consumption or refresh power consumption required for data retention and the data loading power consumption during system startup, making them highly suitable for edge devices. Compared to other emerging two-terminal non-volatile memories such as resistive random access memory (RRAM), phase-change memory (PCM), and magnetic random access memory (MRAM), FeFET also has advantages such as low write power consumption, high on / off ratio, and three-terminal structure.
[0003] However, due to the non-uniformity of ferroelectric domain distribution and the random switching characteristics of ferroelectric polarization in the polycrystalline multi-domain ferroelectric layer of FeFET, FeFET suffers from significant write fluctuations. This limits the consistency of FeFET weighted devices, affecting calculation accuracy and severely restricting the application of FeFET-based CIM technology in edge AI devices. To mitigate FeFET write fluctuations: some solutions involve gate stacking engineering, but this often leads to degradation of other performance characteristics such as retention and durability, as well as increased process complexity; some solutions propose connecting a current-limiting resistor or current-limiting transistor in series at the FeFET source, but sacrifice the dynamic range of the weighted cells; some solutions propose write verification methods similar to NAND flash, but require complex timing control circuits and high write power consumption; other solutions propose a negative feedback write method based on a source follower structure, but rely on DC path adjustment of voltage division strength, sacrificing the advantage of FeFET's zero DC write power consumption. In summary, existing methods for reducing FeFET write fluctuations all incur significant additional overhead. Summary of the Invention
[0004] To address the problems in the prior art described above, the purpose of this invention is to propose a method for suppressing write fluctuations of ferroelectric transistors based on capacitive voltage division negative feedback. This method can reduce write fluctuations of ferroelectric transistor weighting devices with extremely low additional overhead, improve the computational accuracy of in-memory computing technology based on ferroelectric transistors, and provide a highly promising hardware solution for highly reliable edge-side artificial intelligence devices.
[0005] To achieve the above objectives, the present invention provides the following technical solution:
[0006] A method for suppressing write fluctuations in ferroelectric transistors (FeFETs) based on capacitive voltage divider negative feedback, see [link to relevant documentation]. Figure 1 The gate of the FeFET is connected to the first port of a dielectric capacitor (with a capacitance of C0) (denoted as node A); during writing, a write voltage V is applied to the second port of the dielectric capacitor. W The source and drain terminals of the FeFET are grounded, creating a voltage divider path between the dielectric capacitance and the FeFET gate capacitance (capacitance C); the actual write gate voltage V of the FeFET... A The calculation formula is:
[0007]
[0008] When the gate voltage is relatively high, due to the non-ideal inversion behavior of the actual transistor channel, the gate capacitance of a FeFET generally increases with the gate voltage amplitude, forming a voltage-dependent CV relationship. This CV relationship gradually shifts with the polarization reversal of the ferroelectric layer, resulting in a change in the initial voltage division V. A1 As the gate capacitance of the FeFET increases from C1 to C2, the voltage drop across the FeFET gate capacitance changes from V0. A1 Reduce to V A2 This causes the FeFET gate capacitance to decrease from C2 to C3; the resulting negative feedback process can adaptively and dynamically adjust the actual write gate voltage V of the FeFET according to the degree of ferroelectric polarization reversal. A This causes the polarization reversal of the FeFET to converge, reducing the write fluctuations of the FeFET.
[0009] Furthermore, the ferroelectric transistor can be a unipolar ferroelectric transistor (n-type or p-type) or a bipolar ferroelectric transistor; the ferroelectric transistor can adopt a metal-ferroelectric-semiconductor structure (MFS), a metal-ferroelectric-channel-side dielectric-semiconductor structure (MFIS), a metal-ferroelectric-metal-channel-side dielectric-semiconductor structure (MFMIS), or a metal-gate-side dielectric-ferroelectric-channel-side dielectric-semiconductor structure (MIFIS); the ferroelectric layer in the ferroelectric transistor can be made of perovskite ferroelectric material, two-dimensional ferroelectric material, organic ferroelectric material, III-V group nitride ferroelectric material, or doped hafnium oxide-based ferroelectric material.
[0010] The beneficial technical effects of this invention are as follows:
[0011] This invention utilizes a voltage divider path formed by the gate capacitance and dielectric capacitance of a FeFET, combined with the voltage correlation of the FeFET gate capacitance, to achieve adaptive negative feedback adjustment of the FeFET write gate voltage. This causes the polarization reversal amount of the ferroelectric layer of the FeFET, which has fluctuating polarization reversal rate, to tend towards a convergent value, enhancing the consistency of the FeFET weighted devices. Furthermore, it does not produce other reliability degradation, additional process complexity, or sacrifice the dynamic range of the weighted units, requires no complex timing control circuits, or generate DC write power consumption. This is beneficial for improving the accuracy of in-memory computation based on FeFET, providing a highly promising hardware solution for highly reliable edge artificial intelligence. Attached Figure Description
[0012] Figure 1 This is a schematic diagram of the circuit structure of the present invention for suppressing write fluctuations of ferroelectric transistors based on capacitor voltage division negative feedback.
[0013] Figure 2 This is a schematic diagram illustrating the principle of suppressing write fluctuations in n-type ferroelectric transistors based on capacitor voltage division negative feedback.
[0014] Figure 3 This is a schematic diagram illustrating the principle of suppressing write fluctuations in bipolar ferroelectric transistors based on capacitive voltage division negative feedback. Detailed Implementation
[0015] The present invention will be further clearly and completely described below with reference to the accompanying drawings and specific embodiments.
[0016] This invention is based on a structure that suppresses write fluctuations in ferroelectric transistors using capacitive voltage divider negative feedback, as shown below. Figure 1 As shown: The gate of the FeFET is connected to the first port of the dielectric capacitor C0 (node A); during writing, a write voltage V is applied to the second port of the dielectric capacitor C0. W Both the source and drain terminals of the FeFET are grounded, forming a voltage divider path between C0 and the gate capacitance C of the FeFET.
[0017] Example 1
[0018] This embodiment is based on the principle of suppressing write fluctuations in n-type ferroelectric transistors using capacitive voltage division negative feedback, as follows: Figure 2 As shown: When the gate voltage is negative, the gate capacitance of an n-type FeFET device is generally a small value independent of the voltage; when the gate voltage is positive and the amplitude is relatively high, the gate capacitance of an actual n-type FeFET device generally increases with the gate voltage amplitude, forming a voltage-dependent CV relationship; before writing, a block erase scheme is first applied to the FeFET array; thereafter, each FeFET is independently addressed and programmed (V W> 0), the CV relationship gradually shifts to the left as the polarization of the ferroelectric layer reverses, resulting in a change in the initial voltage V. A1 As the gate capacitance C of the FeFET increases from C1 to C2, the voltage drop across the gate capacitance C decreases from V. A1 Reduce to V A2 This causes the FeFET gate capacitance C to decrease from C2 to C3. During this negative feedback process, the faster the polarization switching rate, the faster the FeFET gate capacitance C increases and the faster the gate voltage amplitude decreases, which can suppress excessively fast programming. Conversely, the slower the polarization switching rate, the slower the FeFET gate capacitance C increases and the slower the gate voltage amplitude decreases, which can promote excessively slow programming.
[0019] Example 2
[0020] This embodiment is based on the principle of suppressing write fluctuations in bipolar ferroelectric transistors using capacitive voltage division negative feedback. Figure 3 As shown: When the gate voltage is positive or negative and the amplitude is relatively high, the gate capacitance of a practical bipolar FeFET device generally increases with the gate voltage amplitude, forming a voltage-dependent CV relationship; each FeFET is addressed, programmed, or erased independently:
[0021] 1) During programming (V) W > 0), the CV relationship gradually shifts to the left as the polarization of the ferroelectric layer reverses, resulting in a change in the initial voltage V. pA1 (V) A > 0) FeFET gate capacitance C from C p1 Increase to C p2 This causes the voltage drop across the FeFET gate capacitance C to decrease from V. pA1 Reduce to V pA2 This causes the FeFET gate capacitance C to drop from C p2 Reduce to C p3 In this negative feedback process, the faster the polarization switching rate, the faster the FeFET gate capacitance C increases and the faster the gate voltage amplitude decreases, which can suppress excessively fast programming; the slower the polarization switching rate, the slower the FeFET gate capacitance C increases and the slower the gate voltage amplitude decreases, which can promote excessively slow programming.
[0022] 2) During erasure (V) W < 0), the CV relationship gradually shifts to the right as the polarization of the ferroelectric layer reverses, resulting in a lower initial gate voltage V. eA1 (V) A < 0) FeFET gate capacitance C from C e1 Increase to C e2 This causes the voltage drop across the FeFET gate capacitance C to decrease from V. eA1 Increase to V eA2 This causes the FeFET gate capacitance C to drop from C e2 Reduce to C e3In this negative feedback process, the faster the polarization switching rate, the faster the FeFET gate capacitance C increases and the faster the gate voltage amplitude decreases, which can suppress excessively fast erasure; the slower the polarization switching rate, the slower the FeFET gate capacitance C increases and the slower the gate voltage amplitude decreases, which can promote excessively slow erasure.
[0023] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.
Claims
1. A method for suppressing write fluctuations in ferroelectric transistors, characterized in that, The gate terminal of the ferroelectric transistor is connected to the first port of a dielectric capacitor, denoted as node A; during writing, a writing voltage V is applied to the second port of the dielectric capacitor. W The source and drain terminals of the ferroelectric transistor are grounded, creating a voltage divider path between the dielectric capacitance and the gate capacitance of the ferroelectric transistor, thus enabling the actual write gate voltage V of the ferroelectric transistor to be determined. A Achieve adaptive negative feedback regulation to reduce write fluctuations in ferroelectric transistors.
2. The method for suppressing write fluctuations in ferroelectric transistors as described in claim 1, characterized in that, The actual write gate voltage V of the ferroelectric transistor A for: Where C0 is the capacitance of the dielectric capacitor, C is the capacitance of the ferroelectric transistor gate capacitor, and V W The write voltage applied to the second port of the dielectric capacitor; the CV relationship between the gate capacitance and gate voltage of the ferroelectric transistor gradually shifts as the polarization of the ferroelectric layer reverses, resulting in an initial voltage division V A1 The lower gate capacitance increases from C1 to C2, which in turn causes the voltage drop across the gate capacitance to change from V. A1 Reduce to V A2 This causes the gate capacitance to decrease from C2 to C3. The resulting negative feedback process adaptively and dynamically adjusts the actual gate voltage V written to the ferroelectric transistor according to the degree of ferroelectric polarization reversal. A This causes the polarization reversal of the ferroelectric transistor to converge, reducing the write fluctuations of the ferroelectric transistor.
3. The method for suppressing write fluctuations in ferroelectric transistors as described in claim 1, characterized in that, The ferroelectric transistor adopts an MFS, MFIS, MFMIS, or MIFIS structure.
4. The method for suppressing write fluctuations in ferroelectric transistors as described in claim 1, characterized in that, The ferroelectric layer of the ferroelectric transistor is made of perovskite ferroelectric material, two-dimensional ferroelectric material, organic ferroelectric material, III-V group nitride ferroelectric material or doped hafnium oxide-based ferroelectric material.
5. The method for suppressing write fluctuations in ferroelectric transistors as described in claim 1, characterized in that, The ferroelectric transistor is a unipolar or bipolar ferroelectric transistor.