Dynamic Random Access Memory Cell Structure and its Three-Dimensional Array Structure

Abstract

This disclosure provides a DRAM cell structure, including: a first sub-cell composed of a first gate-all-around transistor (GAB) and a first storage capacitor; wherein the first source / drain of the GAB is shorted to the first electrode of the first storage capacitor at a first storage node, the second source / drain of the GAB is shorted to a bit line extending vertically, and the second electrode of the first storage capacitor is connected to the source line; a second sub-cell composed of a second GAB and a second storage capacitor; wherein the first source / drain of the second GAB is shorted to the first electrode of the second storage capacitor at a second storage node, the second source / drain of the second GAB is shorted to the bit line, and the second electrode of the second storage capacitor is connected to the source line; wherein the first and second sub-cells are arranged in a vertically mirrored manner with a third GAB as the center, the third GAB is connected in series between the first and second GABs and electrically isolates the first and second storage nodes. In this DRAM cell structure, the first electrode of the storage capacitor and the source / drain regions and channel regions of the three GABs are formed from the same semiconductor material layer, thus having advantages such as simple structure and good switching performance, and facilitating the vertical stacking to form a three-dimensional multilayer memory array.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to dynamic random access memory (DRAM) cell structures and their three-dimensional array structures. Background Technology

[0002] Since Intel Corporation invented Dynamic Random Access Memory (DRAM) in the 1970s, DRAM has been widely used in various computing or control electronic circuit systems.

[0003] A DRAM cell circuit typically consists of a selection transistor for selection and a storage capacitor for storing charge (1T1C structure). In DRAM cell structures using conventional planar horizontal transistors, such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), the source, gate, and drain of the transistor are arranged horizontally parallel to the substrate surface. Because the source, gate, and drain each occupy an independent area in the horizontal direction, the miniaturization of DRAM cell circuit structures is limited by gate length and contact size, failing to meet the demands of continuous miniaturization of DRAM devices, thus restricting further increases in the integration density and bandwidth of DRAM devices.

[0004] Therefore, in recent years, a vertical DRAM cell structure has been proposed, in which the source, gate, and drain of the transistor are arranged in a vertical direction perpendicular to the substrate surface, without occupying additional area, which is beneficial for the miniaturization of DRAM array structure.

[0005] DRAM manufacturing is a highly competitive industry. The industry continuously needs to reduce the size of individual cells and increase memory cell density, thereby allowing a single memory chip to hold more memory.

[0006] The information disclosed in this background section is only for understanding the background of the inventive concept and may therefore contain information that does not constitute prior art. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this disclosure proposes a novel vertical dynamic random access memory (DRAM) cell structure.

[0008] According to one aspect of this disclosure, a dynamic random access memory (DRAM) cell structure is provided, comprising: a first sub-cell consisting of a first gate-all-around transistor (GAB) and a first storage capacitor; wherein a first source / drain of the GAB is shorted to a first electrode of the first storage capacitor at a first storage node, a second source / drain of the GAB is shorted to a bit line extending in a vertical direction, and a second electrode of the first storage capacitor is connected to a source line; a second sub-cell consisting of a second GAB and a second storage capacitor; wherein a first source / drain of the GAB is shorted to a second storage node at a second storage node, a second source / drain of the GAB is shorted to the bit line, and a second electrode of the second storage capacitor is connected to a source line; wherein the first sub-cell and the second sub-cell are arranged in a vertically mirror manner with a third GAB as the center, the third GAB being connected in series between the first GAB and the second GAB and electrically isolating the first storage node and the second storage node. In the DRAM cell structure according to the present disclosure, the first gate-enclosed transistor, the third gate-enclosed transistor, and the second gate-enclosed transistor each have a tubular channel structure and are sequentially disposed in the vertical direction; the first storage capacitor has a tubular structure and is disposed in the vertical direction between the first gate-enclosed transistor and the third gate-enclosed transistor; the second storage capacitor has a tubular structure and is disposed in the vertical direction between the second gate-enclosed transistor and the third gate-enclosed transistor; the bit line extends in the vertical direction inside the tubular structure jointly formed by the first gate-enclosed transistor, the second gate-enclosed transistor, the third gate-enclosed transistor, the first storage capacitor, and the second storage capacitor and is connected to the second source / drain of the first gate-enclosed transistor and the second gate-enclosed transistor.

[0009] In the DRAM cell structure according to this disclosure, a first word line extends along a first horizontal direction and is connected to the gate of a first gate-around transistor, and a second word line extends along the first horizontal direction and is connected to the gate of a second gate-around transistor.

[0010] The isolation control line extends along the first horizontal direction and is connected to the gate of the third gate-enclosed transistor. The first word line, the second word line, and the isolation control line overlap in the vertical direction.

[0011] The DRAM cell structure disclosed herein includes two gate-enclosed transistors and two storage capacitors arranged in a vertical direction with the third gate-enclosed transistor as the center. The first electrodes of the two storage capacitors and the source / drain and channel regions of the two gate-enclosed transistors are formed by the same semiconductor material layer. Therefore, it has the advantages of simple structure and good switching performance, and is conducive to stacking in the vertical direction to form a three-dimensional multilayer memory array.

[0012] According to another aspect of this disclosure, a three-dimensional dynamic random access memory (DRAM) array structure is provided, comprising: The DRAM cell structures provided in any of the above embodiments are arranged in L layers, M rows, and N columns, where L, M, and N are natural numbers greater than 1. Each of the plurality of DRAM cell structures includes: The first sub-unit comprises a first gate-all-enclosed transistor (GAB) and a first storage capacitor. The first source / drain of the GAB is shorted to the first electrode of the first storage capacitor at a first storage node. The second source / drain of the GAB is shorted to a vertically extending bit line, and the second electrode of the first storage capacitor is connected to the source line. The second sub-unit comprises a second gate-all-enclosed transistor (GAB) and a second storage capacitor. The first source / drain of the GAB is shorted to the first electrode of the second storage capacitor at a second storage node. The second source / drain of the GAB is shorted to the bit line, and the second electrode of the second storage capacitor is connected to the source line. The first and second sub-units are arranged in a vertically mirrored manner with a third gate-all-enclosed transistor as the center. The third gate-all-enclosed transistor is connected in series between the first and second gate-all-enclosed transistors and electrically isolates the first and second storage nodes. M×N bit lines extend vertically inside the tubular structure formed by the first gate-enclosed transistor, the second gate-enclosed transistor, the third gate-enclosed transistor, the first storage capacitor, and the second storage capacitor in the M-row N-column DRAM cell structure, and are respectively connected to the second source / drain of the first gate-enclosed transistor and the second gate-enclosed transistor in the M-row N-column DRAM cell structure. L×M first word lines extend along the first horizontal direction and are respectively connected to the gate of the first gate-enclosed transistor in the L-layer M-row DRAM cell structure; L×M second word lines, extending along a first horizontal direction and respectively connected to the gates of the second gate-enclosed transistors in the L-layer M-row DRAM cell structure; and L×M isolation control lines extend along the first horizontal direction and are respectively connected to the gate of the third gate-enclosed transistor in the L-layer M-row DRAM cell structure.

[0013] The three-dimensional DRAM array structure according to this disclosure also includes one or more common bit line groups extending along a second horizontal direction perpendicular to the first horizontal direction, each common bit line group including N common bit lines. Each of the M×N bit lines has a selection transistor above and / or below it for connecting the bit line and the common bit line.

[0014] However, the effects of this disclosure are not limited to those described above, and various extensions can be made without departing from the spirit and scope of this disclosure. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further illustration of the claimed disclosure. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present disclosure and, together with the specification, serve to explain the inventive concept.

[0016] Figure 1 This is an equivalent circuit diagram illustrating a dynamic random access memory (DRAM) cell structure according to an embodiment of the present disclosure.

[0017] Figure 2 This is a perspective view showing a DRAM cell structure according to one embodiment of the present disclosure.

[0018] Figure 3 This is a top view showing a DRAM cell structure according to one embodiment of the present disclosure.

[0019] Figure 4 It shows along Figure 3 The image shows a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken by line AA'.

[0020] Figure 5 It shows along Figure 3 The image shows a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken by line BB'.

[0021] Figure 6 It shows along Figure 4 The image shows a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken by line CC'.

[0022] Figure 7 It shows along Figure 4 The image shows a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure, taken by line DD'.

[0023] Figure 8 This illustrates an embodiment according to the present disclosure. Figure 1 The equivalent circuit diagram of the DRAM array structure formed by the DRAM cell structure shown is shown.

[0024] Figure 9 It is shown Figure 8 The diagram shows an equivalent circuit diagram of the DRAM cell structure in the first row of a DRAM array structure according to an embodiment of the present disclosure.

[0025] Figure 10 It is shown Figure 8 The diagram shows a schematic perspective view of the first row of DRAM cells in the first layer of a DRAM array structure according to an embodiment of the present disclosure.

[0026] Figure 11 It is shown Figure 8 The diagram shows a top view of a partial DRAM array structure according to an embodiment of the present disclosure.

[0027] Figure 12 It shows along Figure 11 The image shows a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken by line AA'.

[0028] Figure 13 It shows along Figure 11 The image shows a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken from line BB'.

[0029] Figure 14 It shows along Figure 12 The image shows a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken by line CC'.

[0030] Figure 15 It shows along Figure 12 The image shows a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure, taken by line DD'.

[0031] Figure 16 This is an equivalent circuit diagram illustrating a DRAM array structure with alternative word line configurations according to an embodiment of the present disclosure.

[0032] Figure 17 This is an equivalent circuit diagram illustrating a DRAM array structure with an alternative configuration of bit lines according to an embodiment of the present disclosure.

[0033] Figure 18 It is shown in Figure 1 The diagram shows the equivalent circuit diagram of adding a selection transistor to the DRAM cell structure shown.

[0034] Figure 19 It is shown in Figure 4 A cross-sectional view of the selected transistor is added above the DRAM cell structure shown.

[0035] Figure 20 It is shown in Figure 5 A cross-sectional view of the selected transistor is added above the DRAM cell structure shown.

[0036] Figure 21 This is an equivalent circuit diagram illustrating a DRAM array structure with a selectable transistor layer according to an embodiment of the present disclosure.

[0037] Figure 22 This is an equivalent circuit diagram illustrating a DRAM array structure with a selectable transistor layer according to another embodiment of the present disclosure.

[0038] Figure 23 and Figure 24 An equivalent circuit diagram of the first row group in a DRAM array structure having a selectable transistor layer according to another embodiment of the present disclosure is shown.

[0039] Figure 25 and Figure 26 An equivalent circuit diagram of the first row group in a DRAM array structure having a selectable transistor layer according to another embodiment of the present disclosure is shown.

[0040] Figure 27 This is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0041] Figure 28 This is a schematic block diagram illustrating a semiconductor device according to one embodiment of the present disclosure.

[0042] Figure 29 This is a schematic block diagram illustrating a semiconductor device according to another embodiment of the present disclosure. Detailed Implementation

[0043] In the following description, numerous specific details are set forth for illustrative purposes in order to provide a thorough understanding of the various exemplary embodiments of this disclosure. As used herein, “implementation” is a non-limiting example of an apparatus or method employing one or more inventive concepts disclosed herein. However, it will be apparent that the exemplary embodiments may be implemented without these specific details or with one or more equivalent configurations. Furthermore, the exemplary embodiments may be different, but not necessarily exclusive. For example, specific features of other exemplary embodiments may be used or implemented in some exemplary embodiments without departing from the inventive concept.

[0044] Unless otherwise stated, the exemplary embodiments described are to be understood as exemplary features providing details of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) of the various embodiments may be combined, separated, interchanged and / or reconfigured without departing from the inventive concept.

[0045] For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0046] Although terms such as “first” and “second” may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0047] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms “comprising” and / or “including” mean the presence of the stated features, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximations rather than terms of degree, and are therefore used to account for inherent deviations in measurements, calculations, and / or values ​​provided that are recognized by those skilled in the art.

[0048] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having meanings consistent with their meanings in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0049] Various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure may be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be exhaustive and complete, and will fully convey the scope of the disclosure to those skilled in the art. The same reference numerals denote the same parts throughout the drawings. Furthermore, in the drawings, parts are not necessarily drawn to scale for clarity, and the scale and dimensions of parts may be enlarged.

[0050] The dynamic random access memory (DRAM) cell structure according to embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0051] Figure 1 An equivalent circuit diagram of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown.

[0052] like Figure 1The DRAM cell structure 100 according to the embodiments of this disclosure includes a first sub-cell 101, a second sub-cell 102, and a third gate-all-apart (GAA) transistor T3. Specifically, the first sub-cell 101 consists of a first GAA transistor T1 and a first storage capacitor C1, wherein the first source / drain S / D11 of the first GAA transistor T1 is shorted to the first electrode of the first storage capacitor C1 at a first storage node SN1, the second source / drain S / D12 of the first GAA transistor T1 is shorted to a bit line BL extending in the vertical direction, and the second electrode of the first storage capacitor C1 is connected to the source line SL. The second sub-cell 102 consists of a second GAA transistor T2 and a second storage capacitor C2, wherein the first source / drain S / D21 of the second GAA transistor T2 is shorted to the first electrode of the second storage capacitor C2 at a second storage node SN2, the second source / drain S / D22 of the second GAA transistor T2 is shorted to the bit line BL extending in the vertical direction, and the second electrode of the second storage capacitor C2 is connected to the source line SL.

[0053] See Figure 1 The first sub-unit 101 and the second sub-unit 102 are arranged in a vertically mirror image with the third GAA transistor T3 as the center. The third GAA transistor T3 is connected in series between the first GAA transistor T1 and the second GAA transistor T2, and electrically isolates the first memory node SN1 and the second memory node SN2. In conventional DRAM manufacturing processes, adjacent memory nodes are physically disconnected by etching to achieve electrical isolation between adjacent memory nodes. However, in the manufacturing process of vertical DRAM, it is not possible to achieve electrical isolation between the upper and lower memory nodes SN1 and SN2 by etching. The embodiments of this disclosure electrically isolate the first memory node SN1 and the second memory node SN2 by controlling the third GAA transistor T3 to remain off.

[0054] According to embodiments of this disclosure, the first, second, and third GAA transistors T1, T2, and T3 can all have (see below for reference) Figures 2 to 17 The described tubular channel is arranged vertically and serves as a gate transistor for the DRAM cell structure 100. According to an embodiment of this disclosure, the third GAA transistor T3 can be kept off by default to achieve electrical isolation between the first memory node SN1 and the second memory node SN2.

[0055] According to embodiments of this disclosure, the first and second storage capacitors C1 and C2 have tubular structures. The first storage capacitor is vertically disposed between the first gate-around-the-gate transistor (GAP) and the third gate-around-the-gate transistor (GAP); the second storage capacitor is vertically disposed between the second GAP and the third GAP. The bit line BL extends vertically within the tubular structure formed by the first GAP transistor T1, the second GAP transistor T2, the third GAP transistor T3, the first storage capacitor C1, and the second storage capacitor C2, and connects to the second source / drain of the first GAP transistor T1 and the second GAP transistor T2. For ease of understanding and description, the first electrodes of the first and second storage capacitors C1 and C2 will be collectively referred to as internal electrodes, and the second electrodes of the first and second storage capacitors C1 and C2 will be collectively referred to as external electrodes.

[0056] According to an embodiment of this disclosure, the first source / drain S / D11 of the first GAA transistor T1 and the first source / drain S / D31 of the third GAA transistor T3 are jointly connected to one plate (i.e., the first electrode or internal electrode) of the first memory capacitor C1. The second source / drain S / D32 of the third GAA transistor T3 and the first source / drain S / D21 of the second GAA transistor T2 are jointly connected to one plate (i.e., the first electrode or internal electrode) of the second memory capacitor C2. The second source / drain S / D12 of the first GAA transistor T1 and the second source / drain S / D22 of the second GAA transistor T2 are jointly connected to the bit line BL. According to an embodiment of this disclosure, the bit line BL can extend in the vertical direction (z direction).

[0057] Furthermore, according to embodiments of this disclosure, the gate G1 of the first GAA transistor T1 can be connected to the first word line WLA, the gate G2 of the second GAA transistor T2 can be connected to the second word line WLB, and the gate G3 of the third GAA transistor T3 can be connected to the isolation control line ISO. According to embodiments of this disclosure, the first word line WLA and the second word line WLB can extend along a first horizontal direction (y-direction) and overlap in the vertical direction (z-direction). According to embodiments of this disclosure, the first word line WLA and the second word line WLB are not shorted together to control the first GAA transistor T1 and the second GAA transistor T2 respectively.

[0058] Furthermore, according to embodiments of this disclosure, the other electrode (i.e., the second electrode or external electrode) of the first storage capacitor C1 can be connected to the source line SL, and the other electrode (i.e., the second electrode or external electrode) of the second storage capacitor C2 can be connected to the source line SL. Those skilled in the art will recognize that in a DRAM array structure composed of the DRAM cell structure 100 according to this disclosure, the source lines SL of all DRAM cell structures can be connected together commonly or in groups; therefore, the source line SL can also be referred to herein as a "common electrode".

[0059] Figure 2 A perspective view of a DRAM cell structure 100 according to one embodiment of the present disclosure is shown. Figure 3 A top view of a DRAM cell structure 100 according to one embodiment of the present disclosure is shown. Figure 4 It shows along Figure 3 The image shows a cross-sectional view of a DRAM cell structure 100 according to one embodiment of the present disclosure, taken by line AA'. Figure 5 It shows along Figure 3 The image shows a cross-sectional view of a DRAM cell structure 100 according to one embodiment of the present disclosure, taken from line BB'. Figure 6 It shows along Figure 4 The image shows a cross-sectional view of a DRAM cell structure 100 according to one embodiment of the present disclosure, taken by line CC'. Figure 7 It shows along Figure 4 The image shows a cross-sectional view of a DRAM cell structure 100 according to one embodiment of the present disclosure, taken by line DD'.

[0060] like Figures 2 to 7 As shown, according to embodiments of this disclosure, the DRAM cell structure 100 may include bit line holes (such as...) extending in the vertical direction (z-direction). Figure 3 , Figure 6 and Figure 7 The hole located at the center (e.g., a circular cross-section) and the common electrode trench (e.g., extending in the first horizontal direction (y direction) and penetrating the DRAM cell structure 100 in the vertical direction (z direction) are shown. Figure 2 , Figure 3 , Figure 4 , Figure 6 and Figure 7 The slots located on both sides of the bit line hole in the center are shown.

[0061] like Figures 2 to 7 As shown, according to embodiments of this disclosure, the DRAM cell structure 100 may include conductor lines 109 disposed in bit line holes. The conductor lines 109 extend in the vertical direction (z-direction) and can be used as... Figure 1The bit line BL of the DRAM cell structure 100 shown. According to embodiments of the present disclosure, the material used to form the conductor line 109 may include tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), nickel (Ni), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof. In particular, according to embodiments of the present disclosure, the conductor line 109 may have a cylindrical shape extending in the vertical direction (z-direction). For example, as Figure 3 , Figure 6 and Figure 7 As shown, conductor line 109 can be a cylinder with a first diameter d1.

[0062] like Figures 2 to 7 As shown, according to embodiments of this disclosure, the DRAM cell structure 100 may include a semiconductor material layer 107 with a tubular structure and a first isolation material layer 111 disposed in a bit line hole surrounding a conductor line 109. Specifically, as Figure 4 and Figure 5 As shown more clearly, the upper and lower ends of the semiconductor material layer 107 are in direct contact with the conductor line 109, and the middle portion of the semiconductor material layer 107 is separated from the conductor line 109 by the first insulating material layer 111. In other words, according to embodiments of this disclosure, both the semiconductor material layer 107 and the first insulating material layer 111 have a tubular structure surrounding the conductor line 109. Although in Figure 3 , Figure 6 and Figure 7 In this invention, the tubular structure has a circular cross-section, but this disclosure is not limited to this. Those skilled in the art should recognize that the tubular structure may also have other arbitrary cross-sections, such as elliptical, square or rectangular cross-sections, in which case the cross-sectional shape of the conductor line 109 can be adjusted accordingly.

[0063] According to embodiments of this disclosure, the material used to form the first isolation material layer 111 can be a dielectric material commonly used in integrated circuit processes, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, glass phosphate, or a combination thereof. According to embodiments of this disclosure, the material used to form the first isolation material layer 111 can also be a low-k material. Low-k materials can have a lower dielectric constant than silicon oxide. Silicon oxide can have a dielectric constant of about 3.9, and the first isolation material layer 111 can include a low-k material having a dielectric constant of about 3.9 or lower. According to embodiments of this disclosure, low-k materials can include porous silicon oxide (SiO2), organosilicon, fluorinated silicon glass (FSG), silsesquioxane (HSQ), silicon carbide (SiCOH), or polymer materials such as parylene and polyimide (PI). According to embodiments of this disclosure, the material used to form the first isolation material layer 111 can also be a combination of the above-mentioned dielectric materials and the above-mentioned low-k materials.

[0064] According to embodiments of this disclosure, the material used to form the semiconductor material layer 107 can be a semiconductor thin film material, such as single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, compound semiconductor, oxide semiconductor, sulfide semiconductor, graphene, or a combination thereof. According to embodiments of this disclosure, the material used to form the semiconductor material layer 107 can be an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), indium oxide (InO), zinc oxide (ZnO), indium tungsten oxide (InWO), or indium aluminum oxide (InAlO) in different proportions. In particular, according to embodiments of this disclosure, the semiconductor material layer 107 may include a single layer of IGZO or a stack of multiple layers of IGZO in different proportions.

[0065] Furthermore, according to embodiments of this disclosure, as described in more detail below, the semiconductor material layer 107 can be formed as follows: Figure 1 The source / drain regions and channel regions of the first GAA transistor T1, the second GAA transistor T2, and the third GAA transistor T3 are shown, wherein the source / drain regions of the first GAA transistor T1, the second GAA transistor T2, and the third GAA transistor T3 correspond to the first source / drain S / D11 and the second source / drain S / D12 of the first GAA transistor T1, the first source / drain S / D21 and the second source / drain S / D22 of the second GAA transistor T2, and the first source / drain S / D31 and the second source / drain S / D32 of the third GAA transistor T3. It should be noted that the source / drain regions described from a structural perspective are equivalent to the source / drain regions described from a circuit perspective. Furthermore, according to embodiments of this disclosure, the semiconductor material layer 107 may also be formed as shown in the figure. Figure 1 The internal electrodes of the first and second storage capacitors C1 and C2 are shown. Therefore, according to embodiments of this disclosure, the first and second storage capacitors C1 and C2 may also have a tubular structure.

[0066] like Figures 2 to 7 As shown, according to embodiments of the present disclosure, the DRAM cell structure 100 may include three first dielectric layers 106 disposed in bit line vias, respectively surrounding the upper, middle, and lower ends of the semiconductor material layer 107. According to embodiments of the present disclosure, the three first dielectric layers 106 may be respectively formed as shown in the diagram. Figure 1 The gate dielectrics of the first GAA transistor T1, the second GAA transistor T2, and the third GAA transistor T3 are shown. Figure 4 and Figure 5 As shown, according to embodiments of this disclosure, the first dielectric layer 106 may also have a tubular structure with a bent cross-section. In other words, as... Figures 2 to 5As shown, in a cross-section along the vertical direction (z-direction), the first dielectric layer 106 may have a thinner first portion near the end of the conductor line 109 and a thicker second portion relative to the first portion and away from the end of the conductor line 109, the first portion and the second portion being connected by a horizontal connecting portion. According to embodiments of this disclosure, the material used to form the first dielectric layer 106 may include, for example, silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), or combinations thereof.

[0067] Therefore, according to the embodiments of this disclosure, the first GAA transistor T1, the second GAA transistor T2 and the third GAA transistor T3 are all formed with a tubular structure and each has a tubular channel.

[0068] like Figures 2 to 7 As shown, according to embodiments of the present disclosure, the DRAM cell structure 100 may include a lower first gate layer 1041 and an upper second gate layer 1042 configured to surround a thicker second portion of a lower and upper first dielectric layer 106, respectively, and a third gate layer 1043 surrounding a middle section of the semiconductor material 107. Figure 2 and Figure 6 As shown, according to embodiments of the present disclosure, the first gate layer 1041, the second gate layer 1042, and the third gate layer 1043 may have a strip shape with a hole in the middle. According to embodiments of the present disclosure, the first gate layer 1041 may correspond to... Figure 1 The gate G1 of the first GAA transistor T1 shown, and the second gate layer 1042 can correspond to, as shown in the figure. Figure 1 The second GAA transistor T2 is shown with gate G2, and the third gate layer 1043 corresponds to the gate G3 of the third GAA transistor T3. Furthermore, as shown... Figure 2 , Figure 3 and Figure 5 As shown, according to an embodiment of this disclosure, the first gate layer 1041 may extend in a first horizontal direction (y-direction) to further correspond to, as Figure 1 The first word line WLA is shown, connected to the first gate G1 of the first GAA transistor T1. Accordingly, according to embodiments of this disclosure, the second gate layer 1042 may extend in the first horizontal direction (y direction) to further correspond to, as shown in the figure. Figure 1 The second word line WLB is shown, connected to the gate G2 of the second GAA transistor T2. According to an embodiment of this disclosure, the third gate layer 1043 may extend in the first horizontal direction (y-direction) to further correspond to... Figure 1The isolation control line ISO is shown connected to the gate G3 of the third GAA transistor T3. According to an embodiment of this disclosure, the first word line WLA, the second word line WLB, and the isolation control line ISO can be led out from the distal end in a first horizontal direction (y direction).

[0069] Therefore, according to embodiments of the present disclosure, the DRAM cell structure 100 may have a bit line BL extending in the vertical direction (z-direction), and a first word line WLA, a second word line WLB, and an isolation control line ISO extending in the first horizontal direction (y-direction). According to embodiments of the present disclosure, the bit line BL of the DRAM cell structure 100 may extend within a tubular structure formed by the first GAA transistor T1, the second GAA transistor T2, the third GAA transistor T3, the first storage capacitor C1, and the second storage capacitor C2 in the vertical direction. Furthermore, according to embodiments of the present disclosure, the first gate layer 1041 and the second gate layer 1042 corresponding to the first word line WLA and the second word line WLB of the DRAM cell structure 100 may overlap in the vertical direction (z-direction). According to embodiments of the present disclosure, the first word line WLA, the second word line WLB, and the isolation control line ISO may overlap in the vertical direction (z-direction).

[0070] Furthermore, according to embodiments of this disclosure, the materials used to form the first gate layer 104, the second gate layer 1042, and the third gate layer 1043 may include titanium nitride (TiN), tantalum nitride (TaN), aluminum titanium carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polycrystalline / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or combinations thereof.

[0071] like Figures 2 to 7 As shown, according to embodiments of the present disclosure, the DRAM cell structure 100 may include two second insulating material layers 103 configured to surround, respectively, a thinner first portion of a first dielectric layer 106 above and below. Figure 2 and Figure 3 As shown, according to embodiments of the present disclosure, the second insulating material layer 103 may have a strip shape with a hole in the middle. According to embodiments of the present disclosure, the material used to form the second insulating material layer 103 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiCOH), or aluminum oxide (Al2O3). According to embodiments of the present disclosure, the first insulating material layer 111 and the second insulating material layer 103 may be formed of the same or different insulating materials.

[0072] like Figure 4 and Figure 5As shown, according to embodiments of this disclosure, as described above, the semiconductor material layer 107 along the vertical direction (z-direction) may include the formation indicated by the shaded area. Figure 1 The first portion 1071 of the channel region of the first, second, and third GAA transistors T1, T2, and T3 shown, and the formation between the first portions 1071. Figure 1 The first source / drain region of the first GAA transistor T1 (corresponding to the first source / drain S / D11 of the first GAA transistor T1), the first source / drain region of the second GAA transistor T2 (corresponding to the first source / drain S / D21 of the second GAA transistor T2), the first source / drain region of the third GAA transistor T3 (corresponding to the first source / drain S / D31 of the third GAA transistor T3), and the second source / drain region (corresponding to the second source / drain S / D32 of the third GAA transistor T3), as well as the second portion 1072 of the internal electrodes of the first and second memory capacitors C1 and C2, are shown. Therefore, according to the embodiments of this disclosure, the first source / drain S / D11 of the first GAA transistor T1 and the first source / drain S / D31 of the third GAA transistor T3 are connected together with the internal electrode of the first memory capacitor C1, and the first source / drain S / D21 of the second GAA transistor T2 and the second source / drain S / D32 of the third GAA transistor T3 are connected together with the internal electrode of the second memory capacitor C2. According to embodiments of the present disclosure, a first portion 1071 and a second portion 1072 of the semiconductor material layer 107 are separated from the conductor line 109 (bit line BL) by a first insulating material layer 111 surrounding the conductor line 109 (bit line BL).

[0073] According to embodiments of this disclosure, the doping type, doping concentration, and / or atomic composition ratio of the second portion 1072 of the semiconductor material layer 107 can be changed through material modification processes such as doping and etching, so that it has better conductivity as the internal electrode of the first and second memory capacitors C1 and C2. That is, according to embodiments of this disclosure, the first portion 1071 and the second portion 1072 of the semiconductor material layer 107 can have different doping types, doping concentrations, and / or atomic composition ratios. According to embodiments of this disclosure, when the semiconductor material layer 107 is an IGZO oxide semiconductor, all or part of the gallium (Ga) atoms in the second portion 1072 can be removed by, for example, etching to improve its conductivity, or part of the oxygen (O) atoms in the second portion 1072 can be removed by, for example, etching to form metal atom interstitials or oxygen atom vacancies to improve its conductivity.

[0074] In addition, such as Figure 4 and Figure 5As shown, according to embodiments of this disclosure, as described above, the semiconductor material layer 107 may further include, along the vertical direction (z-direction), contact conductor lines 109 at both ends serving as... Figure 1 The diagram shows the third portion 1073 of the second source / drain region of the first GAA transistor T1 (corresponding to the second source / drain S / D12 of the first GAA transistor T1) and the second source / drain region of the second GAA transistor T2 (corresponding to the second source / drain S / D22 of the second GAA transistor T2), and the first horizontal connection portion 1074 connecting the first portion 1071 and the third portion 1073. Therefore, according to an embodiment of this disclosure, the third portion 1073 of the semiconductor material layer 107 contacts the conductor line 109, such that the second source / drain S / D12 of the first GAA transistor T1 and the second source / drain S / D22 of the second GAA transistor T2 corresponding to the third portion 1073 of the semiconductor material layer 107 are connected to the bit line BL corresponding to the conductor line 109.

[0075] like Figure 3 As shown, according to an embodiment of this disclosure, the third portion 1073 of the tubular semiconductor material layer 107 may have a second diameter d2, which is larger than the first diameter d1 of the conductor line 109. Furthermore, as... Figures 3 to 7 As shown, according to an embodiment of the present disclosure, the first portion 1071 and the second portion 1072 of the tubular semiconductor material layer 107 may have a third diameter d3, which is larger than the second diameter d2 of the third portion 1073 of the semiconductor material layer 107.

[0076] like Figures 2 to 7 As shown, according to an embodiment of this disclosure, the DRAM cell structure 100 may include a second dielectric layer 108 disposed in a common electrode trench, serving as the capacitor dielectric for a first storage capacitor C1 and a second storage capacitor C2. According to an embodiment of this disclosure, the second dielectric layer 108 may be formed conformally along the trench wall of the common electrode trench. For example... Figure 2 and Figure 4 As shown, according to an embodiment of this disclosure, the second dielectric layer 108 can contact the positions of the inner electrodes of the first and second capacitor memories in the second portion of the two second isolation material layers 103, the first gate layer 1041, the second gate layer 1042, and the third gate layer 1043, and the semiconductor material layer 107 in the second horizontal direction (x direction). Furthermore, the outer electrodes of the first and second memories surround the second dielectric layer 108, and the second dielectric layer 108 surrounds the inner electrodes. Additionally, as... Figure 2 and Figure 5 As shown, according to an embodiment of this disclosure, the second dielectric layer 108 may contact a second portion of the semiconductor material layer 107 in a first horizontal direction (y-direction). The first horizontal direction, i.e., the y-direction, may be perpendicular to the second horizontal direction, i.e., the x-direction.

[0077] Furthermore, according to embodiments of this disclosure, the material used to form the second dielectric layer 108 can be a high-k material. The high-k material can have a higher dielectric constant than silicon oxide. Silicon oxide can have a dielectric constant of about 3.9, and the second dielectric layer 108 can include a high-k material having a dielectric constant of about 4 or greater. According to embodiments of this disclosure, the high-k material can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), strontium titanium oxide (SrTiO3), or combinations thereof.

[0078] According to embodiments of this disclosure, the material used to form the second dielectric layer 108 can be barium titanate (BaTiO3), lead zirconate titanate (PZT: PbZrTiO3), strontium bismuth tantalate (SBT: SrBiTaO3), barium strontium titanate (BST: BaSrTiO3), lead zirconate (PbZrO3), silver niobate (AgNbO3), sodium niobate (NaNbO3), sodium bismuth titanate (BNT: BiNaTiO3), and ferroelectric or antiferroelectric materials such as doped hafnium oxide (HfO2) and doped zirconium oxide (ZrO2) with a certain proportion of elements such as Si, Al, Ti, Ta, and La. According to embodiments of this disclosure, when the second dielectric layer 108 is a ferroelectric or antiferroelectric material, information can be stored for a long time by utilizing the polarization characteristics of ferroelectric / antiferroelectric materials, that is, the DRAM memory cell has non-volatility.

[0079] like Figures 2 to 7 As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include an electrode layer 110 extending along the surface of the second dielectric layer 108 and filling a common electrode trench. According to an embodiment of the present disclosure, the electrode layer 110 may correspond to... Figure 1 The external electrodes of the first storage capacitor C1 and the second storage capacitor C2 shown are the common electrode of the first and second storage capacitors C1 and C2, and the source line SL. Figures 2 to 7As shown, according to embodiments of this disclosure, the electrode layer 110 corresponding to the external electrodes and source line SL of the first and second storage capacitors C1 and C2 can extend in a first horizontal direction (y-direction) and penetrate the DRAM cell structure 100 in a vertical direction (z-direction). According to embodiments of this disclosure, the material used to form the electrode layer 110 may include titanium nitride (TiN), tantalum nitride (TaN), aluminum titanium carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), nickel (Ni), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polycrystalline / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or combinations thereof. Therefore, according to embodiments of this disclosure, the first and second storage capacitors C1 and C2 of the DRAM cell structure 100 can be formed as cylindrical capacitors.

[0080] Furthermore, although not shown in the figures, according to embodiments of this disclosure, a third isolation material layer may be provided between the first gate layer 1041, the second gate layer 1042, and the third gate layer 1043 and the second dielectric layer 108 to reduce the parasitic capacitance and leakage current between the external electrode (source line SL) of the storage capacitor and the gates G1, G2, and G3 (i.e., the first and second word lines WLA and WLB and the isolation control line ISO) of the first, second, and third GAA transistors T1, T2, and T3.

[0081] Furthermore, according to embodiments of this disclosure, a cavity may also be provided in the first isolation material layer 111 in the DRAM cell structure 100.

[0082] According to embodiments of this disclosure, the DRAM cell structure includes two gate-enclosed transistors (first GAA transistor T1 and second GAA transistor T2) arranged vertically in a mirror-image configuration centered on a third GAA transistor T3, and two storage capacitors (first storage capacitor C1 and second storage capacitor C2). The internal electrodes of the first and second storage capacitors, as well as the source / drain and channel regions of the first, second, and third gate-enclosed transistors, are formed from the same semiconductor material layer. Therefore, this structure offers advantages such as simple structure and good switching performance, and is beneficial for stacking in the vertical direction to form a three-dimensional multilayer memory array. In particular, this cell structure can completely isolate the storage capacitors in the middle using the upper and lower gate-enclosed transistors, preventing interference from external signals or adjacent cells from affecting the stored information, thereby improving the reliability of the memory cell. Simultaneously, electrical isolation between the upper and lower storage nodes can be achieved by controlling the third gate-enclosed transistor located in the middle to turn off.

[0083] In particular, this cell structure solves the connection problem between the transistor source / drain and the internal electrode of the storage capacitor by using a vertical structure. It is suitable for three-dimensional vertical integration of multilayer DRAM cells. Moreover, the vertical structure is suitable for the one-time processing of multilayer DRAM cells, without the need for multiple epitaxial processes and processing techniques, resulting in low manufacturing costs.

[0084] Figure 8 This illustrates an embodiment according to the present disclosure. Figure 1 The equivalent circuit diagram of the DRAM array structure 200 formed by the DRAM cell structure shown is as follows. Figure 8 As shown, according to an embodiment of this disclosure, by Figure 1 The DRAM array structure 200 formed by the DRAM cell structure shown can be a three-dimensional DRAM array structure stacked in the vertical direction (z direction).

[0085] like Figure 8 As shown, according to embodiments of this disclosure, the DRAM array structure 200 may include, for example: Figure 1 Multiple DRAM cell structures 100 are shown. For clarity, certain reference numerals within each DRAM cell structure are omitted. According to embodiments of this disclosure, the multiple DRAM cell structures are arranged in L layers, M rows, N columns, and L layers, where L, M, and N are all natural numbers greater than 1. In this document, each of the multiple DRAM cell structures included in the DRAM array structure 200 can be represented as Clmn, that is, the DRAM cell structure located in the m-th row, n-th column, and l-th layer of the DRAM array structure 200, where m, n, and l are natural numbers, and 1 ≤ m ≤ M, 1 ≤ n ≤ N, and 1 ≤ l ≤ L. Furthermore, in this document, M represents the number of rows of DRAM cell structures in the DRAM array structure 200 along the first horizontal direction (y-direction), N represents the number of columns of DRAM cell structures in the DRAM array structure 200 along the second horizontal direction (x-direction), and L represents the number of layers of DRAM cell structures in the DRAM array structure 200 along the vertical direction (z-direction).

[0086] According to embodiments of this disclosure, the cell selection operation of the plurality of DRAM cell structures included in the DRAM array structure 200 can be performed by L×M first word lines WLA11 to WLALM, L×M second word lines WLB11 to WLBLM, and M×N bit lines BL11 to BLMN. According to embodiments of this disclosure, the L×M isolation control lines ISO11 to ISOLM can be kept off to electrically isolate the first memory node SN1 and the second memory node SN2.

[0087] Therefore, as Figure 8As shown, according to the embodiments of this disclosure, in the DRAM array structure 200, each layer of the L-layer DRAM cell structure includes M rows and N columns, totaling M×N DRAM cell structures; each row of the M-row DRAM cell structure includes L layers and N columns, totaling L×N DRAM cell structures; and each column of the N-column DRAM cell structure includes L layers and M rows, totaling L×M DRAM cell structures.

[0088] As mentioned above Figures 1 to 7 As described, each of the plurality of DRAM cell structures included in the DRAM array structure 200 may include: a first sub-cell 101 consisting of a first GAA transistor T1 and a first storage capacitor C1, wherein the first source / drain S / D11 of the first GAA transistor T1 is shorted to the first electrode of the first storage capacitor C1 at a first storage node SN1, the second source / drain S / D12 of the first GAA transistor T1 is shorted to the bit line BL extending in the vertical direction, and the second electrode of the first storage capacitor C1 is connected to the source line SL; a second sub-cell 102 consisting of a second GAA transistor T2 and a second storage capacitor C2, wherein the first source / drain S / D21 of the second GAA transistor T2 is shorted to the first electrode of the second storage capacitor C2 at a second storage node SN2, the second source / drain S / D22 of the second GAA transistor T2 is shorted to the bit line BL extending in the vertical direction, and the second electrode of the second storage capacitor C2 is connected to the source line SL.

[0089] In addition, such as Figure 8 As shown, according to an embodiment of the present disclosure, the DRAM array structure 200 may further include M×N bit lines BL11 to BLMN, which extend vertically inside a tubular structure formed by L first GAA transistors, L second GAA transistors, L third GAA transistors, L first storage capacitors, and L second storage capacitors in the M-row N-column DRAM cell structure, and are respectively connected to the second source / drain of the L first GAA transistors and L second GAA transistors in the M-row N-column DRAM cell structure.

[0090] Furthermore, although not shown, according to embodiments of the present disclosure, in each row of an M-row DRAM array structure, L first word lines WLA1m to WLALm can be electrically isolated from L second word lines WLB1m to WLBLm, respectively, and the L isolation control lines ISO1m to ISOLm can be grouped or connected together. Although not shown, according to alternative embodiments of the present disclosure, the L isolation control lines ISO1m to ISOLm can also be connected together, either jointly or in groups, only outside the DRAM array structure 200, thereby reducing the number of isolation control lines.

[0091] Furthermore, according to embodiments of this disclosure, the DRAM array structure 200 may further include L source lines SL corresponding to the L-layer DRAM cell structure, which extend along a first horizontal direction (y-direction) and are respectively connected to the external electrodes of the first and second storage capacitors C1 and C2 in the L-layer DRAM cell structure. Additionally, as... Figure 8 As shown, according to an embodiment of this disclosure, L source lines SL can be connected together by a common electrode trench disposed between the bit lines that runs vertically (z-direction) through the entire DRAM array structure 200, while the source lines SL also extend vertically (z-direction). Although not shown, according to an alternative embodiment of this disclosure, the L source lines SL can also be connected together simply outside the DRAM array structure 200, either commonly or in groups, thus omitting the common electrode trench.

[0092] Figure 9 It is shown Figure 8 The diagram shown is an equivalent circuit diagram of the DRAM cell structures C111 to CL1N in the first row of a DRAM array structure 200 according to an embodiment of the present disclosure. Figure 9 As shown, a first-row, first-column DRAM cell structure C111 is provided at the intersection of the first row, first column bit line BL11 extending vertically (z-direction) and the first layer word line (first word line WLA11 and second word line WLB11) extending horizontally (y-direction). And so on. Figure 9 The first row of the DRAM array structure 200 shown includes N×L DRAM cell structures C111 to CL1N.

[0093] As mentioned above Figure 1 As described, according to embodiments of the present disclosure, each of the plurality of DRAM cell structures constituting the DRAM array structure 200, for example Figure 9 The DRAM cell structure C111 shown includes a first GAA transistor T1, a second GAA transistor T2, a third GAA transistor T3, a first storage capacitor C1, and a second storage capacitor C2.

[0094] Figure 10 It is shown Figure 8 The diagram shows a schematic perspective view of the first row of DRAM cells in the first layer of a DRAM array structure 200 according to an embodiment of the present disclosure. Figure 10As shown, in the first row of the first layer DRAM cell structure of the DRAM array, the first row word line WL11 (first word line WLA11 and second word line WLB11) and the first row isolation control line ISO11 can extend along a first horizontal direction (y direction), and the first row bit lines (only BL11 to BL13 are shown) can extend along a vertical direction (z direction). According to an embodiment of this disclosure, the source line SL of the first layer DRAM cell structure can extend along the first horizontal direction (y direction). Furthermore, as... Figure 10 As shown, the source line SL can also be connected to the source lines SL in other layers in a common electrode trench that extends in the vertical direction (z direction).

[0095] In addition, such as Figures 8 to 10 As shown, according to an embodiment of this disclosure, the bit line BLmn in the m-th row and n-th column can be connected to the second source / drain of the L first GAA transistors and the L second GAA transistors in the m-th row and n-th column DRAM cell structure of the DRAM array structure 200, for performing a cell selection operation on the m-th row and n-th column DRAM cell structure.

[0096] Figure 11 It is shown Figure 8 The diagram shows a top view of a partial DRAM array structure 201 of a DRAM array structure 200 according to an embodiment of the present disclosure. Figure 12 It shows along Figure 11 The image shows a cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure, taken by line AA'. Figure 13 It shows along Figure 11 The image shows a cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure, taken by line BB'. Figure 14 It shows along Figure 12 The image shows a cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure, taken by line CC'. Figure 15 It shows along Figure 12 The image shows a cross-sectional view of the DRAM array structure 201 according to an embodiment of the present disclosure, taken by line DD'.

[0097] It should be noted that Figures 11 to 15 The example shown is as follows Figure 8 The partial DRAM array structure 201 of the DRAM array structure 200 shown includes DRAM cell structures C111, C112, C121, and C122 in the first row and first column of the first layer. These four DRAM cell structures are arranged in a layer of two rows and two columns.

[0098] According to embodiments of this disclosure, the M rows and N columns of the DRAM array structure 200, from bit lines BL11 to BLMN, can extend vertically (z-direction) and be arranged in an M×N matrix form in the first horizontal direction (y-direction) and the second horizontal direction (x-direction). Furthermore, according to embodiments of this disclosure, the L layers of DRAM cell structures in the DRAM array structure 200 are stacked sequentially in the vertical direction, and each layer of DRAM cell structure includes M×N DRAM cell structures.

[0099] Specifically, such as Figures 11 to 15 As shown, the four bit lines BL11, BL12, BL21, and BL22, arranged in two rows and two columns, can extend vertically (z-direction) and be arranged in a 2×2 matrix in the first horizontal direction (y-direction) and the second horizontal direction (x-direction). Optionally, the uppermost DRAM layer is named the first layer, such as... Figure 11 and Figure 12 The first-layer DRAM cell structures C111, C112, C121 and C122 shown are located at the top layer of the three-dimensional DRAM array, which are stacked on top of the second-layer DRAM cell structures C211, C212, C221 and C222, and so on, until the bottom-layer DRAM cell structures CL1N, CL1N, CL2N and CL2N.

[0100] like Figure 11 and Figure 12As shown, the first word line WLA11 of the first row of the first layer is connected to the gate of the first GAA transistor in the first row of the first layer DRAM cell structures C111 and C112, the second word line WLB11 of the first layer is connected to the gate of the second GAA transistor in the first row of the first layer DRAM cell structures C111 and C112, and the first isolation control line ISO11 of the first layer is connected to the gate of the third GAA transistor in the first row of the first layer DRAM cell structures C111 and C112. Similarly, the first word line WLA12 of the second row of the first layer is connected to the gate of the first GAA transistor in the second row of the first layer DRAM cell structures C121 and C122, the second word line WLB12 of the second row of the first layer is connected to the gate of the second GAA transistor in the second row of the first layer DRAM cell structures C121 and C122, and the first isolation control line ISO12 of the second row of the first layer is connected to the gate of the third GAA transistor in the second row of the first layer DRAM cell structures C121 and C122. Although only the first layer of cells is shown in the figure, by analogy, the first word line WLA21 of the first row of the second layer is connected to the gate of the first GAA transistor in the DRAM cell structures C211 and C212 of the first row of the second layer; the second word line WLB21 of the first row of the second layer is connected to the gate of the second GAA transistor in the DRAM cell structures C211 and C212 of the first row of the second layer; and the isolation control line ISO21 of the first row of the second layer is connected to the gate of the third GAA transistor in the DRAM cell structures C211 and C212 of the first row of the second layer. Similarly, the first word line WLA22 of the second row of the second layer is connected to the gate of the first GAA transistor in the DRAM cell structures C221 and C222 of the second row of the second layer; the second word line WLB22 of the second row of the second layer is connected to the gate of the second GAA transistor in the DRAM cell structures C221 and C222 of the second row of the second layer; and the isolation control line ISO22 of the second row of the second layer is connected to the gate of the third GAA transistor in the DRAM cell structures C221 and C222 of the second row of the second layer.

[0101] like Figures 11 to 15As shown, four bit lines BL11, BL12, BL21, and BL22 are formed in four bit line holes extending vertically (z-direction) through the DRAM array structure. Specifically, bit line BL11 in the first row and first column extends vertically inside the tubular structure formed by the first GAA transistor, second GAA transistor, third GAA transistor, first storage capacitor, and second storage capacitor in the first row and first column DRAM cell structures C111 and C211, and connects to the second source / drain of the first GAA transistor and second GAA transistor in the first row and first column DRAM cell structures C111 and C211. Similarly, bit line BL12 in the first row and second column extends vertically inside the tubular structure formed by the first GAA transistor, second GAA transistor, third GAA transistor, first storage capacitor, and second storage capacitor in the first row and second column DRAM cell structures C112 and C212, and connects to the second source / drain of the first GAA transistor and second GAA transistor in the first row and second column DRAM cell structures C112 and C212. Similarly, the second row, first column bit line BL21 extends vertically within the tubular structure formed by the first GAA transistor, second GAA transistor, third GAA transistor, first storage capacitor, and second storage capacitor in the second row, first column DRAM cell structures C121 and C221, and connects to the second source / drain of the first GAA transistor and second GAA transistor in the second row, first column DRAM cell structures C121 and C221. Similarly, the second row, second column bit line BL22 extends vertically within the tubular structure formed by the first GAA transistor, second GAA transistor, third GAA transistor, first storage capacitor, and second storage capacitor in the second row, second column DRAM cell structures C122 and C222, and connects to the second source / drain of the first GAA transistor and second GAA transistor in the second row, second column DRAM cell structures C122 and C222.

[0102] According to embodiments of this disclosure, in each of the M rows × N columns of the DRAM cell structure, the first source / drain and second source / drain of the first GAA transistor, the second GAA transistor, and the third GAA transistor, the channel region, and the internal electrodes of the first and second storage capacitors are formed from the same semiconductor material layer. That is, according to embodiments of this disclosure, in each of the M × N bit line vias penetrating the L-layer DRAM cell structure in the vertical direction (z-direction), the first source / drain and second source / drain of the first GAA transistor, the second GAA transistor, and the third GAA transistor, the channel region, and the internal electrodes of the first and second storage capacitors in the L-layer DRAM cell structure are formed from the same semiconductor material layer having a tubular structure. In other words, this tubular semiconductor material layer extends vertically (z-direction) throughout the entire DRAM array structure 200.

[0103] Specifically, the internal electrodes of the first source / drain and second source / drain of the first GAA transistor, the second GAA transistor, and the third GAA transistor in the first-layer DRAM cell structure C111 and the second-layer DRAM cell structure C211 connected to the first row, first column bit line BL11 are formed from the same semiconductor material layer. Similarly, the internal electrodes of the first source / drain and second source / drain of the first GAA transistor, the second GAA transistor, and the third GAA transistor in the first-layer DRAM cell structure C112 and the second-layer DRAM cell structure C212 connected to the first row, second column bit line BL12 are formed from the same semiconductor material layer. Similarly, the internal electrodes of the first source / drain and second source / drain of the first GAA transistor, the second GAA transistor, and the third GAA transistor in the first-layer DRAM cell structure C121 and the second-layer DRAM cell structure C221 connected to the second row, first column bit line BL21 are formed from the same semiconductor material layer. Similarly, the first source / drain and second source / drain of the first GAA transistor, the second GAA transistor and the third GAA transistor, the channel region and the internal electrodes of the first and second storage capacitors in the first layer DRAM cell structure C122 and the second layer DRAM cell structure C222 connected to the second row and second column bit line BL22 are formed by the same semiconductor material layer.

[0104] According to embodiments of this disclosure, the common electrode trench can extend in the first horizontal direction (y-direction) and penetrate the L-layer DRAM array structure in the vertical direction (z-direction). In this case, the L source lines SL corresponding to the L-layer DRAM cell structure can be connected together in the vertical direction (z-direction). Furthermore, according to embodiments of this disclosure, adjacent rows of DRAM cell structures in the second horizontal direction (x-direction) can share the common electrode trench. Additionally, as described above, the capacitor dielectric and external electrodes of the storage capacitors in each DRAM cell structure of the DRAM array structure 200 can be disposed in the common electrode trench.

[0105] Alternatively, according to embodiments of the present disclosure, the common electrode slot may be omitted in the DRAM array structure 200. In this case, the source line SL may extend only in the first horizontal direction (y direction) and be connected together commonly or in groups outside the DRAM array structure 200.

[0106] Figure 16 This is an equivalent circuit diagram showing a DRAM array structure 200' with an alternative configuration of word lines according to an embodiment of the present disclosure. Figure 16 In, with Figure 8 Identical parts are indicated by the same reference numerals, and repeated descriptions thereof will be omitted.

[0107] Combination Figure 8 Reference Figure 16 , Figure 16 The DRAM array structure 200' shown is... Figure 8 The difference in the DRAM array structure 200 shown is that, in each layer of the L-layer DRAM cell structure, M first word lines WLAl1 to WLAlM can be connected together to form a common first word line GWLAl of the L-layer, M second word lines WLBl1 to WLBlM can be connected together to form a common second word line GWLBl of the L-layer, and M isolation control lines ISOl1 to ISOlM can be connected together to form a common isolation control line GISOl of the L-layer. Specifically, as... Figure 16As shown, the first word lines WLA11 to WLA1M of the first-layer DRAM cell structure are connected together to form the first-layer common first word line GWLA1, and the second word lines WLB11 to WLB1M of the first-layer DRAM cell structure are connected together to form the first-layer common second word line GWLB1, and the isolation control lines ISO11 to ISO1M of the first-layer DRAM cell structure are connected together to form the first-layer common isolation control line GISO1. Similarly, the first word lines WLA21 to WLA2M of the second-layer DRAM cell structure are connected together to form the second-layer common first word line GWLA2, the second word lines WLB21 to WLB2M of the second-layer DRAM cell structure are connected together to form the first-layer common second word line GWLB2, and the isolation control lines ISO21 to ISO2M of the second-layer DRAM cell structure are connected together to form the first-layer common isolation control line GISO2. And so on, until the first word lines WLAL1 to WLALM of the Lth DRAM cell structure are connected together to form the Lth common first word line GWLAL, the second word lines WLBL1 to WLBLM of the Lth DRAM cell structure are connected together to form the Lth common second word line GWLBL, and the isolation control lines ISOL1 to ISOLM of the Lth DRAM cell structure are connected together to form the Lth common isolation control line GISOL.

[0108] At this time, according to the embodiments of the present disclosure, the DRAM array structure 200' has L common first word lines GWLA1 to GWLAL, L common second word lines GWLB1 to GWLBL, L common isolation control lines GISO1 to GISOL, and M×N bit lines BL11 to BLMN. According to the embodiments of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200' can be implemented through the common first word line GWLA1, the common second word line GWLB1, and the bit line BLmn. According to the embodiments of the present disclosure, the electrical isolation between the first memory node and the second memory node in each DRAM cell structure Clmn in the DRAM array structure 200' is achieved through the isolation control line ISO1 connected to the common isolation control line GISO1.

[0109] therefore, Figure 16 The DRAM array structure 200' shown is compared to Figure 8 The DRAM array structure 200 shown simplifies word line configuration.

[0110] Figure 17 This is an equivalent circuit diagram showing a DRAM array structure 200" with an alternative configuration of bit lines according to an embodiment of the present disclosure. Figure 17 In, with Figure 8Identical parts are indicated by the same reference numerals, and repeated descriptions thereof will be omitted.

[0111] Combination Figure 8 Reference Figure 17 , Figure 17 The DRAM array structure shown is 200". Figure 8 The difference in the DRAM array structure 200 shown is that, in each column of the N-column DRAM cell structure, M bit lines BL1n to BLMn can be connected together to form the common bit line GBLn of the nth column. Specifically, as... Figure 17 As shown, bit lines BL11 to BLM1 of the first column of DRAM cell structure are connected together to form the common bit line GBL1 of the first column. Similarly, bit lines BL12 to BLM2 of the second column of DRAM cell structure are connected together to form the common bit line GBL2 of the first column. And so on, bit lines BL1N to BLMN of the Nth column of DRAM cell structure are connected together to form the common bit line GBLN of the Nth column.

[0112] At this time, according to the embodiments of the present disclosure, the DRAM array structure 200" has L×M first word lines WLA11 to WLALM, L×M second word lines WLB11 to WLBLM, L×M isolation control lines ISO11 to ISOLM, and N common bit lines GBL1 to GBLN. According to the embodiments of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200" can be implemented by the first word line WLAlm, the second word line WLBlm, the isolation control line ISOlm, and the common bit line GBLn.

[0113] therefore, Figure 17 The DRAM array structure shown is 200", compared to Figure 8 The DRAM array structure 200 shown can simplify bit line configuration.

[0114] As is well known in the art, the parasitic capacitance generated by the bit lines (BL) (referred to as bit line parasitic capacitance, denoted by CBL) can adversely affect the performance of the DRAM array structure, such as power consumption and speed. To solve the above problem, the DRAM array structure according to this disclosure can have M×N selection transistors disposed above and / or below the L-layer DRAM cell structure to select M×N bit lines respectively.

[0115] Figure 18 It shows in Figure 1 The equivalent circuit diagram of adding a selection transistor ST to the DRAM cell structure 100 shown.

[0116] like Figure 1As shown, according to embodiments of this disclosure, the selection transistor ST can be connected in series with a DRAM cell structure having a 2T1C form. For example, see the following description... Figure 22 The described transistor ST can be positioned vertically (z-direction) above and connected in series with the topmost DRAM cell structure in each column of DRAM cell structure.

[0117] According to embodiments of this disclosure, such as Figure 18 As shown, the first source / drain S / D1 of the selection transistor ST is connected to the bit line BL, and the second source / drain S / D2 of the selection transistor ST is connected to the common bit line GBL extending in the second horizontal direction (x direction). Figure 22 (one of GBL1 to GBLN shown), and the gate G of the selection transistor ST is connected to the common selection line GBLS (e.g., Figure 22 (One of GBLS1 to GBLSM shown).

[0118] Figure 19 It shows in Figure 4 A cross-sectional view of the selected transistor is added above the DRAM cell structure shown. Figure 20 It shows in Figure 5 A cross-sectional view of the selected transistor is added above the DRAM cell structure shown.

[0119] Combination Figure 18 Reference Figure 19 and Figure 20 According to embodiments of this disclosure, similar to the first transistor T1 and the second transistor T2 in a DRAM cell structure, the selection transistor ST can also be in the form of a transistor. Furthermore, as... Figure 19 and Figure 20 As shown, according to an embodiment of this disclosure, the select transistor ST can share the first dielectric layer 106 and the semiconductor material layer 107 with the first transistor T1 and the second transistor T2. Similar to the first transistor T1 and the second transistor T2, the gate dielectric of the select transistor ST can be formed by the first dielectric layer 106, and its first source / drain S / D1 and second source / drain S / D2, as well as its channel region, can be formed by the semiconductor material layer 107.

[0120] like Figure 19 and Figure 20 As shown, according to an embodiment of this disclosure, the conductor line 109, serving as the bit line BL, extends only to and contacts the portion of the semiconductor material layer 107 that serves as the first source / drain S / D1 of the selection transistor ST. Furthermore, as... Figure 19 and Figure 20As shown, according to an embodiment of this disclosure, a portion of the semiconductor material layer 107 serving as the second source / drain S / D2 of the selection transistor ST contacts the conductive plug 121, and the conductive plug 121 can be connected to the common bit line 124. According to an embodiment of this disclosure, the material used to form the conductive plug 121 may include, for example, tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), nickel (Ni), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof. Furthermore, as... Figure 19 and Figure 20 As shown, according to an embodiment of the present disclosure, the conductive plug 121 and the conductor line 109 used as the bit line BL are separated from and insulated from each other by an insulating plug 122. According to an embodiment of the present disclosure, the material used to form the insulating plug 122 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, glass phosphate, or combinations thereof.

[0121] In addition, such as Figure 19 and Figure 20 As shown, according to an embodiment of the present disclosure, the gate layer 120 serving as the gate of the select transistor ST can be formed as a tubular structure surrounding a portion of the first dielectric layer 106 that serves as the gate dielectric layer of the select transistor ST. According to an embodiment of the present disclosure, the material used to form the gate layer 120 may include titanium nitride (TiN), tantalum nitride (TaN), aluminum titanium carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), nickel (Ni), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polycrystalline / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or combinations thereof.

[0122] In addition, such as Figure 19 and Figure 20 As shown, according to an embodiment of the present disclosure, a capping layer 123 covers the select transistor ST, and a conductive plug 121 can pass through the capping layer 123 to connect to a common bit line 124 disposed on the capping layer 123. According to an embodiment of the present disclosure, the material used to form the capping layer 123 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, glass phosphate, or combinations thereof.

[0123] Reference Figure 19 and Figure 20 According to embodiments of this disclosure, the selected transistor ST can be formed simultaneously with each DRAM cell structure, compatible with three-dimensional vertical integration of multilayer cells.

[0124] Figure 21 An equivalent circuit diagram of a DRAM array structure with a selectable transistor layer according to an embodiment of the present disclosure is shown. Figure 19 and Figure 17The difference in the DRAM array structure 200" shown is that, Figure 19 In addition, a selection transistor layer is provided above the DRAM array structure, which includes selection transistors disposed above each bit line BL.

[0125] In contrast, Figure 19 In the nth column DRAM cell structure, M bit lines BL1n to BLMn can be connected to the nth column common bit line GBLn, which extends in the second horizontal direction (x direction) and is located below the DRAM array structure. Figure 22 In the nth column DRAM cell structure, M bit lines BL1n to BLMn can be connected together with the nth column common bit line GBLn, which extends in the second horizontal direction (x direction), and is located above the DRAM array structure, through a selection transistor disposed above each bit line.

[0126] In addition, such as Figure 21 As shown, according to an embodiment of this disclosure, the gates of N selection transistors disposed above the m-th row bit lines BLm1 to BLmN are connected together via a common selection line GBLSm. In other words, the connection and disconnection of the m-th row bit lines BLm1 to BLmN with the corresponding common bit lines GBL1 to GBLN are controlled by the common selection line GBLSm.

[0127] like Figure 21 As shown, according to an embodiment of this disclosure, the DRAM array structure includes a common bit line group. Each of the N common bit lines GBL1 to GBLN in the common bit line group is connected to a bit line with the same column number in each row of DRAM cell structures via a select transistor, and the gate of the select transistor in each row of DRAM cell structures is connected to a common select line. Therefore, according to an embodiment of this disclosure, when performing a read or write operation on the DRAM array structure, N DRAM cell structures in each layer of each row can be operated simultaneously through the N common bit lines GBL1 to GBLN in a common bit line group.

[0128] Despite Figure 21 In this configuration, all selection transistors are positioned above their respective bit lines, and therefore the common bit line is also positioned above the DRAM array structure. However, those skilled in the art will recognize that this disclosure is not limited thereto. Based on the teachings of this disclosure, those skilled in the art will realize that the selection transistors can be positioned below their respective bit lines, and therefore the common bit line can also be positioned below the DRAM array structure.

[0129] According to embodiments of this disclosure, the multiple DRAM cell structures included in the three-dimensional DRAM array structure can be disposed on a substrate. At this time, the selection transistor disposed below the bit line can also be disposed in the substrate, with its first source / drain connected to the bit line and its second source / drain connected to the common bit line.

[0130] Figure 22 An equivalent circuit diagram of a DRAM array structure with a selectable transistor layer according to another embodiment of the present disclosure is shown. Figure 21 Compared to the array structure shown, in Figure 22 In the DRAM array structure shown, a selection transistor is positioned above and below each bit line BL. Specifically, as... Figure 22 As shown, the first column bit line BL can be connected to the first column common bit line GBL1, which extends in the second horizontal direction (x direction) below the DRAM array structure, via a selection transistor disposed below each bit line BL. Similarly, the second column bit line BL can be connected to the second column common bit line GBL2, which extends in the second horizontal direction (x direction) above the DRAM array structure, via a selection transistor disposed above each bit line BL. Likewise, the (N-1)th column bit line BL can be connected to the (N-1)th column common bit line GBL(N-1), which extends in the second horizontal direction (x direction) below the DRAM array structure, via a selection transistor disposed below each bit line BL. The Nth column bit line BL can be connected to the Nth column common bit line GBLN, which extends in the second horizontal direction (x direction) above the DRAM array structure, via a selection transistor disposed above each bit line BL. That is, in Figure 22 In this configuration, the common bit lines of odd-numbered columns can be connected to the corresponding bit lines via selection transistors disposed below each bit line BL, while the common bit lines of even-numbered columns can be connected to the corresponding bit lines via selection transistors disposed above each bit line BL. Thus, according to embodiments of this disclosure, N common bit lines GBL1 to GBLN can be separately disposed above and below the DRAM array structure, thereby reducing the density of common bit lines and decreasing the parasitic capacitance introduced by the common bit lines.

[0131] Furthermore, since in each row of bit lines, the bit lines of odd-numbered columns are connected to the common bit line of odd-numbered columns through select transistors located below the bit lines, and the bit lines of even-numbered columns are connected to the common bit line of even-numbered columns through select transistors located above the bit lines, each row of DRAM cell structure requires two common select lines, GBLSA and GBLSB, to control the on and off states of the select transistors located above and below each bit line, thereby controlling the connection and disconnection of each bit line with the corresponding common bit line. Specifically, as... Figure 22As shown, the gates of N selection transistors located below the m-th row bit lines BLm1 to BLmN are connected together via a common selection line GBLSAm to control the connection and disconnection of odd-numbered column bit lines with the odd-numbered column common bit lines. The gates of N selection transistors located above the m-th row bit lines BLm1 to BLmN are connected together via a common selection line GBLSBm to control the connection and disconnection of even-numbered column bit lines with the even-numbered column common bit lines.

[0132] Those skilled in the art should recognize that Figure 22 The configuration of common bit lines shown is merely an example, and this disclosure is not limited thereto. In fact, according to the teachings of this disclosure, in order to reduce the density of common bit lines, it is sufficient to place a portion of the common bit lines above the DRAM array structure and place the remaining portion of the common bit lines below the DRAM array structure.

[0133] like Figure 23 and Figure 24 As shown, according to embodiments of this disclosure, the M-row DRAM cell structure of the DRAM array can be divided into M / S row groups, where S is a natural number greater than 1 that is divisible by M, and each row group has S rows of DRAM cell structures. Furthermore, the first word lines of each layer in each row group are connected via a common first word line, the second word lines of each layer in each row group are connected via a common second word line, and the isolation control lines of each layer in each row group are connected via a common isolation control line. Additionally, the DRAM array structure may include S common bit line groups. Each of the N common bit lines included in each of the S common bit line groups is connected via a select transistor to a bit line in each row group that has the same row number and the same column number, and the gate of the select transistor of the DRAM cell structure in each row group is connected to a common select line. Therefore, according to embodiments of this disclosure, when performing a read or write operation on the DRAM array structure, the S×N DRAM cell structures of each layer in each row group can be operated simultaneously through the S common bit line groups.

[0134] Reference Figure 23 and Figure 24 According to embodiments of this disclosure, the M-row DRAM cell structure is divided into M / S row groups, where S is a natural number greater than 1 that can divide M (in Figure 25 and Figure 26 In this configuration (S=4), each row group has an S-row DRAM cell structure. Furthermore, the DRAM array structure includes S common bit line groups, and each of the N common bit lines included in each of the S common bit line groups is connected via a select transistor to a bit line in each row group that has the same row number and the same column number. Additionally, the gate of the select transistor in the DRAM cell structure of each row group is connected to a common select line.

[0135] Figure 23 and Figure 24 An equivalent circuit diagram of the first row group in a DRAM array structure having a select transistor layer according to an embodiment of the present disclosure is shown. Figure 23 and Figure 24 The DRAM array structure shown employs a simplified word line configuration. Figure 23 and Figure 24 In this context, an M-row DRAM cell structure can include M / 4 row groups (i.e., S=4), meaning that every four rows of DRAM cell structures can be combined into a row group, and a selection transistor is added between the bit lines and the common bit line. For ease of description, Figure 24 It is shown in a flat, unfolded manner. Figure 23 The diagram shows the first row group of a four-row DRAM array structure. It should be noted that, according to embodiments of this disclosure, the other row groups of the DRAM array structure have... Figure 23 and Figure 24 The first row group shown has the same configuration.

[0136] like Figure 23 and Figure 24 As shown, the word lines of the DRAM cell structures in the first to fourth rows of the first row group can be connected together by a common word line extending in the second horizontal direction (x direction). Specifically, in Figure 23 and Figure 24 In the first row group shown, the first word line, second word line, and isolation control line of the two rows of DRAM cell structures in the first layer can be connected together via the common first word line GWLA11, the second word line GWLB11, and the common isolation control line GISO11, respectively. Similarly, the first word line, second word line, and isolation control line of the two rows of DRAM cell structures in the second layer can be connected together via the common first word line GWLA21, the common second word line GWLB21, and the common isolation control line GISO21, respectively. Likewise, in the first row group, the first word line, second word line, and isolation control line of the two rows of DRAM cell structures in the Lth layer can be connected together via the common first word line GWLAL1, the common second word line GWLBL1, and the common isolation control line GISOL1, respectively.

[0137] In addition, Figure 23 and Figure 24In this configuration, corresponding rows within each row group, i.e., the same columns of DRAM cell structures with the same row number, i.e., the same column number, can be connected together. Specifically, the bit lines of the first row (i.e., row number 1) and first column (i.e., column number 1) of DRAM cell structures in each row group can be connected together via a common bit line GBL11 extending in the second horizontal direction (x direction). The bit lines of the first row and second column of DRAM cell structures in each row group can be connected together via a common bit line GBL12 extending in the second horizontal direction (x direction), and so on, until the bit lines of the first row and Nth column of DRAM cell structures in each row group can be connected together via a common bit line GBL1N extending in the second horizontal direction (x direction). These common bit lines can be represented together as GBL1 or GBL1<1:N>. Similarly, the bit lines of the DRAM cell structure in the first column of the second row (i.e., row number 2) in each row group can be connected together by a common bit line GBL21 extending in the second horizontal direction (x direction), and the bit lines of the DRAM cell structure in the second column of the second row in each row group can be connected together by a common bit line GBL22 extending in the second horizontal direction (x direction), until the bit lines of the DRAM cell structure in the Nth column of the second row in each row group can be connected together by a common bit line GBL2N extending in the second horizontal direction (x direction). These common bit lines can be represented together as GBL2 or GBL2<1:N>. Similarly, the bit lines of the DRAM cell structure in the third row and first column of each row group can be connected together by a common bit line GBL31 extending in the second horizontal direction (x direction), and the bit lines of the DRAM cell structure in the third row and second column of each row group can be connected together by a common bit line GBL32 extending in the second horizontal direction (x direction), until the bit lines of the DRAM cell structure in the third row and Nth column of each row group can be connected together by a common bit line GBL3N extending in the second horizontal direction (x direction). These common bit lines can be represented together as GBL3 or GBL3<1:N>. Similarly, the bit lines of the DRAM cell structure in the fourth row and first column of each row group can be connected together by a common bit line GBL41 extending in the second horizontal direction (x direction), and the bit lines of the DRAM cell structure in the fourth row and second column of each row group can be connected together by a common bit line GBL42 extending in the second horizontal direction (x direction), until the bit lines of the DRAM cell structure in the fourth row and Nth column of each row group can be connected together by a common bit line GBL4N extending in the second horizontal direction (x direction). These common bit lines can be represented together as GBL4 or GBL4<1:N>.

[0138] In other words, Figure 23 and Figure 24In the DRAM cell array of each row group, the bit lines BL are connected together through four sets of common bit lines GBL1<1:N> to GBL4<1:N>, and each set of common bit lines GBL includes N common bit lines GBL.

[0139] In addition, such as Figure 23 and Figure 24 As shown, according to an embodiment of this disclosure, selection transistors corresponding to each bit line BL are disposed above the L-layer DRAM cell structure. Specifically, as... Figure 23 and Figure 24 As shown, the source and drain of each selection transistor are connected to the corresponding bit line BL and the common bit line GBL. Furthermore, Figure 24 The parasitic capacitance of each bit line BL is also shown; for example, the parasitic capacitance of bit line BL11 in the first row and first column can be represented by C11. It should be understood here that... Figure 24 The parasitic capacitances shown for each bit line BL are equivalent capacitances in the circuit, not actual capacitors. The values ​​of the parasitic capacitances for each bit line BL can be assumed to be the same and uniformly denoted as CBL. Furthermore, as mentioned above, the 4N common bit lines GBL1<1:N> to GBL4<1:N> all extend in the second horizontal direction (x-direction), which will also result in corresponding parasitic capacitances for the common bit lines. The values ​​of the parasitic capacitances for each common bit line GBL can also be assumed to be the same and uniformly denoted as CGBL.

[0140] In addition, such as Figure 23 and Figure 24 As shown, the gates of all the selection transistors in the first row are connected to the common selection line GBLS1. That is, in Figure 23 and Figure 24 In an embodiment of this disclosure, the select transistors of each bit line BL in each row group are controlled to be turned on and off by a common select line corresponding to that row group, so as to connect or disconnect the bit line BL and the common bit line GBL.

[0141] In addition, such as Figure 23 and Figure 24 As shown, the selection transistors (and their corresponding parasitic capacitances) positioned above the L-layer DRAM cell structure can be collectively referred to as the selection transistor layer (STL). Although in Figure 23 In this embodiment, the Select Transistor Layer (STL) is disposed above the L-layer DRAM cell structure; however, this disclosure is not limited thereto. According to embodiments of this disclosure, the Select Transistor Layer (STL) may also be disposed below the L-layer DRAM cell structure.

[0142] Figure 25 and Figure 26An equivalent circuit diagram of the first row group in a DRAM array structure having a selectable transistor layer according to another embodiment of the present disclosure is shown. Figure 25 and Figure 26 The DRAM array structure shown employs a method that simplifies both bit line and word line configurations. Figure 25 and Figure 26 In this context, an M-row DRAM cell structure can comprise M / 4 row groups (i.e., S=4), meaning that every four rows of DRAM cell structures can be combined into one row group. For ease of description, Figure 26 It is shown in a flat, unfolded manner. Figure 25 The diagram shows the first row group of a four-row DRAM array structure. It should be noted that, according to embodiments of this disclosure, the other row groups of the DRAM array structure have... Figure 25 and Figure 26 The first row group shown has the same configuration.

[0143] like Figure 25 and Figure 26 As shown, the word lines of the DRAM cell structures in the first row group of the DRAM array can be connected together by a common word line extending in the second horizontal direction (x direction). Specifically, in Figure 24 In the first row group shown, the first word line, second word line, and isolation control line of the two rows of DRAM cell structures in the first layer can be connected together via the common first word line GWLA11, the common second word line GWLB11, and the common isolation control line GISO11, respectively. Similarly, the first word line, second word line, and isolation control line of the two rows of DRAM cell structures in the second layer can be connected together via the common first word line GWLA21, the common second word line GWLB21, and the common isolation control line GISO21, respectively. Likewise, in the first row group, the first word line, second word line, and isolation control line of the two rows of DRAM cell structures in the Lth layer can be connected together via the common first word line GWLAL1, the common second word line GWLBL1, and the common isolation control line GISOL1, respectively.

[0144] In addition, Figure 25 and Figure 26 In China, unlike Figure 23 and Figure 24The bit lines BL of the DRAM cell array in each row group are connected together by two sets (instead of four sets) of common bit lines GBL1<1:N> to GBL2<1:N>. Each set of common bit lines GBL includes N common bit lines. The first set of common bit lines GBL1<1:N> is connected to the bit lines BL of the first and third rows of DRAM cell structures in each row group, respectively. The second set of common bit lines GBL2<1:N> is connected to the bit lines BL of the second and fourth rows of DRAM cell structures in each row group, respectively. For example, the bit lines BL1<1:N> and BL3<1:N> of the first row of DRAM cell structures in the first row group are connected to the first set of common bit lines GBL1<1:N>, and the bit lines BL2<1:N> and BL4<1:N> of the second and fourth rows of DRAM cell structures in the first row group are connected to the second set of common bit lines GBL2<1:N>.

[0145] In addition, such as Figure 25 and Figure 26 As shown, according to an embodiment of this disclosure, selection transistors corresponding to each bit line BL are disposed above the L-layer DRAM cell structure. Specifically, as... Figure 25 and Figure 26 As shown, the source and drain of each selection transistor are connected to the corresponding bit line BL. Furthermore, Figure 26 The parasitic capacitance of each bit line BL is also shown; for example, the parasitic capacitance of bit line BL11 in the first row and first column can be represented by C11. It should be understood here that... Figure 26 The parasitic capacitances shown for each bit line BL are equivalent capacitances in the circuit, not actual capacitors. The values ​​of the parasitic capacitances for each bit line BL can be assumed to be the same and uniformly denoted as CBL. Furthermore, as mentioned above, the 2N common bit lines GBL1<1:N> to GBL2<1:N> all extend in the second horizontal direction (x-direction), which will also result in corresponding parasitic capacitances for the common bit lines. The values ​​of the parasitic capacitances for each common bit line GBL can also be assumed to be the same and uniformly denoted as CGBL.

[0146] exist Figure 25 and Figure 26 In order to achieve independent addressing of the bit lines BL of each DRAM cell structure, the number of common selection lines is increased accordingly. Specifically, such as... Figure 25 and Figure 26 As shown, the gates of all selection transistors in the first and second rows of the first group are connected to the common selection line GBLS11, and the gates of all selection transistors in the third and fourth rows of the first group are connected to the common selection line GBLS12. That is, in Figure 25 and Figure 26 In an embodiment of this disclosure, the selection transistors of each bit line BL of each row group are controlled to be turned on and off by two common selection lines corresponding to that row group.

[0147] In addition, such as Figure 25 and Figure 26 As shown, the selection transistors (and their corresponding parasitic capacitances) positioned above the L-layer DRAM cell structure can be collectively referred to as the selection transistor layer (STL). Although in Figure 25 and Figure 26 In this embodiment, the Select Transistor Layer (STL) is disposed above the L-layer DRAM cell structure; however, this disclosure is not limited thereto. According to embodiments of this disclosure, the Select Transistor Layer (STL) may also be disposed below the L-layer DRAM cell structure.

[0148] Compared to Figure 23 and Figure 24 The configuration of the DRAM array structure shown is as follows: Figure 25 and Figure 26 The configuration of the DRAM array structure shown can further simplify the configuration of common bit lines. Specifically, for an M-row, N-column, L-layer DRAM array structure, the L×M / 4 common isolation lines can be shared by layers or by the entire array structure. Figure 23 and 24 The operation of the DRAM array structure shown requires L×M / 4 common first word lines, L×M / 4 common second word lines, 4N common bit lines, and M / 4 common select lines, which means a total of 2×L×M / 4+4N+M / 4 lines are needed. Figure 25 and Figure 26 The operation of the DRAM array structure shown requires L×M / 4 common first word lines, L×M / 4 common second word lines, 2N common bit lines, and M / 2 common select lines, totaling 2×L×M / 4 + 2N + M / 2 lines. For example, in a DRAM array structure comprising 64 layers of 1024 rows × 1024 columns (L=64, M=N=1024), Figure 23 and Figure 24 The DRAM array structure shown requires 37,120 lines to operate, while Figure 25 and Figure 26 The DRAM array structure shown requires 35,328 lines to operate.

[0149] Reference Figure 23 and Figure 24 According to embodiments of this disclosure, the M-row DRAM cell structure is divided into M / S row groups, where S is a natural number greater than 1 that can divide M (in Figure 25 and Figure 26In this configuration (S=4), each row group has an S-row DRAM cell structure. Furthermore, the DRAM array structure includes S common bit line groups, and each of the N common bit lines included in each of the S common bit line groups is connected via a select transistor to a bit line in each row group that has the same row number and the same column number. Additionally, the gate of the select transistor in the DRAM cell structure of each row group is connected to a common select line.

[0150] For comparison, refer to Figure 25 and Figure 26 According to embodiments of this disclosure, the M-row DRAM cell structure is divided into M / S row groups, where S is a natural number greater than 1 that can divide M (in Figure 25 and Figure 26 In this configuration, S=4), meaning each row group has an S-row DRAM cell structure. Furthermore, compared to... Figure 24 and Figure 26 Each row group is further divided into S / T sub-row groups, where T is a natural number greater than 1 that divides S (in Figure 25 and Figure 26 In this configuration, T=2), meaning each sub-row group has a T-row DRAM cell structure. Furthermore, the DRAM array structure includes T common bit line groups, and each of the N common bit lines included in each of the T common bit line groups is connected via a select transistor to a bit line in each sub-row group that has the same row number and column number. Additionally, the gate of the select transistor in the DRAM cell structure of each sub-row group is connected to a common select line.

[0151] like Figure 25 and Figure 26As shown, according to embodiments of this disclosure, the M-row DRAM cell structure of the DRAM array can be divided into M / S row groups, where S is a natural number greater than 1 that divides M, and each row group has S rows of DRAM cell structures. Furthermore, each row group can be further divided into S / T sub-row groups, where T is a natural number greater than 1 that divides S, and each sub-row group has T rows of DRAM cell structures. Additionally, the first word lines of each layer in each row group are connected via a common first word line, the second word lines of each layer in each row group are connected via a common second word line, and the isolation control lines of each layer in each row group are connected via a common isolation control line. Furthermore, the DRAM array structure includes T common bit line groups, each of the N common bit lines included in each of the T common bit line groups is connected via a select transistor to a bit line in each sub-row group having the same row number and the same column number, and the gate of the select transistor of the DRAM cell structure in each sub-row group is connected to a common select line. Therefore, according to the embodiments of this disclosure, when performing read or write operations on the DRAM array structure, the S×N DRAM cell structures of each layer in each row group can be operated step by step through the T common bit line groups.

[0152] According to embodiments of this disclosure, since the DRAM array structure 200 is a three-dimensional vertically integrated DRAM array structure, it can be stacked on a circuit board including various circuits to realize a vertically integrated semiconductor device.

[0153] Figure 27 This is a schematic cross-sectional view illustrating a semiconductor device 400 according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the semiconductor device 400 may include a circuit board 300 and a DRAM array structure 200 disposed on the circuit board 300. Although Figure 27 Only shown as Figure 8 The partial DRAM array structure of the DRAM array structure 200 shown, namely the two memory cells CLmn and CL(m+1)n of the Lth layer at the bottom of the DRAM cell structure, are stacked on the circuit board 300. However, those skilled in the art should recognize that the DRAM array structure 200 can be entirely stacked on the circuit board 300.

[0154] like Figure 27 As shown, according to embodiments of the present disclosure, the circuit board 300 may be a semiconductor substrate on which multiple circuits may be fabricated using semiconductor manufacturing processes such as standard CMOS processes. According to embodiments of the present disclosure, the L-layer DRAM cell structures of the DRAM array structure 200 may be stacked on the circuit board 300 in the vertical direction (z-direction), thereby achieving system-level three-dimensional vertical integration.

[0155] According to embodiments of this disclosure, a plurality of circuits on the circuit board 300 can be connected to the DRAM array structure 200 via, for example, wires and vias extending in the vertical direction (z direction).

[0156] Figure 28 This is a schematic block diagram illustrating a semiconductor device 400 according to an embodiment of the present disclosure.

[0157] like Figure 28 As shown, according to an embodiment of the present disclosure, the circuit board 300 may include a memory controller circuit 302, a word line circuit 303, and a bit line circuit 304.

[0158] According to embodiments of this disclosure, the memory controller circuit 302 may be the main management circuit of the DRAM array structure 200, used to process all instructions related to read and write operations of the DRAM array structure 200. Furthermore, the memory controller circuit 302 is also used to refresh the DRAM cell structure, because the data stored in the DRAM cell structure gradually disappears over time, so it needs to be refreshed periodically to maintain data integrity.

[0159] According to embodiments of this disclosure, word line circuitry 303 is used to select a group of DRAM cell structures connected to a specified word line in the DRAM array structure 200. For example, when data needs to be read from or written to the DRAM array structure, word line circuitry 303 is activated to select a group of DRAM cell structures connected to the specified word line. Furthermore, bit line circuitry 304 is used to select a specific DRAM cell structure from the group of DRAM cell structures connected to the specified word line. When word line circuitry 303 selects a group of DRAM cell structures, bit line circuitry 304 can select a bit line connected to one of the DRAM cell structures in that group, thereby determining the precise location of the data. Additionally, bit line circuitry 304 is also used to transmit data during read and write operations.

[0160] According to embodiments of the present disclosure, word line circuit 303 can be connected to the first word line WLA and the second word line WLB of DRAM array structure 200, and bit line circuit 304 can be connected to the bit line BL of DRAM array structure 200.

[0161] According to embodiments of this disclosure, when Figure 8 When the DRAM array structure 200 shown is stacked on the circuit board 300, the word line circuit 303 can be connected to L×M first word lines WLA11 to WLALM and L×M second word lines WLB11 to WLBLM, and the bit line circuit 304 can be connected to M×N bit lines BL11 to BLMN. Furthermore, according to embodiments of this disclosure, when... Figure 16When the DRAM array structure 200' shown is stacked on the circuit board 300, the word line circuit 303 can be connected to L first word lines WLA1 to WLAL and L second word lines WLB1 to WLBL, and the bit line circuit 304 can be connected to M×N bit lines BL11 to BLMN. Furthermore, according to embodiments of this disclosure, when... Figure 17 When the DRAM array structure 200" shown is stacked on the circuit board 300, the word line circuit 303 can be connected to L×M first word lines WLA11 to WLALM and L×M second word lines WLB11 to WLBLM, and the bit line circuit 304 can be connected to N bit lines BL1 to BLN.

[0162] According to embodiments of the present disclosure, since word lines WL and isolation control lines ISO extend in the first horizontal direction (y-direction) in the three-dimensional DRAM array structures (200, 200', and 200") according to embodiments of the present disclosure, word line circuit 303 can be connected to word lines WL of the three-dimensional DRAM array structure via conductors and vias extending in the vertical direction (z-direction). Furthermore, according to embodiments of the present disclosure, since bit lines BL extend in the vertical direction (z-direction) in the three-dimensional DRAM array structures (200, 200', and 200") according to embodiments of the present disclosure, bit line circuit 304 can be directly connected to bit lines BL.

[0163] Furthermore, according to embodiments of this disclosure, the circuit board 300 may include a circuit 301, which may be a processor circuit or a memory interface circuit. According to embodiments of this disclosure, circuit 301 may be connected to memory controller circuit 302 for sending address, instruction, and / or data information to it, and may be connected to bit line circuit 304 for transmitting or receiving data from it.

[0164] According to embodiments of this disclosure, when circuit 301 is a processor circuit, semiconductor device 400 can be a computing system, and when circuit 301 is a memory interface circuit, semiconductor device 400 can be a memory system.

[0165] Figure 29 This is a schematic block diagram illustrating a semiconductor device 400 according to another embodiment of the present disclosure.

[0166] like Figure 29 As shown, according to an embodiment of the present disclosure, the circuit board 300 may include a memory controller circuit 302, a word line circuit 303, and a bit line circuit 304.

[0167] According to embodiments of this disclosure, the memory controller circuit 302 may be the main management circuit of the DRAM array structure 200, used to process all instructions related to read and write operations of the DRAM array structure 200. Furthermore, the memory controller circuit 302 is also used to refresh the DRAM cell structure, because the data stored in the DRAM cell structure gradually disappears over time, so it needs to be refreshed periodically to maintain data integrity.

[0168] According to embodiments of this disclosure, word line circuitry 303 is used to select a group of DRAM cell structures connected to a specified word line in the DRAM array structure 200. For example, when data needs to be read from or written to the DRAM array structure, word line circuitry 303 is activated to select a group of DRAM cell structures connected to the specified word line. Furthermore, bit line circuitry 304 is used to select a specific DRAM cell structure from the group of DRAM cell structures connected to the specified word line. When word line circuitry 303 selects a group of DRAM cell structures, bit line circuitry 304 can control the connection of the corresponding bit lines of that group of DRAM cell structures to the common bit line group via the common selection line GBLS to determine the exact location of the data. In addition, bit line circuitry 304 is also connected to one or more common bit line groups for data transmission during read and write operations.

[0169] According to embodiments of this disclosure, word line circuit 303 can be connected to word line WL of DRAM array structure 200, and bit line circuit 304 can be connected to common select line GBLS and one or more common bit line groups of DRAM array structure 200 to control the connection and disconnection of common bit line groups and bit lines.

[0170] According to embodiments of this disclosure, when Figure 21 When the DRAM array structure 200 shown is stacked on the circuit board 300, the word line circuit 303 can be connected to L×M first word lines WLA11 to WLALM and L×M second word lines WLB11 to WLBLM, and the bit line circuit 304 can be connected to N common bit lines GBL1 to GBLN. Furthermore, according to embodiments of this disclosure, when... Figure 23 When the DRAM array structure 200' shown is stacked on the circuit board 300, the word line circuit 303 can be connected to L×M / S common first word lines GWLA11 to GWLAL(M / S) and L×M / S common second word lines GWLB11 to GWLBL(M / S), and the bit line circuit 304 can be connected to S×N common bit lines GBL1<1:N> to GBLS<1:N>. Furthermore, according to embodiments of this disclosure, when... Figure 24When the DRAM array structure 200" shown is stacked on the circuit board 300, the word line circuit 303 can be connected to L×M / S common first word lines WLA11 to WLAL(M / S) and L×M / 4 common second word lines WLB11 to WLBL(M / S), and the bit line circuit 304 can be connected to T×N common bit lines GBL1<1:N> to GBLT<1:N>.

[0171] According to embodiments of the present disclosure, since word lines WL and isolation control lines ISO extend in the first horizontal direction (y direction) in the three-dimensional DRAM array structures (200, 200', and 200") according to embodiments of the present disclosure, word line circuit 303 can be connected to the word lines WL of the three-dimensional DRAM array structure via wires and vias extending in the vertical direction (z direction). Furthermore, according to embodiments of the present disclosure, since common bit lines GBL extend in the second horizontal direction (x direction) and are disposed above and / or below the array in the three-dimensional DRAM array structures (200, 200', and 200") according to embodiments of the present disclosure, bit line circuit 304 can be connected to the common bit lines GBL of the three-dimensional DRAM array structure via wires and vias extending in the vertical direction (z direction).

[0172] Furthermore, according to embodiments of this disclosure, the circuit board 300 may include a circuit 301, which may be a processor circuit or a memory interface circuit. According to embodiments of this disclosure, circuit 301 may be connected to memory controller circuit 302 for sending address, instruction, and / or data information to it, and may be connected to bit line circuit 304 for transmitting or receiving data from it.

[0173] The DRAM cell structure constituting the DRAM array structure according to this disclosure includes two gate-enclosed transistors and a storage capacitor arranged in a vertical direction, wherein the inner electrode of the storage capacitor and the source / drain and channel regions of the two gate-enclosed transistors are formed by the same semiconductor material layer, thus having the advantages of simple structure and good switching performance.

[0174] In particular, this cell structure solves the connection problem between the source and drain of the transistor and the internal electrode of the storage capacitor by using a vertical structure. It is suitable for three-dimensional vertical integration of multi-layer cells. Moreover, the vertical structure is suitable for the one-time processing of multi-layer cells, without the need for multiple epitaxial processes and processing techniques, resulting in low manufacturing costs.

[0175] Furthermore, the DRAM array structure according to this disclosure can achieve three-dimensional vertical integration by stacking multiple layers of DRAM cells, thereby increasing integration density. Additionally, the DRAM array structure according to this disclosure can be stacked on a circuit board including multiple circuits, thus enabling system-level three-dimensional vertical integration and significantly reducing the area overhead of the circuit system.

[0176] Although this document contains numerous details, these details should not be construed as limiting the scope of this disclosure or any potentially claimed protection, but rather as descriptions of features that may be specific to a particular implementation. Some features described herein in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in certain combinations, and even initially stated so, in some cases one or more features may be removed from the claimed combination, and the claimed combination may involve sub-combinations or variations thereof.

Claims

1. A dynamic random access memory (DRAM) cell structure, comprising: The first sub-unit consists of a first gate-all-around transistor and a first storage capacitor; wherein, the first source / drain of the first gate-all-around transistor is shorted to the first electrode of the first storage capacitor at the first storage node, the second source / drain of the first gate-all-around transistor is shorted to the bit line extending in the vertical direction, and the second electrode of the first storage capacitor is connected to the source line. The second sub-unit is composed of a second gate-enclosed transistor and a second storage capacitor; wherein, the first source / drain of the second gate-enclosed transistor and the first electrode of the second storage capacitor are shorted to the second storage node, the second source / drain of the second gate-enclosed transistor are shorted to the bit line, and the second electrode of the second storage capacitor is connected to the source line; The first sub-unit and the second sub-unit are arranged in a vertical direction with the third gate-enclosed transistor as the center. The third gate-enclosed transistor is connected in series between the first gate-enclosed transistor and the second gate-enclosed transistor and electrically isolates the first memory node and the second memory node.

2. The DRAM cell structure according to claim 1, wherein, The first gate-enclosed transistor, the third gate-enclosed transistor, and the second gate-enclosed transistor all have tubular channels, which are arranged sequentially in the vertical direction. The first storage capacitor has a tubular structure and is disposed vertically between the first gate-enclosed transistor and the third gate-enclosed transistor; The second storage capacitor has a tubular structure and is disposed vertically between the second gate-enclosed transistor and the third gate-enclosed transistor; The bit line extends vertically within the tubular structure formed by the first gate-enclosed transistor, the second gate-enclosed transistor, the third gate-enclosed transistor, the first storage capacitor, and the second storage capacitor, and connects to the second source / drain of the first gate-enclosed transistor and the second gate-enclosed transistor.

3. The DRAM cell structure according to claim 1 or 2, wherein, The first word line extends along a first horizontal direction and connects to the gate of the first gate-enclosed transistor. The second word line extends along the first horizontal direction and connects to the gate of the second gate-around transistor, and An isolation control line extends along the first horizontal direction and is connected to the gate of the third gate-enclosed transistor, and the first word line, the second word line, and the isolation control line overlap in the vertical direction.

4. The DRAM cell structure according to claim 1, wherein, The source / drain regions and channel regions of the first gate-enclosed transistor, the second gate-enclosed transistor, and the third gate-enclosed transistor, as well as the first electrode of the first storage capacitor and the second storage capacitor, are formed from the same semiconductor material layer.

5. The DRAM cell structure according to claim 4, wherein, The semiconductor material layer includes: The first part forms the channel regions of the first, second, and third gate-enclosed transistors; The second part, between the first part, forms the first source / drain regions of the first gate-enclosed transistor and the second gate-enclosed transistor, the first source / drain region and the second source / drain region of the third gate-enclosed transistor, and the first electrode of the first storage capacitor and the second storage capacitor; The third part forms the second source / drain regions of the first and second gate-enclosed transistors; and The first horizontal connecting portion connects the first part and the third part. Wherein, the diameter of the second portion of the semiconductor material layer is greater than or equal to the diameter of the first portion of the semiconductor material layer, and The diameter of the first portion of the semiconductor material layer is larger than the diameter of the third portion of the semiconductor material layer.

6. The DRAM cell structure according to claim 5, wherein, The first and second portions of the semiconductor material layer have different doping types, doping concentrations, and / or atomic composition ratios.

7. The DRAM cell structure according to claim 4, wherein, The semiconductor material layer includes a single layer of IGZO or a stack of multiple layers of IGZO with different ratios.

8. The DRAM cell structure according to claim 4, wherein, The semiconductor material layer includes monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, compound semiconductor, oxide semiconductor, sulfide semiconductor, graphene, or a combination thereof.

9. The DRAM cell structure according to claim 5, further comprising: Bit line holes extend through the DRAM cell structure in the vertical direction; as well as A common electrode trench extends in the first horizontal direction and penetrates the DRAM cell structure in the vertical direction.

10. The DRAM cell structure according to claim 9, wherein, The bit line and the semiconductor material layer are disposed in the bit line via, and the semiconductor material layer surrounds the bit line. The third portion of the semiconductor material layer is in contact with the bit line, and the first and second portions of the semiconductor material layer are separated from the bit line by a first insulating material layer surrounding the bit line.

11. The DRAM cell structure according to claim 10, wherein, The first insulating material layer is formed of a low-K material.

12. The DRAM cell structure according to claim 10, wherein, The first insulating material layer includes a cavity.

13. The DRAM cell structure according to claim 9, wherein, The capacitor dielectric and the second electrode of the first and second storage capacitors are disposed in the common electrode slot, and the capacitor dielectric is in direct contact with the first electrode of the first and second storage capacitors. The second electrode, the capacitor dielectric, and the first electrode of the first and second storage capacitors all have tubular structures arranged in a vertical direction, and the second electrode surrounds the capacitor dielectric, while the capacitor dielectric surrounds the first electrode.

14. The DRAM cell structure according to claim 13, wherein, The source electrode line extends in the common electrode slot along the first horizontal direction and the vertical direction.

15. The DRAM cell structure according to claim 3, wherein, The gate dielectrics of the first gate-enclosed transistor, the second gate-enclosed transistor, and the third gate-enclosed transistor, and the capacitance dielectrics of the first and second storage capacitors are formed from the same dielectric layer.

16. The DRAM cell structure according to claim 15, wherein, The source line extends along the first horizontal direction.

17. The DRAM cell structure according to claim 1, wherein, The dielectric material of the first and second storage capacitors is formed of a high-K material.

18. The DRAM cell structure according to claim 1, wherein, The dielectric material of the first and second storage capacitors is formed of ferroelectric or antiferroelectric material.

19. A three-dimensional dynamic random access memory (DRAM) array structure, comprising: Multiple DRAM cell structures according to any one of claims 1-18 are arranged in L layers, M rows, and N columns, wherein L, M, and N are natural numbers greater than 1, and each of the multiple DRAM cell structures includes: The first sub-unit consists of a first gate-all-around transistor and a first storage capacitor; wherein, the first source / drain of the first gate-all-around transistor is shorted to the first electrode of the first storage capacitor at the first storage node, the second source / drain of the first gate-all-around transistor is shorted to the bit line extending in the vertical direction, and the second electrode of the first storage capacitor is connected to the source line. The second sub-unit is composed of a second gate-enclosed transistor and a second storage capacitor; wherein, the first source / drain of the second gate-enclosed transistor and the first electrode of the second storage capacitor are shorted to the second storage node, the second source / drain of the second gate-enclosed transistor are shorted to the bit line, and the second electrode of the second storage capacitor is connected to the source line; The first sub-unit and the second sub-unit are arranged in a mirror image in the vertical direction with the third gate-enclosed transistor as the center. The third gate-enclosed transistor is connected in series between the first gate-enclosed transistor and the second gate-enclosed transistor and electrically isolates the first memory node and the second memory node. M×N bit lines extend vertically inside the tubular structure formed by the first gate-enclosed transistor, the second gate-enclosed transistor, the third gate-enclosed transistor, the first storage capacitor, and the second storage capacitor in the M-row N-column DRAM cell structure, and are respectively connected to the second source / drain of the first gate-enclosed transistor and the second gate-enclosed transistor in the M-row N-column DRAM cell structure. L×M first word lines extend along the first horizontal direction and are respectively connected to the gate of the first gate-enclosed transistor in the L-layer M-row DRAM cell structure; L×M second word lines, extending along a first horizontal direction and respectively connected to the gates of the second gate-enclosed transistors in the L-layer M-row DRAM cell structure; and L×M isolation control lines extend along the first horizontal direction and are respectively connected to the gate of the third gate-enclosed transistor in the L-layer M-row DRAM cell structure.

20. The three-dimensional DRAM array structure according to claim 19, further comprising: M×N bit line holes extend through the DRAM array structure in the vertical direction, and the M×N bit lines are respectively disposed in the M×N bit line holes.

21. The three-dimensional DRAM array structure according to claim 19, wherein, The L-layer DRAM cell structure is stacked sequentially in the vertical direction, and In each row of the M-row DRAM cell structure, L first word lines and L second word lines are stacked alternately in the vertical direction.

22. The three-dimensional DRAM array structure according to claim 19, wherein, In each layer of the L-layer DRAM cell structure, M first word lines are connected together, and M second word lines are connected together.

23. The three-dimensional DRAM array structure according to claim 19, wherein, In each column of an N-column DRAM cell structure, M bit lines are connected together.

24. The three-dimensional DRAM array structure according to claim 19, wherein, L×M isolation control lines are connected together, either collectively or in groups, outside the DRAM array structure.

25. The three-dimensional DRAM array structure according to claim 19, further comprising: L source lines, each corresponding to the L-layer DRAM cell structure, extend along the first horizontal direction and are respectively connected to the second electrode of the storage capacitor in the L-layer DRAM cell structure.

26. The three-dimensional DRAM array structure according to claim 25, further comprising: A common electrode trench extends in the first horizontal direction and penetrates the DRAM array structure in the vertical direction, and is disposed between adjacent rows of DRAM cell structures. The L source lines are connected together through the common electrode trench.

27. The three-dimensional DRAM array structure according to claim 25, wherein, The L source lines are connected together, either collectively or in groups, outside the DRAM array structure.

28. The three-dimensional DRAM array structure according to claim 19, wherein, The first source / drain and second source / drain of the first gate-enclosed transistor, the second gate-enclosed transistor, and the third gate-enclosed transistor in each of the M rows and N columns of the L-layer DRAM cell structure, the channel region, and the first electrode of the first storage capacitor and the second storage capacitor are formed from the same semiconductor material layer.

29. The three-dimensional DRAM array structure according to any one of claims 19-28, further comprising: One or more common bit line groups extend along a second horizontal direction perpendicular to the first horizontal direction, and each common bit line group includes N common bit lines. Each of the M×N bit lines has a selection transistor above and / or below it for connecting the bit line and the common bit line.

30. The three-dimensional DRAM array structure according to claim 29, wherein, The M-row DRAM cell structure is divided into M / S row groups, where S is a natural number greater than 1 that is divisible by M. Each row group has an S-row DRAM cell structure. In this configuration, the first word lines of each layer within each row group are connected by a common first word line, and the second word lines of each row group are connected by a common second word line. Furthermore, the isolation control lines of each layer within each row group are connected by a common isolation control line. The three-dimensional DRAM array structure includes S common bit line groups. Each of the N common bit lines in each of the S common bit line groups is connected via a select transistor to a bit line having the same row number and column number in each row group. In this configuration, the gate of the selection transistor in each row group of the DRAM cell structure is connected to a common selection line.

31. The three-dimensional DRAM array structure according to claim 29, in, The M-row DRAM cell structure is divided into M / S row groups, where S is a natural number greater than 1 that is divisible by M. Each row group has an S-row DRAM cell structure. Each row group is divided into S / T sub-row groups, where T is a natural number greater than 1 that divides S. Each sub-row group has a T-row DRAM cell structure. In this configuration, the first word lines of each layer within each row group are connected by a common first word line, and the second word lines of each layer within each row group are connected by a common second word line. Furthermore, the isolation control lines of each layer within each row group are connected by a common isolation control line. The three-dimensional DRAM array structure includes T common bit line groups. Each of the N common bit lines in each of the T common bit line groups is connected via a select transistor to a bit line in each sub-row group that has the same row number and the same column number. In this configuration, the gate of the selection transistor in the DRAM cell structure of each sub-row is connected to a common selection line.

32. A semiconductor device, comprising: The three-dimensional DRAM array structure according to any one of claims 19 to 31; as well as A circuit board, comprising multiple circuits, wherein the three-dimensional DRAM array structure is disposed on the circuit board.

33. The semiconductor device according to claim 32, in, The plurality of circuits includes a memory interface circuit, a memory controller circuit, a word line circuit, and a bit line circuit. The bit line circuit is connected to the bit line of the three-dimensional DRAM array structure as described in any of claims 19-28. The word line circuit is connected to the word lines of the three-dimensional DRAM array structure, and The memory interface circuit is connected to the memory controller circuit and the bit line circuit.

34. The semiconductor device according to claim 32, in, The plurality of circuits includes a memory interface circuit, a memory controller circuit, a word line circuit, and a bit line circuit. The bit line circuit is connected to the common bit line of the three-dimensional DRAM array structure as described in any of claims 29-31. The word line circuit is connected to the word lines of the three-dimensional DRAM array structure, and The memory interface circuit is connected to the memory controller circuit and the bit line circuit.

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