A memory

Abstract

This disclosure provides a memory comprising at least one circuit array; the circuit array includes a common decoding circuit and N control circuit groups, where N is a positive integer; the N control circuit groups are arranged sequentially along a first direction, and the common decoding circuit is located at at least one edge of the circuit array in the first direction; each control circuit group includes multiple local driving circuits, each local driving circuit including an interconnected word line drive control circuit and a word line drive circuit, and each local driving circuit is connected to the common decoding circuit; the common decoding circuit is used to receive a first address signal, perform decoding processing, generate and output a main word line drive signal; the word line drive control circuit is used to receive a first enable signal and a main word line drive signal, and when the first enable signal is enabled, sends the main word line drive signal to the connected word line drive circuit. This solution can reduce circuit area occupation and alleviate line congestion.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory. Background Technology

[0002] With the development of semiconductor technology, semiconductor memories are widely used in electronic devices. Dynamic Random Access Memory (DRAM) is widely used due to its high access speed. DRAM mainly consists of two parts: a peripheral circuit area and a memory array area. To further improve storage density, 3D DRAM places the peripheral circuit and memory array on two separate chips, which are then connected by bonding. This makes the three-dimensional structure and internal traces of the memory more complex and crowded.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a memory including at least one circuit array; the circuit array includes a common decoding circuit and N control circuit groups, where N is a positive integer. The N control circuit groups are arranged sequentially along a first direction, and the common decoding circuit is located at at least one edge of the circuit array in the first direction; The control circuit group includes multiple local driving circuits, each local driving circuit including a word line driving control circuit and a word line driving circuit connected to each other, and each local driving circuit is connected to the common decoding circuit. The common decoding circuit is used to receive the first address signal, perform decoding processing, generate and output the main word line drive signal; The word line drive control circuit is used to receive a first enable signal and the main word line drive signal, and when the first enable signal is in an enabled state, it sends the main word line drive signal to the connected word line drive circuit.

[0005] In some embodiments, the memory includes a plurality of storage units, each of the control circuit groups corresponds to one of the storage units, and the first enable signal corresponds to the storage unit. When the first enable signal is in an enabled state, it indicates that the corresponding storage unit is selected.

[0006] In some embodiments, the word line drive control circuit includes: The logic processing circuit is used to receive the corresponding first enable signal and the main word line drive signal, and when the corresponding first enable signal is in the enabled state, output the main word line drive signal to the level conversion circuit. The level conversion circuit is connected to the logic processing circuit and is used to receive the main word line drive signal output by the logic processing circuit, perform level conversion, and then output it.

[0007] In some embodiments, the common decoding circuit is further configured to receive a second enable signal, and when the second enable signal is in an enabled state, to perform decoding processing on the first address signal.

[0008] In some embodiments, the common decoding circuit is located on one side edge of the circuit array in the first direction; or, the common decoding circuit is distributed on both sides edge of the circuit array in the first direction.

[0009] In some embodiments, the plurality of local driving circuits are connected to the common decoding circuit via a plurality of traces extending along the first direction.

[0010] In some embodiments, the area where the control circuit group is located includes a plurality of word line drive circuit regions arranged along a second direction; the word line drive control circuit is located on at least one side of the word line drive circuit region along the first direction; and / or, the word line drive control circuit is located in the circuit gap region between adjacent word line drive circuit regions.

[0011] In some embodiments, each of the control circuit groups includes at least one word line driving circuit array arranged along a first direction, and each word line driving circuit array includes M word line driving circuits, where M is a positive integer; the main word line driving signal includes M bits of main word line driving sub-signal. The word line drive control circuit is specifically used to receive the main word line drive sub-signal of the corresponding bit and the corresponding first enable signal, and when the first enable signal is in the enabled state, to send the corresponding main word line drive sub-signal to the connected word line drive circuit.

[0012] In some embodiments, the circuit array further includes N sub-word line drive signal decoding circuits; each sub-word line drive signal decoding circuit corresponds to one of the control circuit groups; The sub-word line drive signal decoding circuit is used to receive the second address signal, perform decoding processing, generate and output the sub-word line drive signal, and send the sub-word line drive signal to each of the word line drive circuits in the corresponding control circuit group.

[0013] In some embodiments, the memory includes a first chip and a second chip opposite each other in a third direction; the first chip includes each of the memory units, and the second chip includes each of the circuit arrays; the positions of each memory unit and the corresponding control circuit group are opposite each other in the third direction.

[0014] This disclosure provides a memory that combines functionally redundant main word line drive signal decoding circuits in multiple word line decoding structures into a common decoding circuit. This eliminates the need to set main word line drive signal decoding circuits at positions corresponding to array gaps, reducing circuit area and the number of circuits. Furthermore, placing the common decoding circuit on one or both sides of the circuit array in the first direction, rather than at positions corresponding to array gaps, further saves area at these positions and eliminates the need for main word line drive signals to be transmitted through lateral traces, alleviating congestion in lateral traces. Attached Figure Description

[0015] Figure 1 A top view schematic diagram of a memory provided in an embodiment of this disclosure. Figure 1 ; Figure 2 A schematic diagram of a main drive signal decoding circuit provided in an embodiment of this disclosure; Figure 3 A partially enlarged schematic diagram of a memory provided in an embodiment of this disclosure; Figure 4 A top view schematic diagram of a memory provided in an embodiment of this disclosure. Figure 2 ; Figure 5 A top view schematic diagram of a memory provided in an embodiment of this disclosure. Figure 3 ; Figure 6 A schematic diagram of a local drive circuit provided in an embodiment of this disclosure. Figure 1 ; Figure 7 A bonding diagram of a memory provided in an embodiment of this disclosure; Figure 8 A top view schematic diagram of a memory provided in an embodiment of this disclosure. Figure 4 ; Figure 9 This is a schematic diagram of signal transmission of a circuit provided in an embodiment of the present disclosure; Figure 10 A schematic diagram of a local drive circuit provided in an embodiment of this disclosure. Figure 2 ; Figure 11 This is a schematic diagram of a word line driving circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0016] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant applications and are not intended to limit the scope of this disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0018] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0019] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0020] See Figure 1 The diagram illustrates a device distribution schematic of a memory provided in an embodiment of this disclosure. Figure 1 Specifically, this can be a top-down view of a wafer-on-wafer (WOW) architecture memory. It should be noted that in a WOW architecture memory, the memory array used to store data is located on one chip (which can be referred to as the first chip), and the peripheral circuitry is located on another chip (which can be referred to as the second chip). The two chips can be arranged vertically opposite each other. Figure 1 The top view shown depicts the relevant structures within the second chip.

[0021] like Figure 1 As shown, the first direction is defined as the X direction, the second direction as the Y direction, and the third direction as the Z direction. Both the first and second directions are parallel to the chip surface and intersect. In this embodiment, the first and second directions are taken as perpendicular, and the third direction, i.e., the aforementioned perpendicular direction, is perpendicular to the chip surface. The definitions of directions used here will be followed in the subsequent figures and will not be elaborated upon further.

[0022] The first chip may include multiple memory arrays arranged along a first direction and / or a second direction, with the gap between adjacent memory arrays referred to as the array gap. Here, a memory array may specifically be a bank, and the corresponding array gap may be referred to as a bank gap. In other examples, the memory array may also be a bank group (BG) or other levels of memory arrays, which are not specifically limited here.

[0023] Each storage array may include multiple storage sections arranged along a first direction, such as Figure 1 As shown, in the second chip, at the position corresponding to the memory array, there are multiple circuit groups arranged along the first direction. The multiple circuit groups and multiple memory units correspond one-to-one. Specifically, the projection of the multiple circuit groups along the vertical direction partially or completely overlaps with the corresponding memory array. The projection of each circuit group along the vertical direction can at least partially or completely overlap with the corresponding memory unit.

[0024] In each circuit group, there are bit line sense amplifier (BLSA) areas on both sides along the first direction. Between the BLSA areas, along the second direction, there are multiple word line driver (SWD, also known as word line drive circuit) areas arranged in sequence. There are blank areas without circuits between adjacent SWD areas.

[0025] At the positions corresponding to the array gaps of the second chip, multiple word line (WL) decoding structures (or row decoding modules, which can be denoted as XDEC modules) and sense amplifier control circuits SaCtrl are arranged alternately. Each word line decoding structure includes a main word line drive signal decoding circuit DEC1 and a sub-word line drive signal decoding circuit DEC2. The main word line drive signal decoding circuit DEC1 decodes the row address signal to obtain the main word line drive signal Grdec<2m-1:0>, and the sub-word line drive signal decoding circuit DEC2 decodes the row address signal to obtain the sub-word line drive signal Phdec<2n-1:0>, where n and m are both positive integers. The main word line drive signal Grdec<2m-1:0> is used to select one word line from 2m word lines, and the selected word line can be activated. The sub-word line drive signal Phdec<2n-1:0> is used to control whether the word line selected by the main word line drive signal Grdec<2m-1:0> is activated.

[0026] See Figure 2 This illustration shows a schematic diagram of the structure of a main word line drive signal decoding circuit DEC1 provided in an embodiment of this disclosure. Figure 2As shown, the main word line drive signal decoding circuit DEC1 may include a first level shifter (LVL) LVL1, a second level shifter LVL2, and a third level shifter LVL3. The first level shifter LVL1 receives a first enable signal Sec and a first row address signal 432<7:0>. When the first enable signal Sec is enabled, it performs a level shift on the first row address signal 432<7:0> to obtain a first shifted address signal 432Hv<7:0>. It can be understood that the first level shifter LVL1 only changes the signal level and does not change the signal's logic state. The second level shifter LVL2 receives a second enable signal Gr and a second row address signal 510<7:0>. When the second enable signal Gr is enabled, it performs a level shift on the second row address signal 510<7:0> to obtain a second shifted address signal 510Hv<7:0>. It can be understood that the second level shifter LVL2 only changes the signal level and does not change the signal's logic state. The first enable signal Sec and the second enable signal Gr are also obtained by decoding the address signal. In some embodiments, the first enable signal Sec corresponds one-to-one with a storage unit and is used to indicate whether the corresponding storage unit is selected; the second enable signal Gr corresponds one-to-one with a storage unit group and is used to indicate whether the corresponding storage unit group is selected, wherein the storage unit group includes multiple storage units; the first row address signal 432<7:0> and the second row address signal 510<7:0> form a complete row address signal, and decoding the two can locate the specific row address, i.e., the specific word line.

[0027] The third level converter (LVL3) receives the first conversion address signal 432Hv<7:0> and the second conversion address signal 510Hv<7:0>. Based on the first conversion address signal 432Hv<7:0> and the second conversion address signal 510Hv<7:0>, it performs level conversion and decoding to obtain the main word line drive signal Grdec<2m-1:0>. It then sends the sub-signals of the corresponding bits in the main word line drive signal Grdec<2m-1:0> to the corresponding word line drivers.

[0028] It should be noted that this example uses 8-bit signals for the first row address signal 432<7:0> and the second row address signal 510<7:0>. In other examples, the bit count can vary. For instance, based on the 8-bit first row address signal 432<7:0> and the second row address signal 510<7:0>, a 64-bit main word line drive signal Grdec<63:0> can be decoded, in which case m=32.

[0029] It should also be noted that the main word line drive signal Grdec<2m-1:0> includes a 2m-bit main word line drive sub-signal Grdec, and the sub-word line drive signal Phdec<2n-1:0> includes a 2n-bit sub-word line drive sub-signal Phdec. The word line driver receives 1 bit of the main word line drive sub-signal Grdec and 1 bit of the sub-word line drive sub-signal Phdec. The main word line drive sub-signal Grdec can act on at least one word line driver in the circuit group to determine whether at least one word line connected to at least one word line driver circuit is allowed to be activated. When this bit of the main word line drive sub-signal Grdec is enabled, it indicates that the memory cell connected to the corresponding at least one word line may be accessed. The 1 bit of the sub-word line drive sub-signal Phdec can act on at least one word line driver in the circuit group to determine whether to activate at least one word line connected to at least one word line driver. When this bit of the sub-word line drive sub-signal Phdec is enabled, the corresponding word line can be activated. For each word line driver, the connected word line will only be activated if both the main word line driver sub-signal Grdec and the sub-word line driver sub-signal Phdec are enabled. In other words, the main word line driver sub-signal Grdec determines whether the word line driver transmits the sub-word line driver sub-signal Phdec to the word line, thus allowing the word line to be activated, while the sub-word line driver sub-signal Phdec determines whether the word line is activated at all.

[0030] It should also be noted that, in Figure 1 In the diagram, only one bold solid line represents the horizontal trace from the word line decoding structure to the circuit group; the rest are not shown. Figure 3 It shows Figure 1 A magnified view of the area within the dashed box, as shown below. Figure 3 As shown, in the SWD region, each SWD receives the sub-word line drive sub-signal Phdec and the main word line drive sub-signal Grdec for the corresponding bit. Based on the state of the corresponding sub-word line drive sub-signal Phdec and the main word line drive sub-signal Grdec, it is determined whether to enable the corresponding word line.

[0031] Because the signal lines of the main word line drive signal Grdec<2m-1:0> and the sub-word line drive signal Phdec<2n-1:0> are routed together through the word line decoding structure to the corresponding position of the memory array, the horizontal traces at the corresponding position of the memory array become congested. In addition, the main word line drive signal decoding circuit DEC1 is repeated in the word line decoding structure corresponding to each memory section, resulting in wasted area.

[0032] Based on this, embodiments of the present disclosure provide a memory including at least one circuit array; the circuit array includes a common decoding circuit and N control circuit groups, where N is a positive integer; the N control circuit groups are arranged sequentially along a first direction, and the common decoding circuit is located at at least one edge of the circuit array in the first direction; each control circuit group includes a plurality of local driving circuits, each local driving circuit including a word line driving control circuit and a word line driving circuit interconnected, and each local driving circuit is connected to the common decoding circuit; the common decoding circuit is used to receive a first address signal, perform decoding processing, generate and output a main word line driving signal; the word line driving control circuit is used to receive a first enable signal and a main word line driving signal, and when the first enable signal is in an enabled state, sends the main word line driving signal to the connected word line driving circuit.

[0033] In this embodiment, the main word line drive signal decoding circuits with overlapping functions in multiple word line decoding structures are merged into a common decoding circuit. This eliminates the need to place the main word line drive signal decoding circuit DEC1 at the position corresponding to the array gap, reducing the circuit area and the number of circuits. Furthermore, placing the common decoding circuit on one or both sides of the circuit array in the first direction, rather than at the position corresponding to the array gap, further saves area at the array gap position and eliminates the need for the main word line drive signal to be transmitted through lateral traces, alleviating congestion in the lateral traces. A detailed description will follow with reference to the accompanying drawings.

[0034] In one embodiment of this disclosure, a memory is provided. Figure 4 This is a top view schematic diagram of the memory. Figure 5 This is another top view schematic diagram of the memory. Figure 6 This is a schematic diagram of a local drive circuit. For example... Figure 4 or Figure 5 As shown, the memory includes at least one circuit array 100; the circuit array 100 includes a common decoding circuit 110 (which may be denoted as GrCon) and N control circuit groups 120, where N is a positive integer; N control circuit groups 120 are arranged sequentially along a first direction, and a common decoding circuit 110 is located at at least one edge of the circuit array 100 in the first direction. The control circuit group 120 includes a plurality of local drive circuits 130 (which may be referred to as GrLoc). The local drive circuit 130 includes word line drive control circuit 140 and word line drive circuit 150 connected to each other, and each local drive circuit 130 is connected to the common decoding circuit 110. The common decoding circuit 110 is used to receive the first address signal, perform decoding processing, generate and output the main word line drive signal Grdec<2m-1:0>. The word line drive control circuit 140 is used to receive the first enable signal Sec and the main word line drive signal Grdec<2m-1:0>. When the first enable signal Sec is enabled, the main word line drive signal Grdec<2m-1:0> is sent to the connected word line drive circuit 150.

[0035] It should be noted that, as Figure 4 or Figure 5 As shown, the N control circuit groups 120 are respectively denoted as control circuit group 120-1 to control circuit group 120-N. Figure 4 In the example, the common decoding circuit 110 is located on both sides of the circuit array 100 in the first direction. Specifically, the common decoding circuits 110 on both sides can be the same common decoding circuit 110. In this way, each local driving circuit 130 receives the main word line driving signal output from the two identical common decoding circuits, thereby increasing the signal driving capability, improving accuracy, and effectively ensuring signal quality. Figure 5 In the example, the common decoding circuit 110 is located on one side edge of the circuit array 100 in the first direction. Here, it is taken as an example that it is located on the side closer to the control circuit group 120-1. In other examples, it can also be located on the side closer to the control circuit group 120-N. In this way, by setting the common decoding circuit 110 only on one side edge of the circuit array 100, the area occupied can be further reduced.

[0036] It should also be noted that, in this embodiment of the disclosure, a circuit array 100 corresponds to a storage array, which can be a bank. In other examples, the storage array can also be a bank group (BG) or a storage array divided in other ways, without specific limitation. In the following description, a bank will be used as an example.

[0037] In this embodiment of the disclosure, the memory can be of a WOW structure, such as... Figure 7 As shown, the memory may include a first chip 700 and a second chip 800 opposite each other along a third direction. The first chip 700 and the second chip 800 are interconnected by a plurality of bonding structures 900 to form a three-dimensional memory structure. The bonding structures 900 may be hybrid bonding structures, solder ball bonding, etc., and are not specifically limited thereto.

[0038] The first chip 700 is an array area chip, which includes multiple memory arrays, each of which includes multiple memory cells for storing data. The second chip 800 is a circuit area chip, which is used to perform related operations on the data stored in the first chip 700. It includes each circuit array 100, specifically including each control circuit group 120 involved in the embodiments of this disclosure, as well as other data input / output circuits, row / column decoders, clock generation / processing circuits, etc.

[0039] Each memory array may include N memory sections arranged along a first direction, with each of the N memory sections corresponding to one of the N control circuit groups 120. Multiple memory sections may form a memory section group. For example... Figure 4 or Figure 5 As shown, each storage unit and its corresponding control circuit group 120 are positioned opposite each other in the third direction, and their projections in the third direction at least partially overlap; the array gap is the gap between adjacent storage arrays, and multiple circuits are provided at the position of the second chip corresponding to the array gap in the third direction.

[0040] Thus, in this embodiment of the present disclosure, the common decoding circuit 110 is disposed on one or both edges of the circuit array 100 in the first direction. When the common decoding circuit 110 transmits the main word line driving signal Grdec<2m-1:0> to the local driving circuit 130, it can be connected by multiple traces extending along the first direction to realize the transmission of the main word line driving signal Grdec<2m-1:0> to the local driving circuit 130. Since the main word line driving signal Grdec<2m-1:0> is transmitted through the traces in the first direction (vertical direction), the traces in the second direction (horizontal direction) are reduced, and the congestion of the horizontal traces is alleviated.

[0041] In this embodiment of the disclosure, the memory can be DRAM. For DRAM, it can not only conform to memory specifications such as Double Data Rate (DDR), DDR2, DDR3, DDR4, DDR5, DDR6, etc., but also conform to memory specifications such as Low Power DDR (LPDDR), LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc. There are no limitations here.

[0042] It should also be noted that, such as Figure 4 or Figure 5As shown, the area where each control circuit group 120 is located extends along the second direction, and the two sides of the area where the control circuit group 120 is located in the first direction are BLSA areas. In other examples, the BLSA area may also be located only on one side edge of the area where the control circuit group 120 is located in the first direction.

[0043] For each control circuit group 120, between the BLSA regions on both sides, there are multiple SWD regions arranged along the second direction, each SWD region including at least one word line drive circuit 150. Here, only... Figure 4 and Figure 5 A word line driver circuit 150 is shown in the lower right SWD area; the rest are not shown. The word line driver control circuit 140, connected to the word line driver circuit 150, can be located on one side of the corresponding SWD area in the first direction, for example... Figure 4 or Figure 5 The area indicated by the bold black solid line is located between the BLSA and SWD areas. Here, only... Figure 4 and Figure 5 The black bold solid line area in the lower right corner shows a word line drive control circuit 140, while the others are not shown. This ensures that the word line drive control circuit 140 is connected and driven by the corresponding word line drive circuit 150 in close proximity, avoiding excessive delay. Alternatively, the word line drive control circuit 140 connected to the word line drive circuit 150 can also be located on both sides of the corresponding SWD area in the first direction, so that it can not only drive in close proximity, but also avoid congestion on one side.

[0044] In other embodiments, such as Figure 8 As shown, the word line drive control circuit 140 can also be placed in the blank area (called the circuit gap area) between adjacent SWD areas. Here, it is only in the blank area between adjacent SWD areas. Figure 8 A word line drive control circuit 140 is shown in the blank area in the lower right corner; the rest are not shown. This eliminates the need to allocate a new area between the SWD and BLSA areas for the word line drive control circuit 140, fully utilizing the existing blank area of ​​the chip and achieving efficient use of the chip area.

[0045] Alternatively, in this embodiment, a portion of the word line driving control circuit 140 may be disposed on at least one side of the SWD region in the first direction, and a portion of the word line driving control circuit 140 may be disposed in the circuit gap region. The specific configuration can be determined according to actual conditions, and no specific limitation is made here.

[0046] In this embodiment of the disclosure, the first address signal is a row address signal (or word line address signal). In conjunction with the foregoing... Figure 2As shown, the row address signal may include a first row address signal 432<7:0> and a second row address signal 510<7:0>, that is, the first address signal includes the first row address signal 432<7:0> and the second row address signal 510<7:0>. It is understood that the type and number of bits of the row address signal shown here are only an example and are not limited thereto.

[0047] The common decoding circuit 110 directly decodes the first address signal to obtain the main word line drive signal Grdec<2m-1:0>. Here, the common decoding circuit 110 is a shared circuit for N control circuit groups 120. That is, for N control circuit groups 120, only the shared common decoding circuit 110 needs to be set, and there is no need to set multiple main word line drive signal decoding circuits DEC1 with overlapping functions. This can greatly reduce the area occupied by the circuit and avoid the area waste caused by setting multiple circuits with overlapping functions.

[0048] In this embodiment of the disclosure, the first enable signal Sec is also a signal obtained by decoding the address signal. Specifically, it is obtained by decoding the address signal of the storage unit, that is, the first enable signal Sec corresponds to the storage unit, each storage unit has its own first enable signal Sec, and multiple word line drive control circuits 140 corresponding to the same storage unit receive the same first enable signal Sec. When the first enable signal Sec is enabled, it indicates that the corresponding memory section is selected. At this time, the word line drive control circuit 140 sends the main word line drive signal Grdec<2m-1:0> to its connected word line drive circuit 150, so that the word line drive circuit 150 determines whether to allow activation of the corresponding word line based on the main word line drive signal Grdec<2m-1:0>. Otherwise, if the first enable signal Sec is disabled, it means that the corresponding memory section is not selected. At this time, the word line drive control circuit 140 will not send the main word line drive signal Grdec<2m-1:0> to its connected word line drive circuit 150, and the word line corresponding to the word line drive circuit 150 will not be activated.

[0049] For example, Figure 9 This is a schematic diagram of the signal transmission between the common decoding circuit 110 and the word line drive control circuit 140. Figure 9 In the example where m=32, the first address signal includes the first row address signal 432<7:0> and the second row address signal 510<7:0>. Figure 9 As shown, the common decoding circuit 110 is also used to receive the second enable signal Gr, and to perform decoding processing on the first address signal when the second enable signal Gr is in the enabled state.

[0050] It should be noted that the common decoding circuit 110 also receives a second enable signal Gr, which is used to control whether the common decoding circuit 110 performs a decoding operation. That is, the common decoding circuit 110 performs a decoding operation only when the second enable signal Gr is enabled; otherwise, if the second enable signal Gr is disabled, the common decoding circuit 110 will not perform a decoding operation to save power consumption.

[0051] It should also be noted that the second enable signal Gr is also obtained by decoding the address signal, specifically, by decoding the memory group address signal. The second enable signal Gr indicates whether the corresponding memory group is selected; the corresponding decoding operation will only be executed when the corresponding memory group is selected. Here, a memory group includes at least one memory unit.

[0052] In this embodiment of the present disclosure, the decoding circuits for decoding the address signal to obtain the first enable signal Sec and the decoding circuits for decoding the address signal to obtain the second enable signal Gr can also be located at positions corresponding to the array gaps, or at other positions in the memory.

[0053] In some embodiments, the memory group address signal and the memory address signal can be implemented by multiplexing a portion of the bits in the row address signal. That is, in the complete address signal, there may not necessarily be bits that serve solely as the memory group address signal and the memory address signal; instead, a portion of the bits in the row address signal may be used as the memory group address signal and the memory address signal.

[0054] Thus, when the second enable signal Gr is enabled, the common decoding circuit 110 decodes the first address signal to obtain the main word line drive signal Grdec<63:0>. Here, taking the main word line drive signal as 64 bits as an example, each bit is recorded as a main word line drive sub-signal, denoted by Grdec. That is, the main word line drive signal Grdec<63:0> includes 64 bits of main word line drive sub-signal Grdec.

[0055] It should be noted that each word line drive control circuit 140 receives the corresponding bit of the main word line drive sub-signal Grdec. That is, for the 64-bit main word line drive signal Grdec<63:0>, there are actually 64 word line drive control circuits 140. Each word line drive control circuit 140 receives the corresponding first enable signal Sec and the corresponding bit of the main word line drive sub-signal Grdec. When the first enable signal Sec is enabled, the corresponding main word line drive sub-signal Grdec is output to the connected word line drive circuit 150.

[0056] In some embodiments, such as Figure 9As shown, the word line drive control circuit 140 can also perform level conversion on the corresponding main word line drive sub-signal Grdec<63:0> to obtain the converted main word line drive signal GrdecHv<63:0>, which is then transmitted to the corresponding word line drive circuit 150. Each bit of the converted main word line drive signal GrdecHv<63:0> is denoted as the converted main word line drive sub-signal GrdecHv.

[0057] In this way, the main word line drive signal decoding circuit, which was originally located in the word line decoding structure, is moved to the vicinity of the longitudinal edge region and SWD region of the memory array. The main word line drive signal is fully decoded at one or both edges of the memory array in the first direction. The level conversion of the main word line drive signal is performed in front of the word line drive circuit 150 of each memory section before it is sent to the word line drive circuit 150. This will not have any adverse effect on the normal operation of the word line drive circuit 150.

[0058] It should be noted that, in the embodiments of this disclosure, the main word line driving sub-signal Grdec<63:0> and the converted main word line driving signal GrdecHv<63:0> can be signals with different level magnitudes but the same logic state. In the following description, the two will not be specifically distinguished and will be regarded as the same. For ease of description, they will be uniformly referred to as main word line driving signal and main word line driving sub-signal, and the level conversion will not be specifically emphasized.

[0059] It should also be noted that different word line driver circuits 150 may receive the same main word line driver sub-signal Grdec. Therefore, in some implementations, multiple word line driver circuits 150 receiving the same main word line driver sub-signal Grdec can be connected to the same word line driver control circuit 140. That is, the number of word line driver control circuits 140 and the number of word line driver circuits 150 are not the same. This also saves area.

[0060] In some embodiments, such as Figure 10 As shown, the word line drive control circuit 140 may include: The logic processing circuit 160 is used to receive the corresponding first enable signal Sec and the main word line drive signal Grdec<2m-1:0>. When the corresponding first enable signal Sec is in the enabled state, the main word line drive signal Grdec<2m-1:0> is output to the level conversion circuit 170. The level conversion circuit 170 is connected to the logic processing circuit 160 and is used to receive the main word line drive signal Grdec<2m-1:0> output by the logic processing circuit 160, perform level conversion, and then output it.

[0061] like Figure 10As shown, the word line drive control circuit 140 may further include: a buffer circuit 180, connected to the level conversion circuit 170, for receiving the signal output by the level conversion circuit, performing drive enhancement, and then sending it to the word line drive circuit 150.

[0062] It should be noted that the logic processing circuit 160 can specifically be an AND logic circuit. The level conversion circuit 170 is a level converter (LVL). An LVL can achieve compatible signal level conversion between different voltage domains, ensuring that digital signals can be correctly identified and transmitted. When two devices (such as a processor and peripherals, or chip modules with different power domains) operate at different voltages (e.g., 1.8V and 3.3V respectively), direct connection may result in the logic level not being recognized. An LVL can convert the signal from one voltage range to another, solving the voltage mismatch problem. At the same time, by adjusting the high / low level matching of the signal, the LVL avoids logic errors, signal distortion, or device damage, ensuring communication reliability.

[0063] like Figure 10 As shown, the logic processing circuit 160 can be an AND gate. In each word line drive control circuit 140, the AND gate receives the corresponding first enable signal Sec and the corresponding bit's main word line drive sub-signal Grdec. When the first enable signal Sec is in the enabled state (i.e., 1), the corresponding bit's main word line drive sub-signal Grdec is output to the level conversion circuit 170. The level conversion circuit 170 performs level conversion to obtain the converted main word line drive sub-signal GrdecHv. That is, before the word line drive circuit 150, the main word line drive sub-signal Grdec is enabled by the first enable signal Sec and then level conversion is performed. At the same time, the buffer circuit 180 can further enhance the drive capability of the converted main word line drive sub-signal GrdecHv before outputting it to the word line drive circuit 150.

[0064] It should also be noted that the AND gate in logic processing circuit 160 is only one example when the enable state of the first enable signal Sec is 1; in other examples, the enable state can also be designed to be 0 and / or other logic gates or combinations of logic gates can be used to implement logic processing circuit 160.

[0065] In some embodiments, such as Figure 4 or Figure 5 or Figure 8 As shown, the circuit array 100 also includes N sub-word line drive signal decoding circuits DEC2; each sub-word line drive signal decoding circuit DEC2 corresponds to a control circuit group 120; The sub-word line drive signal decoding circuit DEC2 is used to receive the second address signal, perform decoding processing, generate and output the sub-word line drive signal Phdec<2n-1:0>, and send the sub-word line drive signal Phdec<2n-1:0> to each word line drive circuit 150 in the corresponding control circuit group 120.

[0066] It should be noted that the sub-word line drive signal decoding circuit DEC2 is still located in Figure 1 In the word-line decoding structure, the region corresponding to the array gap has a decoding method and connection method similar to... Figure 1 Similarly, the sub-word line drive signal Phdec<2n-1:0> is transmitted to the corresponding word line drive circuit 150 through the lateral trace.

[0067] It should also be noted that the sub-word line drive signal Phdec<2n-1:0> includes 2n bits of sub-word line drive sub-signal Phdec. Each word line drive circuit 150 actually receives the corresponding 1 bit of sub-word line drive sub-signal Phdec. 1 bit of sub-word line drive sub-signal Phdec can correspond to multiple word line drive circuits 150 in the same control circuit group 120.

[0068] It should also be noted that the sub-word line drive signal decoding circuit DEC2 corresponds one-to-one with the control circuit group 120, and the second address signal is the address signal used to decode and determine whether the selected word line is activated.

[0069] For example, see Figure 11 This illustrates a schematic diagram of a word line driving circuit 150 provided in an embodiment of this disclosure. Figure 11 As shown, the word line driving circuit 150 includes three transistors: a first transistor M1, a second transistor M2, and a third transistor M3. The first transistor M1 is a PMOS transistor, while the second and third transistors M2 are NMOS transistors. The gates of the first and second transistors M1 and M2 receive the main word line driving sub-signal GrdecHv. In other examples, the gates of the first and second transistors M1 and M2 may also receive the inverted signal GrdecHvN of the main word line driving sub-signal. The gate of the third transistor M3 receives the inverted signal PhdecN of the sub-word line driving sub-signal Phdec. The source of the first transistor M1 receives the sub-word line driving sub-signal Phdec. The sources of the second and third transistors M2 are connected to ground. The drains of the first, second, and third transistors M1 and M3 are all connected to the corresponding word line WL.

[0070] In one scenario, if the main word line driver sub-signal GrdecHv = 0 (enabled state) and the sub-word line driver sub-signal Phdec = 1 (enabled state), it indicates that the word line WL connected to the word line driver circuit 150 has been selected and activated, and word line WL is at a high level. In all other scenarios, it indicates that the word line has not been selected, and word line WL is at a low level.

[0071] In another scenario, if the gates of the first transistor M1 and the second transistor M2 receive the inverted signal GrdecHvN of the main word line drive sub-signal, then if GrdecHvN = 0 (enabled state) and Phdec = 1 (enabled state), it indicates that the word line WL connected to the word line drive circuit 150 has been selected, and word line WL is at a high level. In all other cases, word line WL is not selected, and word line WL is at a low level.

[0072] In addition, the third transistor M3 is used to quickly shut down the corresponding word line after the word line WL is selected and the corresponding operation is completed.

[0073] It should be noted that the main word line driving sub-signal GrdecHv or the inverted signal GrdecHvN of the main word line driving sub-signal is obtained by the common decoding circuit 110 decoding the first address signal; the sub-word line driving word signal Phdec and the inverted signal PhdecN of the sub-word line driving word signal are obtained by the sub-word line driving signal decoding circuit DEC2 decoding the second address signal. Specifically, one of them can be obtained by decoding the second address signal, and then inverted or delayed to obtain the other.

[0074] It should also be noted that the main word line drive sub-signal Grdec and the word line drive circuit 150 are not necessarily in a one-to-one correspondence, nor are the sub-word line drive word signal Phdec and the word line drive circuit 150. Multiple different word line drive circuits 150 may receive the same main word line drive sub-signal Grdec, and / or, multiple different word line drive circuits 150 may receive the same sub-word line drive signal Phdec and the inverted signal PhdecN of the same sub-word line drive signal.

[0075] For example, Figure 4 or Figure 5 or Figure 8As shown, in each control circuit group 120, multiple SWD regions are arranged sequentially along the second direction. Each SWD region includes multiple word line driving circuits 150. Multiple word line driving circuits 150 located in different control circuit groups 120 along the first direction and at the same or similar positions in the second direction can receive the same main word line driving sub-signal Grdec. Multiple word line driving circuits 150 located in different SWD regions of the same control circuit group along the first direction can receive the same sub-word line driving signal Phdec and the inverted signal PhdecN of the same sub-word line driving signal. In other examples, the specific main word line driving sub-signal Grdec, sub-word line driving sub-signal Phdec, and the inverted signal PhdecN of the sub-word line driving signal can be set according to the odd / even order of the word lines, etc. This disclosure does not specifically limit this aspect.

[0076] In some embodiments, such as Figure 4 or Figure 5 or Figure 8 As shown, a single SWD region or multiple adjacent SWD regions along the second direction constitute a word line driver circuit array. Each control circuit group 120 includes at least one word line driver circuit array arranged along the first direction. For N word line driver circuit arrays arranged along the first direction, they share the same main word line driver signal Grdec<2m-1:0>. For example... Figure 4 As shown, along the first direction in order from left to right, the first and second SWD regions form the 0th word line driver circuit array, and their shared main word line driver signal is denoted as the 0th main word line driver signal Grdec0<2m-1:0>; the third and fourth SWD regions form the 1st word line driver circuit array, and their shared main word line driver signal is denoted as the 1st main word line driver signal Grdec1<2m-1:0>; the fifth and sixth SWD regions form the 2nd word line driver circuit array, and their shared main word line driver signal is denoted as the 2nd main word line driver signal Grdec2<2m-1:0>... and so on.

[0077] Assuming that for each control circuit group 120, the area it belongs to includes 2P SWD regions, forming P word line drive circuit arrays, where P is a positive integer, then the 2P-1th and 2Pth SWD regions form the P-1th word line drive circuit array, and their shared main word line drive signal is denoted as the P-1th main word line drive signal GrdecP-1<2m-1:0>.

[0078] Correspondingly, the common decoding circuit 110 may include P sub-common decoding circuits, which are used to decode the first address signal respectively and generate the corresponding main word line drive signal Grdec<2m-1:0>.

[0079] Each word line driver circuit array includes M word line driver circuits 150, meaning each word line driver circuit array corresponds to M word lines. Here, M is a positive integer, and M can be equal to 2m. The main word line driver signal Grdec<2m-1:0> includes 2m bits of main word line driver sub-signal Grdec. Each bit of main word line driver sub-signal Grdec is transmitted to one of the word line driver circuits 150 in the N word line driver circuit arrays via a trace along the second direction.

[0080] In summary, this disclosure provides a memory that reduces area and the number of horizontal traces in the corresponding positions of the memory array. The main word line drive signal decoding circuit, originally located in the word line decoding structure, is split into two parts: a common decoding circuit 110 and a word line drive control circuit 140. The common decoding circuit 110 is a decoding module shared by the memory array, and the word line drive control circuit 140 is a level conversion module in the memory array. The main word line drive signal decoding circuits corresponding to each memory unit in the word line decoding structure are merged into a common decoding circuit 110 and moved to the vertical edge of the memory array. The split word line drive control circuit is moved to the vicinity of the SWD region corresponding to the memory array, saving circuit area at the corresponding positions of the array gaps. The common decoding circuit 110 can be distributed on one edge of the memory array in the first direction or on both edges. All memory units share the common decoding circuit 110, and decoding is performed near the SWD region using a local drive circuit 130, reducing the area occupied by a separate main word line drive signal decoding circuit for each memory unit.

[0081] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0082] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0083] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0084] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0085] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0086] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0087] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory, comprising: It includes at least one circuit array; the circuit array includes a common decoding circuit and N control circuit groups, where N is a positive integer; The N control circuit groups are arranged sequentially along a first direction, and the common decoding circuit is located at at least one edge of the circuit array in the first direction; The control circuit group includes multiple local driving circuits, each local driving circuit including a word line driving control circuit and a word line driving circuit connected to each other, and each local driving circuit is connected to the common decoding circuit. The common decoding circuit is used to receive the first address signal, perform decoding processing, generate and output the main word line drive signal; The word line drive control circuit is used to receive a first enable signal and the main word line drive signal, and when the first enable signal is in an enabled state, it sends the main word line drive signal to the connected word line drive circuit.

2. The memory of claim 1, wherein, The memory includes multiple storage units, and each of the control circuit groups corresponds to one storage unit. The first enable signal corresponds to the storage unit, and when the first enable signal is in the enabled state, it indicates that the corresponding storage unit is selected.

3. The memory of claim 2, wherein, The word line driving control circuit includes: The logic processing circuit is used to receive the corresponding first enable signal and the main word line drive signal, and when the corresponding first enable signal is in the enabled state, output the main word line drive signal to the level conversion circuit. The level conversion circuit is connected to the logic processing circuit and is used to receive the main word line drive signal output by the logic processing circuit, perform level conversion, and then output it.

4. The memory according to claim 2, characterized in that, The common decoding circuit is also used to receive a second enable signal, and when the second enable signal is in an enabled state, to perform decoding processing on the first address signal.

5. The memory of claim 1, wherein, The common decoding circuit is located on one side edge of the circuit array in the first direction; or, the common decoding circuit is distributed on both sides edge of the circuit array in the first direction.

6. The memory of claim 1, wherein, The plurality of local driving circuits are connected to the common decoding circuit via a plurality of traces extending along the first direction.

7. The memory of claim 1, wherein, The area containing the control circuit group includes a plurality of word line drive circuit areas arranged along the second direction; the word line drive control circuit is located on at least one side of the word line drive circuit area along the first direction; and / or, the word line drive control circuit is located in the circuit gap area between adjacent word line drive circuit areas.

8. The memory of any of claims 1-7, wherein, Each of the control circuit groups includes at least one word line driving circuit array arranged along a first direction, and each word line driving circuit array includes M word line driving circuits, where M is a positive integer; the main word line driving signal includes M bits of main word line driving sub-signal; The word line drive control circuit is specifically used to receive the main word line drive sub-signal of the corresponding bit and the corresponding first enable signal, and when the first enable signal is in the enabled state, to send the corresponding main word line drive sub-signal to the connected word line drive circuit.

9. The memory of claim 8, wherein, The circuit array further includes N sub-word line drive signal decoding circuits; each sub-word line drive signal decoding circuit corresponds to one of the control circuit groups. The sub-word line drive signal decoding circuit is used to receive the second address signal, perform decoding processing, generate and output the sub-word line drive signal, and send the sub-word line drive signal to each of the word line drive circuits in the corresponding control circuit group.

10. The memory of claim 2, wherein, The memory includes a first chip and a second chip that are opposite each other in a third direction; the first chip includes each of the memory units, and the second chip includes each of the circuit arrays; the positions of each memory unit and the corresponding control circuit group are opposite each other in the third direction.

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