Semiconductor device and method for performing read operation on memory device

Abstract

A semiconductor device and a method for performing a read operation on a memory device are disclosed. The semiconductor device may include a memory array having bit lines and memory cells coupled to the bit lines. The semiconductor device further includes sensing circuitry for sensing data from the memory cells. The semiconductor device further includes a pre-charge circuitry having an asymmetric clock inverter having an input terminal, an output terminal, and at least one enable terminal. The input terminal is connected to the bit lines. The output terminal is connected to the bit lines. In response to receiving an enable signal on at least one enable terminal, the pre-charge circuitry pre-charges the bit lines to a pre-charge voltage. The pre-charge voltage is higher than a threshold voltage of the sensing circuitry and lower than a supply voltage.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for performing a read operation on a memory device. Background Technology

[0002] Memory devices such as Read-Only Memory (ROM), Static Random Access Memory (SRAM), Resistive Random Access Memory (RRAM), and Magnetic Random Access Memory (MRAM) include multiple cells arranged in columns and rows to form an array. Memory cells in a row are connected to bit lines, which in turn are connected to a sense amplifier. When a read operation is performed on a target memory cell in a row corresponding to a predetermined address, the bit lines are charged to a predetermined voltage level (also known as the pre-charge phase of the read operation). The memory cell is then coupled to the bit lines so that the voltage level of the bit lines changes in response to data stored in the memory cell (also known as the evaluation phase of the read operation). The sense amplifier then converts the voltage level on the bit lines into a logic 1 output or a logic 0 output (also known as the output phase of the read operation). Therefore, the time required to perform a read operation is determined by many factors, including the time required to charge the bit line to a predetermined voltage level and the time required to discharge during the evaluation phase. Summary of the Invention

[0003] Some embodiments disclosed herein include a semiconductor device. The semiconductor device includes: a memory array having bit lines and memory cells coupled to the bit lines; a sensing circuit for sensing data from the memory cells; and a pre-charge circuit including an asymmetric clock inverter having an input terminal, an output terminal, and at least one enable terminal, wherein: the input terminal is connected to the bit lines, the output terminal is connected to the bit lines, and in response to receiving an enable signal on the at least one enable terminal, the pre-charge circuit pre-charges the bit lines to a pre-charge voltage, wherein the pre-charge voltage is higher than a threshold voltage of the sensing circuit and lower than a supply voltage.

[0004] Some embodiments disclosed herein include a semiconductor device. The semiconductor device includes: a memory array having bit lines and memory cells coupled to the bit lines; a precharge circuit including a first terminal, a second terminal, and at least one enable terminal, wherein the first terminal is connected to the bit lines, and wherein in response to receiving a precharge enable signal on the at least one enable terminal, the precharge circuit precharges the bit lines to a precharge voltage; and a voltage detector circuit including a first terminal and a second terminal, wherein the first terminal of the voltage detector is connected to the bit lines, and the second terminal of the voltage detector is connected to the second terminal of the precharge circuit, the voltage detector being configured to sense the bit line voltage of the bit lines and provide a bit line feedback signal to the precharge circuit based on the sensed bit line voltage, the precharge circuit being configured to change the precharge of the bit lines based on the bit line feedback signal.

[0005] Some embodiments disclosed herein include a method for performing a read operation on a memory device. The method includes: selecting a bit line of a memory array of the memory device, the device having bit lines and memory cells coupled to the bit lines; an enable precharge circuit precharges the bit lines to a precharge voltage, wherein the precharge circuit includes an asymmetric clock inverter having an input terminal, an output terminal, and at least one enable terminal, wherein: the input terminal is connected to the bit line, the output terminal is connected to the bit line, and the precharge circuit precharges the bit lines to the precharge voltage in response to receiving an enable signal on at least one enable terminal; and after charging the bit lines, an enable sensing circuit performs a read operation on the memory cells connected to the bit lines. Attached Figure Description

[0006] The state of this disclosure is in relation to the accompanying items. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a schematic diagram illustrating a portion of a memory device according to some embodiments;

[0008] Figure 2 This is a timing diagram illustrating the signals of a memory device during a read operation according to some embodiments;

[0009] Figure 3 This is a block diagram of a pre-charge circuit according to some embodiments;

[0010] Figure 4A According to some embodiments Figure 3 The first example circuit diagram of the pre-charge circuit;

[0011] Figure 4BThe illustrations are based on some embodiments. Figure 4A The first example circuit diagram is a schematic diagram of the input and output signals of the pre-charge circuit;

[0012] Figure 4C The illustration is based on some embodiments when Figure 4A The timing diagram of the precharge circuit in the first example circuit diagram is used for the signal when the bit line is high precharged.

[0013] Figure 4D According to some embodiments Figure 3 The second example circuit diagram of the pre-charging circuit;

[0014] Figure 4E According to some embodiments Figure 3 The third example circuit diagram of the pre-charging circuit;

[0015] Figure 4F According to some embodiments Figure 3 The fourth example circuit diagram of the pre-charging circuit;

[0016] Figure 5A The illustration is based on some embodiments when Figure 4A The first example circuit diagram is a schematic diagram of the input and output signals of the precharge circuit used for low precharge of the bit line.

[0017] Figure 5B The illustration is based on some embodiments when Figure 4A The timing diagram of the precharge circuit in the first example circuit diagram is used for the signal when the bit line is high precharged.

[0018] Figure 6 This is a block diagram of an enhanced pre-charge circuit according to some embodiments;

[0019] Figure 7A According to some embodiments Figure 6 A circuit diagram of a first example of an enhanced precharge circuit;

[0020] Figure 7B The illustration is based on some embodiments when Figure 7A The timing diagram of the enhanced precharge circuit for high precharge of bit lines in the first example circuit diagram;

[0021] Figure 7C According to some embodiments Figure 6 A second example circuit diagram of the enhanced pre-charge circuit;

[0022] Figure 7D According to some embodiments Figure 6 The third example circuit diagram of the enhanced pre-charge circuit;

[0023] Figure 7E According to some embodiments Figure 6 The fourth example circuit diagram of the enhanced pre-charge circuit;

[0024] Figure 8 This is a block diagram of an enhanced low precharge circuit according to some embodiments;

[0025] Figure 9A According to some embodiments Figure 8 A circuit diagram of a first example of an enhanced low precharge circuit;

[0026] Figure 9B The illustration is based on some embodiments when Figure 9A The timing diagram of the enhanced low precharge circuit for low precharge of bit lines in the first example circuit diagram;

[0027] Figure 9C According to some embodiments Figure 8 A second example circuit diagram of an enhanced low precharge circuit;

[0028] Figure 9D According to some embodiments Figure 8 The third example circuit diagram of the enhanced low precharge circuit;

[0029] Figure 9E According to some embodiments Figure 8 The fourth example circuit diagram of the enhanced low precharge circuit;

[0030] Figure 10 This is a timing diagram illustrating the signals of a memory device during a read operation with high precharge bit lines, according to some embodiments.

[0031] Figure 11 This is a timing diagram illustrating the signals of a memory device during a read operation with low precharge bit lines, according to some embodiments.

[0032] Figure 12 This is a block diagram of a voltage-controlled pre-charge circuit according to some embodiments;

[0033] Figure 13 According to some embodiments Figure 12 Example circuit diagram of a voltage-controlled pre-charge circuit;

[0034] Figure 14A According to some embodiments Figure 12 A first example circuit diagram of a voltage detector circuit for a voltage-controlled precharge circuit.

[0035] Figure 14B The illustration is based on some embodiments and Figure 14AThe first example circuit diagram is a graph of the signals at the input and output terminals of the associated voltage detector circuit;

[0036] Figure 14C According to some embodiments Figure 14A The timing diagram of the signals of the voltage-controlled precharge circuit in the first example circuit diagram;

[0037] Figure 14D According to some embodiments Figure 12 The second example circuit diagram of the voltage detector circuit of the voltage-controlled precharge circuit;

[0038] Figure 14E According to some embodiments Figure 12 The third example circuit diagram of the voltage detector circuit of the voltage-controlled pre-charge circuit.

[0039] Figure 14F The illustration is based on some embodiments and Figure 14D The second example circuit diagram and Figure 14E Example curves of signals at the input and output terminals of the associated voltage detector circuits in the third example circuit diagram;

[0040] Figure 15A This is a block diagram of a voltage-controlled low precharge circuit according to some embodiments;

[0041] Figure 15B According to some embodiments Figure 15A Example circuit diagram of a low precharge circuit;

[0042] Figure 15C The illustrations are based on some embodiments. Figure 15A The graphs of the signals at the input and output terminals of the low voltage detector circuit;

[0043] Figure 15D According to some embodiments Figure 15A Timing diagram of the signals of the voltage-controlled low precharge circuit;

[0044] Figure 16A This is a block diagram of a pre-charge circuit with enhanced voltage control according to some embodiments;

[0045] Figure 16B According to some embodiments Figure 16A First example circuit diagram of an enhanced voltage detector circuit

[0046] Figure 16C According to some embodiments Figure 16B The timing diagram of the signal for the enhanced voltage control precharge circuit in the first example circuit diagram;

[0047] Figure 16D According to some embodiments Figure 16A The second example circuit diagram of the enhanced voltage detector circuit;

[0048] Figure 16E According to some embodiments Figure 16A The third example circuit diagram of the voltage detector circuit;

[0049] Figure 17A This is a block diagram of a low precharge circuit with enhanced voltage control according to some embodiments;

[0050] Figure 17B This is a timing diagram of the signals of a low precharge circuit with enhanced voltage control according to some embodiments;

[0051] Figure 18 This is a flowchart illustrating a method for performing a read or write operation in a memory device according to some embodiments.

[0052] [Symbol Explanation]

[0053] 100: Part

[0054] 110[1,N]: Memory unit

[0055] 110[M,N]: Memory unit

[0056] 120: Sensing Circuit

[0057] 130: Pre-charge circuit

[0058] 140: Time Series Diagram

[0059] 150: Arrow

[0060] 160: Arrow

[0061] 165:Terminal

[0062] 170:Terminal

[0063] 175: Enable Terminal

[0064] 180: Enable Terminal

[0065] 205: Circuit Diagram

[0066] 210: Transistor

[0067] 215: Transistor

[0068] 220: Transistor

[0069] 225: Transistor

[0070] 230: Internal node

[0071] 235: Internal Node

[0072] 240: Curve Graph

[0073] 245: Time Series Diagram

[0074] 250: Circuit Diagram

[0075] 255: Circuit Diagram

[0076] 260: Circuit Diagram

[0077] 270: Curve Graph

[0078] 275: Time Series Diagram

[0079] 300: Enhanced pre-charge circuit

[0080] 305: Enable Terminal

[0081] 310: First Example Circuit Diagram

[0082] 315: Transistor

[0083] 320: Timing Diagram

[0084] 321~327: Curves

[0085] 330: Second Example Circuit Diagram

[0086] 340: Circuit diagram of the third example

[0087] 350: Fourth Example Circuit Diagram

[0088] 400: Pre-charge circuit

[0089] 405: Enable Terminal

[0090] 410: First Example Circuit Diagram

[0091] 415: Transistor

[0092] 420: Timing Diagram

[0093] 430: Second Example Circuit Diagram

[0094] 440: Circuit diagram of the third example

[0095] 450: Fourth Example Circuit Diagram

[0096] 470: Timing Diagram

[0097] 480: Timing Diagram

[0098] 500: Pre-charge circuit

[0099] 510: Pre-charge circuit

[0100] 512: Transistor

[0101] 514: Logic

[0102] 520: Voltage Detector Circuit

[0103] 522: First Example Circuit Diagram

[0104] 524: Transistor

[0105] 526: Transistor

[0106] 530: Schematic diagram

[0107] 540: Timing Diagram

[0108] 542: Curve

[0109] 544: Curve

[0110] 546: Curve

[0111] 550: Second Example Circuit Diagram

[0112] 552: Transistor

[0113] 554: Transistor

[0114] 556: Transistor

[0115] 558: Transistor

[0116] 560: Internal Nodes

[0117] 562: Internal Node

[0118] 580: Circuit diagram of the third example

[0119] 582: Transistor

[0120] 584: Transistor

[0121] 586: Internal node

[0122] 590: Curve Graph

[0123] 600: Pre-charge circuit

[0124] 610: Pre-charge circuit

[0125] 612: Transistor

[0126] 614: NAND Logic

[0127] 620: Detector Circuit

[0128] 625: Curve Graph

[0129] 630: Timing Diagram

[0130] 632: Curve

[0131] 634: Curve

[0132] 636: Curve

[0133] 700: Pre-charge circuit

[0134] 720: Voltage Detector Circuit

[0135] 722: First Example Circuit Diagram

[0136] 724: Transistor

[0137] 726: Transistor

[0138] 728: Internal Node

[0139] 730: Internal node

[0140] 740: Timing Diagram

[0141] 750: Second Example Circuit Diagram

[0142] 754: Transistor

[0143] 756: Transistor

[0144] 758: Internal node

[0145] 760: Internal node

[0146] 770: Circuit diagram of the third example

[0147] 772: Transistor

[0148] 774: Transistor

[0149] 776: Internal Node

[0150] 778: Internal node

[0151] 800: Pre-charge circuit

[0152] 820: Detector Circuit

[0153] 840: Timing Diagram

[0154] 900: Method

[0155] 910, 920, 930: Stages Detailed Implementation

[0156] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0157] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly. Furthermore, when a first element is described as “connected” or “coupled” to a second element, this description includes embodiments where the first and second elements are directly connected or coupled to each other, and also includes embodiments where the first and second elements are indirectly connected or coupled to each other using one or more other intermediate elements.

[0158] Figure 1 The figure illustrates a portion 100 of a memory device according to various embodiments. In one example, portion 100 is a row of the memory device. The memory device includes a plurality of memory cells configured as a matrix of multiple columns and multiple rows. Each of the multiple columns includes a first plurality of memory cells connected to a word line among a plurality of word lines. Furthermore, each of the multiple rows includes a second plurality of memory cells. Each of the second plurality of memory cells in a row is connected to a bit line BL or an inverted bit line BLB.

[0159] In one example, section 100 is the Nth row of a memory device with M columns, and includes M memory cells, for example, memory cells 110[1, N], ..., memory cells 110[M, N]. Memory cells 110[1, N] are connected to word line WL[1], extending to memory cells 110[M, N], which are connected to word line [N]. Memory cells 110[M, N] are conducting cells, that is, N-channel metal-oxide-semiconductor (NMOS) transistors with their sources connected to ground. Memory cells 110[1, N] are cut-off cells, that is, N-channel metal-oxide-semiconductor (NMOS) transistors with their sources floating. In part 100, memory cells 110[1, N], ..., memory cells 110[M, N] are illustrated as NMOS-based memory cells; however, they may be PMOS-based memory cells or a combination of NMOS-based and PMOS-based memory cells.

[0160] Memory cells 110[1, N], ..., 110[M, N] are connected to bit line BL. For any read or write operation to any of the memory cells 110[1, N], ..., 110[M, N], bit line BL is pre-charged. Pre-charge circuit 130 pre-charges bit line BL to a predetermined voltage. Furthermore, the word line WL associated with the selected memory cell is determined. Determining the word line activates the selected memory cell. Next, bit line BL is connected to sensing circuit 120. Sensing circuit 120 is enabled using a sense enable (SE) signal; when enabled, sensing circuit 120 senses voltage changes on bit line BL. Based on the bit line BL voltage, sensing circuit 120 provides the sensed data as output Q.

[0161] The precharge circuit 130 is used to improve the cycle time and access time for read operations. For example, as described above, during a read operation, bit line BL is precharged before the memory cell is powered on (i.e., before word line WL is powered on), and bit line BL is discharged through the selected memory cell. If the selected memory cell is a conducting cell (i.e., an NMOS transistor with its source connected to ground), bit line BL is discharged through the selected memory cell. Conversely, if the selected memory cell is a cut-off cell (i.e., an NMOS transistor with its source floating), the voltage of bit line BL remains high. The state of the selected cell, whether it is on or off (i.e., 0 or 1), is detected by sensing the voltage of bit line BL. Therefore, the cycle time and access time for read operations are governed by the sensing time and the precharge time.

[0162] The precharge circuit 130 is designed and configured to reduce precharge time and sensing during read operations on the memory device. For example, the precharge circuit 130 precharges the bit line BL associated with the selected memory cell to a predetermined voltage (also referred to as the precharge voltage VPC), which is less than the supply voltage VDD and greater than the threshold voltage of the sensing circuit 120. Because the bit line BL is not continuously charged to the supply voltage VDD, this results in a reduction in precharge time during the read operation. For PMOS-based memory cells, the precharge circuit 130 precharges the bit line BL associated with the selected memory cell to a predetermined voltage, which is less than the threshold voltage of the sensing circuit 120 but greater than 0 volts.

[0163] Figure 2 This is a timing diagram 140 illustrating the signals of the memory device during a read operation. (For example...) Figure 2 As shown, the anti-precharge PCB signal drops to logic low, triggering the precharge of bit line BL. This causes bit line BL to precharge to a precharge voltage VPC that is lower than the supply voltage VDD. The time it takes for bit line BL to precharge to the precharge voltage VPC is indicated as the precharge time t. PC .like Figure 2 Arrow 150 indicates the pre-charge time t used to charge bit line BL to the pre-charge voltage VPC. PC Less than the precharge time t used to charge bit line BL to the supply voltage VDD PC .

[0164] continue Figure 2 After pre-charging bit line BL, word line WL is determined. Determining word line WL causes the selected memory cell to be started, and bit line BL to discharge from the pre-charge voltage VPC (or the supply voltage VDD in conventional read operations) via the selected memory cell. When the bit line BL voltage drops to the read voltage VR, the SCE signal is triggered to sense the data stored in the selected memory cell via sensing circuit 120. Figure 2 As shown, the bit line BL discharges from the pre-charge voltage VPC to the supply voltage V. DD Faster. This results in a smaller clock-to-data time Tcd, as indicated by arrow 160. Therefore, the precharge circuit 130 enables faster read operations in the memory device compared to conventional precharge circuits.

[0165] Figure 3 This is a block diagram of the precharge circuit 130. In one example, the precharge circuit 130 is an asymmetric clock inverter (ACINV) circuit. The ACINV circuit has different rise and fall edge delays, thus providing a configurable precharge voltage VPC. Figure 3 As shown, the precharge circuit 130 includes a first terminal 165 (also referred to as an input terminal) and a second terminal 170 (also referred to as an output terminal). Both the first terminal 165 and the second terminal 170 are connected to the bit line BL. The precharge circuit 130 further includes a first enable terminal 175 for receiving a first enable signal EN1 and a second enable terminal 180 for receiving a second enable signal EN2. The first enable signal EN1 and the second enable signal EN2 activate the precharge circuit 130 to precharge the bit line BL to a predetermined voltage. In some embodiments, and discussed in the following sections of this disclosure, the precharge circuit 130 may include more or fewer enable terminals, and therefore can be enabled by more or fewer enable signals.

[0166] Figure 4A This is a first example circuit diagram 205 of the pre-charge circuit 130. As shown in the first example circuit diagram 205, the pre-charge circuit 130 includes a first transistor 210, a second transistor 215, a third transistor 220, and a fourth transistor 225. In this example, each of the first transistor 210 and the third transistor 220 is a PMOS transistor, and each of the second transistor 215 and the fourth transistor 225 is an NMOS transistor. However, other types of transistors may also be used for each of the first transistor 210, the second transistor 215, the third transistor 220, and the fourth transistor 225.

[0167] The first source / drain (S / D) structure of the third transistor 220 is connected to the supply voltage VDD. The second S / D structure of the third transistor 220 is connected to the first S / D structure of the first transistor 210 at the first internal node 230. The second S / D structure of the first transistor 210 is connected to the first S / D structure of the second transistor 215 at the output node. The output node is connected to the output terminal 170. The second S / D structure of the second transistor 215 is connected to the first S / D structure of the fourth transistor 225 at the second internal node 235. The second S / D structure of the fourth transistor 225 is connected to ground. The gate structure of the first transistor 210 is connected to the gate structure of the second transistor 215 at the input node connected to the input terminal 165. Therefore, the first transistor 210 and the second transistor 215 form a diode between the first internal node 230 and the second internal node 235. Furthermore, the first transistor 210, the second transistor 215, the third transistor 220, and the fourth transistor 225 are thus connected to form an ACINV circuit between the input terminal 165 and the output terminal 170. The gate structure of the fourth transistor 225 is connected to the first enable terminal 175 to receive the first enable signal EN1, and the gate structure of the third transistor 220 is connected to the second enable terminal 180 to receive the second enable signal EN2.

[0168] Combination Figure 4B and Figure 4C Explain the operation of the first example circuit diagram 205. Figure 4B Is it displayed as follows Figure 4A The first example circuit diagram 205 shows the input and output signal curves of the pre-charge circuit 130. As described above, the first example circuit 205 is the ACINV circuit between the input terminal 165 and the output terminal 170. Therefore, as... Figure 4B As shown, when the input signal is logic low, the output signal is logic high; when the input signal rises above the precharge voltage VPC, the output voltage drops to logic low. Furthermore, the coupling between input terminal 165 and output terminal 170 introduces the additional constraint that the input signal is approximately equal to the output signal. Figure 4C This is a timing diagram 245 illustrating the signals of the precharge circuit 130 when used for a high precharge bit line (i.e., precharging bit line BL to a precharge voltage VPC greater than the threshold voltage of the sensing circuit 120).

[0169] like Figure 4C As shown, to precharge bit line BL, the first enable signal EN1 is determined to be at a logic high level (i.e., to the supply voltage VDD), and the second enable signal EN2 is determined to be at a logic low level (i.e., to ground voltage or 0V). This causes the third transistor 220 and the fourth transistor 225 of the precharge circuit 130 to turn on. Additionally, since bit line BL is not yet charged, the gate structures of both the first transistor 210 and the second transistor 215 are at a logic low level, thereby turning on the first transistor 210 and turning off the second transistor 215. This causes the output node (and therefore bit line BL) to be connected to the supply voltage VDD, and precharges the bit line BL. When the voltage of the output node (and therefore bit line BL) rises to the threshold voltage of the first transistor 210, the first transistor 210 turns off, thereby disconnecting the output node (and therefore bit line BL) from the supply voltage VDD.

[0170] For example, such as Figure 4C As shown, the first enable signal EN1 is determined to be logic high at time t0. Furthermore, at time t0, the second enable signal EN2 is determined to be logic low. The bit line BL signal begins to rise from time t0 and stabilizes at the pre-charge voltage V. PC In some instances, the first enable signal EN1 and the second enable signal EN2 are not determined simultaneously.

[0171] Furthermore, when the voltage at the input node is higher than the threshold voltage of the second transistor 215, the output node is connected to ground until the voltage at the input node drops below the threshold voltage of the second transistor 215. Therefore, the pre-charge voltage VPC of the pre-charge circuit 130 can be set to be sufficiently greater than 1 / 2 VDD, for example, 0.6 VDD. Moreover, the pre-charge voltage VPC can be configured or tuned using the magnitudes of the threshold voltages of the first transistor 210 and the second transistor 215. That is, the pre-charge voltage VPC can be increased by increasing the magnitude of the threshold voltage of the first transistor 210, and vice versa.

[0172] Figure 4D This is a second example circuit diagram 250 of the pre-charge circuit 130. For example... Figure 4D As shown, the first S / D structure of the first transistor 210 is connected to the supply voltage VDD, and the second S / D structure of the first transistor 210 is connected to the first S / D structure of the third transistor 220 at the first internal node 230. The second S / D structure of the third transistor 220 is connected to the first S / D structure of the second transistor 215 at the output node connected to the output terminal 170. The second S / D structure of the second transistor 215 is connected to the first S / D structure of the fourth transistor 225 at the second internal node 235. The second S / D structure of the fourth transistor 225 is connected to ground. The gate structure of the first transistor 210 is connected to the gate structure of the second transistor 215 at the input node connected to the input terminal 165. The gate structure of the third transistor 220 is connected to the second enable terminal 180 to receive the second enable signal EN2, and the gate structure of the fourth transistor 225 is connected to the first enable terminal 175 to receive the first enable signal EN1. The pre-charge circuit 130 of the second example circuit diagram 250 functions similarly to the pre-charge circuit 130 of the first example circuit diagram 205, but has a different pre-charge rate, and therefore will not be described further for the sake of simplicity.

[0173] Figure 4E This is the third example circuit diagram 255 of the pre-charge circuit 130. For example... Figure 4EAs shown, the first S / D structure of the third transistor 220 is connected to the supply voltage VDD, and the second S / D structure of the third transistor 220 is connected to the first S / D structure of the first transistor 210 at the first internal node 230. The second S / D structure of the first transistor 210 is connected to the first S / D structure of the fourth transistor 225 at the output node connected to the output terminal 170. The second S / D structure of the fourth transistor 225 is connected to the first S / D structure of the second transistor 215 at the second internal node 235. The second S / D structure of the second transistor 215 is connected to ground. The gate structure of the first transistor 210 is connected to the gate structure of the second transistor 215 at the input node connected to the input terminal 165. The gate structure of the third transistor 220 is connected to the second enable terminal 180 to receive the second enable signal EN2, and the gate structure of the fourth transistor 225 is connected to the first enable terminal 175 to receive the first enable signal EN1. The pre-charge circuit 130 of the third example circuit diagram 255 functions similarly to the pre-charge circuit 130 of the first example circuit diagram 205, but has a different pre-charge rate. Therefore, for the sake of simplicity, it will not be described further.

[0174] Figure 4F This is the fourth example circuit diagram 260 of the pre-charge circuit 130. For example... Figure 4F As shown, the first S / D structure of the first transistor 210 is connected to the supply voltage VDD, and the second S / D structure of the first transistor 210 is connected to the first S / D structure of the third transistor 220 at the first internal node 230. The second S / D structure of the third transistor 220 is connected to the first S / D structure of the fourth transistor 225 at the output node connected to the output terminal 170. The second S / D structure of the fourth transistor 225 is connected to the first S / D structure of the second transistor 215 at the second internal node 235. The second S / D structure of the second transistor 215 is connected to ground. The gate structure of the first transistor 210 is connected to the gate structure of the second transistor 215 at the input node connected to the input terminal 165. The gate structure of the third transistor 220 is connected to the second enable terminal 180 to receive the second enable signal EN2, and the gate structure of the fourth transistor 225 is connected to the first enable terminal to receive the first enable signal EN1. The pre-charge circuit 130 of the fourth example circuit diagram 260 functions similarly to the pre-charge circuit 130 of the first example circuit diagram 205, but has a different pre-charge rate. Therefore, for the sake of simplicity, it will not be described further.

[0175] Figure 5A It is illustrated when Figure 4AThe first example circuit diagram 205 shows the precharge circuit 130 used for low precharge of bit line BL, as illustrated in the signal curve 270. Low precharge is performed on bit line BL when the selected memory cell for bit line BL is a PMOS-based memory cell. For example... Figure 5A As shown, when the input signal is logic low, the output signal is logic high; when the input signal rises above the precharge voltage VPC, the output voltage drops to logic low. Furthermore, the coupling between input terminal 165 and output terminal 170 introduces the additional constraint that the input signal is approximately equal to the output signal. However, the precharge voltage VPC at which the input signal drops to logic low is below the threshold voltage of the sensing circuit 120 but above 0V.

[0176] Figure 5B It is illustrated when Figure 4A The timing diagram 275 of the precharge circuit in the first circuit diagram is used for the signals during low precharge of bit line BL. For low precharge of bit line BL, the first enable signal EN1 is determined to be logic high and the second enable signal EN2 is determined to be logic low. This causes the third transistor 220 and the fourth transistor 225 to turn on. In addition, since bit line BL is at the supply voltage VDD (i.e., logic high level), the first transistor 210 is turned off and the second transistor 215 is turned on. In addition, since the first enable signal EN1 is at the logic high level, the fourth transistor 225 is turned on. This causes the output node to discharge to ground via the second transistor 215 and the fourth transistor 225. When the voltage of the output node reaches the threshold voltage of the second transistor 215, the second transistor 215 turns off, thereby stopping the discharge of the output node (and therefore the bit line BL) to ground. Therefore, the precharge voltage VPC of the precharge circuit 130 can be set to be sufficiently less than the threshold voltage of the sensing circuit 120, for example, 0.4VDD. Furthermore, the threshold voltage of the pre-charge circuit 130 can be tuned using the magnitudes of the threshold voltages of the first transistor 210 and the second transistor 215.

[0177] like Figure 5B As shown, the first enable signal EN1 is determined to be logic high at time t0. Furthermore, at time t0, the second enable signal EN2 is determined to be logic low. The bit line BL voltage begins to decrease from the supply voltage VDD at time t0 and stabilizes at the precharge voltage VPC. In some instances, when a low precharge is applied to the bit line BL, the first enable signal EN1 and the second enable signal EN2 are not determined simultaneously. That is, the precharge voltage VPC can be reduced by decreasing the threshold voltage of the second transistor 215, and vice versa.

[0178] Figure 6 This is a block diagram of the enhanced pre-charge circuit 300. In one example, the enhanced pre-charge circuit 300 is an ACINV circuit. Figure 6 As shown, with Figure 3 Compared to the precharge circuit 130, the enhanced precharge circuit 300 includes an additional enable terminal, namely, a third enable terminal 305. The third enable terminal 305 is used to receive a third enable signal EN3. Furthermore, as discussed in more detail below, the enhanced precharge circuit 300 includes an additional transistor. In this example, compared to the precharge circuit 130, the enhanced precharge circuit 300 enables faster high precharge of the circuit BL and provides better control over the precharge voltage VPC.

[0179] Figure 7A This is a first example circuit diagram 310 of the enhanced pre-charge circuit 300. In this example, the first example circuit diagram 310 is similar to... Figure 4A The first circuit diagram is 205, but with additional transistors. (See diagram 205.) Figure 7A As shown, the enhanced pre-charge circuit 300 includes a first transistor 210, a second transistor 215, a third transistor 220, a fourth transistor 225, and an additional fifth transistor 315. The additional fifth transistor 315 is connected in parallel with the first transistor 210. For example, as... Figure 7A As shown, the first S / D structure of the third transistor 220 is connected to the supply voltage VDD, and the second S / D structure of the third transistor 220 is connected to the first S / D structure of the first transistor 210 at the first internal node 230. The second S / D structure of the first transistor 210 is connected to the first S / D structure of the second transistor 215 at the output node connected to the output terminal 170. The second S / D structure of the second transistor 215 is connected to the first S / D structure of the fourth transistor 225 at the second internal node 235. The second S / D structure of the fourth transistor 225 is connected to ground. The gate structure of the first transistor 210 is connected to the gate structure of the second transistor 215 at the input node connected to the input terminal 165. Therefore, the first transistor 210 and the second transistor 215 form a diode between the first internal node 230 and the second internal node 235. The gate structure of the fourth transistor 225 is connected to the first enable terminal 175 to receive the first enable signal EN1, and the gate structure of the third transistor 220 is connected to the second enable terminal 180 to receive the second enable signal EN2.

[0180] Therefore, the first transistor 210, the second transistor 215, the third transistor 220, and the fourth transistor 225 of the enhanced pre-charge circuit 300 are connected to the pre-charge circuit 130. Figure 4AThe circuit diagram is identical to that of the first circuit diagram 205 and connected in a similar manner. Furthermore, the first S / D structure of the fifth transistor 315 is connected to the first internal node 230, and the second S / D structure of the fifth transistor 315 is connected to the output node connected to the output terminal 170. The gate structure of the fifth transistor 315 is connected to the third enable terminal 305 to receive the third enable signal EN3. Therefore, the fifth transistor 315 is connected in parallel with the first transistor 210. In an exemplary embodiment, the fifth transistor 315 is a PMOS transistor. However, the fifth transistor 315 may also be an NMOS transistor.

[0181] The enhanced precharge circuit 300 functions similarly to the above-mentioned... Figure 4A The first example circuit diagram 205 shows the precharge circuit 130. However, the enhanced precharge circuit 300 precharges the bit line BL in a slightly shorter time (i.e., faster) and provides better control over the precharge circuit 130. Figure 7B It is illustrated when Figure 7A The first example circuit diagram 310 shows the timing diagram 320 for the enhanced precharge circuit 300 used to perform high precharge on bit line BL. (See circuit diagram 310 for example.) Figure 7B As shown, the second enable signal EN2 is determined to be logic low at time t0, as represented by curve 321. This not only turns on the first transistor 210 but also the third transistor 220, thereby connecting the bit line BL to the supply voltage. Therefore, the bit line BL signal rises from the time t0 when the second enable signal EN2 is determined, as shown by curve 322. Then, at time t1, the first enable signal EN1 and the third enable signal EN3 are determined to be logic high, as shown by curves 323 and 324.

[0182] When the third enable signal EN3 is determined to be logic high, it turns off the fifth transistor 315. Furthermore, when the first enable signal EN1 is determined to be logic high, it turns on the second transistor 215. Therefore, when the first enable signal EN1 and the third enable signal EN3 are determined at time t1, the bit line BL signal rises above the precharge voltage VPC and then stabilizes at the precharge voltage VPC, as shown in curve 322. In an alternative example, the first enable signal EN1 and the third enable signal EN3 are determined to be logic high at time t1', slightly earlier than time t1, as shown in curves 325 and 326. When the first enable signal EN1 and the third enable signal EN3 are determined at time t1', the bit line BL signal rises to the precharge voltage VPC but does not rise above it, as shown in curve 327. In some examples, the first enable signal EN1 and the second enable signal EN2 are not determined simultaneously.

[0183] Figure 7CThis is a second example circuit diagram 330 of the enhanced pre-charge circuit 300. In this example, the second example circuit diagram 330 is similar to... Figure 4D The second circuit diagram 250, but with additional transistors. For example, such as Figure 7C As shown, the first transistor 210, the second transistor 215, the third transistor 220, and the fourth transistor 225 of the enhanced pre-charge circuit 300 in the second example circuit diagram 330 are connected to the pre-charge circuit 130. Figure 4D The second example circuit diagram is the same as 250 and is connected in a similar manner. That is, as... Figure 7C As shown, the first S / D structure of the first transistor 210 is connected to the supply voltage VDD, and the second S / D structure of the first transistor 210 is connected to the first S / D structure of the third transistor 220 at the first internal node 230. The second S / D structure of the third transistor 220 is connected to the first S / D structure of the second transistor 215 at the output node connected to the output terminal 170. The second S / D structure of the second transistor 215 is connected to the first S / D structure of the fourth transistor 225 at the second internal node 235. The second S / D structure of the fourth transistor 225 is connected to ground. The gate structure of the first transistor 210 is connected to the gate structure of the second transistor 215 at the input node connected to the input terminal 165. The gate structure of the third transistor 220 is connected to the second enable terminal 180 to receive the second enable signal EN2, and the gate structure of the fourth transistor 225 is connected to the first enable terminal 175 to receive the first enable signal EN1.

[0184] Furthermore, the fifth transistor 315 is connected in parallel with the first transistor 210. That is, the first S / D structure of the fifth transistor 315 is connected to the supply voltage, and the second S / D structure of the fifth transistor 315 is connected to the first internal node 230. The gate structure of the fifth transistor 315 is connected to the third enable terminal 305 to receive the third enable signal EN3. The enhanced precharge circuit 300 of the second example circuit diagram 330 functions similarly to the enhanced precharge circuit 300 of the first example circuit diagram 310, but with a different precharge rate; therefore, for the sake of simplicity, it will not be described further.

[0185] Figure 7D This is a third example circuit diagram 340 of the enhanced pre-charge circuit 300. The first transistor 210, second transistor 215, third transistor 220, and fourth transistor 225 of the enhanced pre-charge circuit 300 in the third example circuit diagram 340 are... Figure 4E The pre-charge circuit 130 is the same as the third example circuit diagram 255 and is connected in a similar manner. That is, as... Figure 7DAs shown, the first S / D structure of the third transistor 220 is connected to the supply voltage VDD, and the second S / D structure of the third transistor 220 is connected to the first S / D structure of the first transistor 210 at the first internal node 230. The second S / D structure of the first transistor 210 is connected to the first S / D structure of the fourth transistor 225 at the output node connected to the output terminal 170. The second S / D structure of the fourth transistor 225 is connected to the first S / D structure of the second transistor 215 at the second internal node 235. The second S / D structure of the second transistor 215 is connected to ground. The gate structure of the first transistor 210 is connected to the gate structure of the second transistor 215 at the input node connected to the input terminal 165. The gate structure of the third transistor 220 is connected to the second enable terminal 180 to receive the second enable signal EN2, and the gate structure of the fourth transistor 225 is connected to the first enable terminal 175 to receive the first enable signal EN1.

[0186] Furthermore, the fifth transistor 315 is connected in parallel with the first transistor 210. That is, the first S / D structure of the fifth transistor 315 is connected to the first internal node 230, and the second S / D structure of the fifth transistor 315 is connected to the output node connected to the output terminal 170. The gate structure of the fifth transistor 315 is connected to the third enable terminal 305 to receive the third enable signal EN3. The enhanced precharge circuit 300 of the third example circuit diagram 340 functions similarly to the enhanced precharge circuit 300 of the first example circuit diagram 310, but with a different precharge rate; therefore, for the sake of simplicity, it will not be described further.

[0187] Figure 7E This is a fourth example circuit diagram 350 of the enhanced pre-charge circuit 300. The first transistor 210, second transistor 215, third transistor 220, and fourth transistor 225 of the enhanced pre-charge circuit 300 in the fourth example circuit diagram 350 are connected to the pre-charge circuit 130. Figure 4F The fourth circuit diagram 260 is the same and connected in a similar manner. That is, as... Figure 7EAs shown, the first S / D structure of the first transistor 210 is connected to the supply voltage VDD, and the second S / D structure of the first transistor 210 is connected to the first S / D structure of the third transistor 220 at the first internal node 230. The second S / D structure of the third transistor 220 is connected to the first S / D structure of the fourth transistor 225 at the output node. The second S / D structure of the fourth transistor 225 is connected to the first S / D structure of the second transistor 215 at the second internal node 235. The second S / D structure of the second transistor 215 is connected to ground. The gate structure of the first transistor 210 is connected to the gate structure of the second transistor 215 at the input node connected to the input terminal 165. The gate structure of the third transistor 220 is connected to the second enable terminal 180 to receive the second enable signal EN2, and the gate structure of the fourth transistor 225 is connected to the first enable terminal to receive the first enable signal EN1.

[0188] Furthermore, the fifth transistor 315 is connected in parallel with the first transistor 210. That is, the first S / D structure of the fifth transistor 315 is connected to the supply voltage, and the second S / D structure of the fifth transistor 315 is connected to the first internal node 230. The gate structure of the fifth transistor 315 is connected to the third enable terminal 305 to receive the third enable signal EN3. The enhanced precharge circuit 300 of the fourth example circuit diagram 350 functions similarly to the enhanced precharge circuit 300 of the first example circuit diagram 310, but with a different precharge rate; therefore, for the sake of simplicity, it will not be described further.

[0189] Figure 8 This is a block diagram of an enhanced low precharge circuit 400 for low precharge of bit line BL. In one example, the enhanced low precharge circuit 400 is an ACINV circuit. Figure 8 As shown, with Figure 3 Compared to the precharge circuit 130, the enhanced low precharge circuit 400 includes an additional enable terminal, namely, a third enable terminal 405. The third enable terminal 405 is used to receive a third enable signal EN3. Furthermore, as discussed in more detail below, compared to... Figure 3 Compared to the precharge circuit 130, the enhanced low precharge circuit 400 includes additional transistors.

[0190] Figure 9A This is a first example circuit diagram 410 of the enhanced low precharge circuit 400. (See diagram 410 for details.) Figure 9AAs shown, the low precharge circuit 400 includes a first transistor 210, a second transistor 215, a third transistor 220, a fourth transistor 225, and a fifth transistor 415. The first S / D structure of the third transistor 220 is connected to the supply voltage VDD, and the second S / D structure of the third transistor 220 is connected to the first S / D structure of the first transistor 210 at a first internal node 230. The second S / D structure of the first transistor 210 is connected to the first S / D structure of the second transistor 215 at an output node connected to the output terminal 170. The second S / D structure of the second transistor 215 is connected to the first S / D structure of the fourth transistor 225 at a second internal node 235. The second S / D structure of the fourth transistor 225 is connected to ground. The gate structure of the first transistor 210 is connected to the gate structure of the second transistor 215 and the input terminal 165. Therefore, the first transistor 210 and the second transistor 215 form a diode between the first internal node 230 and the second internal node 235. The gate structure of the fourth transistor 225 is connected to the first enable terminal 175 to receive the first enable signal EN1, and the gate structure of the third transistor 220 is connected to the second enable terminal 180 to receive the second enable signal EN2.

[0191] Therefore, the first transistor 210, the second transistor 215, the third transistor 220, and the fourth transistor 225 of the enhanced pre-charge circuit 300 are... Figure 4A The pre-charge circuit 130 is identical to the first example circuit diagram 205 and is connected in a similar manner. Furthermore, the first S / D structure of the fifth transistor 415 is connected to the output node connected to the output terminal 170. The second S / D structure of the fifth transistor 415 is connected to the second internal node 235. The gate structure of the fifth transistor 415 is connected to the third enable terminal 405 to receive the third enable signal EN3. Therefore, the fifth transistor 415 is connected in parallel with the second transistor 215. In the example embodiment, the fifth transistor 415 is an NMOS transistor. However, the fifth transistor 415 may also be a PMOS transistor.

[0192] The enhanced low precharge circuit 400 functions similarly to the above-mentioned... Figure 4A The first example circuit diagram 205 shows the precharge circuit 130. However, the enhanced low precharge circuit 400 precharges the bit line BL to a precharge voltage VPC that is below the threshold voltage of the sensing circuit 120 and above 0V. In addition, the enhanced low precharge circuit 400 precharges the bit line BL in a slightly shorter time (i.e., faster) than the precharge circuit 130. Figure 9B It is illustrated when Figure 9A The timing diagram 420 shows the enhanced low precharge circuit 400 of the first example circuit diagram 410 used for the signal when performing low precharge on bit line BL.

[0193] like Figure 9B As shown, the first enable signal EN1 is determined to be logic high at time t0. The determination of the first enable signal EN1 to be logic high turns on the second transistor 215, thereby connecting the bit line BL to ground. Therefore, the voltage on the bit line BL drops from the logic high level starting from time t0 when the first enable signal EN1 is determined. At time t1, the second enable signal EN2 and the third enable signal EN3 are determined to be logic low.

[0194] When the second enable signal EN2 is logic low, the third transistor 220 is turned on. And when the third enable signal EN3 is determined to be logic low, the fifth transistor 415 is turned off. The determination of the second enable signal EN2 and the third enable signal EN3 prevents further discharge of bit line BL. When the second enable signal EN2 and the third enable signal EN3 are determined at time t1, the bit line BL voltage drops below the precharge voltage VPC and then rises to the precharge voltage VPC. In an alternative embodiment, the second enable signal EN2 and the third enable signal EN3 are determined to be logic high at time t1', slightly earlier than time t1. When the second enable signal EN2 and the third enable signal EN3 are determined at time t1', the bit line BL voltage drops to the precharge voltage VPC, but does not drop below the precharge voltage VPC. In some instances, the second enable signal EN2 and the third enable signal EN3 are not determined simultaneously.

[0195] Figure 9C This is a second example circuit diagram 430 of the enhanced precharge circuit 400. The first transistor 210, second transistor 215, third transistor 220, and fourth transistor 225 of the enhanced precharge circuit 400 are connected to... Figure 4D The second circuit diagram 250 of the pre-charging circuit 130 is the same and connected in a similar manner. That is, as... Figure 9B As shown, the first S / D structure of the first transistor 210 is connected to the supply voltage VDD, and the second S / D structure of the first transistor 210 is connected to the first S / D structure of the third transistor 220 at the first internal node 230. The second S / D structure of the third transistor 220 is connected to the first S / D structure of the second transistor 215 at the output node connected to the output terminal 170. The second S / D structure of the second transistor 215 is connected to the first S / D structure of the fourth transistor 225 at the second internal node 235. The second S / D structure of the fourth transistor 225 is connected to ground. The gate structure of the first transistor 210 is connected to the gate structure of the second transistor 215 and is connected to the input terminal 165. The gate structure of the third transistor 220 is connected to the second enable terminal 180 to receive the second enable signal EN2, and the gate structure of the fourth transistor 225 is connected to the first enable terminal 175 to receive the first enable signal EN1.

[0196] Furthermore, the fifth transistor 415 is connected in parallel with the second transistor 215. That is, the first S / D structure of the fifth transistor 415 is connected to the output node, and the second S / D structure of the fifth transistor 415 is connected to the second internal node 235. The gate structure of the fifth transistor 415 is connected to the third enable terminal 405 to receive the third enable signal EN3. The enhanced low precharge circuit 400 of the second example circuit diagram 430 functions similarly to the enhanced low precharge circuit 400 of the first example circuit diagram 410, but with a different precharge rate; therefore, for the sake of simplicity, it will not be described further.

[0197] Figure 9D This is a third example circuit diagram 440 of the enhanced low precharge circuit 400. The first transistor 210, second transistor 215, third transistor 220, and fourth transistor 225 of the enhanced precharge circuit 400 are connected to... Figure 4E The pre-charge circuit 130 is identical to the third circuit diagram 255 and is connected in a similar manner. That is, as... Figure 9D As shown, the first S / D structure of the third transistor 220 is connected to the supply voltage VDD, and the second S / D structure of the third transistor 220 is connected to the first S / D structure of the first transistor 210 at the first internal node 230. The second S / D structure of the first transistor 210 is connected to the first S / D structure of the fourth transistor 225 at the output node connected to the output terminal 170. The second S / D structure of the fourth transistor 225 is connected to the first S / D structure of the second transistor 215 at the second internal node 235. The second S / D structure of the second transistor 215 is connected to ground. The gate structure of the first transistor 210 is connected to the gate structure of the second transistor 215 and is connected to the input terminal 165. The gate structure of the third transistor 220 is connected to the second enable terminal 180 to receive the second enable signal EN2, and the gate structure of the fourth transistor 225 is connected to the first enable terminal 175 to receive the first enable signal EN1.

[0198] Furthermore, the fifth transistor 415 is connected in parallel with the second transistor 215. That is, the first S / D structure of the fifth transistor 415 is connected to the second internal node 235, and the second S / D structure of the fifth transistor 415 is connected to ground. The gate structure of the fifth transistor 415 is connected to the third enable terminal 405 to receive the third enable signal EN3. The enhanced low precharge circuit 400 of the third example circuit diagram 440 functions similarly to the enhanced low precharge circuit 400 of the first example circuit diagram 410, but with a different precharge rate; therefore, for the sake of simplicity, it will not be described further.

[0199] Figure 9EThis is a third example circuit diagram 440 of the enhanced low precharge circuit 400. The first transistor 210, the second transistor 215, the third transistor 220, and the fourth transistor 225 of the enhanced low precharge circuit 400 are... Figure 4D The pre-charge circuit 130 is identical to the fourth circuit diagram 250 and is connected in a similar manner. That is, as... Figure 9E As shown, the first S / D structure of the first transistor 210 is connected to the supply voltage VDD. The second S / D structure of the first transistor 210 is connected to the first S / D structure of the third transistor 220 at the first internal node 230. The second S / D structure of the third transistor 220 is connected to the first S / D structure of the fourth transistor 225 at the output node. The second S / D structure of the fourth transistor 225 is connected to the first S / D structure of the second transistor 215 at the second internal node 235. The second S / D structure of the second transistor 215 is connected to ground. The gate structure of the first transistor 210 is connected to the gate structure of the second transistor 215 and is connected to the input terminal 165. The gate structure of the third transistor 220 is connected to the second enable terminal 180 to receive the second enable signal EN2, and the gate structure of the fourth transistor 225 is connected to the first enable terminal to receive the first enable signal EN1.

[0200] Furthermore, the fifth transistor 415 is connected in parallel with the second transistor 215. That is, the first S / D structure of the fifth transistor 415 is connected to the second internal node 235, and the second S / D structure of the fifth transistor 415 is connected to ground. The gate structure of the fifth transistor 415 is connected to the third enable terminal 405 to receive the third enable signal EN3. The enhanced low precharge circuit 400 of the fourth example circuit diagram 450 functions similarly to the enhanced low precharge circuit 400 of the first example circuit diagram 410, but with a different precharge rate; therefore, for the sake of simplicity, it will not be described further.

[0201] Figure 10 This is a timing diagram 470 illustrating signals of a memory device during a read operation with a high precharge bit line BL, according to some embodiments. Figure 10 As shown, after bit line BL is pre-charged to the pre-charge voltage VPC, at time t2, the first enable signal EN1 is denied logic low, the second enable signal EN2 is denied logic high, and the third enable signal EN3 is denied logic low. Then, as... Figure 10 As shown, the word line WL signal is determined to be logic high at time t3. This causes the selected memory cell to be activated, thereby discharging the word line BL signal. Then, as... Figure 10As shown, the SE signal is determined to enable the sensing circuit 120 to read data from the selected memory cell. Once the sensing circuit 120 senses data from the selected memory cell, the word line WL signal is negated at time t4, thus completing the read cycle. The next read cycle starts again at time t0, where the first enable signal EN1 is determined to be logic high, the second enable signal EN2 is determined to be logic low, and the third enable signal EN3 is determined to be logic high at times t0 and t1 to precharge the bit line to the precharge voltage VPC.

[0202] Figure 11 This is a timing diagram 480 illustrating signals of a memory device during a read operation with a low precharge bit line BL, according to some embodiments. Figure 11 As shown, at time t2, after bit line BL is pre-charged to a pre-charge voltage VPC that is lower than the threshold voltage of sensing circuit 120 but higher than 0V, the first enable signal EN1 is denied to logic low, the second enable signal EN2 is denied to logic high, and the third enable signal EN3 is denied to logic high. Then, as... Figure 11 As shown, the word line WL signal is determined to be logic high at time t3. This causes the selected memory cell to be activated, thereby recharging the word line BL signal. Then, as... Figure 11 As shown, the SE signal is determined to enable the sensing circuit 120 to read data from the selected memory cell. Once the sensing circuit 120 senses data from the selected memory cell, the word line WL signal is negated at time t4, thus completing the read cycle. The next read cycle starts again at time t0, where the first enable signal EN1 is redefined as logic high, the second enable signal EN2 is redefined as logic low, and the third enable signal EN3 is redefined at times t0 and t1, precharging the bit line to the precharge voltage VPC.

[0203] Figure 12 This is a block diagram of the voltage-controlled precharge circuit 500. The voltage-controlled precharge circuit 500 precharges the bit line BL to a precharge voltage VPC for read or write operations that are greater than the threshold voltage of the sensing circuit 120 but lower than the supply voltage VDD. Figure 12 As shown, the voltage-controlled precharge circuit 500 includes a precharge circuit 510 and a voltage detector circuit 520. The precharge circuit 510 includes a first terminal for receiving a precharge enable signal PCE, a second terminal for receiving a bit line feedback signal BLFB, and a third terminal connected to the bit line BL. In this example, the precharge circuit 510 is enabled by the precharge enable signal PCE and precharges the bit line BL.

[0204] The voltage detector circuit 520 includes a first terminal connected to the bit line BL and a second terminal connected to the second terminal of the precharge circuit 510. The voltage detector circuit 520 senses the bit line voltage and generates a bit line feedback signal BLFB, which is then provided to the precharge circuit 510. The precharge circuit 510 can then adjust the precharge of the bit line BL based on the bit line feedback signal BLFB.

[0205] Figure 13 This is an example circuit diagram of the pre-charge circuit 510. (Example circuit diagram follows.) Figure 13 As shown, the precharge circuit 510 includes a first transistor 512 and an (AND) logic 514. A first S / D structure of the first transistor 512 is connected to the supply voltage VDD, and a second S / D structure of the first transistor 512 is connected to the bit line. The gate structure of the first transistor 512 is connected to the output terminal of the AND logic 514. A first input terminal of the AND logic 514 is connected to receive a precharge enable signal PCE, and a second input terminal of the AND logic 514 is connected to receive the inverted bit line feedback signal BLFB. In some embodiments, the first transistor 512 is an NMOS transistor.

[0206] Figure 14A This is the first example circuit diagram 522 of the voltage detector circuit 520. (See diagram 522 for reference.) Figure 14A As shown, the voltage detector circuit 520 includes a first transistor 524 and a second transistor 526. The first S / D structure of the first transistor 524 is connected to the supply voltage VDD, and the second S / D structure of the first transistor 524 is connected to the output node connected to the output terminal. The output terminal is the same as the second terminal of the voltage detector circuit 520. Therefore, the output terminal is connected to the precharge circuit 510 and provides a bit line feedback signal BLFB to the precharge circuit 510. The first S / D structure of the second transistor 526 is connected to the output node, and the second S / D structure of the second transistor 526 is connected to ground. The gate structure of the first transistor 524 is connected to the gate structure of the second transistor 526 at the input node connected to the input terminal. The input terminal is the same as the first terminal of the voltage detector circuit 520. Therefore, the input terminal is connected to the bit line BL.

[0207] In the first example circuit diagram 522 of the voltage detector circuit 520, the first transistor 524 is a PMOS transistor and the second transistor 526 is an NMOS transistor. Therefore, the first transistor 524 and the second transistor 526 form an inverter between the input and output terminals. In some examples, different types of transistors may also be used for both the first transistor 524 and the second transistor 526.

[0208] Figure 14B It is a diagram and Figure 14AThe first example circuit diagram is a schematic diagram 530 of the signals at the input and output terminals of the associated voltage detector circuit 520. (See diagram 530 for details.) Figure 14B As shown, when the input signal Vin is lower than the precharge voltage VPC (i.e., the bit line BL voltage is lower than the precharge voltage VPC), the output signal Vout (i.e., the bit line feedback signal BLFB) is at logic high. When the input signal (i.e., the bit line BL voltage) reaches the precharge voltage VPC, the output signal Vout (i.e., the bit line feedback signal BLFB) drops to logic low.

[0209] Figure 14C yes Figure 14A The timing diagram 540 shows the signals of the voltage-controlled pre-charge circuit 500 in the first example circuit diagram 522. (See also...) Figure 14C As shown, when the precharge enable signal PCE rises to logic high at time t0, it triggers the precharge of bit line BL, as shown in curve 542. Since the voltage of bit line BL is lower than the precharge voltage VPC when the precharge of bit line BL is triggered, the output of voltage detector circuit 520 is logic high. Therefore, the output of AND logic 514 of the precharge circuit is logic high. This causes the first transistor 512 of the precharge circuit 510 to turn on, thereby connecting bit line BL to the supply voltage and then precharging bit line BL, as shown in curve 544. As the voltage on bit line BL rises to the precharge voltage VPC at time t1, the output of voltage detector circuit 520 drops to logic low, as shown in curve 546. This causes the output of voltage detector circuit 520 (i.e., bit line feedback signal BLFB) to drop to logic high. The bit line feedback signal BLFB dropping to logic high causes the output of AND logic 514 to drop to logic low, which causes the first transistor 512 of the precharge circuit 510 to turn off. The shutdown of the first transistor 512 causes the bit line BL to disconnect from the supply voltage VDD. Therefore, the bit line BL is pre-charged to the pre-charge voltage VPC. In some instances, the pre-charge voltage VPC is greater than the threshold voltage of the sensing circuit 120 but less than the supply voltage VDD, and can be changed by altering the dimensions of one or both of the first transistor 524 and the second transistor 526 in the first example circuit diagram 522.

[0210] Figure 14DThis is a second example circuit diagram 550 of the voltage detector circuit 520. Compared to the first example circuit diagram 522, the second example circuit diagram 550 includes four additional transistors for the voltage detector circuit 520. For example, as shown in the second example circuit diagram 550, the voltage detector circuit 520 includes a first transistor 524, a second transistor 526, a third transistor 552, a fourth transistor 554, a fifth transistor 556, and a sixth transistor 558. The first S / D structure of the first transistor 524 is connected to the supply voltage VDD, and the second S / D structure of the first transistor 524 is connected to a first internal node 560. The gate structure of the first transistor 524 is connected to an input node connected to an input terminal. The input terminal is also a first terminal of the voltage detector circuit 520 and is connected to bit line BL.

[0211] The first S / D structure of the second transistor 526 is connected to the second internal node 562, and the second S / D structure of the second transistor 526 is connected to ground. The gate structure of the second transistor 526 is connected to the input node. The first S / D structure of the third transistor 552 is connected to the first internal node 560, and the second S / D structure of the third transistor 552 is connected to the output node connected to the output terminal. The output terminal is also the second terminal of the voltage detector circuit 520 and is connected to the second input terminal of the NAND logic 514 of the precharge circuit 510. The gate structure of the third transistor 552 is connected to the input node.

[0212] The first S / D structure of the fourth transistor 554 is connected to the output node, and the second S / D structure of the fourth transistor 554 is connected to the second internal node 562. The gate structure of the fourth transistor 554 is connected to the input node. The first S / D structure of the fifth transistor 556 is connected to the first internal node 560, and the second S / D structure of the fifth transistor 556 is connected to ground. The gate structure of the fifth transistor 556 is connected to the output node. The first S / D structure of the sixth transistor 558 is connected to the second internal node 562, and the second S / D structure of the sixth transistor 558 is connected to the supply voltage. The gate structure of the sixth transistor 558 is connected to the output node. In this example, each of the first transistor 524, the third transistor 552, and the fifth transistor 556 is a PMOS transistor, and each of the second transistor 526, the fourth transistor 554, and the sixth transistor 558 is an NMOS transistor. However, each of the first transistor 524, the third transistor 552, and the fifth transistor 556 can be an NMOS transistor, and each of the second transistor 526, the fourth transistor 554, and the sixth transistor 558 can be a PMOS transistor. In some examples, Figure 14D The voltage detector circuit 520 is also known as a Schmitt flip-flop inverter.

[0213] Figure 14E This is a third example circuit diagram 580 of the voltage detector circuit 520. Compared to the first example circuit diagram 522, the third example circuit diagram 580 includes two additional transistors for the voltage detector circuit 520. As shown in the third example circuit diagram 580, the voltage detector circuit 520 includes a first transistor 524, a second transistor 526, a third transistor 582, and a fourth transistor 584. The first S / D structure of the first transistor 524 is connected to the supply voltage VDD, and the second S / D structure of the first transistor 524 is connected to the output node connected to the output terminal. The output terminal is also the second terminal of the voltage detector circuit 520 and is connected to the second input terminal of the NAND logic 514 of the precharge circuit 510. The gate structure of the first transistor 524 is connected to the input node connected to the input terminal. The input terminal is also the first terminal of the voltage detector circuit 520 and is connected to the bit line BL.

[0214] The first S / D structure of the second transistor 526 is connected to the first internal node 586, and the second S / D structure of the second transistor 526 is connected to ground. The gate structure of the second transistor 526 is connected to the input node. The first S / D structure of the third transistor 582 is connected to the output node, and the second S / D structure of the third transistor 582 is connected to the first internal node 586. The gate structure of the third transistor 582 is connected to the input node. The first S / D structure of the fourth transistor 584 is connected to the first internal node 586, and the second S / D structure of the fourth transistor 584 is connected to the supply voltage VDD. The gate structure of the fourth transistor 584 is connected to the output node. In this example, each of the third transistor 582 and the fourth transistor 584 is an NMOS transistor. However, each of the third transistor 582 and the fourth transistor 584 may also be a PMOS transistor.

[0215] Figure 14F It is a diagram and Figure 14D The second example circuit diagram 550 and Figure 14E Example curves of the signals at the input and output terminals of the voltage detector circuit 520 associated with each of the components in the third example circuit diagram 580 are shown in diagram 590. Figure 14F As shown, when the input signal Vin is lower than the precharge voltage VPC (i.e., the bit line BL voltage is lower than the precharge voltage VPC), the output signal Vout (i.e., the bit line feedback signal BLFB) is at logic high. When the input signal (i.e., the bit line BL voltage) reaches the precharge voltage VPC, the output signal Vout (i.e., the bit line feedback signal BLFB) drops to logic low.

[0216] Figure 15AThis is a block diagram of a voltage-controlled low precharge circuit 600. The voltage-controlled low precharge circuit 600 precharges the bit line BL to a threshold voltage lower than half the supply voltage but greater than 0V for read or write operations. Figure 15A As shown, the voltage-controlled low precharge circuit 600 includes a low precharge circuit 610 and a low voltage detector circuit 620. The low precharge circuit 610 includes a first terminal for receiving a precharge enable signal PCE, a second terminal for receiving a bit line feedback signal BLFB, and a third terminal connected to the bit line BL. In this example, the low precharge circuit 610 is enabled by the precharge enable signal PCE and precharges the bit line BL.

[0217] The low-voltage detector circuit 620 includes a first terminal connected to the bit line BL and a second terminal connected to the second terminal of the low-precharge circuit 610. The low-voltage detector circuit 620 senses the bit line voltage and generates a bit line feedback signal BLFB, which is provided to the low-precharge circuit 610. The low-precharge circuit 610 can then adjust the precharge of the bit line BL based on the bit line feedback signal BLFB. In an example, the low-voltage detector circuit 620 may be similar to the circuit described above. Figure 14A , Figure 14B , Figure 14D ,and Figure 14F The voltage detector circuit 520 is described above.

[0218] Figure 15B This is an example circuit diagram of the low precharge circuit 610. (Example circuit diagram follows.) Figure 15B As shown, the low precharge circuit 610 includes a first transistor 612 and NAND logic 614. The first S / D structure of the first transistor 612 is connected to ground, and the second S / D structure of the first transistor 612 is connected to bit line BL. The gate structure of the first transistor 612 is connected to the output terminal of the NAND logic 614. The first input terminal of the NAND logic 614 is connected to receive a precharge enable signal PCE, and the second input terminal of the NAND logic 614 is connected to receive a bit line feedback signal BLFB. In some embodiments, the first transistor 612 is a PMOS transistor.

[0219] Figure 15C This is graph 625 showing the signal curves at the input and output terminals of the low-voltage detector circuit 620. (Example:) Figure 15CAs shown, when the input signal Vin is lower than the pre-charge voltage VPC (i.e., the bit line BL voltage is lower than the pre-charge voltage VPC), the output signal Vout (i.e., the bit line feedback signal BLFB) is at logic high. When the input signal (i.e., the bit line BL voltage) reaches the pre-charge voltage VPC, the output signal Vout (i.e., the bit line feedback signal BLFB) drops to logic low. The pre-charge voltage VPC is lower than the threshold voltage of the sensing circuit 120 but higher than 0V.

[0220] Figure 15D This is the timing diagram 630 for the signals of the voltage-controlled low precharge circuit 600. (For example...) Figure 15D As shown, when the precharge enable signal PCE rises to logic high at time t0, it triggers the precharge of bit line BL, as shown in curve 632. Since the voltage of bit line BL is higher than the precharge voltage VPC when the precharge of bit line BL is triggered, the output of low voltage detector circuit 620 is logic high. Therefore, the output of NAND logic 614 of low precharge circuit 610 is logic high. This causes the first transistor 612 of low precharge circuit 610 to turn on, thereby connecting bit line BL to ground, and then precharging bit line BL, as shown in curve 634. When the voltage on bit line BL discharges to the precharge voltage VPC at time t1, the output of low voltage detector circuit 620 rises to logic high, as shown in curve 636. This causes the output of low voltage detector circuit 620 (i.e., bit line feedback signal BLFB) to drop to logic low. The bit line feedback signal BLFB drops to logic low, causing the output of NAND logic 614 to rise to logic high. This causes the first transistor 612 of the low precharge circuit 610 to turn off. The turning off of the first transistor 612 causes the bit line BL to be disconnected from ground. Therefore, the bit line BL is precharged to a precharge voltage VPC that is lower than the threshold voltage of the sensing circuit 120 but greater than 0V, and this can be changed by altering the size of one or both of the first transistor 524 and the second transistor 526 in the first example circuit diagram 522.

[0221] Figure 16A This is a block diagram of the enhanced voltage control pre-charge circuit 700. The enhanced voltage control pre-charge circuit 700 functions similarly to... Figure 12 The voltage-controlled precharge circuit 500 precharges the bit line BL to a precharge voltage VPC for read operations that are greater than the threshold voltage of the sensing circuit 102 but lower than the supply voltage VDD. Figure 16A As shown, the enhanced voltage control precharge circuit 700 includes a precharge circuit 510 and an enhanced voltage detector circuit 720.

[0222] The enhanced voltage detector circuit 720 includes a first terminal connected to the bit line BL and a second terminal connected to the second terminal of the precharge circuit 510. The enhanced voltage detector circuit 720 senses the bit line voltage and generates a bit line feedback signal BLFB, which is provided to the precharge circuit 510. The precharge circuit 510 can then adjust the precharge of the bit line BL based on the bit line feedback signal BLFB. In this example, the enhanced voltage detector circuit 720 is triggered by two enable signals, rather than a single enable signal.

[0223] Figure 16B This is the first example circuit diagram 722 of the enhanced voltage detector circuit 720. (See diagram 722 for reference.) Figure 16B As shown, with Figure 14A Compared to the voltage detector circuit 520, the enhanced voltage detector circuit 720 includes two additional transistors. For example, the enhanced voltage detector circuit 720 includes a first transistor 524, a second transistor 526, a third transistor 724, and a fourth transistor 726. The first S / D structure of the third transistor 724 is connected to the supply voltage VDD, and the second S / D structure of the third transistor 724 is connected to a first internal node 728. The first S / D structure of the first transistor 524 is connected to the first internal node 728, and the second S / D structure of the first transistor 524 is connected to an output node connected to an output terminal. The output terminal is the same as the second terminal of the voltage detector circuit 520. Therefore, the output terminal is connected to the precharge circuit 510 and provides a bit line feedback signal BLFB to the precharge circuit 510. The first S / D structure of the second transistor 526 is connected to the output node, and the second S / D structure of the second transistor 526 is connected to a second internal node 730. The first S / D structure of the fourth transistor 726 is connected to the second internal node 730, and the second S / D structure of the fourth transistor 726 is connected to ground.

[0224] The gate structure of the first transistor 524 is connected to the gate structure of the second transistor 526 at the input node connected to the input terminal. The input terminal is the same as the first terminal of the voltage detector circuit 520. Therefore, the input terminal is connected to the bit line BL. The gate structure of the third transistor 724 is connected to receive the first enable signal EN1, and the gate structure of the fourth transistor 726 is connected to receive the second enable signal EN2. The third transistor 724 is a PMOS transistor, and the fourth transistor 726 is an NMOS transistor. In some instances, different types of transistors may be used for both the third transistor 724 and the fourth transistor 726.

[0225] Figure 16C yes Figure 16B The timing diagram 740 shows the signals of the enhanced voltage-controlled pre-charge circuit 700 in the first example circuit diagram 722. (See also...) Figure 16C As shown, when the precharge enable signal PCE rises to logic high, precharging of bit line BL is triggered. Furthermore, at time t0, the first enable signal EN1 rises to logic high, and the second enable signal EN2 rises to logic low. This causes the third transistor 724 and the fourth transistor 726 to turn on. Since the voltage of bit line BL is lower than the precharge voltage VPC when precharging of bit line BL is triggered, the output of the enhancement voltage detector circuit 720 is logic high. As the voltage on bit line BL rises to the precharge voltage VPC at time t1, the output of the enhancement voltage detector circuit 720 drops to logic low. This causes the output of the enhancement voltage detector circuit 720 (i.e., the bit line feedback signal BLFB) to drop to logic low. In some instances, the precharge voltage VPC is greater than the threshold voltage of the sensing circuit 120 but less than the supply voltage VDD, and can be changed by altering the dimensions of one or both of the first transistor 524 and the second transistor 526 in the first example circuit diagram 522.

[0226] Figure 16D This is a second example circuit diagram 750 of the enhanced voltage detector circuit 720. (Compared to...) Figure 14D Compared to the second example circuit diagram 550, the second example circuit diagram 750 includes two additional transistors for the voltage detector circuit 720. For example, as shown in the second example circuit diagram 750, the voltage detector circuit 520 includes a first transistor 524, a second transistor 526, a third transistor 552, a fourth transistor 554, a fifth transistor 556, a sixth transistor 558, a seventh transistor 754, and an eighth transistor 754. The first S / D structure of the seventh transistor 754 is connected to the supply voltage VDD, and the second S / D structure of the seventh transistor 754 is connected to a third internal node 758. The gate structure of the seventh transistor 754 is connected to receive a second enable signal EN2. The first S / D structure of the first transistor 524 is connected to the third internal node 758, and the second S / D structure of the first transistor 524 is connected to a first internal node 560. The gate structure of the first transistor 524 is connected to an input node connected to an input terminal. The input terminal is also the first terminal of the voltage detector circuit 520 and is connected to bit line BL.

[0227] The first S / D structure of the second transistor 526 is connected to the second internal node 562, and the second S / D structure of the second transistor 526 is connected to the fourth internal node 760. The gate structure of the second transistor 526 is connected to the input node. The first S / D structure of the eighth transistor 756 is connected to the fourth internal node 760, and the second S / D structure of the eighth transistor 756 is connected to ground. The gate structure of the eighth transistor 756 is connected to receive the first enable signal EN1. The first S / D structure of the third transistor 552 is connected to the first internal node 560, and the second S / D structure of the third transistor 552 is connected to the output node connected to the output terminal. The output terminal is also the second terminal of the voltage detector circuit 520 and is connected to the second input terminal of the NAND logic 514 of the precharge circuit 510. The gate structure of the third transistor 552 is connected to the input node.

[0228] The first S / D structure of the fourth transistor 554 is connected to the output node, and the second S / D structure of the fourth transistor 554 is connected to the second internal node 562. The gate structure of the fourth transistor 554 is connected to the input node. The first S / D structure of the fifth transistor 556 is connected to the first internal node 560, and the second S / D structure of the fifth transistor 556 is connected to ground. The gate structure of the fifth transistor 556 is connected to the output node. The first S / D structure of the sixth transistor 558 is connected to the second internal node 562, and the second S / D structure of the sixth transistor 558 is connected to the supply voltage. The gate structure of the sixth transistor 558 is connected to the output node. In this example, the seventh transistor 754 is a PMOS transistor, and the eighth transistor 756 is an NMOS transistor. However, the seventh transistor 754 could be an NMOS transistor, and the eighth transistor 756 could be a PMOS transistor. The function of the enhancement voltage detector circuit 720 in the second example circuit diagram 750 is substantially similar to that of the enhancement voltage detector circuit 720 in the first example circuit diagram 722, and therefore will not be described further for simplicity.

[0229] Figure 16E This is the third example circuit diagram 770 of the voltage detector circuit 720. (And...) Figure 14ECompared to the third example circuit diagram 580, the third example circuit diagram 770 includes two additional transistors for the voltage detector circuit 720. As shown in the third example circuit diagram 770, the voltage detector circuit 720 includes a first transistor 524, a second transistor 526, a third transistor 582, a fourth transistor 584, a fifth transistor 772, and a sixth transistor 774. The first S / D structure of the fifth transistor 772 is connected to the supply voltage VDD, and the second S / D structure of the fifth transistor 772 is connected to the second internal node 776. The gate of the fifth transistor 772 is connected to receive a second enable signal EN2. The first S / D structure of the first transistor 524 is connected to the second internal node 776, and the second S / D structure of the first transistor 524 is connected to the output node connected to the output terminal. The gate structure of the first transistor 524 is connected to the input node connected to the input terminal.

[0230] The first S / D structure of the second transistor 526 is connected to the first internal node 586, and the second S / D structure of the second transistor 526 is connected to the third internal node 778. The gate structure of the second transistor 526 is connected to the input node. The first S / D structure of the sixth transistor 774 is connected to the third internal node 778, and the second S / D structure of the sixth transistor 774 is connected to ground. The gate structure of the sixth transistor 774 is connected to receive the first enable signal EN1. The first S / D structure of the third transistor 582 is connected to the output node, and the second S / D structure of the third transistor 582 is connected to the first internal node 586. The gate structure of the third transistor 582 is connected to the input node. The first S / D structure of the fourth transistor 584 is connected to the first internal node 586, and the second S / D structure of the fourth transistor 584 is connected to the supply voltage VDD. The gate structure of the fourth transistor 584 is connected to the output node. In this example, each of the third transistor 582 and the fourth transistor 584 is an NMOS transistor. However, each of the third transistor 582 and the fourth transistor 584 may also be a PMOS transistor. The enhanced voltage detector circuit 720 of the third example circuit diagram 770 is essentially similar in function to the enhanced voltage detector circuit 720 of the first example circuit diagram 722, so for simplicity, it will not be described further.

[0231] Figure 17A This is a block diagram of the low precharge circuit 800 with enhanced voltage control. The low precharge circuit 800 with enhanced voltage control functions similarly to... Figure 15A The voltage-controlled low precharge circuit 600 precharges the bit line BL to a precharge voltage VPC for read or write operations below the threshold voltage of the sensing circuit 120 but above ground or 0V. Figure 17AAs shown, the enhanced voltage control low precharge circuit 800 includes a precharge circuit 610 and an enhanced low voltage detector circuit 820.

[0232] The enhanced low-voltage detector circuit 820 includes a first terminal connected to bit line BL and a second terminal connected to a second terminal of pre-charge circuit 610. The enhanced low-voltage detector circuit 820 senses the bit line voltage and generates a bit line feedback signal BLFB, which is provided to the pre-charge circuit 610. The pre-charge circuit 610 can then adjust the pre-charge of bit line BL based on the bit line feedback signal BLFB. In this example, the enhanced low-voltage detector circuit 820 is triggered by two enable signals, instead of a single enable signal used to trigger voltage detector circuit 520. The function of the enhanced low-voltage detector circuit 820 is substantially similar to that of the enhanced low-voltage detector circuit 720, and therefore will not be described further for simplicity.

[0233] Figure 17B This is the timing diagram 840 for the signals of the low precharge circuit 800 with enhanced voltage control. (For example...) Figure 17B As shown, when the precharge enable signal PCE rises to logic high, precharging of bit line BL is triggered. Furthermore, at time t0, the first enable signal EN1 rises to logic high, and the second enable signal EN2 rises to logic low. This causes discharge of bit line BL from logic high. As the voltage on bit line BL drops to the precharge voltage VPC, the bit line feedback signal BLFB rises to logic high, thereby stopping any further discharge of bit line BL.

[0234] Figure 18 This is a flowchart of a method 900 for pre-charging bit lines BL of a memory device. At stage 910 of method 900, bit lines BL of a memory array of the memory device are selected. The memory array may include bit lines and memory cells coupled to the bit lines.

[0235] At stage 920 of method 900, a precharge circuit is enabled to precharge the bit line to a precharge voltage. The precharge circuit may include an asymmetric clock inverter having an input terminal, an output terminal, and at least one enable terminal. The input terminal is connected to the bit line. The output terminal is connected to the bit line. In response to receiving an enable signal on at least one enable terminal, the precharge circuit precharges the bit line to a threshold voltage.

[0236] At stage 930 of method 900, sensing circuit 120 is enabled to perform a read operation on a memory cell connected to a bit line. As described above, the precharge voltage may be higher than the threshold voltage of sensing circuit 120 and lower than the supply voltage VDD. In another embodiment, the precharge voltage may be lower than the threshold voltage of sensing circuit 120 and higher than the ground voltage.

[0237] According to an example embodiment, a semiconductor device includes: a memory array having bit lines and memory cells coupled to the bit lines; a sensing circuit for sensing data from the memory cells; and a precharge circuit including an asymmetric clock inverter having an input terminal, an output terminal, and at least one enable terminal, wherein: the input terminal is connected to the bit lines, the output terminal is connected to the bit lines, and in response to receiving an enable signal on the at least one enable terminal, the precharge circuit precharges the bit lines to a precharge voltage, wherein the precharge voltage is higher than a threshold voltage of the sensing circuit and lower than a supply voltage. In some embodiments, the memory array is a read memory array. In some embodiments, the precharge circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first transistor and the second transistor are connected together to form a diode, and wherein the third transistor is connected between the supply voltage and a first terminal of the diode, and wherein the fourth transistor is connected between a second terminal of the diode and ground. In some embodiments, a first source / drain structure of the third transistor is connected to a supply voltage, a second source / drain structure of the third transistor is connected to a first source / drain structure of the first transistor at a first internal node, wherein a second source / drain structure of the first transistor is connected to a first source / drain structure of the second transistor at an output node, wherein the output node is connected to an output terminal, wherein a second source / drain structure of the second transistor is connected to a first source / drain structure of the fourth transistor at a second internal node, wherein a second source / drain structure of the fourth transistor is connected to ground, wherein a gate structure of the first transistor is connected to a gate structure of the second transistor at an input node connected to an input terminal, wherein a gate structure of the fourth transistor is connected to a first enable terminal to receive a first enable signal, and a gate structure of the third transistor is connected to a second enable terminal to receive a second enable signal. In some embodiments, the semiconductor device further includes a fifth transistor connected in parallel with the first transistor. In some embodiments, a third enable signal is provided to a gate of the fifth transistor. In some embodiments, the threshold voltage is tuned based on a size or a voltage threshold value of one or more of the third and fourth transistors. In some embodiments, the semiconductor device further includes: a voltage detector circuit connected to a bit line, wherein the voltage detector circuit is configured to provide a feedback signal to a precharge circuit based on a bit line voltage. In some embodiments, the precharge voltage is greater than 0.6 times the supply voltage.

[0238] According to other example embodiments, a semiconductor device includes: a memory array having bit lines and memory cells coupled to the bit lines; a precharge circuit including a first terminal, a second terminal, and at least one enable terminal, wherein the first terminal is connected to the bit lines, and wherein in response to receiving an enable signal on the at least one enable terminal, the precharge circuit precharges the bit lines to a precharge voltage; and a voltage detector circuit including a first terminal and a second terminal, wherein the first terminal of the voltage detector is connected to the bit lines, the second terminal of the voltage detector is connected to the second terminal of the precharge circuit, the voltage detector is configured to sense the bit line voltage of the bit lines, and provide a bit line feedback signal to the precharge circuit based on the sensed bit line voltage, the precharge circuit being configured to change the precharge of the bit lines based on the bit line feedback signal. In some embodiments, the precharge circuit includes a first transistor and an AND logic circuit, wherein a first source / drain structure of the first transistor is connected to a supply voltage, a second source / drain structure of the first transistor is connected to a bit line, a gate structure of the first transistor is connected to an output terminal of the AND logic circuit, a first input terminal of the AND logic circuit is connected to receive a precharge enable signal, and a second input terminal of the AND logic circuit is connected to receive an inverted bit line feedback signal. In some embodiments, the voltage detector circuit includes a second transistor and a third transistor, wherein a first source / drain structure of the second transistor is connected to a supply voltage, and a second source / drain structure of the second transistor is connected to an output node connected to a second terminal, a first source / drain structure of the third transistor is connected to the output node, a second source / drain structure of the third transistor is connected to ground, and a gate structure of the second transistor is connected to a gate structure of the third transistor at an input node connected to the first terminal. In some embodiments, the precharge voltage is tuned based on a size or a voltage threshold value of one or more of the second and third transistors. In some embodiments, the precharge voltage is greater than a threshold voltage of a sensing circuit and lower than a supply voltage. In some embodiments, the pre-charge voltage is greater than 0.6 times a supply voltage. In some embodiments, the pre-charge voltage is lower than a threshold voltage of a sensing circuit and higher than a ground voltage. In some embodiments, the pre-charge voltage is less than 0.4 times a supply voltage.

[0239] According to another embodiment, a method for performing a read operation on a memory device includes: selecting a bit line of a memory array of the memory device, the memory device having a bit line and memory cells coupled to the bit line; an enable precharge circuit precharges the bit line to a precharge voltage, wherein the precharge circuit includes an asymmetric clock inverter having an input terminal, an output terminal, and at least one enable terminal, wherein: the input terminal is connected to the bit line, the output terminal is connected to the bit line, and in response to receiving an enable signal on the at least one enable terminal, the precharge circuit precharges the bit line to the precharge voltage; and after charging the bit line, an enable sensing circuit performs a read operation on the memory cells connected to the bit line. In some embodiments, the enable precharge circuit precharging the bit line to the precharge voltage includes: the enable precharge circuit precharging the bit line to a precharge voltage higher than a threshold voltage of the sensing circuit and lower than a supply voltage. In some embodiments, enabling the precharge circuit to precharge the bit line to a precharge voltage includes: enabling the precharge circuit to precharge the bit line to a threshold voltage that is lower than a threshold voltage of the sensing circuit and higher than a ground voltage.

[0240] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, It includes: A memory array having a bit line and a memory cell coupled to the bit line; A sensing circuit for sensing data from the memory cell; and A pre-charge circuit includes an asymmetric clock inverter having an input terminal, an output terminal, and at least one enable terminal, wherein: The input terminal is connected to the bit line. The output terminal is connected to the bit line, and In response to receiving an enable signal on at least one enable terminal, the precharge circuit precharges the bit line to a precharge voltage, wherein the precharge voltage is higher than a threshold voltage of the sensing circuit and lower than a supply voltage.

2. The semiconductor device as claimed in claim 1, characterized in that, The pre-charge circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor and the second transistor are connected together to form a diode. The third transistor is connected between the supply voltage and a first terminal of the diode. The fourth transistor is connected between a second terminal of the diode and a ground.

3. The semiconductor device as claimed in claim 2, characterized in that, The third transistor has a first source / drain structure connected to the supply voltage, a second source / drain structure connected to the first source / drain structure of the first transistor at a first internal node, a second source / drain structure connected to the first source / drain structure of the second transistor at an output node, the output node connected to the output terminal, a second source / drain structure of the second transistor connected to the first source / drain structure of the fourth transistor at a second internal node, a second source / drain structure of the fourth transistor connected to ground, a gate structure of the first transistor connected to the gate structure of the second transistor at an input node connected to the input terminal, a gate structure of the fourth transistor connected to a first enable terminal to receive a first enable signal, and a gate structure of the third transistor connected to a second enable terminal to receive a second enable signal.

4. The semiconductor device as claimed in claim 2, characterized in that, It further includes a fifth transistor connected in parallel with the first transistor. A third enable signal is provided to a gate of the fifth transistor.

5. A semiconductor device, characterized in that, Include: A memory array having a bit line and a memory cell coupled to the bit line; A pre-charge circuit includes a first terminal, a second terminal, and at least one enable terminal, wherein the first terminal is connected to the bit line, and wherein in response to receiving a pre-charge enable signal on the at least one enable terminal, the pre-charge circuit pre-charges the bit line to a pre-charge voltage; and A voltage detector circuit includes a first terminal and a second terminal, wherein the first terminal of the voltage detector is connected to the bit line, and the second terminal of the voltage detector is connected to the second terminal of the pre-charge circuit, wherein the voltage detector is used to sense a bit line voltage of the bit line and provide a bit line feedback signal to the pre-charge circuit based on the sensed bit line voltage, and wherein the pre-charge circuit is used to change the pre-charge of the bit line based on the bit line feedback signal.

6. The semiconductor device as claimed in claim 5, characterized in that, The precharge circuit includes a first transistor and an AND logic circuit. A first source / drain structure of the first transistor is connected to a supply voltage, a second source / drain structure of the first transistor is connected to the bit line, a gate structure of the first transistor is connected to an output terminal of the AND logic circuit, a first input terminal of the AND logic circuit is connected to receive the precharge enable signal, and a second input terminal of the AND logic circuit is connected to receive an inverted bit line feedback signal.

7. The semiconductor device as claimed in claim 5, characterized in that, The voltage detector circuit includes a second transistor and a third transistor. A first source / drain structure of the second transistor is connected to a supply voltage, and a second source / drain structure of the second transistor is connected to an output node connected to the second terminal. A first source / drain structure of the third transistor is connected to the output node, and a second source / drain structure of the third transistor is connected to ground. A gate structure of the second transistor is connected to the gate structure of the third transistor at an input node connected to the first terminal. The pre-charge voltage is tuned based on a size or a voltage threshold of one or more of the second and third transistors.

8. A method for performing a read operation on a memory device, characterized in that, The method includes: Select a bit line of a memory array of the memory device, and the memory device has a memory cell coupled to the bit line. A pre-charge circuit enables the bit line to pre-charge to a pre-charge voltage, wherein the pre-charge circuit includes an asymmetric clock inverter having an input terminal, an output terminal, and at least one enable terminal, wherein: The input terminal is connected to the bit line. The output terminal is connected to the bit line, and In response to receiving an enable signal on at least one enable terminal, the precharge circuit precharges the bit line to the precharge voltage; and After precharging the bit line, a sensing circuit is enabled to perform the read operation on the memory cell connected to the bit line.

9. The method as described in claim 8, characterized in that, Enabling the precharge circuit to precharge the bit line to the precharge voltage includes: enabling the precharge circuit to precharge the bit line to the precharge voltage, which is higher than a threshold voltage of the sensing circuit and lower than a supply voltage.

10. The method as described in claim 8, characterized in that, Enabling the precharge circuit to precharge the bit line to the precharge voltage includes: enabling the precharge circuit to precharge the bit line to the threshold voltage, which is lower than a threshold voltage of the sensing circuit and higher than a ground voltage.

Images