Register clock driver with chip select feedback

Abstract

In one embodiment, an apparatus including a memory module is described. The memory module may include a plurality of memory rows and columns and a register clock driver (RCD) coupled to the plurality of memory rows and columns. The RCD may include a receiver configured to receive a chip select signal for selecting one or more memory rows and columns. The RCD may also include logic circuitry coupled to the receiver and an output driver coupled to the logic circuitry. The RCD may also include loopback circuitry configured to sample the chip select signal from one or more of a first sampling point between the receiver and the logic circuitry and a second sampling point between the logic circuitry and the output driver.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202111465727.3, filed on December 3, 2021, entitled "Register Clock Driver with Chip Select Feedback". Summary of the Invention

[0002] This disclosure relates to memory devices. More specifically, in some embodiments, this disclosure relates to register clock drivers for dual data rate (DDR) random access memory (RAM) modules. Background Technology

[0003] Power consumption and efficiency are becoming increasingly important in both stationary and portable computing devices to reduce power costs and ensure longer battery life. Portable computing devices, such as laptops, notebooks, netbooks, or other computing devices that may rely on battery power, typically have stringent requirements for power consumption and efficiency. In such devices, it is typical to optimize each component to reduce power consumption. On one hand, dual data rate generation 5 (DDR5) memory modules can be used in these devices. Compared to its predecessors, such as DDR3 and DDR4 memory modules, DDR5 memory modules reduce power consumption, increase bandwidth, and improve efficiency (e.g., are faster). On the other hand, DDR5 memory modules can incorporate onboard voltage regulators to achieve even higher speeds. Summary of the Invention

[0004] In this embodiment, means in a memory module are generally described. The means may include a receiver configured to receive a chip select signal for selecting one or more memory rows / columns of the memory module. The means may also include logic circuitry coupled to the receiver. The means may also include an output driver coupled to the logic circuitry. The logic circuitry may be configured to decode the chip select signal to generate an output signal for selecting one or more memory rows / columns of the memory module. The output driver may be configured to select one or more memory rows / columns using the output signal. The means may also include loopback circuitry configured to sample the chip select signal from one or more of a first sampling point between the receiver and the logic circuitry and a second sampling point between the logic circuitry and the output driver.

[0005] In another embodiment, an apparatus including a memory module is generally described. The memory module may include a plurality of memory rows and columns and a register clock driver (RCD). The RCD may be coupled to the plurality of memory rows and columns. The RCD may include a receiver configured to receive a chip select signal for selecting one or more memory rows and columns among the plurality of memory rows and columns. The RCD may also include logic circuitry coupled to the receiver. The RCD may also include an output driver coupled to the logic circuitry. The logic circuitry may be configured to decode the chip select signal to generate an output signal for selecting one or more memory rows and columns of the memory module. The output driver may be configured to select one or more memory rows and columns using the output signal. The RCD may also include loopback circuitry configured to sample the chip select signal from one or more of a first sampling point between the receiver and the logic circuitry and a second sampling point between the logic circuitry and the output driver.

[0006] In another embodiment, a method for operating a memory module is generally described. The method may include receiving a chip select signal by a register clock driver (RCD) of the memory module for selecting one or more rows or columns of memory in the memory module. The method may include sampling the chip select signal from one or more of a first sampling point between the RCD's receiver and the RCD's logic circuitry, and a second sampling point between the RCD's logic circuitry and the RCD's output driver.

[0007] The foregoing overview is illustrative only and is not intended to be limiting in any way. Other aspects, embodiments, and features, besides those described above, will become apparent from the accompanying drawings and the detailed description below. In the drawings, the same reference numerals indicate the same or similarly functional elements. Attached Figure Description

[0008] Figure 1 This is a diagram of an example memory system according to an embodiment of the present disclosure.

[0009] Figure 2 The illustration is based on an embodiment of the present disclosure. Figure 1 A block diagram of an example memory module for a memory system.

[0010] Figure 3 This is a block diagram of an example memory module including a register clock driver with chip select feedback circuitry, according to embodiments of the present disclosure.

[0011] Figure 4 This is a diagram illustrating details of a register clock driver with chip select feedback circuitry according to an embodiment of the present disclosure.

[0012] Figure 5This is a circuit diagram of a feedback circuit according to an embodiment of the present disclosure.

[0013] Figure 6 This is a flowchart of an example process 600 that can implement a register clock driver with chip select feedback according to an embodiment of the present disclosure. Detailed Implementation

[0014] Register clock drivers (RCDs) are devices used on memory modules such as DDR5 memory modules. RCDs buffer the command address (CA) bus, chip select signals, and clock signals between the host controller and the DDR5 memory module. When used in load-reducing dual in-line memory modules (LRDIMMs), RCDs can also create a buffer communication (BCOM) bus to control the LRDIMM's data buffers. LRDIMMs can support relatively higher densities than other memory modules and include memory buffer chips. In one application, LRDIMMs can be used, for example, in servers, and the memory buffer chips in LRDIMMs can reduce and minimize the load on the server's memory bus. For example, LRDIMMs can use memory buffer chips to combine the electrical loads of rows and columns on the LRDIMM into a single electrical load, allowing them to have, for example, up to eight rows and columns on a single DIMM module. Therefore, using LRDIMMs allows the system to be configured with the largest possible memory footprint.

[0015] However, LRDIMMs use memory buffer chips instead of registers like other DIMMs, which can negatively impact signal integrity, especially as the speed of DDR5 memory modules increases (e.g., higher speeds result in worse signal integrity). In one example, the disclosed embodiments may integrate a loopback or feedback circuit with hardware components to form a feedback path for the chip select signal of the RCD. This feedback path can drive the chip select signal of the RCD back to the host controller for debugging, testing, or training. Furthermore, in one embodiment, the feedback path for the chip select signal may utilize a portion of other existing feedback paths reserved for other internal signals of the RCD that can be fed back to the host controller. Additionally, the feedback circuitry integrated into the RCD can sample the chip select signal from different locations within the RCD, allowing the host controller to determine which part of the RCD or processing stage might be causing a problem. Furthermore, integrating the feedback circuitry into the RCD allows the RCD to undergo testing of the chip select signal at any time, including during normal operation of the memory module. By being able to test the chip select signal at any time, the signal integrity of the chip select signal can be maintained to improve the functionality of the memory module.

[0016] Figure 1 and Figure 2An example embodiment of the memory system 10 is illustrated. The memory system 10 includes memory modules 201, 202…20 N Connector 70 and memory controller 80, the memory modules are also collectively referred to herein or individually as (one or more) memory modules 20.

[0017] refer to Figure 1 In one example embodiment, memory module 20 may include a dual in-line memory module (DIMM). In some embodiments, memory module 20 may be implemented as a dual data rate fifth generation (DDR5) SDRAM module. Although specific types, arrangements, and numbers of components are described and illustrated herein, in other embodiments, memory module 20 may include any other type, arrangement, or number of components.

[0018] Example memory module 20 includes circuit blocks 301, 302, 303, 304, 305…30 P-4 30 P-3 30 P-2 30 P-1 and 30 P Circuit blocks 401, 402…40 M-1 and 40 M Register clock driver (RCD) 50, PMIC 60, connector 70, and any other blocks, circuits, pins, connectors, traces, or other components typically found in memory modules. In some embodiments, circuit blocks 301, 302, 303, 304, 305,…30 P-4 30 P-3 30 P-2 30 P-1 and 30 P It can be configured as a data buffer and will also be collectively or individually referred to herein as data buffer 30. In some embodiments, circuit blocks 401, 402, ... 40 M-1 and 40 M It can be configured as a memory device and will also be collectively or individually referred to herein as memory device 40(one or more). Although described herein as data buffer 30 and memory device 40, circuit blocks 30 and 40 may also be used by memory module 20 for any other purpose.

[0019] In some embodiments, the data buffer 30 and memory device 40 include a synchronous dynamic random access memory (SDRAM) device, chip, or module. In some embodiments, the data buffer 30 and memory device 40 also include, or alternatively include, any other type of memory device, such as SRAM, DRAM, MROM, PROM, EPROM, and EEPROM. The data buffer 30, memory device 40, or both may be physically located on one or both sides of the memory module 20 (e.g., the front and back).

[0020] PMIC 60 is configured to perform power management on memory module 20. For example, PMIC 60 may be configured to scale up or down voltage, perform DC-DC conversion, or perform other similar power management operations. In some embodiments, PMIC 60 may include a low dropout regulator (LDO), a DC-DC converter such as a buck or boost converter, pulse frequency modulation (PFM), pulse width modulation (PWM), a power field-effect transistor (FET), a real-time clock (RTC), or any other circuitry typically found in a PMIC.

[0021] Connector 70 may include pins, traces, or other connections configured to connect memory module 20 to other components of the computing system, such as memory controller 80, motherboard, or other components. In some embodiments, connector 70 may include, for example, a 288-pin configuration or any other pin configuration.

[0022] In some embodiments, memory module 20 includes connector 70. In other embodiments, motherboard, memory controller 80, or any other component of the computing device includes connector 70. In yet another embodiment, one or more of connectors 70 may be part of memory module 20, and one or more of connectors 70 may be part of motherboard, memory controller 80, or other component of the computing device.

[0023] The memory module 20 can be connected, for example, via connector 70 to a motherboard, memory controller 80, or other components of the computing device to transfer data between components of the computing device and the memory module 20. For example, in an embodiment implementing a UDIMM, connector 70 may include a 64-bit bus, a 72-bit bus, or a bus including any other bit width.

[0024] Memory module 20 is shown as a memory controller 80 connected to a computing device. In an example embodiment, memory controller 80 may be implemented as a component of the computer motherboard or motherboard of the computing device, for example, on the northbridge of the motherboard. In another example, memory controller 80 may be implemented as a component of the microprocessor of the computing device. In yet another example, memory controller 80 may be implemented as a component of the central processing unit (CPU) of the computing device. In other embodiments, memory controller 80 may be implemented as part of any other component of the computing device.

[0025] In some embodiments, memory module 20 is implemented as a DDR5 SDRAM memory module. As an example, memory module 20 may include memory module densities of 128 gigabytes (GB), 512 GB, 1 terabyte (TB), or higher per module. Memory module 20 may operate at frequencies ranging from approximately 1.2 to approximately 3.2 gigahertz (GHz) and data rates ranging from approximately 3.2 GT / s to approximately 4.6 GT / s, and in some cases up to approximately 8 GT / s or higher. In some embodiments, memory module 20 may alternatively include smaller or larger densities, operate at lower or higher frequencies, and operate at lower or higher data rates.

[0026] Now for reference Figure 2 , showed Figure 1 The following is a block diagram of an example memory module 20. Memory module 20 may represent memory modules 20A-20N. Memory module 20 is shown communicating with memory controller 80. Memory controller 80 is shown as part of circuitry 90, such as the motherboard, mainboard, or other component of a computing device communicating with memory module 20.

[0027] The memory module 20 includes circuits 221, 222, 223, 224, 225…22 Q-4 , twenty two Q-3 , twenty two Q-2 , twenty two Q-1 and 22 Q This is also collectively referred to herein or individually as data path 22 of memory module 20. In the illustrated example, memory module 20 may include five data paths 22 (e.g., data paths 221, 222, 223, 224, and 225) on one side of RCD 50 and five data paths 22 (e.g., data path 221, 222, 223, 224, and 225) on the other side of RCD 50. Q-4 ,twenty two Q-3 , twenty two Q-2 , twenty two Q-1 and 22 QIn other embodiments, the memory module 20 may include other arrangements having more or fewer data paths 22 on each side of the RCD 50.

[0028] Data paths 22 may each include corresponding memory channels 421, 422, 423, 424, 425…42 R-4 42 R-3 , 42 R-2 , 42 R-1 and 42 R These are also collectively referred to herein as memory channels 42. Each memory channel 42 may include one or more of the memory devices 40. For example, memory channel 421 may include memory devices 401 to 40. S , and memory channel 42 R It may include a memory device 40 T Up to 40 M .

[0029] The memory controller 80 is configured to generate various signals, including clock signals (CLK), control signals (ADDR and CMD), and command signals. One or more of the CLK, ADDR, and CMD signals can be provided to the RCD 50, for example, via one or more buses 23.

[0030] Signals from the memory controller 80 can also be transmitted from the memory controller 80 to the PMIC 60 via bus 24, which is also referred to herein as the host interface bus 24. In some embodiments, the host interface bus 24 is bidirectional and configured to transmit commands or other data between the PMIC 60 and the memory controller 80 or other components of the memory module 20. The host interface bus 24 can implement I... 2 C protocol, I 3 C protocol or any other protocol.

[0031] A data bus 72 may be connected between the memory controller 80 and the data path 22 (e.g., having a data buffer 30), and the data bus may include a connector 70, such as a trace, pin, and other connection, between the memory controller 80 and the data path 22.

[0032] The memory controller 80 can generate or receive data signals (e.g., DQa-DQn) and data strobe signals (e.g., DQSa-DQSn), which can be submitted to or received from the data bus 72. A portion of the signals DQa-DQn and DQSa-DQSn can be submitted to or received from the corresponding data path 22. In the example shown, each of the signals DQa-DQn can have a corresponding signal DQSa-DQSn. In some embodiments, one DQS signal can strobe multiple DQ signals; for example, in some embodiments, one DQS signal is used for four DQ signals.

[0033] RCD 50 is configured to communicate with memory controller 80, data buffer 30, memory channel 42, and PMIC 60. RCD 50 is configured to decode instructions, such as control words, received from memory controller 80. For example, RCD 50 may be configured to receive and decode register command words (RCWs). In another example, RCD 50 may be configured to receive and decode buffer control words (BCWs). RCD 50 is configured to train one or more of the command and address lines between RCD 50 and memory controller 80, memory device 40, and data buffer 30. For example, RCWs may flow from memory controller 80 to RCD 50 and be used to configure RCD 50.

[0034] In some embodiments, RCD 50 can implement a command / address register, such as a 32-bit 1:2 command / address register. RCD 50 can support a full-speed bus, such as a unidirectional buffered communication (BCOM) bus between RCD 50 and data buffer 30. In some embodiments, RCD 50 can implement automatic impedance calibration, command / address parity checking, control register RCW readback, and, for example, a 1 MHz internal integrated circuit (I... 2 C) bus and 12.5 MHz internal integrated circuit (I) 3 C) One or more of the serial buses of the bus. The inputs of the RCD 50 can be pseudo-differential using external and internal voltages. The clock output, command / address output, control output, and data buffer control output of the RCD 50 can be enabled in groups and driven independently with different intensities.

[0035] RCD 50 is configured to receive CLK, ADDR, and CMD signals or other signals (e.g., RCW and BCW) from memory controller 80, and is configured to generate corresponding output signals based on the CLK, ADDR, and CMD signals using various digital logic components. For example, RCD 50 is configured to generate corresponding signals, such as CLK', ADDR', and CMD' signals, based on the received CLK, ADDR, and CMD signals. The CLK', ADDR', and CMD' signals can be submitted to memory channel 42. For example, the CLK' signal can be sent from RCD 50 to memory channel 42 on common bus 25, and the ADDR' and CMD' signals can be sent from RCD 50 to memory channel 42 on common bus 26. RCD 50 is also configured to generate one or more data buffer control (DBC) signals, which are sent, for example, to data buffer 30 on common bus 27, which is also referred to as data buffer control bus 27.

[0036] Data buffer 30 is configured to receive commands and data from data buffer control bus 27, and to generate data, receive data from data bus 72, or send data to data bus 72. Each data path 22 also includes a bus 28 between its data buffer 30 and memory channel 42, configured to carry data between the data buffer 30 and memory channel 42. For example, as Figure 2 As shown, data path 221 includes bus 28 between data buffer 301 and memory channel 421.

[0037] Data buffer 30 is configured to buffer data on buses 72 and 28 for write operations (e.g., data transfer from memory controller 80 to the corresponding memory channel 42) and read operations (e.g., data transfer from the corresponding memory channel 42 to memory channel 80).

[0038] In some example embodiments, data buffer 30 exchanges data with memory device 40 in small units, such as 4-bit nibbles, via bus 28. In other embodiments, larger or smaller data transfer sizes may be used instead. In some cases, memory devices 40 may be arranged in multiple sets, such as two sets. For example, in a two-set / two-memory-device implementation, such as memory devices 401 and 402, each set may contain a single memory device 40 (e.g., 401 or 402), where each memory device 40 is connected to a corresponding data buffer 30 via an overbyte and a underbyte. In a two-set / four-memory-device implementation, each set may contain two memory devices 40. The first set may be connected to the corresponding data buffer 30 via an overbyte, and the second set may be connected to the corresponding data buffer 30 via an underbyte. In a two-set / eight-memory-device implementation, each set may contain four memory devices 40. The first set of four memory devices 40 may be connected to the corresponding data buffer 30 via an overbyte, and the second set of four memory devices may be connected to the corresponding data buffer 30 via an underbyte. Alternatively, other numbers of sets, each set having other numbers of memory devices and other data unit sizes, can be used.

[0039] The memory module 20 may also include an interface 29 configured to enable communication between the RCD 50 and the PMIC 60. For example, interface 29 may be used as part of a register clock driver / power management integrated circuit interface, such as an RCD-PMIC interface. Interface 29 is configured to support one or more signals or connections, which may be bidirectional or unidirectional.

[0040] Figure 3 This is a block diagram of an example 300 of a register clock driver with chip select feedback circuitry, implemented according to embodiments of the present disclosure. System 300 may include a host controller 302 and a memory module 304. Memory module 304 may be one of memory modules 20, and host device 302 may be... Figure 1 and Figure 2The memory controller 80 is shown. In one or more embodiments, the host device 302 may be, for example, a part of a circuit, a motherboard, a motherboard, a processor or processor core, a central processing unit (CPU), or other components of a computing device that communicate with the memory module 304. The system 300 may be implemented in a computing device such as a desktop computer, a laptop computer, a server, a benchmark device, etc. In embodiments, the memory module 304 may be, for example, a dual in-line memory module (DIMM). In some embodiments, the memory module 304 may be implemented as a dual data rate fifth generation (DDR5) load-reduced dual in-line memory module (LRDIMM) including synchronous dynamic random access memory (SDRAM) devices.

[0041] Memory module 304 may include a register clock driver (RCD) 306 and multiple memory rows and columns. Figure 3 In the example shown, memory module 304 may include four memory rows labeled row 0, row 1, row 2, and row 3. In one or more embodiments, memory module 304 may include fewer than four rows or more than four rows up to, for example, eight rows. In some embodiments, RCD 306 may implement a command / address register and may support a one-way buffer communication (BCOM) bus between RCD 306 and the data buffer in memory module 304.

[0042] RCD 306 can be configured to receive a plurality of input signals 308 from host device 302. The input signals 308 may include control signals, such as address signals (e.g., library address signals, row address signals, column address signals, gated column address strobe signals, chip select signals, parity signals) and command signals (e.g., refresh, precharge, etc.) and data signals (e.g., data to be written to the memory device in memory module 304).

[0043] RCD 306 can be configured to operate in loopback and pass-through modes. Pass-through mode allows RCD 306 to decode input signal 308 and, based on input signal 308, continue reading and / or writing to memory rows in memory module 304. In one embodiment, RCD 306 may include one or more logic circuits configured to receive input signal 308 and generate a set of output control signals that can be sent to appropriate memory devices in memory module 304. Furthermore, RCD 306 can be configured to decode instructions from input signal 308. For example, RCD 306 can be configured to receive and decode register command words (RCWs) and buffer control words (BCWs) received from host device 302. Pass-through mode allows input signal 308 to be processed by the logic circuitry of RCD 306 and output to one or more memory rows in memory module 304.

[0044] The loopback mode allows the RCD 306 to feed back samples of one or more signals from the input signal 308 or other internal signals within the RCD 306 (e.g., signals exchanged between components within the RCD 306) to the host device 302 or other devices for testing, debugging, and training purposes. In one embodiment, the loopback mode of the RCD 306 can be activated by enabling the loopback circuitry 310 within the RCD 306. The loopback circuitry 310 can be configured to sample signals from the input signal 308 or internal signals of the RCD 306 and send the sampled signals to the host device 302. In one or more embodiments, the pass-through mode and the loopback mode can be activated individually or simultaneously.

[0045] On one hand, sampling external signals (e.g., signals provided to RCD 306 by another device outside RCD 306, or signals provided to another device by RCD 306) and sampling the output signals of RCD 306 can allow host device 302 to determine whether an error exists in RCD 306. However, such sampling techniques may not allow host device 302 to determine which part, processing stage, or component of RCD 306 is causing the error. Integration of feedback circuitry 310 into RCD 306 allows feedback circuitry 310 to sample internal signals within RCD 306 from one or more sampling points within RCD 306. Sampled signals from one or more sampling points within RCD 306 can allow host device 302 to identify components or specific processing stages in RCD 306 that may be causing the error. In one embodiment, in response to processing by different processing stages in RCD 306, the chip select signal in input signal 308 can be sampled at multiple sampling points in RCD 306 to determine if any errors related to the chip select signal exist (e.g., an incorrect chip select signal, or unwanted delays, etc.). In another embodiment, loopback circuitry 310 can use existing internal loopback lines in RCD 306 to sample the chip select signal, thereby reducing the number of hardware or traces that can be used to integrate chip select signal loopback features.

[0046] Figure 4 The illustration is based on an embodiment of the present disclosure. Figure 3 A detailed diagram of the example register clock driver (RCD) 306. Figure 4 In the example shown, RCD 306 may include feedback circuitry 310, receiver 404, logic circuitry 406, and output driver 408. Receiver 404 may be configured to receive input signal 308 from host device 302 (see [link to example]). Figure 3 In one embodiment, receiver 404 may include hardware or circuit components such as buffers and amplifiers. Input signal 308 can pass through these components in receiver 404 and can be output as intermediate signal 407. On one hand, intermediate signal 407 may deviate from the expected output from receiver 404 due to variations such as process and temperature changes in the components in receiver 404. Receiver 404 may buffer intermediate signal 407 and send it to logic circuit 406.

[0047] Logic circuit 406 can be configured to decode intermediate signal 407 to generate another set of intermediate signals 409, and send intermediate signals 409 to output driver 408. In an embodiment, input signal 308 may include a selection memory module 304 (see...) Figure 3The chip select signal 412 is one or more memory rows in the memory module 304. An intermediate signal 407 may include a processed version of the chip select signal 412 (e.g., buffered, amplified, etc.). Logic circuitry 406 may decode the intermediate signal 407, including the processed chip select signal 412, and generate an intermediate signal 409 representing a voltage that can be applied to memory module 304 to activate the selected memory row. Logic circuitry 406 may send the intermediate signal 409 to output driver 408. Output driver 408 may output voltage 430 to activate the memory row selected in the chip select signal 412.

[0048] The feedback circuit 310 can be configured to sample the chip select signal 412 at different sampling points within the RCD 306. For example, the feedback circuit 310 can sample the chip select signal 412 by obtaining a copy of an intermediate signal 407, labeled as sample signal 422, from sampling point 414 between the receiver 404 and the logic circuit 406. The feedback circuit 310 can also sample the chip select signal 412 by obtaining a copy of an intermediate signal 409, labeled as sample signal 424, from another sampling point 416 between the logic circuit 406 and the output driver 408. The feedback circuit 310 can then transmit the sampled signals 422 and 424 to the host device 302.

[0049] In one embodiment, host device 302 may store a copy of chip select signal 412. Host device 302 may compare chip select signal 412 with sampled signals 422, 424 to determine the difference between chip select signal 412 and sampled signals 422, 424. In one embodiment, host device 302 may simulate the operation of receiver 404 and logic circuit 406. Simulation may result in the generation of analog signals 434, 436, which may be analog versions of intermediate signals 407, 409, respectively. Host device 302 may compare intermediate signal 407 with analog signal 434 to identify whether a difference exists between intermediate signal 407 and analog signal 434. If the difference between intermediate signal 407 and analog signal 434 exceeds a predefined difference (which may be stored in host device 302), host device 302 may determine that an error may exist in receiver 404. The host device 302 can generate a flag and output the flag on a user interface, such as a display connected to the host device 302, to notify the user that there may be an error in the receiver 404 and / or indicate that the receiver 404 may need to be reconfigured to maintain the signal integrity of the chip select signal 412 and / or future chip select signals.

[0050] If the difference between the intermediate signal 409 and the analog signal 436 exceeds a predefined difference (which may be stored in the host device 302), the host device 302 can determine that there may be an error in the logic circuit 406. The host device 302 can generate a flag and output the flag on a user interface, for example, in a display connected to the host device 302, to notify the user that there may be an error in the logic circuit 406 and / or indicate that the logic circuit 406 may need to be reconfigured to maintain the signal integrity of the chip select signal 412 and / or future chip select signals.

[0051] In one embodiment, host device 302 may sample voltage 430 at the output of RCD 306. Host device 302 may simulate voltage 430 and compare the sampled voltage with the simulated voltage. If there is no difference between intermediate signals 407, 409 and simulated signals 434, 436, or if the difference does not exceed a predefined difference stored in host device 302, but there is a difference between the sampled version and the simulated version of voltage 430, then host device 302 may determine that there may be an error in output driver 408 and that output driver 408 may need to be reconfigured to maintain the signal integrity of chip select signal 412 and / or future chip select signals.

[0052] In one embodiment, if there is no difference between intermediate signal 407 and analog signal 434, or if the difference between intermediate signal 407 and analog signal 434 does not exceed a predefined difference stored in host device 302, but there is a difference between intermediate signal 409 and analog signal 436, then host device 302 can determine that there may be an error in logic circuit 406, but no error in receiver 404.

[0053] In one embodiment, if there is no difference between intermediate signal 409 and analog signal 436, or if the difference between intermediate signal 409 and analog signal 436 does not exceed a predefined difference stored in host device 302, but there is a difference between intermediate signal 407 and analog signal 434, then host device 302 can determine that there may be an error in receiver 404, but no error in logic circuit 406.

[0054] Furthermore, in one embodiment, the host device 302 may send an enable signal 440 to the feedback circuit 310 to enable or disable the feedback circuit 310. The enable signal 440 may be, for example, a binary signal, such that binary zero disables the feedback circuit 310 and binary one enables the feedback circuit 310 (or vice versa). In response to disabling the feedback circuit 310, the RCD 306 may operate in normal or pass-through mode, wherein the RCD may buffer and decode the input signal 308 for controlling the memory rows and columns of the memory module 304, reading from and / or writing to the memory rows and columns of the memory module 304. Note that when the feedback circuit 310 is disabled, the connections between sampling point 414 and the feedback circuit 310, and between sampling point 416 and the feedback circuit 310, may be opened or closed, such that signals are not sampled from sampling points 414, 416. In response to enabling the feedback circuit 310, the connections between sampling point 414 and the feedback circuit 310, and between sampling point 416 and the feedback circuit 310, can be turned off or on, allowing the feedback circuit 310 to sample signals from sampling points 414 and 416. In one embodiment, the pass-through mode and the feedback mode can be activated simultaneously, allowing the feedback circuit 310 to sample signals during normal operation of the RCD 306.

[0055] By integrating the feedback circuitry 310 into the RCD 306, one or more test points can be inserted into the RCD 306 to maintain signal integrity. For example, it is possible to... Figure 4 The RCD 306 shown internally samples the chip select signal at more than one sampling point. Different sampling points within the RCD 306 can provide information about which specific parts or stages of the RCD 306 may be faulty and require attention. Furthermore, the integration of the loopback circuit 310 allows dedicated ports of the RCD 306 to be assigned to the sampling points (e.g., 414, 416), enabling periodic testing to improve and maintain signal integrity during normal operation.

[0056] Figure 5 This is a block diagram of a feedback circuit 310 according to an embodiment of the present disclosure. The feedback circuit 310 may include multiple circuit components to facilitate feedback to the host device 302 (see [link to documentation]). Figure 4 The sampling and selection of the sampled signal. Figure 5 In the example shown, the feedback circuit 310 may include multiplexers 502, 504, 506, 508, and 510. Multiplexer 502 may be configured to receive multiple command / address signals (DCA0_A to DCA6_A), and from RCD 306 (see...). Figure 3 , Figure 4The parity signal or parity bit (DPAR_A) sampled from one or more sampling points in the RCD 306. The sampled signals DPAR_A and DCA0_A to DCA6_A may correspond to the first channel (“Channel A”) of the memory module 304 and RCD 306. The multiplexer 504 may be configured to receive multiple command / address signals (DCA0_B to DCA6_B), and the parity signal or parity bit (DPAR_B) sampled from one or more sampling points in the RCD 306. The sampled signals DPAR_B and DCA0_B to DCA6_B may correspond to the second channel (“Channel B”) of the memory module 304 and RCD 306. This may be achieved by the RCD 306 and / or the host device 302 (see [link to documentation]). Figure 3 , Figure 4 A selection signal 520, labeled RX_LOOPBACK_SEL, is provided to select one of the sampled signals received by multiplexers 502 and 504 for output to multiplexer 510. In one embodiment, the selection signal 520 may be a three-bit signal having a first, second, and third bit.

[0057] Multiplexer 506 can be configured to receive a sampled chip select signal (DCS0_A) from a sampling point in RCD 306, where the sampled chip select signal DCS0_A corresponds to channel A. Multiplexer 508 can be configured to receive a sampled chip select signal (DCS0_B) from a sampling point in RCD 306, where the sampled chip select signal DCS0_B corresponds to channel B. The sampled chip select signal received by multiplexers 502 and 504 can be from... Figure 4 One or more of the signals sampled at sampling points 414 and 416 are shown. In one embodiment, one bit of the selection signal 520 can be used to select one of the input sampled signals received by multiplexers 506 and 508 to be output to multiplexer 510.

[0058] Multiplexer 510 can be configured to receive outputs from multiplexers 502, 504, 506, and 508. Multiplexer 510 can also receive sampled external signals, such as DLBD_A and DLBD_B, which can be sampled externally, such as at sampling points outside RCD 306, sampling points between RCD 306 and host device 302, and / or sampling points between RCD 306 and memory rows and columns of memory module 304 (see [link to relevant documentation]). Figure 3 The multiplexer 510 can also receive sampling clock signals that can be internal or external to the RCD 306 (e.g., Figure 5The internal clock signal marked as internal QCK can be provided by RCD 306 and / or host device 302. A selection signal 522 marked RX_LOOPBACK_CTRL can be provided for selecting one of the sampled signals received by multiplexer 510 as the internal clock signal. Figure 4 The sampling signals 422 and 424 are shown as outputs. In one embodiment, the selection signal 522 may be a three-bit signal with a first bit, a second bit, and a third bit.

[0059] In one embodiment, selection signal 522 can control the selection of the sampling chip selection signal output by multiplexer 510. For example, the third bit (or least significant bit) of selection signal 520 can be used to select the sampling signal in multiplexers 506 and 508. Thus, selection signal 520 as "000", "010", "100", or "110" can cause binary "0" to be sent to the selection pins of multiplexers 506 and 508. In the example, selection signal 520 as "000" can cause multiplexer 502 to select DCA0_A, multiplexer 504 to select DCA0_B, and binary "0" can cause multiplexers 506 and 508 to select chip selection signals DCS0_A and DCS0_B, respectively. Therefore, selection signal 520 as "000" can cause multiplexers 502, 504, 506, and 508 to output DCA0_A, DCA0_B, DCS0_A, and DCS0_B, respectively. Selection signal 522 can select one of outputs DCA0_A, DCA0_B, DCS0_A, and DCS0_B, so that even if the third bit of selection signal 520 is shared by multiple multiplexers, multiplexer 510 can still output the desired sampled signal. By using existing bits in the selection signal for internal signals of other samples, feedback circuit 310 can internally provide sampling of the chip selection signal without having to design and allocate new control word bits for chip selection sampling and feedback.

[0060] In one embodiment, multiplexers 502, 504, 506, 508, and 510 can be considered as a group of feedback blocks within feedback circuit 310. Feedback circuit 310 may include... Figure 5 The example shown uses more than one feedback block, which can receive different types of sampled signals to feed back to the host device 302. For example, Figure 5The multiplexers 502, 504, 506, 508, and 510 shown can be configured to sample command / address signals, parity signals, chip select signals, and external data signals DLBD_A and DLBD_B from within the RCD 306. The feedback circuit 310 may include another feedback block with a similar arrangement of multiplexers 502, 504, 506, 508, and 510, which can be configured to sample command / address signals, parity signals, chip select signals, and external clock signals from within the RCD 306 (e.g., instead of DLBD_A and DLBD_B, multiplexer 510 can receive the external clock signal).

[0061] Figure 6 This is a flowchart of an example process 600 for implementing a register clock driver with chip select feedback circuitry according to embodiments of the present disclosure. Process 600 may include one or more operations, actions, or functions as shown in one or more of blocks 602, 604, and / or 606. Although shown as discrete blocks, the individual blocks may be divided into additional blocks, combined into fewer blocks, eliminated, executed in a different order, or in parallel, depending on the desired implementation.

[0062] Process 600 can be implemented via a register clock driver (RCD) of the memory module. Process 600 can be located at block 602. At block 602, the RCD can receive a chip select signal for selecting one or more memory rows and columns of the memory module. In one embodiment, the memory module can be a DDR5 load-reduced dual in-line memory module (LRDIMM) including synchronous dynamic random access memory (SDRAM) devices.

[0063] Process 600 can proceed from block 602 to block 604. At block 604, the RCD samples the chip select signal from a first sampling point between the RCD's receiver and the RCD's logic circuitry. Process 600 can proceed from block 604 to block 606. At block 606, the RCD samples the chip select signal from a second sampling point between the RCD's logic circuitry and the RCD's output driver. Process 600 can proceed from block 606 to block 608. At block 608, the RCD can send the sampled chip select signal to the memory controller. In one embodiment, the RCD can perform the operations in either block 604 or block 606. In another embodiment, the RCD can perform operations in both blocks 604 and 606, individually or simultaneously.

[0064] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It will also be understood that the terms “comprising” and / or “including” as used in this specification designate the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0065] The corresponding structures, materials, actions, and equivalents of all components or steps plus functional elements (if any) in the following claims are intended to include any structure, material, or action for performing a function in conjunction with other claimed elements as specifically claimed. The disclosed embodiments of the invention have been presented for illustrative and descriptive purposes, but are not intended to be exhaustive or to limit the forms disclosed herein. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described to best explain the principles of the invention and its practical application, so that others skilled in the art can understand the invention through various embodiments and various modifications as suited to the particular intended use.

Claims

1. A memory module, comprising: Register clock driver, including: The feedback circuit is configured to receive: One or more command / address signals; One or more parity check signals; One or more sampled chip selection signals sampled at one or more sampling points inside the register clock driver; One or more sampled external signals are sampled at one or more sampling points outside the register clock driver; One or more sampled clock signals sampled at one or more sampling points inside or outside the register clock driver; The first selection signal is configured to select a signal from the one or more command / address signals, the one or more parity signals, and the one or more sampling chip selection signals; and The second selection signal is configured as follows: A signal is selected from the one or more external sampling signals, the one or more sampling clock signals, the one or more command / address signals selected by the first selection signal, and the one or more sampling chip selection signals selected by the first selection signal; and It is configured to determine the output signal to be output to the host device based on the first selection signal and the second selection signal.

2. The memory module according to claim 1, wherein: The one or more externally sampled signals are sampled between the register clock driver and the host device; and / or The one or more sampled external signals are sampled between the register clock driver and the memory rows and columns of the memory module.

3. The memory module according to claim 1, wherein: The first selection signal includes: Corresponding to the first portion of the first channel of the memory module and the register clock driver, and The second portion of the second channel corresponding to the memory module and the register clock driver; and The second selection signal includes: Corresponding to the first portion of the first channel of the memory module and the register clock driver, and The second part of the second channel corresponding to the memory module and the register clock driver.

4. The memory module according to claim 1, wherein: The first selection signal includes a three-bit signal comprising three bits, and One of the three bits of the three-bit signal is used to select the sampling chip selection signal and the sampling command / address signal.

5. The memory module according to claim 1, wherein, The feedback circuit is activated when an enable signal is received.

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